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Searched refs:Reg0 (Results 1 – 23 of 23) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h121 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
125 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
127 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
129 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
131 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
133 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
137 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
139 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsSEFrameLowering.cpp462 unsigned Reg0 = in emitPrologue() local
468 std::swap(Reg0, Reg1); in emitPrologue()
471 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
480 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
484 std::swap(Reg0, Reg1); in emitPrologue()
487 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp175 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
184 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
188 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
194 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
196 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
219 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
[all …]
H A DMipsMCCodeEmitter.cpp96 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
101 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
102 if (Reg0 < Reg1) in LowerCompactBranch()
105 if (Reg0 >= Reg1) in LowerCompactBranch()
109 if (Reg1 >= Reg0) in LowerCompactBranch()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp233 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
234 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
238 if (Reg0.isVirtual()) { in runOnMachineFunction()
240 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
H A DHexagonBitTracker.cpp314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
845 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
847 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
849 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
851 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
/openbsd-src/gnu/llvm/llvm/include/llvm/MC/
H A DMCRegisterInfo.h755 uint16_t Reg0 = 0; variable
763 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
769 return Reg0;
774 return Reg0; in isValid()
780 Reg0 = Reg1;
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2168 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2190 Ops.push_back(Reg0); in SelectVLD()
2193 Ops.push_back(Reg0); in SelectVLD()
2206 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
2219 Ops.push_back(Reg0); in SelectVLD()
2223 Ops.push_back(Reg0); in SelectVLD()
2303 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2350 Ops.push_back(Reg0); in SelectVST()
2354 Ops.push_back(Reg0); in SelectVST()
2379 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
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H A DThumb2SizeReduction.cpp754 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
760 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
763 if (Reg0 != Reg2) { in ReduceTo2Addr()
766 if (Reg1 != Reg0) in ReduceTo2Addr()
773 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
778 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
785 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
H A DARMAsmPrinter.cpp320 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
321 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp298 Register Reg0 = Op0.getReg(); in legalizeCustom() local
304 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) { in legalizeCustom()
309 Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GR)); in legalizeCustom()
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp230 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
253 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
268 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp193 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm() local
217 CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1)); in selectInlineAsm()
231 CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, Chain.getValue(1)); in selectInlineAsm()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1436 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1439 printRegName(O, Reg0); in printVectorListTwo()
1449 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1452 printRegName(O, Reg0); in printVectorListTwoSpaced()
1504 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1507 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1551 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1554 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ExpandPseudo.cpp466 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
470 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
500 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
513 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill)); in ExpandMI()
H A DX86InstrInfo.cpp6223 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
6233 if ((HasDef && Reg0 == Reg1 && Tied1) || in foldMemoryOperandImpl()
6234 (HasDef && Reg0 == Reg2 && Tied2)) in foldMemoryOperandImpl()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp183 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
203 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
206 Reg0 = Reg2; in commuteInstructionImpl()
208 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
211 Reg0 = Reg1; in commuteInstructionImpl()
225 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
H A DRegisterCoalescer.cpp2639 Register Reg0; in valuesIdentical() local
2640 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2641 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2651 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2657 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
H A DRegAllocFast.cpp1243 Register Reg0 = MO0.getReg(); in allocateInstruction() local
1245 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in allocateInstruction()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp991 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
994 .addImm(Reg0) in InsertSEH()
1004 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1006 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1012 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
1042 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1045 .addImm(Reg0) in InsertSEH()
1053 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
1055 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1061 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp799 Register Reg0 = UseMI->getOperand(0).getReg(); in foldOperand() local
801 if (TRI->isAGPR(*MRI, Reg0) && TRI->isVGPR(*MRI, Reg1)) in foldOperand()
803 else if (TRI->isVGPR(*MRI, Reg0) && TRI->isAGPR(*MRI, Reg1)) in foldOperand()
805 else if (ST->hasGFX90AInsts() && TRI->isAGPR(*MRI, Reg0) && in foldOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1972 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in loadImmediate() local
1974 BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0); in loadImmediate()
1976 .addReg(Reg0).addImm(Value >> 32); in loadImmediate()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1166 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1176 if (Reg0 == Reg1) { in commuteInstructionImpl()
1196 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1199 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()