| /openbsd-src/gnu/llvm/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 41 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
42 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
48 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
52 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 65 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
73 LLT Ty = MRI.getType(ExtReg); in assignValueToReg()
80 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0); in assignValueToReg()
82 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
86 {MRI.getType(ExtReg)}, false) in assignValueToReg()
87 .addReg(ExtReg); in assignValueToReg()
88 ExtReg = ToSGPR.getReg(0); in assignValueToReg()
91 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
233 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
234 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| H A D | AMDGPUInstructionSelector.cpp | 2396 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
2401 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
2408 .addReg(ExtReg) in selectG_SZA_EXT()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 111 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
112 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
118 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
122 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| H A D | X86FastISel.cpp | 1090 Register ExtReg = createResultReg(&X86::GR64RegClass); in X86SelectCallAddress() local
1092 TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) in X86SelectCallAddress()
1096 Reg = ExtReg; in X86SelectCallAddress()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCCallLowering.cpp | 53 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
54 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 120 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
121 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
127 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
130 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 222 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
223 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
254 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
255 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 931 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
934 SrcReg1 = ExtReg; in PPCEmitCmp()
937 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
940 SrcReg2 = ExtReg; in PPCEmitCmp()
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| H A D | PPCISelLowering.cpp | 11627 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
11629 ExtReg).addReg(dest); in EmitAtomicBinary()
11630 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ExtReg).addReg(incr); in EmitAtomicBinary()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 287 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
288 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| H A D | AArch64InstructionSelector.cpp | 6410 Register ExtReg = moveScalarRegClass(OffsetInst->getOperand(1).getReg(), in selectAddrModeWRO() local
6416 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
6705 Register ExtReg; in selectArithExtendedRegister() local
6732 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
6738 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
6744 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
6745 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg); in selectArithExtendedRegister()
6754 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB); in selectArithExtendedRegister()
6756 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()
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