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Searched refs:pll (Results 1 – 25 of 237) sorted by relevance

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/netbsd-src/sys/arch/arm/amlogic/
H A Dmeson_clk_pll.c43 struct meson_clk_pll *pll = &clk->u.pll; in meson_clk_pll_get_rate() local
62 val = CLK_READ(sc, pll->n.reg); in meson_clk_pll_get_rate()
63 n = __SHIFTOUT(val, pll->n.mask); in meson_clk_pll_get_rate()
65 val = CLK_READ(sc, pll->m.reg); in meson_clk_pll_get_rate()
66 m = __SHIFTOUT(val, pll->m.mask); in meson_clk_pll_get_rate()
68 if (pll->frac.mask) { in meson_clk_pll_get_rate()
69 val = CLK_READ(sc, pll->frac.reg); in meson_clk_pll_get_rate()
70 frac = __SHIFTOUT(val, pll->frac.mask); in meson_clk_pll_get_rate()
80 rate += howmany(frac_rate, __SHIFTOUT_MASK(pll->frac.mask) + 1); in meson_clk_pll_get_rate()
88 meson_clk_pll_wait_lock(struct meson_clk_softc *sc, struct meson_clk_pll *pll) in meson_clk_pll_wait_lock() argument
[all …]
H A Dmeson_clk.h259 struct meson_clk_pll *pll);
267 .u.pll.parent = (_parent), \
268 .u.pll.enable = _enable, \
269 .u.pll.m = _m, \
270 .u.pll.n = _n, \
271 .u.pll.frac = _frac, \
272 .u.pll.l = _l, \
273 .u.pll.reset = _reset, \
274 .u.pll.flags = (_flags), \
285 .u.pll.parent = (_parent), \
[all …]
/netbsd-src/sys/arch/arm/rockchip/
H A Drk_cru_pll.c90 struct rk_cru_pll *pll = &clk->u.pll; in rk_cru_pll_get_rate() local
105 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); in rk_cru_pll_get_rate()
106 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1); in rk_cru_pll_get_rate()
107 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2); in rk_cru_pll_get_rate()
108 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3); in rk_cru_pll_get_rate()
110 if ((pll->flags & RK_PLL_RK3288) != 0) { in rk_cru_pll_get_rate()
122 } else if ((pll->flags & RK_PLL_RK3588) != 0) { in rk_cru_pll_get_rate()
160 struct rk_cru_pll *pll = &clk->u.pll; in rk_cru_pll_set_rate() local
167 if (pll->rates == NULL || rate == 0 || !HAS_GRF(sc)) in rk_cru_pll_set_rate()
170 for (int i = 0; i < pll->nrates; i++) in rk_cru_pll_set_rate()
[all …]
H A Drk3399_pmucru.c164 struct rk_cru_pll *pll = &clk->u.pll; in rk3399_pmucru_pll_get_rate() local
179 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); in rk3399_pmucru_pll_get_rate()
180 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1); in rk3399_pmucru_pll_get_rate()
181 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2); in rk3399_pmucru_pll_get_rate()
182 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3); in rk3399_pmucru_pll_get_rate()
207 struct rk_cru_pll *pll = &clk->u.pll; in rk3399_pmucru_pll_set_rate() local
214 if (pll->rates == NULL || rate == 0) in rk3399_pmucru_pll_set_rate()
217 for (int i = 0; i < pll->nrates; i++) in rk3399_pmucru_pll_set_rate()
218 if (pll->rates[i].rate == rate) { in rk3399_pmucru_pll_set_rate()
219 pll_rate = &pll->rates[i]; in rk3399_pmucru_pll_set_rate()
[all …]
H A Drk3399_cru.c236 struct rk_cru_pll *pll = &clk->u.pll; in rk3399_cru_pll_get_rate() local
251 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); in rk3399_cru_pll_get_rate()
252 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1); in rk3399_cru_pll_get_rate()
253 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2); in rk3399_cru_pll_get_rate()
254 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3); in rk3399_cru_pll_get_rate()
279 struct rk_cru_pll *pll = &clk->u.pll; in rk3399_cru_pll_set_rate() local
286 if (pll->rates == NULL || rate == 0) in rk3399_cru_pll_set_rate()
290 for (int i = 0; i < pll->nrates; i++) { in rk3399_cru_pll_set_rate()
293 if (rate > pll->rates[i].rate) in rk3399_cru_pll_set_rate()
294 diff = rate - pll->rates[i].rate; in rk3399_cru_pll_set_rate()
[all …]
H A Drk_cru.h117 .u.pll.parents = (_parents), \
118 .u.pll.nparents = __arraycount(_parents), \
119 .u.pll.con_base = (_con_base), \
120 .u.pll.mode_reg = (_mode_reg), \
121 .u.pll.mode_mask = (_mode_mask), \
122 .u.pll.lock_mask = (_lock_mask), \
123 .u.pll.rates = (_rates), \
124 .u.pll.nrates = __arraycount(_rates), \
125 .u.pll.flags = _flags, \
419 struct rk_cru_pll pll; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_pll.c121 void amdgpu_pll_compute(struct amdgpu_pll *pll, in amdgpu_pll_compute() argument
129 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? in amdgpu_pll_compute()
139 fb_div_min = pll->min_feedback_div; in amdgpu_pll_compute()
140 fb_div_max = pll->max_feedback_div; in amdgpu_pll_compute()
142 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { in amdgpu_pll_compute()
148 if (pll->flags & AMDGPU_PLL_USE_REF_DIV) in amdgpu_pll_compute()
149 ref_div_min = pll->reference_div; in amdgpu_pll_compute()
151 ref_div_min = pll->min_ref_div; in amdgpu_pll_compute()
153 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && in amdgpu_pll_compute()
154 pll->flags & AMDGPU_PLL_USE_REF_DIV) in amdgpu_pll_compute()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_dpll_mgr.c63 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_atomic_duplicate_dpll_state() local
65 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
111 struct intel_shared_dpll *pll) in intel_get_shared_dpll_id() argument
113 if (WARN_ON(pll < dev_priv->shared_dplls|| in intel_get_shared_dpll_id()
114 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) in intel_get_shared_dpll_id()
117 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); in intel_get_shared_dpll_id()
122 struct intel_shared_dpll *pll, in assert_shared_dpll() argument
128 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) in assert_shared_dpll()
131 cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state); in assert_shared_dpll()
134 pll->info->name, onoff(state), onoff(cur_state)); in assert_shared_dpll()
[all …]
H A Dintel_dpll_mgr.h252 struct intel_shared_dpll *pll);
261 struct intel_shared_dpll *pll);
271 struct intel_shared_dpll *pll);
281 struct intel_shared_dpll *pll,
361 struct intel_shared_dpll *pll);
363 struct intel_shared_dpll *pll,
/netbsd-src/sys/dev/i2c/
H A Dtvpll.c47 const struct tvpll_data * pll; member
63 tvpll->pll = p; in tvpll_open()
65 if (tvpll->pll->initdata) { in tvpll_open()
68 &tvpll->pll->initdata[1], tvpll->pll->initdata[0], in tvpll_open()
73 device_printf(parent, "tvpll: %s\n", tvpll->pll->name); in tvpll_open()
88 const struct tvpll_data *pll; in tvpll_algo() local
92 pll = tvpll->pll; in tvpll_algo()
95 (p->frequency < pll->min || p->frequency > pll->max)) in tvpll_algo()
98 for(i = 0; i < pll->count; i++) { in tvpll_algo()
99 if (p->frequency > pll->entries[i].limit) in tvpll_algo()
[all …]
/netbsd-src/sys/arch/arm/nxp/
H A Dimx_ccm_pll.c48 struct imx_ccm_pll *pll = &clk->u.pll; in imx_ccm_pll_enable() local
53 if ((pll->flags & IMX_PLL_ENET) != 0) in imx_ccm_pll_enable()
58 val = CCM_READ(sc, clk->regidx, pll->reg); in imx_ccm_pll_enable()
63 CCM_WRITE(sc, clk->regidx, pll->reg, val); in imx_ccm_pll_enable()
72 struct imx_ccm_pll *pll= &clk->u.pll; in imx_ccm_pll_get_rate() local
86 if ((pll->flags & IMX_PLL_ENET) != 0) { in imx_ccm_pll_get_rate()
88 return pll->div_mask; in imx_ccm_pll_get_rate()
91 const uint32_t val = CCM_READ(sc, clk->regidx, pll->reg); in imx_ccm_pll_get_rate()
92 const u_int div = __SHIFTOUT(val, pll->div_mask); in imx_ccm_pll_get_rate()
94 if ((pll->flags & IMX_PLL_ARM) != 0) { in imx_ccm_pll_get_rate()
[all …]
H A Dimx6_ccm.c161 struct imx6_clk_pll *pll = &iclk->clk.pll; in imxccm_clk_get_rate_pll_generic() local
164 KASSERT((pll->type == IMX6_CLK_PLL_GENERIC) || in imxccm_clk_get_rate_pll_generic()
165 (pll->type == IMX6_CLK_PLL_USB)); in imxccm_clk_get_rate_pll_generic()
167 uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll->reg); in imxccm_clk_get_rate_pll_generic()
168 uint32_t div = __SHIFTOUT(v, pll->mask); in imxccm_clk_get_rate_pll_generic()
177 struct imx6_clk_pll *pll = &iclk->clk.pll; in imxccm_clk_get_rate_pll_sys() local
180 KASSERT(pll->type == IMX6_CLK_PLL_SYS); in imxccm_clk_get_rate_pll_sys()
182 uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll in imxccm_clk_get_rate_pll_sys()
195 struct imx6_clk_pll *pll = &iclk->clk.pll; imxccm_clk_get_rate_pll_audio_video() local
216 struct imx6_clk_pll *pll = &iclk->clk.pll; imxccm_clk_get_rate_pll_enet() local
242 struct imx6_clk_pll *pll = &iclk->clk.pll; imxccm_clk_get_rate_pll() local
538 struct imx6_clk_pll *pll = &iclk->clk.pll; imxccm_clk_enable_pll() local
[all...]
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
H A Dnouveau_nvkm_subdev_clk_gk20a.c70 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument
76 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
77 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
78 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
82 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_write_mnp() argument
87 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; in gk20a_pllg_write_mnp()
88 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; in gk20a_pllg_write_mnp()
89 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; in gk20a_pllg_write_mnp()
94 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_calc_rate() argument
99 rate = clk->parent_rate * pll->n; in gk20a_pllg_calc_rate()
[all …]
H A Dnouveau_nvkm_subdev_clk_gm20b.c165 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
171 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
173 pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) & in gm20b_pllg_read_mnp()
178 gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll) in gm20b_pllg_write_mnp() argument
183 pll->sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT); in gm20b_pllg_write_mnp()
184 gk20a_pllg_write_mnp(&clk->base, &pll->base); in gm20b_pllg_write_mnp()
275 struct gm20b_pll pll; in gm20b_pllg_slide() local
283 gm20b_pllg_read_mnp(clk, &pll); in gm20b_pllg_slide()
285 if (n_int == pll.base.n && sdm_din == pll.sdm_din) in gm20b_pllg_slide()
297 pll.base.n = n_int; in gm20b_pllg_slide()
[all …]
H A Dnouveau_nvkm_subdev_clk_gt215.c113 read_pll(struct gt215_clk *clk, int idx, u32 pll) in read_pll() argument
116 u32 ctrl = nvkm_rd32(device, pll + 0); in read_pll()
122 u32 coef = nvkm_rd32(device, pll + 4); in read_pll()
130 if ((pll & 0x00ff00) == 0x00e800) in read_pll()
240 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, in gt215_pll_info() argument
249 info->pll = 0; in gt215_pll_info()
255 if (!pll || (diff >= -2000 && diff < 3000)) { in gt215_pll_info()
260 ret = nvbios_pll_parse(subdev->device->bios, pll, &limits); in gt215_pll_info()
270 info->pll = (P << 16) | (N << 8) | M; in gt215_pll_info()
280 int idx, u32 pll, int dom) in calc_clk() argument
[all …]
H A Dnouveau_nvkm_subdev_clk_nv40.c133 struct nvbios_pll pll; in nv40_clk_calc_pll() local
136 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); in nv40_clk_calc_pll()
140 if (khz < pll.vco1.max_freq) in nv40_clk_calc_pll()
141 pll.vco2.max_freq = 0; in nv40_clk_calc_pll()
143 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_display.c953 void radeon_compute_pll_avivo(struct radeon_pll *pll, in radeon_compute_pll_avivo() argument
961 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? in radeon_compute_pll_avivo()
971 fb_div_min = pll->min_feedback_div; in radeon_compute_pll_avivo()
972 fb_div_max = pll->max_feedback_div; in radeon_compute_pll_avivo()
974 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
980 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
981 ref_div_min = pll->reference_div; in radeon_compute_pll_avivo()
983 ref_div_min = pll->min_ref_div; in radeon_compute_pll_avivo()
985 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && in radeon_compute_pll_avivo()
986 pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
[all …]
H A Dradeon_atombios_crtc.c1078 struct radeon_pll *pll; in atombios_crtc_set_pll() local
1089 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
1092 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
1097 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
1102 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1103 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1104 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1108 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1111 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1114 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/qca/
H A Dar9132.dtsi17 clocks = <&pll ATH79_CLK_CPU>;
64 clocks = <&pll ATH79_CLK_AHB>;
89 pll: pll-controller@18050000 { label
90 compatible = "qca,ar9132-pll",
91 "qca,ar9130-pll";
107 clocks = <&pll ATH79_CLK_AHB>;
151 clocks = <&pll ATH79_CLK_AHB>;
H A Dar9331.dtsi17 clocks = <&pll ATH79_CLK_CPU>;
90 pll: pll-controller@18050000 { label
91 compatible = "qca,ar9330-pll";
126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
281 clocks = <&pll ATH79_CLK_AHB>;
/netbsd-src/sys/arch/mips/atheros/
H A Dar9344.c124 uint32_t pll; in ar9344_get_freqs() local
139 pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG); in ar9344_get_freqs()
140 out_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_OUTDIV); in ar9344_get_freqs()
141 ref_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_REFDIV); in ar9344_get_freqs()
142 nint = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NINT); in ar9344_get_freqs()
150 pll = GETPLLREG(ARCHIP_PLL_DDR_PLL_CONFIG); in ar9344_get_freqs()
151 out_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_OUTDIV); in ar9344_get_freqs()
152 ref_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_REFDIV); in ar9344_get_freqs()
153 nint = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_NINT); in ar9344_get_freqs()
H A Dar7100.c152 const uint32_t pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG); in ar7100_get_freqs() local
156 ref_freq * (__SHIFTOUT(pll, AR7100_PLL_PLL_FB) + 1); in ar7100_get_freqs()
159 pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_CPU_DIV_SEL) + 1); in ar7100_get_freqs()
162 pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_DDR_DIV_SEL) + 1); in ar7100_get_freqs()
165 cpu_freq / ((__SHIFTOUT(pll, AR7100_CPU_PLL_AHB_DIV) + 1) * 2); in ar7100_get_freqs()
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dwm8850.dtsi90 compatible = "wm,wm8850-pll-clock";
97 compatible = "wm,wm8850-pll-clock";
104 compatible = "wm,wm8850-pll-clock";
111 compatible = "wm,wm8850-pll-clock";
118 compatible = "wm,wm8850-pll-clock";
125 compatible = "wm,wm8850-pll-clock";
132 compatible = "wm,wm8850-pll-clock";
H A Dkeystone-k2e-clocks.dtsi11 compatible = "ti,keystone,main-pll-clock";
19 compatible = "ti,keystone,pll-clock";
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "ddr-3a-pll-clk";
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
H A Dnouveau_nvkm_subdev_fb_ramnv40.c44 struct nvbios_pll pll; in nv40_ram_calc() local
48 ret = nvbios_pll_parse(bios, 0x04, &pll); in nv40_ram_calc()
54 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
59 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20; in nv40_ram_calc()

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