| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | HowToUseInstrMappings.rst | 14 could be to use switch cases which list all the instructions along with formats
24 TableGen uses relationship models to map instructions with each other. These
27 describe all the instructions using that model. TableGen parses all the relation
29 instructions with each other. These tables are emitted in the
36 // Used to reduce search space only to the instructions using this
40 // List of fields/attributes that should be same for all the instructions in
42 // by all the instructions related by this relationship.
45 // List of fields/attributes that are same for all the instructions
55 // each column in the relation table. These are the instructions a key
67 to define a relationship model that relates predicated instructions to their
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/mips/ |
| H A D | loongson2ef.md | 27 ;; Automaton for integer instructions.
44 ;; Reservations for ALU1 (ALU2) instructions.
52 ;; Reservation for ALU1/2 instructions.
62 ;; Automaton for floating-point instructions.
79 ;; Reservations for FALU1 (FALU2) instructions.
87 ;; Reservation for FALU1/2 instructions.
97 ;; The following 4 instructions each subscribe one of
99 ;; These instructions are used in mips.cc: sched_ls2_dfa_post_advance_cycle.
154 ;; Reservation for integer instructions.
161 ;; Reservation for branch instructions.
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| H A D | mips.opt | 59 Use PMC-style 'mad' instructions.
63 Use integer madd/msub instructions.
71 -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
75 Use Branch Likely instructions, overriding the architecture default.
87 -mcode-readable=SETTING Specify when instructions are allowed to access code.
108 Use trap instructions to check for integer divide by zero.
112 Allow the use of MDMX instructions.
116 Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
120 Use MIPS-DSP instructions.
124 Use MIPS-DSP REV 2 instructions.
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/mips/ |
| H A D | loongson2ef.md | 27 ;; Automaton for integer instructions.
44 ;; Reservations for ALU1 (ALU2) instructions.
52 ;; Reservation for ALU1/2 instructions.
62 ;; Automaton for floating-point instructions.
79 ;; Reservations for FALU1 (FALU2) instructions.
87 ;; Reservation for FALU1/2 instructions.
97 ;; The following 4 instructions each subscribe one of
99 ;; These instructions are used in mips.c: sched_ls2_dfa_post_advance_cycle.
154 ;; Reservation for integer instructions.
161 ;; Reservation for branch instructions.
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| H A D | mips.opt | 59 Use PMC-style 'mad' instructions.
63 Use integer madd/msub instructions.
71 -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
75 Use Branch Likely instructions, overriding the architecture default.
87 -mcode-readable=SETTING Specify when instructions are allowed to access code.
108 Use trap instructions to check for integer divide by zero.
112 Allow the use of MDMX instructions.
116 Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
120 Use MIPS-DSP instructions.
124 Use MIPS-DSP REV 2 instructions.
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/csky/ |
| H A D | csky.opt | 61 Enable hardware floating-point instructions.
73 Generate C-SKY FPU double float instructions (default for hard float).
77 Generate frecipd/fsqrtd/fdivd instructions (default for hard float).
89 Enable interrupt stack instructions.
93 Enable multiprocessor instructions.
97 Enable coprocessor instructions.
101 Enable cache prefetch instructions.
105 Enable C-SKY SECURE instructions.
112 Enable C-SKY TRUST instructions.
116 Enable C-SKY DSP instructions.
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPC.td | 59 "Enable 64-bit instructions">;
65 "Enable floating-point instructions">;
71 "Enable classic FPU instructions",
74 "Enable Altivec instructions",
77 "Enable SPE instructions",
80 "Enable Embedded Floating-Point APU 2 instructions",
111 "Enable the fri[mnpz] instructions",
114 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
121 "Enable extended divide instructions">;
129 "Enable Book E instructions",
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/sparc/ |
| H A D | m8.md | 22 ;; - Store instructions are implemented by micro-ops, one of which
27 ;; implementation assumes that all the instructions executing in a
31 ;; slot 0 and slot 1 instructions. This is not currently reflected
39 ;; instructions per-cycle, and up to 4 instructions are committed each
62 ;; Some instructions stall the pipeline and avoid any other
73 ;; Most of the instructions executing in the integer units have a
89 ;; The integer multiplication instructions have a latency of 10 cycles
92 ;; Likewise for array*, edge* and pdistn instructions.
105 ;; The integer division instructions `sdiv' and `udivx' have a latency
113 ;; Both integer and floating-point load instructions have a latency of
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| H A D | niagara7.md | 24 ;; up to 2 instructions are committed each cycle. Each slot serves
39 ;; Some instructions stall the pipeline and avoid any other
50 ;; Most of the instructions executing in the integer unit have a
65 ;; The integer multiplication instructions have a latency of 12 cycles
68 ;; Likewise for array*, edge* and pdistn instructions.
75 ;; The integer division instructions have a latency of 35 cycles and
83 ;; Both integer and floating-point load instructions have a latency of
102 ;; Both integer and floating-point store instructions have a latency
110 ;; Control-transfer instructions execute in the Branch Unit in the
118 ;; Many instructions executing in the Floating-point and Graphics unit
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/sparc/ |
| H A D | m8.md | 22 ;; - Store instructions are implemented by micro-ops, one of which
27 ;; implementation assumes that all the instructions executing in a
31 ;; slot 0 and slot 1 instructions. This is not currently reflected
39 ;; instructions per-cycle, and up to 4 instructions are committed each
62 ;; Some instructions stall the pipeline and avoid any other
73 ;; Most of the instructions executing in the integer units have a
89 ;; The integer multiplication instructions have a latency of 10 cycles
92 ;; Likewise for array*, edge* and pdistn instructions.
105 ;; The integer division instructions `sdiv' and `udivx' have a latency
113 ;; Both integer and floating-point load instructions have a latency of
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| H A D | niagara7.md | 24 ;; up to 2 instructions are committed each cycle. Each slot serves
39 ;; Some instructions stall the pipeline and avoid any other
50 ;; Most of the instructions executing in the integer unit have a
65 ;; The integer multiplication instructions have a latency of 12 cycles
68 ;; Likewise for array*, edge* and pdistn instructions.
75 ;; The integer division instructions have a latency of 35 cycles and
83 ;; Both integer and floating-point load instructions have a latency of
102 ;; Both integer and floating-point store instructions have a latency
110 ;; Control-transfer instructions execute in the Branch Unit in the
118 ;; Many instructions executing in the Floating-point and Graphics unit
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/or1k/ |
| H A D | or1k.opt | 29 Enable generation of hardware divide (l.div, l.divu) instructions. This is the
39 Enable generation of hardware multiply instructions (l.mul, l.muli) instructions.
54 Enable generation of hardware floating point instructions. The default is
60 point instructions. By default functions from libgcc are used to perform
66 compare and set flag (lf.sfun*) instructions. By default functions from libgcc
87 Enable generation of conditional move (l.cmov) instructions. By default the
92 Enable generation of rotate right (l.ror) instructions. By default functions
97 Enable generation of rotate right with immediate (l.rori) instructions. By
103 Enable generation of sign extension (l.ext*) instructions. By default memory
108 Enable generation of compare and set flag with immediate (l.sf*i) instructions.
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/csky/ |
| H A D | csky.opt | 94 Generate C-SKY FPU double float instructions (default for hard float).
98 Generate frecipd/fsqrtd/fdivd instructions (default for hard float).
110 Enable interrupt stack instructions.
114 Enable multiprocessor instructions.
118 Enable coprocessor instructions.
122 Enable cache prefetch instructions.
126 Enable C-SKY SECURE instructions.
133 Enable C-SKY TRUST instructions.
137 Enable C-SKY DSP instructions.
141 Enable C-SKY Enhanced DSP instructions.
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARM.td | 88 "Enable VFP2 instructions with "
93 "Enable VFP2 instructions",
96 defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
100 "Enable NEON instructions",
107 defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
120 "floating point fml instructions",
125 "Enable divide instructions in Thumb">;
129 "Enable divide instructions in ARM mode">;
133 "Has data barrier (dmb/dsb) instructions">;
144 " etc) instructions">;
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| /netbsd-src/external/gpl3/binutils.old/dist/gas/doc/ |
| H A D | c-xtensa.texi | 46 @code{L32R} instructions in the text section. Literals are grouped into
48 @code{ENTRY} instructions. These options only affect literals referenced
49 via PC-relative @code{L32R} instructions; literals for absolute mode
50 @code{L32R} instructions are handled separately.
65 @code{L32R} instructions at the end. These options only affect
66 literals referenced via PC-relative @code{L32R} instructions; literals
67 for absolute mode @code{L32R} instructions are handled separately.
75 Indicate to the assembler whether @code{L32R} instructions use absolute
87 that the assembler will always align instructions like @code{LOOP} that
93 Enable or disable transformation of call instructions to allow calls
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| H A D | c-mips.texi | 29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
35 generation of MIPS ASE instructions
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
156 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent
170 provides a number of new instructions which target smartcard and
178 This tells the assembler to accept MIPS-3D instructions.
184 This tells the assembler to accept MDMX instructions.
190 This tells the assembler to accept DSP Release 1 instructions.
197 This tells the assembler to accept DSP Release 2 instructions.
204 This tells the assembler to accept DSP Release 3 instructions.
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| H A D | c-csky.texi | 61 Enable/disable transformation of the short branch instructions
72 instructions to the linker.
86 Enable/disable transformation of @code{jbsr} instructions to @code{bsr}.
99 Enable/disable transformation of @code{jsri} instructions to @code{bsr}.
106 Enable/disable transformation of @code{lrw} instructions into a
113 Enable/disable extended @code{lrw} instructions.
141 Enable/disable interrupt stack instructions. This option is enabled by
146 The following options explicitly enable certain optional instructions.
153 Enable hard float instructions.
157 Enable multiprocessor instructions.
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| /netbsd-src/external/gpl3/binutils/dist/gas/doc/ |
| H A D | c-xtensa.texi | 46 @code{L32R} instructions in the text section. Literals are grouped into
48 @code{ENTRY} instructions. These options only affect literals referenced
49 via PC-relative @code{L32R} instructions; literals for absolute mode
50 @code{L32R} instructions are handled separately.
65 @code{L32R} instructions at the end. These options only affect
66 literals referenced via PC-relative @code{L32R} instructions; literals
67 for absolute mode @code{L32R} instructions are handled separately.
75 Indicate to the assembler whether @code{L32R} instructions use absolute
87 that the assembler will always align instructions like @code{LOOP} that
93 Enable or disable transformation of call instructions to allow calls
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| H A D | c-mips.texi | 29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
35 generation of MIPS ASE instructions
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
156 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent
170 provides a number of new instructions which target smartcard and
178 This tells the assembler to accept MIPS-3D instructions.
184 This tells the assembler to accept MDMX instructions.
190 This tells the assembler to accept DSP Release 1 instructions.
197 This tells the assembler to accept DSP Release 2 instructions.
204 This tells the assembler to accept DSP Release 3 instructions.
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| H A D | c-csky.texi | 61 Enable/disable transformation of the short branch instructions
72 instructions to the linker.
86 Enable/disable transformation of @code{jbsr} instructions to @code{bsr}.
99 Enable/disable transformation of @code{jsri} instructions to @code{bsr}.
106 Enable/disable transformation of @code{lrw} instructions into a
113 Enable/disable extended @code{lrw} instructions.
141 Enable/disable interrupt stack instructions. This option is enabled by
146 The following options explicitly enable certain optional instructions.
153 Enable hard float instructions.
157 Enable multiprocessor instructions.
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | Hexagon.td | 31 "Hexagon ZReg extension instructions">;
34 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
36 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
39 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
42 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
45 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
49 "Hexagon::ArchEnum::V67", "Hexagon HVX instructions",
52 "Hexagon::ArchEnum::V68", "Hexagon HVX instructions",
57 "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
59 "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86.td | 34 "Enable X87 float instructions">;
40 "Enable conditional move instructions">;
43 "Support CMPXCHG8B instructions">;
49 "Support fxsave/fxrestore instructions">;
52 "Support xsave instructions">;
55 "Support xsaveopt instructions",
59 "Support xsavec instructions",
63 "Support xsaves instructions",
67 "Enable SSE instructions">;
69 "Enable SSE2 instructions",
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/HistoricalNotes/ |
| H A D | 2002-05-12-InstListChange.txt | 12 instructions. To iterate over instructions, we must actually iterate over
13 the instlist, and access the instructions through the instlist.
22 instructions.
24 Additionally, adding or removing instructions to a basic block
29 the instructions be represented with a doubly linked list in the
30 instructions themselves, instead of an external data structure. This is
40 Iteration over the instructions in a basic block remains the simple:
46 After converting instructions over, I'll convert basic blocks and
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredExynos.td | 16 // Check the shift in arithmetic and logic instructions.
32 // Identify arithmetic instructions without or with limited extension or shift.
60 // Identify logic instructions with limited shift.
76 // Identify more logic instructions with limited shift.
111 // Identify FP instructions.
117 // Identify 128-bit NEON instructions.
120 // Identify instructions that reset a register efficiently.
148 // Identify cheap arithmetic and logic immediate instructions.
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/spu/ |
| H A D | constraints.md | 33 …"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as …
39 …"An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32-bit valu…
44 "An immediate for and/xor/or instructions. const_int is treated as a 32-bit value."
54 …"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extend…
59 "An immediate for shift and rotate instructions. const_int is treated as a 32-bit value."
64 "An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit."
74 …"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as …
79 "An immediate for and/xor/or instructions. const_int is treated as a 64-bit value."
94 …"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is trea…
99 …"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is trea…
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