1@c Copyright (C) 1991-2022 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@ifset GENERIC 5@page 6@node MIPS-Dependent 7@chapter MIPS Dependent Features 8@end ifset 9@ifclear GENERIC 10@node Machine Dependencies 11@chapter MIPS Dependent Features 12@end ifclear 13 14@cindex MIPS processor 15@sc{gnu} @code{@value{AS}} for MIPS architectures supports several 16different MIPS processors, and MIPS ISA levels I through V, MIPS32, 17and MIPS64. For information about the MIPS instruction set, see 18@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 19For an overview of MIPS assembly conventions, see ``Appendix D: 20Assembly Language Programming'' in the same work. 21 22@menu 23* MIPS Options:: Assembler options 24* MIPS Macros:: High-level assembly macros 25* MIPS Symbol Sizes:: Directives to override the size of symbols 26* MIPS Small Data:: Controlling the use of small data accesses 27* MIPS ISA:: Directives to override the ISA level 28* MIPS assembly options:: Directives to control code generation 29* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 30* MIPS insn:: Directive to mark data as an instruction 31* MIPS FP ABIs:: Marking which FP ABI is in use 32* MIPS NaN Encodings:: Directives to record which NaN encoding is being used 33* MIPS Option Stack:: Directives to save and restore options 34* MIPS ASE Instruction Generation Overrides:: Directives to control 35 generation of MIPS ASE instructions 36* MIPS Floating-Point:: Directives to override floating-point options 37* MIPS Syntax:: MIPS specific syntactical considerations 38@end menu 39 40@node MIPS Options 41@section Assembler options 42 43The MIPS configurations of @sc{gnu} @code{@value{AS}} support these 44special options: 45 46@table @code 47@cindex @code{-G} option (MIPS) 48@item -G @var{num} 49Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes. 50@xref{MIPS Small Data,, Controlling the use of small data accesses}. 51 52@cindex @code{-EB} option (MIPS) 53@cindex @code{-EL} option (MIPS) 54@cindex MIPS big-endian output 55@cindex MIPS little-endian output 56@cindex big-endian output, MIPS 57@cindex little-endian output, MIPS 58@item -EB 59@itemx -EL 60Any MIPS configuration of @code{@value{AS}} can select big-endian or 61little-endian output at run time (unlike the other @sc{gnu} development 62tools, which must be configured for one or the other). Use @samp{-EB} 63to select big-endian output, and @samp{-EL} for little-endian. 64 65@item -KPIC 66@cindex PIC selection, MIPS 67@cindex @option{-KPIC} option, MIPS 68Generate SVR4-style PIC. This option tells the assembler to generate 69SVR4-style position-independent macro expansions. It also tells the 70assembler to mark the output file as PIC. 71 72@item -mvxworks-pic 73@cindex @option{-mvxworks-pic} option, MIPS 74Generate VxWorks PIC. This option tells the assembler to generate 75VxWorks-style position-independent macro expansions. 76 77@cindex MIPS architecture options 78@item -mips1 79@itemx -mips2 80@itemx -mips3 81@itemx -mips4 82@itemx -mips5 83@itemx -mips32 84@itemx -mips32r2 85@itemx -mips32r3 86@itemx -mips32r5 87@itemx -mips32r6 88@itemx -mips64 89@itemx -mips64r2 90@itemx -mips64r3 91@itemx -mips64r5 92@itemx -mips64r6 93Generate code for a particular MIPS Instruction Set Architecture level. 94@samp{-mips1} corresponds to the R2000 and R3000 processors, 95@samp{-mips2} to the R6000 processor, @samp{-mips3} to the 96R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. 97@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, 98@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, 99@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to 100generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 101Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 102Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, 103respectively. You can also switch instruction sets during the assembly; 104see @ref{MIPS ISA, Directives to override the ISA level}. 105 106@item -mgp32 107@itemx -mfp32 108Some macros have different expansions for 32-bit and 64-bit registers. 109The register sizes are normally inferred from the ISA and ABI, but these 110flags force a certain group of registers to be treated as 32 bits wide at 111all times. @samp{-mgp32} controls the size of general-purpose registers 112and @samp{-mfp32} controls the size of floating-point registers. 113 114The @code{.set gp=32} and @code{.set fp=32} directives allow the size 115of registers to be changed for parts of an object. The default value is 116restored by @code{.set gp=default} and @code{.set fp=default}. 117 118On some MIPS variants there is a 32-bit mode flag; when this flag is 119set, 64-bit instructions generate a trap. Also, some 32-bit OSes only 120save the 32-bit registers on a context switch, so it is essential never 121to use the 64-bit registers. 122 123@item -mgp64 124@itemx -mfp64 125Assume that 64-bit registers are available. This is provided in the 126interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. 127 128The @code{.set gp=64} and @code{.set fp=64} directives allow the size 129of registers to be changed for parts of an object. The default value is 130restored by @code{.set gp=default} and @code{.set fp=default}. 131 132@item -mfpxx 133Make no assumptions about whether 32-bit or 64-bit floating-point 134registers are available. This is provided to support having modules 135compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can 136only be used with MIPS II and above. 137 138The @code{.set fp=xx} directive allows a part of an object to be marked 139as not making assumptions about 32-bit or 64-bit FP registers. The 140default value is restored by @code{.set fp=default}. 141 142@item -modd-spreg 143@itemx -mno-odd-spreg 144Enable use of floating-point operations on odd-numbered single-precision 145registers when supported by the ISA. @samp{-mfpxx} implies 146@samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg} 147 148@item -mips16 149@itemx -no-mips16 150Generate code for the MIPS 16 processor. This is equivalent to putting 151@code{.module mips16} at the start of the assembly file. @samp{-no-mips16} 152turns off this option. 153 154@item -mmips16e2 155@itemx -mno-mips16e2 156Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent 157to putting @code{.module mips16e2} at the start of the assembly file. 158@samp{-mno-mips16e2} turns off this option. 159 160@item -mmicromips 161@itemx -mno-micromips 162Generate code for the microMIPS processor. This is equivalent to putting 163@code{.module micromips} at the start of the assembly file. 164@samp{-mno-micromips} turns off this option. This is equivalent to putting 165@code{.module nomicromips} at the start of the assembly file. 166 167@item -msmartmips 168@itemx -mno-smartmips 169Enables the SmartMIPS extensions to the MIPS32 instruction set, which 170provides a number of new instructions which target smartcard and 171cryptographic applications. This is equivalent to putting 172@code{.module smartmips} at the start of the assembly file. 173@samp{-mno-smartmips} turns off this option. 174 175@item -mips3d 176@itemx -no-mips3d 177Generate code for the MIPS-3D Application Specific Extension. 178This tells the assembler to accept MIPS-3D instructions. 179@samp{-no-mips3d} turns off this option. 180 181@item -mdmx 182@itemx -no-mdmx 183Generate code for the MDMX Application Specific Extension. 184This tells the assembler to accept MDMX instructions. 185@samp{-no-mdmx} turns off this option. 186 187@item -mdsp 188@itemx -mno-dsp 189Generate code for the DSP Release 1 Application Specific Extension. 190This tells the assembler to accept DSP Release 1 instructions. 191@samp{-mno-dsp} turns off this option. 192 193@item -mdspr2 194@itemx -mno-dspr2 195Generate code for the DSP Release 2 Application Specific Extension. 196This option implies @samp{-mdsp}. 197This tells the assembler to accept DSP Release 2 instructions. 198@samp{-mno-dspr2} turns off this option. 199 200@item -mdspr3 201@itemx -mno-dspr3 202Generate code for the DSP Release 3 Application Specific Extension. 203This option implies @samp{-mdsp} and @samp{-mdspr2}. 204This tells the assembler to accept DSP Release 3 instructions. 205@samp{-mno-dspr3} turns off this option. 206 207@item -mmt 208@itemx -mno-mt 209Generate code for the MT Application Specific Extension. 210This tells the assembler to accept MT instructions. 211@samp{-mno-mt} turns off this option. 212 213@item -mmcu 214@itemx -mno-mcu 215Generate code for the MCU Application Specific Extension. 216This tells the assembler to accept MCU instructions. 217@samp{-mno-mcu} turns off this option. 218 219@item -mmsa 220@itemx -mno-msa 221Generate code for the MIPS SIMD Architecture Extension. 222This tells the assembler to accept MSA instructions. 223@samp{-mno-msa} turns off this option. 224 225@item -mxpa 226@itemx -mno-xpa 227Generate code for the MIPS eXtended Physical Address (XPA) Extension. 228This tells the assembler to accept XPA instructions. 229@samp{-mno-xpa} turns off this option. 230 231@item -mvirt 232@itemx -mno-virt 233Generate code for the Virtualization Application Specific Extension. 234This tells the assembler to accept Virtualization instructions. 235@samp{-mno-virt} turns off this option. 236 237@item -mcrc 238@itemx -mno-crc 239Generate code for the cyclic redundancy check (CRC) Application Specific 240Extension. This tells the assembler to accept CRC instructions. 241@samp{-mno-crc} turns off this option. 242 243@item -mginv 244@itemx -mno-ginv 245Generate code for the Global INValidate (GINV) Application Specific 246Extension. This tells the assembler to accept GINV instructions. 247@samp{-mno-ginv} turns off this option. 248 249@item -mloongson-mmi 250@itemx -mno-loongson-mmi 251Generate code for the Loongson MultiMedia extensions Instructions (MMI) 252Application Specific Extension. This tells the assembler to accept MMI 253instructions. 254@samp{-mno-loongson-mmi} turns off this option. 255 256@item -mloongson-cam 257@itemx -mno-loongson-cam 258Generate code for the Loongson Content Address Memory (CAM) 259Application Specific Extension. This tells the assembler to accept CAM 260instructions. 261@samp{-mno-loongson-cam} turns off this option. 262 263@item -mloongson-ext 264@itemx -mno-loongson-ext 265Generate code for the Loongson EXTensions (EXT) instructions 266Application Specific Extension. This tells the assembler to accept EXT 267instructions. 268@samp{-mno-loongson-ext} turns off this option. 269 270@item -mloongson-ext2 271@itemx -mno-loongson-ext2 272Generate code for the Loongson EXTensions R2 (EXT2) instructions 273Application Specific Extension. This tells the assembler to accept EXT2 274instructions. 275@samp{-mno-loongson-ext2} turns off this option. 276 277@item -minsn32 278@itemx -mno-insn32 279Only use 32-bit instruction encodings when generating code for the 280microMIPS processor. This option inhibits the use of any 16-bit 281instructions. This is equivalent to putting @code{.set insn32} at 282the start of the assembly file. @samp{-mno-insn32} turns off this 283option. This is equivalent to putting @code{.set noinsn32} at the 284start of the assembly file. By default @samp{-mno-insn32} is 285selected, allowing all instructions to be used. 286 287@item -mfix7000 288@itemx -mno-fix7000 289Cause nops to be inserted if the read of the destination register 290of an mfhi or mflo instruction occurs in the following two instructions. 291 292@item -mfix-rm7000 293@itemx -mno-fix-rm7000 294Cause nops to be inserted if a dmult or dmultu instruction is 295followed by a load instruction. 296 297@item -mfix-loongson2f-jump 298@itemx -mno-fix-loongson2f-jump 299Eliminate instruction fetch from outside 256M region to work around the 300Loongson2F @samp{jump} instructions. Without it, under extreme cases, 301the kernel may crash. The issue has been solved in latest processor 302batches, but this fix has no side effect to them. 303 304@item -mfix-loongson2f-nop 305@itemx -mno-fix-loongson2f-nop 306Replace nops by @code{or at,at,zero} to work around the Loongson2F 307@samp{nop} errata. Without it, under extreme cases, the CPU might 308deadlock. The issue has been solved in later Loongson2F batches, but 309this fix has no side effect to them. 310 311@item -mfix-loongson3-llsc 312@itemx -mno-fix-loongson3-llsc 313Insert @samp{sync} before @samp{ll} and @samp{lld} to work around 314Loongson3 LLSC errata. Without it, under extrame cases, the CPU might 315deadlock. The default can be controlled by the 316@option{--enable-mips-fix-loongson3-llsc=[yes|no]} configure option. 317 318@item -mfix-vr4120 319@itemx -mno-fix-vr4120 320Insert nops to work around certain VR4120 errata. This option is 321intended to be used on GCC-generated code: it is not designed to catch 322all problems in hand-written assembler code. 323 324@item -mfix-vr4130 325@itemx -mno-fix-vr4130 326Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. 327 328@item -mfix-loongson2f-btb 329@itemx -mno-fix-loongson2f-btb 330Clear the Branch Target Buffer before any jump through a register. This 331option is intended to be used on kernel code for the Loongson 2F processor 332only; userland code compiled with this option will fault, and kernel code 333compiled with this option run on another processor than Loongson 2F will 334yield unpredictable results. 335 336@item -mfix-24k 337@itemx -mno-fix-24k 338Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. 339 340@item -mfix-cn63xxp1 341@itemx -mno-fix-cn63xxp1 342Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around 343certain CN63XXP1 errata. 344 345@item -mfix-r5900 346@itemx -mno-fix-r5900 347Do not attempt to schedule the preceding instruction into the delay slot 348of a branch instruction placed at the end of a short loop of six 349instructions or fewer and always schedule a @code{nop} instruction there 350instead. The short loop bug under certain conditions causes loops to 351execute only once or twice, due to a hardware bug in the R5900 chip. 352 353@item -m4010 354@itemx -no-m4010 355Generate code for the LSI R4010 chip. This tells the assembler to 356accept the R4010-specific instructions (@samp{addciu}, @samp{ffc}, 357etc.), and to not schedule @samp{nop} instructions around accesses to 358the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 359option. 360 361@item -m4650 362@itemx -no-m4650 363Generate code for the MIPS R4650 chip. This tells the assembler to accept 364the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 365instructions around accesses to the @samp{HI} and @samp{LO} registers. 366@samp{-no-m4650} turns off this option. 367 368@item -m3900 369@itemx -no-m3900 370@itemx -m4100 371@itemx -no-m4100 372For each option @samp{-m@var{nnnn}}, generate code for the MIPS 373R@var{nnnn} chip. This tells the assembler to accept instructions 374specific to that chip, and to schedule for that chip's hazards. 375 376@item -march=@var{cpu} 377Generate code for a particular MIPS CPU. It is exactly equivalent to 378@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 379understood. Valid @var{cpu} value are: 380 381@quotation 3822000, 3833000, 3843900, 3854000, 3864010, 3874100, 3884111, 389vr4120, 390vr4130, 391vr4181, 3924300, 3934400, 3944600, 3954650, 3965000, 397rm5200, 398rm5230, 399rm5231, 400rm5261, 401rm5721, 402vr5400, 403vr5500, 4046000, 405rm7000, 4068000, 407rm9000, 40810000, 40912000, 41014000, 41116000, 4124kc, 4134km, 4144kp, 4154ksc, 4164kec, 4174kem, 4184kep, 4194ksd, 420m4k, 421m4kp, 422m14k, 423m14kc, 424m14ke, 425m14kec, 42624kc, 42724kf2_1, 42824kf, 42924kf1_1, 43024kec, 43124kef2_1, 43224kef, 43324kef1_1, 43434kc, 43534kf2_1, 43634kf, 43734kf1_1, 43834kn, 43974kc, 44074kf2_1, 44174kf, 44274kf1_1, 44374kf3_2, 4441004kc, 4451004kf2_1, 4461004kf, 4471004kf1_1, 448interaptiv, 449interaptiv-mr2, 450m5100, 451m5101, 452p5600, 4535kc, 4545kf, 45520kc, 45625kf, 457sb1, 458sb1a, 459i6400, 460i6500, 461p6600, 462loongson2e, 463loongson2f, 464gs464, 465gs464e, 466gs264e, 467octeon, 468octeon+, 469octeon2, 470octeon3, 471xlr, 472xlp 473@end quotation 474 475For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are 476accepted as synonyms for @samp{@var{n}f1_1}. These values are 477deprecated. 478 479@item -mtune=@var{cpu} 480Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are 481identical to @samp{-march=@var{cpu}}. 482 483@item -mabi=@var{abi} 484Record which ABI the source code uses. The recognized arguments 485are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 486 487@item -msym32 488@itemx -mno-sym32 489@cindex -msym32 490@cindex -mno-sym32 491Equivalent to adding @code{.set sym32} or @code{.set nosym32} to 492the beginning of the assembler input. @xref{MIPS Symbol Sizes}. 493 494@cindex @code{-nocpp} ignored (MIPS) 495@item -nocpp 496This option is ignored. It is accepted for command-line compatibility with 497other assemblers, which use it to turn off C style preprocessing. With 498@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 499@sc{gnu} assembler itself never runs the C preprocessor. 500 501@item -msoft-float 502@itemx -mhard-float 503Disable or enable floating-point instructions. Note that by default 504floating-point instructions are always allowed even with CPU targets 505that don't have support for these instructions. 506 507@item -msingle-float 508@itemx -mdouble-float 509Disable or enable double-precision floating-point operations. Note 510that by default double-precision floating-point operations are always 511allowed even with CPU targets that don't have support for these 512operations. 513 514@item --construct-floats 515@itemx --no-construct-floats 516The @code{--no-construct-floats} option disables the construction of 517double width floating point constants by loading the two halves of the 518value into the two single width floating point registers that make up 519the double width register. This feature is useful if the processor 520support the FR bit in its status register, and this bit is known (by 521the programmer) to be set. This bit prevents the aliasing of the double 522width register by the single width registers. 523 524By default @code{--construct-floats} is selected, allowing construction 525of these floating point constants. 526 527@item --relax-branch 528@itemx --no-relax-branch 529The @samp{--relax-branch} option enables the relaxation of out-of-range 530branches. Any branches whose target cannot be reached directly are 531converted to a small instruction sequence including an inverse-condition 532branch to the physically next instruction, and a jump to the original 533target is inserted between the two instructions. In PIC code the jump 534will involve further instructions for address calculation. 535 536The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T}, 537@code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from 538relaxation, because they have no complementing counterparts. They could 539be relaxed with the use of a longer sequence involving another branch, 540however this has not been implemented and if their target turns out of 541reach, they produce an error even if branch relaxation is enabled. 542 543Also no MIPS16 branches are ever relaxed. 544 545By default @samp{--no-relax-branch} is selected, causing any out-of-range 546branches to produce an error. 547 548@item -mignore-branch-isa 549@itemx -mno-ignore-branch-isa 550Ignore branch checks for invalid transitions between ISA modes. 551 552The semantics of branches does not provide for an ISA mode switch, so in 553most cases the ISA mode a branch has been encoded for has to be the same 554as the ISA mode of the branch's target label. If the ISA modes do not 555match, then such a branch, if taken, will cause the ISA mode to remain 556unchanged and instructions that follow will be executed in the wrong ISA 557mode causing the program to misbehave or crash. 558 559In the case of the @code{BAL} instruction it may be possible to relax 560it to an equivalent @code{JALX} instruction so that the ISA mode is 561switched at the run time as required. For other branches no relaxation 562is possible and therefore GAS has checks implemented that verify in 563branch assembly that the two ISA modes match, and report an error 564otherwise so that the problem with code can be diagnosed at the assembly 565time rather than at the run time. 566 567However some assembly code, including generated code produced by some 568versions of GCC, may incorrectly include branches to data labels, which 569appear to require a mode switch but are either dead or immediately 570followed by valid instructions encoded for the same ISA the branch has 571been encoded for. While not strictly correct at the source level such 572code will execute as intended, so to help with these cases 573@samp{-mignore-branch-isa} is supported which disables ISA mode checks 574for branches. 575 576By default @samp{-mno-ignore-branch-isa} is selected, causing any invalid 577branch requiring a transition between ISA modes to produce an error. 578 579@cindex @option{-mnan=} command-line option, MIPS 580@item -mnan=@var{encoding} 581This option indicates whether the source code uses the IEEE 2008 582NaN encoding (@option{-mnan=2008}) or the original MIPS encoding 583(@option{-mnan=legacy}). It is equivalent to adding a @code{.nan} 584directive to the beginning of the source file. @xref{MIPS NaN Encodings}. 585 586@option{-mnan=legacy} is the default if no @option{-mnan} option or 587@code{.nan} directive is used. 588 589@item --trap 590@itemx --no-break 591@c FIXME! (1) reflect these options (next item too) in option summaries; 592@c (2) stop teasing, say _which_ instructions expanded _how_. 593@code{@value{AS}} automatically macro expands certain division and 594multiplication instructions to check for overflow and division by zero. This 595option causes @code{@value{AS}} to generate code to take a trap exception 596rather than a break exception when an error is detected. The trap instructions 597are only supported at Instruction Set Architecture level 2 and higher. 598 599@item --break 600@itemx --no-trap 601Generate code to take a break exception rather than a trap exception when an 602error is detected. This is the default. 603 604@item -mpdr 605@itemx -mno-pdr 606Control generation of @code{.pdr} sections. Off by default on IRIX, on 607elsewhere. 608 609@item -mshared 610@itemx -mno-shared 611When generating code using the Unix calling conventions (selected by 612@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code 613which can go into a shared library. The @samp{-mno-shared} option 614tells gas to generate code which uses the calling convention, but can 615not go into a shared library. The resulting code is slightly more 616efficient. This option only affects the handling of the 617@samp{.cpload} and @samp{.cpsetup} pseudo-ops. 618@end table 619 620@node MIPS Macros 621@section High-level assembly macros 622 623MIPS assemblers have traditionally provided a wider range of 624instructions than the MIPS architecture itself. These extra 625instructions are usually referred to as ``macro'' instructions 626@footnote{The term ``macro'' is somewhat overloaded here, since 627these macros have no relation to those defined by @code{.macro}, 628@pxref{Macro,, @code{.macro}}.}. 629 630Some MIPS macro instructions extend an underlying architectural instruction 631while others are entirely new. An example of the former type is @code{and}, 632which allows the third operand to be either a register or an arbitrary 633immediate value. Examples of the latter type include @code{bgt}, which 634branches to the third operand when the first operand is greater than 635the second operand, and @code{ulh}, which implements an unaligned 6362-byte load. 637 638One of the most common extensions provided by macros is to expand 639memory offsets to the full address range (32 or 64 bits) and to allow 640symbolic offsets such as @samp{my_data + 4} to be used in place of 641integer constants. For example, the architectural instruction 642@code{lbu} allows only a signed 16-bit offset, whereas the macro 643@code{lbu} allows code such as @samp{lbu $4,array+32769($5)}. 644The implementation of these symbolic offsets depends on several factors, 645such as whether the assembler is generating SVR4-style PIC (selected by 646@option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols 647(@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}), 648and the small data limit (@pxref{MIPS Small Data,, Controlling the use 649of small data accesses}). 650 651@kindex @code{.set macro} 652@kindex @code{.set nomacro} 653Sometimes it is undesirable to have one assembly instruction expand 654to several machine instructions. The directive @code{.set nomacro} 655tells the assembler to warn when this happens. @code{.set macro} 656restores the default behavior. 657 658@cindex @code{at} register, MIPS 659@kindex @code{.set at=@var{reg}} 660Some macro instructions need a temporary register to store intermediate 661results. This register is usually @code{$1}, also known as @code{$at}, 662but it can be changed to any core register @var{reg} using 663@code{.set at=@var{reg}}. Note that @code{$at} always refers 664to @code{$1} regardless of which register is being used as the 665temporary register. 666 667@kindex @code{.set at} 668@kindex @code{.set noat} 669Implicit uses of the temporary register in macros could interfere with 670explicit uses in the assembly code. The assembler therefore warns 671whenever it sees an explicit use of the temporary register. The directive 672@code{.set noat} silences this warning while @code{.set at} restores 673the default behavior. It is safe to use @code{.set noat} while 674@code{.set nomacro} is in effect since single-instruction macros 675never need a temporary register. 676 677Note that while the @sc{gnu} assembler provides these macros for compatibility, 678it does not make any attempt to optimize them with the surrounding code. 679 680@node MIPS Symbol Sizes 681@section Directives to override the size of symbols 682 683@kindex @code{.set sym32} 684@kindex @code{.set nosym32} 685The n64 ABI allows symbols to have any 64-bit value. Although this 686provides a great deal of flexibility, it means that some macros have 687much longer expansions than their 32-bit counterparts. For example, 688the non-PIC expansion of @samp{dla $4,sym} is usually: 689 690@smallexample 691lui $4,%highest(sym) 692lui $1,%hi(sym) 693daddiu $4,$4,%higher(sym) 694daddiu $1,$1,%lo(sym) 695dsll32 $4,$4,0 696daddu $4,$4,$1 697@end smallexample 698 699whereas the 32-bit expansion is simply: 700 701@smallexample 702lui $4,%hi(sym) 703daddiu $4,$4,%lo(sym) 704@end smallexample 705 706n64 code is sometimes constructed in such a way that all symbolic 707constants are known to have 32-bit values, and in such cases, it's 708preferable to use the 32-bit expansion instead of the 64-bit 709expansion. 710 711You can use the @code{.set sym32} directive to tell the assembler 712that, from this point on, all expressions of the form 713@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} 714have 32-bit values. For example: 715 716@smallexample 717.set sym32 718dla $4,sym 719lw $4,sym+16 720sw $4,sym+0x8000($4) 721@end smallexample 722 723will cause the assembler to treat @samp{sym}, @code{sym+16} and 724@code{sym+0x8000} as 32-bit values. The handling of non-symbolic 725addresses is not affected. 726 727The directive @code{.set nosym32} ends a @code{.set sym32} block and 728reverts to the normal behavior. It is also possible to change the 729symbol size using the command-line options @option{-msym32} and 730@option{-mno-sym32}. 731 732These options and directives are always accepted, but at present, 733they have no effect for anything other than n64. 734 735@node MIPS Small Data 736@section Controlling the use of small data accesses 737 738@c This section deliberately glosses over the possibility of using -G 739@c in SVR4-style PIC, as could be done on IRIX. We don't support that. 740@cindex small data, MIPS 741@cindex @code{gp} register, MIPS 742It often takes several instructions to load the address of a symbol. 743For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion 744of @samp{dla $4,addr} is usually: 745 746@smallexample 747lui $4,%hi(addr) 748daddiu $4,$4,%lo(addr) 749@end smallexample 750 751The sequence is much longer when @samp{addr} is a 64-bit symbol. 752@xref{MIPS Symbol Sizes,, Directives to override the size of symbols}. 753 754In order to cut down on this overhead, most embedded MIPS systems 755set aside a 64-kilobyte ``small data'' area and guarantee that all 756data of size @var{n} and smaller will be placed in that area. 757The limit @var{n} is passed to both the assembler and the linker 758using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,, 759Assembler options}. Note that the same value of @var{n} must be used 760when linking and when assembling all input files to the link; any 761inconsistency could cause a relocation overflow error. 762 763The size of an object in the @code{.bss} section is set by the 764@code{.comm} or @code{.lcomm} directive that defines it. The size of 765an external object may be set with the @code{.extern} directive. For 766example, @samp{.extern sym,4} declares that the object at @code{sym} 767is 4 bytes in length, while leaving @code{sym} otherwise undefined. 768 769When no @option{-G} option is given, the default limit is 8 bytes. 770The option @option{-G 0} prevents any data from being automatically 771classified as small. 772 773It is also possible to mark specific objects as small by putting them 774in the special sections @code{.sdata} and @code{.sbss}, which are 775``small'' counterparts of @code{.data} and @code{.bss} respectively. 776The toolchain will treat such data as small regardless of the 777@option{-G} setting. 778 779On startup, systems that support a small data area are expected to 780initialize register @code{$28}, also known as @code{$gp}, in such a 781way that small data can be accessed using a 16-bit offset from that 782register. For example, when @samp{addr} is small data, 783the @samp{dla $4,addr} instruction above is equivalent to: 784 785@smallexample 786daddiu $4,$28,%gp_rel(addr) 787@end smallexample 788 789Small data is not supported for SVR4-style PIC. 790 791@node MIPS ISA 792@section Directives to override the ISA level 793 794@cindex MIPS ISA override 795@kindex @code{.set mips@var{n}} 796@sc{gnu} @code{@value{AS}} supports an additional directive to change 797the MIPS Instruction Set Architecture level on the fly: @code{.set 798mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, 79932r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. 800The values other than 0 make the assembler accept instructions 801for the corresponding ISA level, from that point on in the 802assembly. @code{.set mips@var{n}} affects not only which instructions 803are permitted, but also how certain macros are expanded. @code{.set 804mips0} restores the ISA level to its original level: either the 805level you selected with command-line options, or the default for your 806configuration. You can use this feature to permit specific MIPS III 807instructions while assembling in 32 bit mode. Use this directive with 808care! 809 810@cindex MIPS CPU override 811@kindex @code{.set arch=@var{cpu}} 812The @code{.set arch=@var{cpu}} directive provides even finer control. 813It changes the effective CPU target and allows the assembler to use 814instructions specific to a particular CPU. All CPUs supported by the 815@samp{-march} command-line option are also selectable by this directive. 816The original value is restored by @code{.set arch=default}. 817 818The directive @code{.set mips16} puts the assembler into MIPS 16 mode, 819in which it will assemble instructions for the MIPS 16 processor. Use 820@code{.set nomips16} to return to normal 32 bit mode. 821 822Traditional MIPS assemblers do not support this directive. 823 824The directive @code{.set micromips} puts the assembler into microMIPS mode, 825in which it will assemble instructions for the microMIPS processor. Use 826@code{.set nomicromips} to return to normal 32 bit mode. 827 828Traditional MIPS assemblers do not support this directive. 829 830@node MIPS assembly options 831@section Directives to control code generation 832 833@cindex MIPS directives to override command-line options 834@kindex @code{.module} 835The @code{.module} directive allows command-line options to be set directly 836from assembly. The format of the directive matches the @code{.set} 837directive but only those options which are relevant to a whole module are 838supported. The effect of a @code{.module} directive is the same as the 839corresponding command-line option. Where @code{.set} directives support 840returning to a default then the @code{.module} directives do not as they 841define the defaults. 842 843These module-level directives must appear first in assembly. 844 845Traditional MIPS assemblers do not support this directive. 846 847@cindex MIPS 32-bit microMIPS instruction generation override 848@kindex @code{.set insn32} 849@kindex @code{.set noinsn32} 850The directive @code{.set insn32} makes the assembler only use 32-bit 851instruction encodings when generating code for the microMIPS processor. 852This directive inhibits the use of any 16-bit instructions from that 853point on in the assembly. The @code{.set noinsn32} directive allows 85416-bit instructions to be accepted. 855 856Traditional MIPS assemblers do not support this directive. 857 858@node MIPS autoextend 859@section Directives for extending MIPS 16 bit instructions 860 861@kindex @code{.set autoextend} 862@kindex @code{.set noautoextend} 863By default, MIPS 16 instructions are automatically extended to 32 bits 864when necessary. The directive @code{.set noautoextend} will turn this 865off. When @code{.set noautoextend} is in effect, any 32 bit instruction 866must be explicitly extended with the @code{.e} modifier (e.g., 867@code{li.e $4,1000}). The directive @code{.set autoextend} may be used 868to once again automatically extend instructions when necessary. 869 870This directive is only meaningful when in MIPS 16 mode. Traditional 871MIPS assemblers do not support this directive. 872 873@node MIPS insn 874@section Directive to mark data as an instruction 875 876@kindex @code{.insn} 877The @code{.insn} directive tells @code{@value{AS}} that the following 878data is actually instructions. This makes a difference in MIPS 16 and 879microMIPS modes: when loading the address of a label which precedes 880instructions, @code{@value{AS}} automatically adds 1 to the value, so 881that jumping to the loaded address will do the right thing. 882 883@kindex @code{.global} 884The @code{.global} and @code{.globl} directives supported by 885@code{@value{AS}} will by default mark the symbol as pointing to a 886region of data not code. This means that, for example, any 887instructions following such a symbol will not be disassembled by 888@code{objdump} as it will regard them as data. To change this 889behavior an optional section name can be placed after the symbol name 890in the @code{.global} directive. If this section exists and is known 891to be a code section, then the symbol will be marked as pointing at 892code not data. Ie the syntax for the directive is: 893 894 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, 895 896Here is a short example: 897 898@example 899 .global foo .text, bar, baz .data 900foo: 901 nop 902bar: 903 .word 0x0 904baz: 905 .word 0x1 906 907@end example 908 909@node MIPS FP ABIs 910@section Directives to control the FP ABI 911@menu 912* MIPS FP ABI History:: History of FP ABIs 913* MIPS FP ABI Variants:: Supported FP ABIs 914* MIPS FP ABI Selection:: Automatic selection of FP ABI 915* MIPS FP ABI Compatibility:: Linking different FP ABI variants 916@end menu 917 918@node MIPS FP ABI History 919@subsection History of FP ABIs 920@cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS 921@cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS 922The MIPS ABIs support a variety of different floating-point extensions 923where calling-convention and register sizes vary for floating-point data. 924The extensions exist to support a wide variety of optional architecture 925features. The resulting ABI variants are generally incompatible with each 926other and must be tracked carefully. 927 928Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} 929directive is used to indicate which ABI is in use by a specific module. 930It was then left to the user to ensure that command-line options and the 931selected ABI were compatible with some potential for inconsistencies. 932 933@node MIPS FP ABI Variants 934@subsection Supported FP ABIs 935The supported floating-point ABI variants are: 936 937@table @code 938@item 0 - No floating-point 939This variant is used to indicate that floating-point is not used within 940the module at all and therefore has no impact on the ABI. This is the 941default. 942 943@item 1 - Double-precision 944This variant indicates that double-precision support is used. For 64-bit 945ABIs this means that 64-bit wide floating-point registers are required. 946For 32-bit ABIs this means that 32-bit wide floating-point registers are 947required and double-precision operations use pairs of registers. 948 949@item 2 - Single-precision 950This variant indicates that single-precision support is used. Double 951precision operations will be supported via soft-float routines. 952 953@item 3 - Soft-float 954This variant indicates that although floating-point support is used all 955operations are emulated in software. This means the ABI is modified to 956pass all floating-point data in general-purpose registers. 957 958@item 4 - Deprecated 959This variant existed as an initial attempt at supporting 64-bit wide 960floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been 961superseded by 5, 6 and 7. 962 963@item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU 964This variant is used by 32-bit ABIs to indicate that the floating-point 965code in the module has been designed to operate correctly with either 96632-bit wide or 64-bit wide floating-point registers. Double-precision 967support is used. Only O32 currently supports this variant and requires 968a minimum architecture of MIPS II. 969 970@item 6 - Double-precision 32-bit FPU, 64-bit FPU 971This variant is used by 32-bit ABIs to indicate that the floating-point 972code in the module requires 64-bit wide floating-point registers. 973Double-precision support is used. Only O32 currently supports this 974variant and requires a minimum architecture of MIPS32r2. 975 976@item 7 - Double-precision compat 32-bit FPU, 64-bit FPU 977This variant is used by 32-bit ABIs to indicate that the floating-point 978code in the module requires 64-bit wide floating-point registers. 979Double-precision support is used. This differs from the previous ABI 980as it restricts use of odd-numbered single-precision registers. Only 981O32 currently supports this variant and requires a minimum architecture 982of MIPS32r2. 983@end table 984 985@node MIPS FP ABI Selection 986@subsection Automatic selection of FP ABI 987@cindex @code{.module fp=@var{nn}} directive, MIPS 988In order to simplify and add safety to the process of selecting the 989correct floating-point ABI, the assembler will automatically infer the 990correct @code{.gnu_attribute 4, @var{n}} directive based on command-line 991options and @code{.module} overrides. Where an explicit 992@code{.gnu_attribute 4, @var{n}} directive has been seen then a warning 993will be raised if it does not match an inferred setting. 994 995The floating-point ABI is inferred as follows. If @samp{-msoft-float} 996has been used the module will be marked as soft-float. If 997@samp{-msingle-float} has been used then the module will be marked as 998single-precision. The remaining ABIs are then selected based 999on the FP register width. Double-precision is selected if the width 1000of GP and FP registers match and the special double-precision variants 1001for 32-bit ABIs are then selected depending on @samp{-mfpxx}, 1002@samp{-mfp64} and @samp{-mno-odd-spreg}. 1003 1004@node MIPS FP ABI Compatibility 1005@subsection Linking different FP ABI variants 1006Modules using the default FP ABI (no floating-point) can be linked with 1007any other (singular) FP ABI variant. 1008 1009Special compatibility support exists for O32 with the four 1010double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically 1011designed to be compatible with the standard double-precision ABI and the 1012@samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be 1013built as @samp{-mfpxx} to ensure the maximum compatibility with other 1014modules produced for more specific needs. The only FP ABIs which cannot 1015be linked together are the standard double-precision ABI and the full 1016@samp{-mfp64} ABI with @samp{-modd-spreg}. 1017 1018@node MIPS NaN Encodings 1019@section Directives to record which NaN encoding is being used 1020 1021@cindex MIPS IEEE 754 NaN data encoding selection 1022@cindex @code{.nan} directive, MIPS 1023The IEEE 754 floating-point standard defines two types of not-a-number 1024(NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version 1025of the standard did not specify how these two types should be 1026distinguished. Most implementations followed the i387 model, in which 1027the first bit of the significand is set for quiet NaNs and clear for 1028signalling NaNs. However, the original MIPS implementation assigned the 1029opposite meaning to the bit, so that it was set for signalling NaNs and 1030clear for quiet NaNs. 1031 1032The 2008 revision of the standard formally suggested the i387 choice 1033and as from Sep 2012 the current release of the MIPS architecture 1034therefore optionally supports that form. Code that uses one NaN encoding 1035would usually be incompatible with code that uses the other NaN encoding, 1036so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which 1037encoding is being used. 1038 1039Assembly files can use the @code{.nan} directive to select between the 1040two encodings. @samp{.nan 2008} says that the assembly file uses the 1041IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses 1042the original MIPS encoding. If several @code{.nan} directives are given, 1043the final setting is the one that is used. 1044 1045The command-line options @option{-mnan=legacy} and @option{-mnan=2008} 1046can be used instead of @samp{.nan legacy} and @samp{.nan 2008} 1047respectively. However, any @code{.nan} directive overrides the 1048command-line setting. 1049 1050@samp{.nan legacy} is the default if no @code{.nan} directive or 1051@option{-mnan} option is given. 1052 1053Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and 1054therefore these directives do not affect code generation. They simply 1055control the setting of the @code{EF_MIPS_NAN2008} flag. 1056 1057Traditional MIPS assemblers do not support these directives. 1058 1059@node MIPS Option Stack 1060@section Directives to save and restore options 1061 1062@cindex MIPS option stack 1063@kindex @code{.set push} 1064@kindex @code{.set pop} 1065The directives @code{.set push} and @code{.set pop} may be used to save 1066and restore the current settings for all the options which are 1067controlled by @code{.set}. The @code{.set push} directive saves the 1068current settings on a stack. The @code{.set pop} directive pops the 1069stack and restores the settings. 1070 1071These directives can be useful inside an macro which must change an 1072option such as the ISA level or instruction reordering but does not want 1073to change the state of the code which invoked the macro. 1074 1075Traditional MIPS assemblers do not support these directives. 1076 1077@node MIPS ASE Instruction Generation Overrides 1078@section Directives to control generation of MIPS ASE instructions 1079 1080@cindex MIPS MIPS-3D instruction generation override 1081@kindex @code{.set mips3d} 1082@kindex @code{.set nomips3d} 1083The directive @code{.set mips3d} makes the assembler accept instructions 1084from the MIPS-3D Application Specific Extension from that point on 1085in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 1086instructions from being accepted. 1087 1088@cindex SmartMIPS instruction generation override 1089@kindex @code{.set smartmips} 1090@kindex @code{.set nosmartmips} 1091The directive @code{.set smartmips} makes the assembler accept 1092instructions from the SmartMIPS Application Specific Extension to the 1093MIPS32 ISA from that point on in the assembly. The 1094@code{.set nosmartmips} directive prevents SmartMIPS instructions from 1095being accepted. 1096 1097@cindex MIPS MDMX instruction generation override 1098@kindex @code{.set mdmx} 1099@kindex @code{.set nomdmx} 1100The directive @code{.set mdmx} makes the assembler accept instructions 1101from the MDMX Application Specific Extension from that point on 1102in the assembly. The @code{.set nomdmx} directive prevents MDMX 1103instructions from being accepted. 1104 1105@cindex MIPS DSP Release 1 instruction generation override 1106@kindex @code{.set dsp} 1107@kindex @code{.set nodsp} 1108The directive @code{.set dsp} makes the assembler accept instructions 1109from the DSP Release 1 Application Specific Extension from that point 1110on in the assembly. The @code{.set nodsp} directive prevents DSP 1111Release 1 instructions from being accepted. 1112 1113@cindex MIPS DSP Release 2 instruction generation override 1114@kindex @code{.set dspr2} 1115@kindex @code{.set nodspr2} 1116The directive @code{.set dspr2} makes the assembler accept instructions 1117from the DSP Release 2 Application Specific Extension from that point 1118on in the assembly. This directive implies @code{.set dsp}. The 1119@code{.set nodspr2} directive prevents DSP Release 2 instructions from 1120being accepted. 1121 1122@cindex MIPS DSP Release 3 instruction generation override 1123@kindex @code{.set dspr3} 1124@kindex @code{.set nodspr3} 1125The directive @code{.set dspr3} makes the assembler accept instructions 1126from the DSP Release 3 Application Specific Extension from that point 1127on in the assembly. This directive implies @code{.set dsp} and 1128@code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP 1129Release 3 instructions from being accepted. 1130 1131@cindex MIPS MT instruction generation override 1132@kindex @code{.set mt} 1133@kindex @code{.set nomt} 1134The directive @code{.set mt} makes the assembler accept instructions 1135from the MT Application Specific Extension from that point on 1136in the assembly. The @code{.set nomt} directive prevents MT 1137instructions from being accepted. 1138 1139@cindex MIPS MCU instruction generation override 1140@kindex @code{.set mcu} 1141@kindex @code{.set nomcu} 1142The directive @code{.set mcu} makes the assembler accept instructions 1143from the MCU Application Specific Extension from that point on 1144in the assembly. The @code{.set nomcu} directive prevents MCU 1145instructions from being accepted. 1146 1147@cindex MIPS SIMD Architecture instruction generation override 1148@kindex @code{.set msa} 1149@kindex @code{.set nomsa} 1150The directive @code{.set msa} makes the assembler accept instructions 1151from the MIPS SIMD Architecture Extension from that point on 1152in the assembly. The @code{.set nomsa} directive prevents MSA 1153instructions from being accepted. 1154 1155@cindex Virtualization instruction generation override 1156@kindex @code{.set virt} 1157@kindex @code{.set novirt} 1158The directive @code{.set virt} makes the assembler accept instructions 1159from the Virtualization Application Specific Extension from that point 1160on in the assembly. The @code{.set novirt} directive prevents Virtualization 1161instructions from being accepted. 1162 1163@cindex MIPS eXtended Physical Address (XPA) instruction generation override 1164@kindex @code{.set xpa} 1165@kindex @code{.set noxpa} 1166The directive @code{.set xpa} makes the assembler accept instructions 1167from the XPA Extension from that point on in the assembly. The 1168@code{.set noxpa} directive prevents XPA instructions from being accepted. 1169 1170@cindex MIPS16e2 instruction generation override 1171@kindex @code{.set mips16e2} 1172@kindex @code{.set nomips16e2} 1173The directive @code{.set mips16e2} makes the assembler accept instructions 1174from the MIPS16e2 Application Specific Extension from that point on in the 1175assembly, whenever in MIPS16 mode. The @code{.set nomips16e2} directive 1176prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither 1177directive affects the state of MIPS16 mode being active itself which has 1178separate controls. 1179 1180@cindex MIPS cyclic redundancy check (CRC) instruction generation override 1181@kindex @code{.set crc} 1182@kindex @code{.set nocrc} 1183The directive @code{.set crc} makes the assembler accept instructions 1184from the CRC Extension from that point on in the assembly. The 1185@code{.set nocrc} directive prevents CRC instructions from being accepted. 1186 1187@cindex MIPS Global INValidate (GINV) instruction generation override 1188@kindex @code{.set ginv} 1189@kindex @code{.set noginv} 1190The directive @code{.set ginv} makes the assembler accept instructions 1191from the GINV Extension from that point on in the assembly. The 1192@code{.set noginv} directive prevents GINV instructions from being accepted. 1193 1194@cindex Loongson MultiMedia extensions Instructions (MMI) generation override 1195@kindex @code{.set loongson-mmi} 1196@kindex @code{.set noloongson-mmi} 1197The directive @code{.set loongson-mmi} makes the assembler accept 1198instructions from the MMI Extension from that point on in the assembly. 1199The @code{.set noloongson-mmi} directive prevents MMI instructions from 1200being accepted. 1201 1202@cindex Loongson Content Address Memory (CAM) generation override 1203@kindex @code{.set loongson-cam} 1204@kindex @code{.set noloongson-cam} 1205The directive @code{.set loongson-cam} makes the assembler accept 1206instructions from the Loongson CAM from that point on in the assembly. 1207The @code{.set noloongson-cam} directive prevents Loongson CAM instructions 1208from being accepted. 1209 1210@cindex Loongson EXTensions (EXT) instructions generation override 1211@kindex @code{.set loongson-ext} 1212@kindex @code{.set noloongson-ext} 1213The directive @code{.set loongson-ext} makes the assembler accept 1214instructions from the Loongson EXT from that point on in the assembly. 1215The @code{.set noloongson-ext} directive prevents Loongson EXT instructions 1216from being accepted. 1217 1218@cindex Loongson EXTensions R2 (EXT2) instructions generation override 1219@kindex @code{.set loongson-ext2} 1220@kindex @code{.set noloongson-ext2} 1221The directive @code{.set loongson-ext2} makes the assembler accept 1222instructions from the Loongson EXT2 from that point on in the assembly. 1223This directive implies @code{.set loognson-ext}. 1224The @code{.set noloongson-ext2} directive prevents Loongson EXT2 instructions 1225from being accepted. 1226 1227Traditional MIPS assemblers do not support these directives. 1228 1229@node MIPS Floating-Point 1230@section Directives to override floating-point options 1231 1232@cindex Disable floating-point instructions 1233@kindex @code{.set softfloat} 1234@kindex @code{.set hardfloat} 1235The directives @code{.set softfloat} and @code{.set hardfloat} provide 1236finer control of disabling and enabling float-point instructions. 1237These directives always override the default (that hard-float 1238instructions are accepted) or the command-line options 1239(@samp{-msoft-float} and @samp{-mhard-float}). 1240 1241@cindex Disable single-precision floating-point operations 1242@kindex @code{.set singlefloat} 1243@kindex @code{.set doublefloat} 1244The directives @code{.set singlefloat} and @code{.set doublefloat} 1245provide finer control of disabling and enabling double-precision 1246float-point operations. These directives always override the default 1247(that double-precision operations are accepted) or the command-line 1248options (@samp{-msingle-float} and @samp{-mdouble-float}). 1249 1250Traditional MIPS assemblers do not support these directives. 1251 1252@node MIPS Syntax 1253@section Syntactical considerations for the MIPS assembler 1254@menu 1255* MIPS-Chars:: Special Characters 1256@end menu 1257 1258@node MIPS-Chars 1259@subsection Special Characters 1260 1261@cindex line comment character, MIPS 1262@cindex MIPS line comment character 1263The presence of a @samp{#} on a line indicates the start of a comment 1264that extends to the end of the current line. 1265 1266If a @samp{#} appears as the first character of a line, the whole line 1267is treated as a comment, but in this case the line can also be a 1268logical line number directive (@pxref{Comments}) or a 1269preprocessor control command (@pxref{Preprocessing}). 1270 1271@cindex line separator, MIPS 1272@cindex statement separator, MIPS 1273@cindex MIPS line separator 1274The @samp{;} character can be used to separate statements on the same 1275line. 1276