1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is a target description file for the Intel i386 architecture, referred 10// to here as the "X86" architecture. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing... 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// X86 Subtarget state 20// 21 22def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", 23 "64-bit mode (x86_64)">; 24def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", 25 "32-bit mode (80386)">; 26def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", 27 "16-bit mode (i8086)">; 28 29//===----------------------------------------------------------------------===// 30// X86 Subtarget features 31//===----------------------------------------------------------------------===// 32 33def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", 34 "Enable X87 float instructions">; 35 36def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true", 37 "Enable NOPL instruction">; 38 39def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 40 "Enable conditional move instructions">; 41 42def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true", 43 "Support CMPXCHG8B instructions">; 44 45def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", 46 "Support POPCNT instruction">; 47 48def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", 49 "Support fxsave/fxrestore instructions">; 50 51def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", 52 "Support xsave instructions">; 53 54def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", 55 "Support xsaveopt instructions", 56 [FeatureXSAVE]>; 57 58def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", 59 "Support xsavec instructions", 60 [FeatureXSAVE]>; 61 62def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", 63 "Support xsaves instructions", 64 [FeatureXSAVE]>; 65 66def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 67 "Enable SSE instructions">; 68def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 69 "Enable SSE2 instructions", 70 [FeatureSSE1]>; 71def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 72 "Enable SSE3 instructions", 73 [FeatureSSE2]>; 74def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 75 "Enable SSSE3 instructions", 76 [FeatureSSE3]>; 77def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", 78 "Enable SSE 4.1 instructions", 79 [FeatureSSSE3]>; 80def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", 81 "Enable SSE 4.2 instructions", 82 [FeatureSSE41]>; 83// The MMX subtarget feature is separate from the rest of the SSE features 84// because it's important (for odd compatibility reasons) to be able to 85// turn it off explicitly while allowing SSE+ to be on. 86def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", 87 "Enable MMX instructions">; 88def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 89 "Enable 3DNow! instructions", 90 [FeatureMMX]>; 91def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 92 "Enable 3DNow! Athlon instructions", 93 [Feature3DNow]>; 94// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 95// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 96// without disabling 64-bit mode. Nothing should imply this feature bit. It 97// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode. 98def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 99 "Support 64-bit instructions">; 100def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", 101 "64-bit with cmpxchg16b", 102 [FeatureCMPXCHG8B]>; 103def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", 104 "SHLD instruction is slow">; 105def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", 106 "PMULLD instruction is slow">; 107def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow", 108 "true", 109 "PMADDWD is slower than PMULLD">; 110// FIXME: This should not apply to CPUs that do not have SSE. 111def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", 112 "IsUAMem16Slow", "true", 113 "Slow unaligned 16-byte memory access">; 114def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", 115 "IsUAMem32Slow", "true", 116 "Slow unaligned 32-byte memory access">; 117def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 118 "Support SSE 4a instructions", 119 [FeatureSSE3]>; 120 121def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", 122 "Enable AVX instructions", 123 [FeatureSSE42]>; 124def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", 125 "Enable AVX2 instructions", 126 [FeatureAVX]>; 127def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", 128 "Enable three-operand fused multiple-add", 129 [FeatureAVX]>; 130def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", 131 "Support 16-bit floating point conversion instructions", 132 [FeatureAVX]>; 133def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", 134 "Enable AVX-512 instructions", 135 [FeatureAVX2, FeatureFMA, FeatureF16C]>; 136def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", 137 "Enable AVX-512 Exponential and Reciprocal Instructions", 138 [FeatureAVX512]>; 139def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", 140 "Enable AVX-512 Conflict Detection Instructions", 141 [FeatureAVX512]>; 142def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ", 143 "true", "Enable AVX-512 Population Count Instructions", 144 [FeatureAVX512]>; 145def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", 146 "Enable AVX-512 PreFetch Instructions", 147 [FeatureAVX512]>; 148def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1", 149 "true", 150 "Prefetch with Intent to Write and T1 Hint">; 151def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", 152 "Enable AVX-512 Doubleword and Quadword Instructions", 153 [FeatureAVX512]>; 154def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", 155 "Enable AVX-512 Byte and Word Instructions", 156 [FeatureAVX512]>; 157def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", 158 "Enable AVX-512 Vector Length eXtensions", 159 [FeatureAVX512]>; 160def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", 161 "Enable AVX-512 Vector Byte Manipulation Instructions", 162 [FeatureBWI]>; 163def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true", 164 "Enable AVX-512 further Vector Byte Manipulation Instructions", 165 [FeatureBWI]>; 166def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", 167 "Enable AVX-512 Integer Fused Multiple-Add", 168 [FeatureAVX512]>; 169def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", 170 "Enable protection keys">; 171def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", 172 "Enable AVX-512 Vector Neural Network Instructions", 173 [FeatureAVX512]>; 174def FeatureAVXVNNI : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true", 175 "Support AVX_VNNI encoding", 176 [FeatureAVX2]>; 177def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true", 178 "Support bfloat16 floating point", 179 [FeatureBWI]>; 180def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true", 181 "Enable AVX-512 Bit Algorithms", 182 [FeatureBWI]>; 183def FeatureVP2INTERSECT : SubtargetFeature<"avx512vp2intersect", 184 "HasVP2INTERSECT", "true", 185 "Enable AVX-512 vp2intersect", 186 [FeatureAVX512]>; 187def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", 188 "Enable packed carry-less multiplication instructions", 189 [FeatureSSE2]>; 190def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true", 191 "Enable Galois Field Arithmetic Instructions", 192 [FeatureSSE2]>; 193def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true", 194 "Enable vpclmulqdq instructions", 195 [FeatureAVX, FeaturePCLMUL]>; 196def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 197 "Enable four-operand fused multiple-add", 198 [FeatureAVX, FeatureSSE4A]>; 199def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", 200 "Enable XOP instructions", 201 [FeatureFMA4]>; 202def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", 203 "HasSSEUnalignedMem", "true", 204 "Allow unaligned memory operands with SSE instructions">; 205def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 206 "Enable AES instructions", 207 [FeatureSSE2]>; 208def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", 209 "Promote selected AES instructions to AVX512/AVX registers", 210 [FeatureAVX, FeatureAES]>; 211def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", 212 "Enable TBM instructions">; 213def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", 214 "Enable LWP instructions">; 215def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", 216 "Support MOVBE instruction">; 217def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", 218 "Support RDRAND instruction">; 219def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", 220 "Support FS/GS Base instructions">; 221def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", 222 "Support LZCNT instruction">; 223def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", 224 "Support BMI instructions">; 225def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", 226 "Support BMI2 instructions">; 227def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", 228 "Support RTM instructions">; 229def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", 230 "Support ADX instructions">; 231def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", 232 "Enable SHA instructions", 233 [FeatureSSE2]>; 234def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", 235 "Support CET Shadow-Stack instructions">; 236def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", 237 "Support PRFCHW instructions">; 238def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", 239 "Support RDSEED instruction">; 240def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true", 241 "Support LAHF and SAHF instructions in 64-bit mode">; 242def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", 243 "Enable MONITORX/MWAITX timer functionality">; 244def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", 245 "Enable Cache Line Zero">; 246def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true", 247 "Enable Cache Demote">; 248def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", 249 "Support ptwrite instruction">; 250def FeatureAMXTILE : SubtargetFeature<"amx-tile", "HasAMXTILE", "true", 251 "Support AMX-TILE instructions">; 252def FeatureAMXINT8 : SubtargetFeature<"amx-int8", "HasAMXINT8", "true", 253 "Support AMX-INT8 instructions", 254 [FeatureAMXTILE]>; 255def FeatureAMXBF16 : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true", 256 "Support AMX-BF16 instructions", 257 [FeatureAMXTILE]>; 258def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", 259 "Use LEA for adjusting the stack pointer">; 260def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", 261 "HasSlowDivide32", "true", 262 "Use 8-bit divide for positive values less than 256">; 263def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl", 264 "HasSlowDivide64", "true", 265 "Use 32-bit divide for positive values less than 2^32">; 266def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", 267 "PadShortFunctions", "true", 268 "Pad short functions">; 269def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", 270 "Invalidate Process-Context Identifier">; 271def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", 272 "Enable Software Guard Extensions">; 273def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", 274 "Flush A Cache Line Optimized">; 275def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", 276 "Cache Line Write Back">; 277def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true", 278 "Write Back No Invalidate">; 279def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true", 280 "Support RDPID instructions">; 281def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", 282 "Wait and pause enhancements">; 283def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true", 284 "Has ENQCMD instructions">; 285def FeatureKL : SubtargetFeature<"kl", "HasKL", "true", 286 "Support Key Locker kl Instructions", 287 [FeatureSSE2]>; 288def FeatureWIDEKL : SubtargetFeature<"widekl", "HasWIDEKL", "true", 289 "Support Key Locker wide Instructions", 290 [FeatureKL]>; 291def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true", 292 "Has hreset instruction">; 293def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true", 294 "Has serialize instruction">; 295def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true", 296 "Support TSXLDTRK instructions">; 297def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true", 298 "Has UINTR Instructions">; 299// On some processors, instructions that implicitly take two memory operands are 300// slow. In practice, this means that CALL, PUSH, and POP with memory operands 301// should be avoided in favor of a MOV + register CALL/PUSH/POP. 302def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", 303 "SlowTwoMemOps", "true", 304 "Two memory operand instructions are slow">; 305def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", 306 "LEA instruction needs inputs at AG stage">; 307def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", 308 "LEA instruction with certain arguments is slow">; 309def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", 310 "LEA instruction with 3 ops or certain registers is slow">; 311def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", 312 "INC and DEC instructions are slower than ADD and SUB">; 313def FeatureSoftFloat 314 : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 315 "Use software floating point features">; 316def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", 317 "HasPOPCNTFalseDeps", "true", 318 "POPCNT has a false dependency on dest register">; 319def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", 320 "HasLZCNTFalseDeps", "true", 321 "LZCNT/TZCNT have a false dependency on dest register">; 322def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true", 323 "platform configuration instruction">; 324// On recent X86 (port bound) processors, its preferable to combine to a single shuffle 325// using a variable mask over multiple fixed shuffles. 326def FeatureFastVariableShuffle 327 : SubtargetFeature<"fast-variable-shuffle", 328 "HasFastVariableShuffle", 329 "true", "Shuffles with variable masks are fast">; 330// On some X86 processors, a vzeroupper instruction should be inserted after 331// using ymm/zmm registers before executing code that may use SSE instructions. 332def FeatureInsertVZEROUPPER 333 : SubtargetFeature<"vzeroupper", 334 "InsertVZEROUPPER", 335 "true", "Should insert vzeroupper instructions">; 336// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency 337// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if 338// vector FSQRT has higher throughput than the corresponding NR code. 339// The idea is that throughput bound code is likely to be vectorized, so for 340// vectorized code we should care about the throughput of SQRT operations. 341// But if the code is scalar that probably means that the code has some kind of 342// dependency and we should care more about reducing the latency. 343def FeatureFastScalarFSQRT 344 : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", 345 "true", "Scalar SQRT is fast (disable Newton-Raphson)">; 346def FeatureFastVectorFSQRT 347 : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", 348 "true", "Vector SQRT is fast (disable Newton-Raphson)">; 349// If lzcnt has equivalent latency/throughput to most simple integer ops, it can 350// be used to replace test/set sequences. 351def FeatureFastLZCNT 352 : SubtargetFeature< 353 "fast-lzcnt", "HasFastLZCNT", "true", 354 "LZCNT instructions are as fast as most simple integer ops">; 355// If the target can efficiently decode NOPs upto 7-bytes in length. 356def FeatureFast7ByteNOP 357 : SubtargetFeature< 358 "fast-7bytenop", "HasFast7ByteNOP", "true", 359 "Target can quickly decode up to 7 byte NOPs">; 360// If the target can efficiently decode NOPs upto 11-bytes in length. 361def FeatureFast11ByteNOP 362 : SubtargetFeature< 363 "fast-11bytenop", "HasFast11ByteNOP", "true", 364 "Target can quickly decode up to 11 byte NOPs">; 365// If the target can efficiently decode NOPs upto 15-bytes in length. 366def FeatureFast15ByteNOP 367 : SubtargetFeature< 368 "fast-15bytenop", "HasFast15ByteNOP", "true", 369 "Target can quickly decode up to 15 byte NOPs">; 370// Sandy Bridge and newer processors can use SHLD with the same source on both 371// inputs to implement rotate to avoid the partial flag update of the normal 372// rotate instructions. 373def FeatureFastSHLDRotate 374 : SubtargetFeature< 375 "fast-shld-rotate", "HasFastSHLDRotate", "true", 376 "SHLD can be used as a faster rotate">; 377 378// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka 379// "string operations"). See "REP String Enhancement" in the Intel Software 380// Development Manual. This feature essentially means that REP MOVSB will copy 381// using the largest available size instead of copying bytes one by one, making 382// it at least as fast as REPMOVS{W,D,Q}. 383def FeatureERMSB 384 : SubtargetFeature< 385 "ermsb", "HasERMSB", "true", 386 "REP MOVS/STOS are fast">; 387 388// Icelake and newer processors have Fast Short REP MOV. 389def FeatureFSRM 390 : SubtargetFeature< 391 "fsrm", "HasFSRM", "true", 392 "REP MOVSB of short lengths is faster">; 393 394// Bulldozer and newer processors can merge CMP/TEST (but not other 395// instructions) with conditional branches. 396def FeatureBranchFusion 397 : SubtargetFeature<"branchfusion", "HasBranchFusion", "true", 398 "CMP/TEST can be fused with conditional branches">; 399 400// Sandy Bridge and newer processors have many instructions that can be 401// fused with conditional branches and pass through the CPU as a single 402// operation. 403def FeatureMacroFusion 404 : SubtargetFeature<"macrofusion", "HasMacroFusion", "true", 405 "Various instructions can be fused with conditional branches">; 406 407// Gather is available since Haswell (AVX2 set). So technically, we can 408// generate Gathers on all AVX2 processors. But the overhead on HSW is high. 409// Skylake Client processor has faster Gathers than HSW and performance is 410// similar to Skylake Server (AVX-512). 411def FeatureHasFastGather 412 : SubtargetFeature<"fast-gather", "HasFastGather", "true", 413 "Indicates if gather is reasonably fast">; 414 415def FeaturePrefer128Bit 416 : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true", 417 "Prefer 128-bit AVX instructions">; 418 419def FeaturePrefer256Bit 420 : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", 421 "Prefer 256-bit AVX instructions">; 422 423def FeaturePreferMaskRegisters 424 : SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true", 425 "Prefer AVX512 mask registers over PTEST/MOVMSK">; 426 427// Lower indirect calls using a special construct called a `retpoline` to 428// mitigate potential Spectre v2 attacks against them. 429def FeatureRetpolineIndirectCalls 430 : SubtargetFeature< 431 "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true", 432 "Remove speculation of indirect calls from the generated code">; 433 434// Lower indirect branches and switches either using conditional branch trees 435// or using a special construct called a `retpoline` to mitigate potential 436// Spectre v2 attacks against them. 437def FeatureRetpolineIndirectBranches 438 : SubtargetFeature< 439 "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true", 440 "Remove speculation of indirect branches from the generated code">; 441 442// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and 443// `retpoline-indirect-branches` above. 444def FeatureRetpoline 445 : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true", 446 "Remove speculation of indirect branches from the " 447 "generated code, either by avoiding them entirely or " 448 "lowering them with a speculation blocking construct", 449 [FeatureRetpolineIndirectCalls, 450 FeatureRetpolineIndirectBranches]>; 451 452// Rely on external thunks for the emitted retpoline calls. This allows users 453// to provide their own custom thunk definitions in highly specialized 454// environments such as a kernel that does boot-time hot patching. 455def FeatureRetpolineExternalThunk 456 : SubtargetFeature< 457 "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", 458 "When lowering an indirect call or branch using a `retpoline`, rely " 459 "on the specified user provided thunk rather than emitting one " 460 "ourselves. Only has effect when combined with some other retpoline " 461 "feature", [FeatureRetpolineIndirectCalls]>; 462 463// Mitigate LVI attacks against indirect calls/branches and call returns 464def FeatureLVIControlFlowIntegrity 465 : SubtargetFeature< 466 "lvi-cfi", "UseLVIControlFlowIntegrity", "true", 467 "Prevent indirect calls/branches from using a memory operand, and " 468 "precede all indirect calls/branches from a register with an " 469 "LFENCE instruction to serialize control flow. Also decompose RET " 470 "instructions into a POP+LFENCE+JMP sequence.">; 471 472// Enable SESES to mitigate speculative execution attacks 473def FeatureSpeculativeExecutionSideEffectSuppression 474 : SubtargetFeature< 475 "seses", "UseSpeculativeExecutionSideEffectSuppression", "true", 476 "Prevent speculative execution side channel timing attacks by " 477 "inserting a speculation barrier before memory reads, memory writes, " 478 "and conditional branches. Implies LVI Control Flow integrity.", 479 [FeatureLVIControlFlowIntegrity]>; 480 481// Mitigate LVI attacks against data loads 482def FeatureLVILoadHardening 483 : SubtargetFeature< 484 "lvi-load-hardening", "UseLVILoadHardening", "true", 485 "Insert LFENCE instructions to prevent data speculatively injected " 486 "into loads from being used maliciously.">; 487 488// Direct Move instructions. 489def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", 490 "Support movdiri instruction">; 491def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", 492 "Support movdir64b instruction">; 493 494def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true", 495 "Indicates that the BEXTR instruction is implemented as a single uop " 496 "with good throughput">; 497 498// Combine vector math operations with shuffles into horizontal math 499// instructions if a CPU implements horizontal operations (introduced with 500// SSE3) with better latency/throughput than the alternative sequence. 501def FeatureFastHorizontalOps 502 : SubtargetFeature< 503 "fast-hops", "HasFastHorizontalOps", "true", 504 "Prefer horizontal vector math instructions (haddp, phsub, etc.) over " 505 "normal vector instructions with shuffles">; 506 507def FeatureFastScalarShiftMasks 508 : SubtargetFeature< 509 "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true", 510 "Prefer a left/right scalar logical shift pair over a shift+and pair">; 511 512def FeatureFastVectorShiftMasks 513 : SubtargetFeature< 514 "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true", 515 "Prefer a left/right vector logical shift pair over a shift+and pair">; 516 517def FeatureFastMOVBE 518 : SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true", 519 "Prefer a movbe over a single-use load + bswap / single-use bswap + store">; 520 521def FeatureUseGLMDivSqrtCosts 522 : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true", 523 "Use Goldmont specific floating point div/sqrt costs">; 524 525// Enable use of alias analysis during code generation. 526def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 527 "Use alias analysis during codegen">; 528 529// Bonnell 530def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">; 531// Silvermont 532def ProcIntelSLM : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">; 533 534//===----------------------------------------------------------------------===// 535// Register File Description 536//===----------------------------------------------------------------------===// 537 538include "X86RegisterInfo.td" 539include "X86RegisterBanks.td" 540 541//===----------------------------------------------------------------------===// 542// Instruction Descriptions 543//===----------------------------------------------------------------------===// 544 545include "X86Schedule.td" 546include "X86InstrInfo.td" 547include "X86SchedPredicates.td" 548 549def X86InstrInfo : InstrInfo; 550 551//===----------------------------------------------------------------------===// 552// X86 Scheduler Models 553//===----------------------------------------------------------------------===// 554 555include "X86ScheduleAtom.td" 556include "X86SchedSandyBridge.td" 557include "X86SchedHaswell.td" 558include "X86SchedBroadwell.td" 559include "X86ScheduleSLM.td" 560include "X86ScheduleZnver1.td" 561include "X86ScheduleZnver2.td" 562include "X86ScheduleZnver3.td" 563include "X86ScheduleBdVer2.td" 564include "X86ScheduleBtVer2.td" 565include "X86SchedSkylakeClient.td" 566include "X86SchedSkylakeServer.td" 567 568//===----------------------------------------------------------------------===// 569// X86 Processor Feature Lists 570//===----------------------------------------------------------------------===// 571 572def ProcessorFeatures { 573 // x86-64 and x86-64-v[234] 574 list<SubtargetFeature> X86_64V1Features = [ 575 FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSE2, 576 FeatureFXSR, FeatureNOPL, Feature64Bit 577 ]; 578 list<SubtargetFeature> X86_64V2Features = !listconcat( 579 X86_64V1Features, 580 [FeatureCMPXCHG16B, FeatureLAHFSAHF, FeaturePOPCNT, FeatureSSE42]); 581 list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [ 582 FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT, 583 FeatureMOVBE, FeatureXSAVE 584 ]); 585 list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [ 586 FeatureBWI, 587 FeatureCDI, 588 FeatureDQI, 589 FeatureVLX, 590 ]); 591 592 // Nehalem 593 list<SubtargetFeature> NHMFeatures = X86_64V2Features; 594 list<SubtargetFeature> NHMTuning = [FeatureMacroFusion, 595 FeatureInsertVZEROUPPER]; 596 597 // Westmere 598 list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL]; 599 list<SubtargetFeature> WSMTuning = NHMTuning; 600 list<SubtargetFeature> WSMFeatures = 601 !listconcat(NHMFeatures, WSMAdditionalFeatures); 602 603 // Sandybridge 604 list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX, 605 FeatureXSAVE, 606 FeatureXSAVEOPT]; 607 list<SubtargetFeature> SNBTuning = [FeatureMacroFusion, 608 FeatureSlow3OpsLEA, 609 FeatureSlowDivide64, 610 FeatureSlowUAMem32, 611 FeatureFastScalarFSQRT, 612 FeatureFastSHLDRotate, 613 FeatureFast15ByteNOP, 614 FeaturePOPCNTFalseDeps, 615 FeatureInsertVZEROUPPER]; 616 list<SubtargetFeature> SNBFeatures = 617 !listconcat(WSMFeatures, SNBAdditionalFeatures); 618 619 // Ivybridge 620 list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND, 621 FeatureF16C, 622 FeatureFSGSBase]; 623 list<SubtargetFeature> IVBTuning = SNBTuning; 624 list<SubtargetFeature> IVBFeatures = 625 !listconcat(SNBFeatures, IVBAdditionalFeatures); 626 627 // Haswell 628 list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2, 629 FeatureBMI, 630 FeatureBMI2, 631 FeatureERMSB, 632 FeatureFMA, 633 FeatureINVPCID, 634 FeatureLZCNT, 635 FeatureMOVBE]; 636 list<SubtargetFeature> HSWTuning = [FeatureMacroFusion, 637 FeatureSlow3OpsLEA, 638 FeatureSlowDivide64, 639 FeatureFastScalarFSQRT, 640 FeatureFastSHLDRotate, 641 FeatureFast15ByteNOP, 642 FeatureFastVariableShuffle, 643 FeaturePOPCNTFalseDeps, 644 FeatureLZCNTFalseDeps, 645 FeatureInsertVZEROUPPER]; 646 list<SubtargetFeature> HSWFeatures = 647 !listconcat(IVBFeatures, HSWAdditionalFeatures); 648 649 // Broadwell 650 list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX, 651 FeatureRDSEED, 652 FeaturePRFCHW]; 653 list<SubtargetFeature> BDWTuning = HSWTuning; 654 list<SubtargetFeature> BDWFeatures = 655 !listconcat(HSWFeatures, BDWAdditionalFeatures); 656 657 // Skylake 658 list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES, 659 FeatureXSAVEC, 660 FeatureXSAVES, 661 FeatureCLFLUSHOPT]; 662 list<SubtargetFeature> SKLTuning = [FeatureHasFastGather, 663 FeatureMacroFusion, 664 FeatureSlow3OpsLEA, 665 FeatureSlowDivide64, 666 FeatureFastScalarFSQRT, 667 FeatureFastVectorFSQRT, 668 FeatureFastSHLDRotate, 669 FeatureFast15ByteNOP, 670 FeatureFastVariableShuffle, 671 FeaturePOPCNTFalseDeps, 672 FeatureInsertVZEROUPPER]; 673 list<SubtargetFeature> SKLFeatures = 674 !listconcat(BDWFeatures, SKLAdditionalFeatures); 675 676 // Skylake-AVX512 677 list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES, 678 FeatureXSAVEC, 679 FeatureXSAVES, 680 FeatureCLFLUSHOPT, 681 FeatureAVX512, 682 FeatureCDI, 683 FeatureDQI, 684 FeatureBWI, 685 FeatureVLX, 686 FeaturePKU, 687 FeatureCLWB]; 688 list<SubtargetFeature> SKXTuning = [FeatureHasFastGather, 689 FeatureMacroFusion, 690 FeatureSlow3OpsLEA, 691 FeatureSlowDivide64, 692 FeatureFastScalarFSQRT, 693 FeatureFastVectorFSQRT, 694 FeatureFastSHLDRotate, 695 FeatureFast15ByteNOP, 696 FeatureFastVariableShuffle, 697 FeaturePrefer256Bit, 698 FeaturePOPCNTFalseDeps, 699 FeatureInsertVZEROUPPER]; 700 list<SubtargetFeature> SKXFeatures = 701 !listconcat(BDWFeatures, SKXAdditionalFeatures); 702 703 // Cascadelake 704 list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI]; 705 list<SubtargetFeature> CLXTuning = SKXTuning; 706 list<SubtargetFeature> CLXFeatures = 707 !listconcat(SKXFeatures, CLXAdditionalFeatures); 708 709 // Cooperlake 710 list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16]; 711 list<SubtargetFeature> CPXTuning = SKXTuning; 712 list<SubtargetFeature> CPXFeatures = 713 !listconcat(CLXFeatures, CPXAdditionalFeatures); 714 715 // Cannonlake 716 list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512, 717 FeatureCDI, 718 FeatureDQI, 719 FeatureBWI, 720 FeatureVLX, 721 FeaturePKU, 722 FeatureVBMI, 723 FeatureIFMA, 724 FeatureSHA]; 725 list<SubtargetFeature> CNLTuning = [FeatureHasFastGather, 726 FeatureMacroFusion, 727 FeatureSlow3OpsLEA, 728 FeatureSlowDivide64, 729 FeatureFastScalarFSQRT, 730 FeatureFastVectorFSQRT, 731 FeatureFastSHLDRotate, 732 FeatureFast15ByteNOP, 733 FeatureFastVariableShuffle, 734 FeaturePrefer256Bit, 735 FeatureInsertVZEROUPPER]; 736 list<SubtargetFeature> CNLFeatures = 737 !listconcat(SKLFeatures, CNLAdditionalFeatures); 738 739 // Icelake 740 list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG, 741 FeatureVAES, 742 FeatureVBMI2, 743 FeatureVNNI, 744 FeatureVPCLMULQDQ, 745 FeatureVPOPCNTDQ, 746 FeatureGFNI, 747 FeatureRDPID, 748 FeatureFSRM]; 749 list<SubtargetFeature> ICLTuning = CNLTuning; 750 list<SubtargetFeature> ICLFeatures = 751 !listconcat(CNLFeatures, ICLAdditionalFeatures); 752 753 // Icelake Server 754 list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG, 755 FeatureCLWB, 756 FeatureWBNOINVD]; 757 list<SubtargetFeature> ICXTuning = CNLTuning; 758 list<SubtargetFeature> ICXFeatures = 759 !listconcat(ICLFeatures, ICXAdditionalFeatures); 760 761 // Tigerlake 762 list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT, 763 FeatureCLWB, 764 FeatureMOVDIRI, 765 FeatureMOVDIR64B, 766 FeatureSHSTK]; 767 list<SubtargetFeature> TGLTuning = CNLTuning; 768 list<SubtargetFeature> TGLFeatures = 769 !listconcat(ICLFeatures, TGLAdditionalFeatures ); 770 771 // Sapphirerapids 772 list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE, 773 FeatureAMXINT8, 774 FeatureAMXBF16, 775 FeatureBF16, 776 FeatureSERIALIZE, 777 FeatureCLDEMOTE, 778 FeatureWAITPKG, 779 FeaturePTWRITE, 780 FeatureAVXVNNI, 781 FeatureTSXLDTRK, 782 FeatureENQCMD, 783 FeatureSHSTK, 784 FeatureVP2INTERSECT, 785 FeatureMOVDIRI, 786 FeatureMOVDIR64B, 787 FeatureUINTR]; 788 list<SubtargetFeature> SPRTuning = ICXTuning; 789 list<SubtargetFeature> SPRFeatures = 790 !listconcat(ICXFeatures, SPRAdditionalFeatures); 791 792 // Atom 793 list<SubtargetFeature> AtomFeatures = [FeatureX87, 794 FeatureCMPXCHG8B, 795 FeatureCMOV, 796 FeatureMMX, 797 FeatureSSSE3, 798 FeatureFXSR, 799 FeatureNOPL, 800 Feature64Bit, 801 FeatureCMPXCHG16B, 802 FeatureMOVBE, 803 FeatureLAHFSAHF]; 804 list<SubtargetFeature> AtomTuning = [ProcIntelAtom, 805 FeatureSlowUAMem16, 806 FeatureLEAForSP, 807 FeatureSlowDivide32, 808 FeatureSlowDivide64, 809 FeatureSlowTwoMemOps, 810 FeatureLEAUsesAG, 811 FeaturePadShortFunctions, 812 FeatureInsertVZEROUPPER]; 813 814 // Silvermont 815 list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42, 816 FeaturePOPCNT, 817 FeaturePCLMUL, 818 FeaturePRFCHW, 819 FeatureRDRAND]; 820 list<SubtargetFeature> SLMTuning = [ProcIntelSLM, 821 FeatureSlowTwoMemOps, 822 FeatureSlowLEA, 823 FeatureSlowIncDec, 824 FeatureSlowDivide64, 825 FeatureSlowPMULLD, 826 FeatureFast7ByteNOP, 827 FeatureFastMOVBE, 828 FeaturePOPCNTFalseDeps, 829 FeatureInsertVZEROUPPER]; 830 list<SubtargetFeature> SLMFeatures = 831 !listconcat(AtomFeatures, SLMAdditionalFeatures); 832 833 // Goldmont 834 list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES, 835 FeatureSHA, 836 FeatureRDSEED, 837 FeatureXSAVE, 838 FeatureXSAVEOPT, 839 FeatureXSAVEC, 840 FeatureXSAVES, 841 FeatureCLFLUSHOPT, 842 FeatureFSGSBase]; 843 list<SubtargetFeature> GLMTuning = [FeatureUseGLMDivSqrtCosts, 844 FeatureSlowTwoMemOps, 845 FeatureSlowLEA, 846 FeatureSlowIncDec, 847 FeatureFastMOVBE, 848 FeaturePOPCNTFalseDeps, 849 FeatureInsertVZEROUPPER]; 850 list<SubtargetFeature> GLMFeatures = 851 !listconcat(SLMFeatures, GLMAdditionalFeatures); 852 853 // Goldmont Plus 854 list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE, 855 FeatureRDPID]; 856 list<SubtargetFeature> GLPTuning = [FeatureUseGLMDivSqrtCosts, 857 FeatureSlowTwoMemOps, 858 FeatureSlowLEA, 859 FeatureSlowIncDec, 860 FeatureFastMOVBE, 861 FeatureInsertVZEROUPPER]; 862 list<SubtargetFeature> GLPFeatures = 863 !listconcat(GLMFeatures, GLPAdditionalFeatures); 864 865 // Tremont 866 list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB, 867 FeatureGFNI]; 868 list<SubtargetFeature> TRMTuning = GLPTuning; 869 list<SubtargetFeature> TRMFeatures = 870 !listconcat(GLPFeatures, TRMAdditionalFeatures); 871 872 // Alderlake 873 list<SubtargetFeature> ADLAdditionalFeatures = [FeatureSERIALIZE, 874 FeaturePCONFIG, 875 FeatureSHSTK, 876 FeatureWIDEKL, 877 FeatureINVPCID, 878 FeatureADX, 879 FeatureFMA, 880 FeatureVAES, 881 FeatureVPCLMULQDQ, 882 FeatureF16C, 883 FeatureBMI, 884 FeatureBMI2, 885 FeatureLZCNT, 886 FeatureAVXVNNI, 887 FeaturePKU, 888 FeatureHRESET, 889 FeatureCLDEMOTE, 890 FeatureMOVDIRI, 891 FeatureMOVDIR64B, 892 FeatureWAITPKG]; 893 list<SubtargetFeature> ADLTuning = SKLTuning; 894 list<SubtargetFeature> ADLFeatures = 895 !listconcat(TRMFeatures, ADLAdditionalFeatures); 896 897 // Knights Landing 898 list<SubtargetFeature> KNLFeatures = [FeatureX87, 899 FeatureCMPXCHG8B, 900 FeatureCMOV, 901 FeatureMMX, 902 FeatureFXSR, 903 FeatureNOPL, 904 Feature64Bit, 905 FeatureCMPXCHG16B, 906 FeaturePOPCNT, 907 FeaturePCLMUL, 908 FeatureXSAVE, 909 FeatureXSAVEOPT, 910 FeatureLAHFSAHF, 911 FeatureAES, 912 FeatureRDRAND, 913 FeatureF16C, 914 FeatureFSGSBase, 915 FeatureAVX512, 916 FeatureERI, 917 FeatureCDI, 918 FeaturePFI, 919 FeaturePREFETCHWT1, 920 FeatureADX, 921 FeatureRDSEED, 922 FeatureMOVBE, 923 FeatureLZCNT, 924 FeatureBMI, 925 FeatureBMI2, 926 FeatureFMA, 927 FeaturePRFCHW]; 928 list<SubtargetFeature> KNLTuning = [FeatureSlowDivide64, 929 FeatureSlow3OpsLEA, 930 FeatureSlowIncDec, 931 FeatureSlowTwoMemOps, 932 FeaturePreferMaskRegisters, 933 FeatureHasFastGather, 934 FeatureFastMOVBE, 935 FeatureSlowPMADDWD]; 936 // TODO Add AVX5124FMAPS/AVX5124VNNIW features 937 list<SubtargetFeature> KNMFeatures = 938 !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]); 939 940 // Barcelona 941 list<SubtargetFeature> BarcelonaFeatures = [FeatureX87, 942 FeatureCMPXCHG8B, 943 FeatureSSE4A, 944 Feature3DNowA, 945 FeatureFXSR, 946 FeatureNOPL, 947 FeatureCMPXCHG16B, 948 FeaturePRFCHW, 949 FeatureLZCNT, 950 FeaturePOPCNT, 951 FeatureLAHFSAHF, 952 FeatureCMOV, 953 Feature64Bit]; 954 list<SubtargetFeature> BarcelonaTuning = [FeatureFastScalarShiftMasks, 955 FeatureSlowSHLD, 956 FeatureInsertVZEROUPPER]; 957 958 // Bobcat 959 list<SubtargetFeature> BtVer1Features = [FeatureX87, 960 FeatureCMPXCHG8B, 961 FeatureCMOV, 962 FeatureMMX, 963 FeatureSSSE3, 964 FeatureSSE4A, 965 FeatureFXSR, 966 FeatureNOPL, 967 Feature64Bit, 968 FeatureCMPXCHG16B, 969 FeaturePRFCHW, 970 FeatureLZCNT, 971 FeaturePOPCNT, 972 FeatureLAHFSAHF]; 973 list<SubtargetFeature> BtVer1Tuning = [FeatureFast15ByteNOP, 974 FeatureFastScalarShiftMasks, 975 FeatureFastVectorShiftMasks, 976 FeatureSlowSHLD, 977 FeatureInsertVZEROUPPER]; 978 979 // Jaguar 980 list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX, 981 FeatureAES, 982 FeaturePCLMUL, 983 FeatureBMI, 984 FeatureF16C, 985 FeatureMOVBE, 986 FeatureXSAVE, 987 FeatureXSAVEOPT]; 988 list<SubtargetFeature> BtVer2Tuning = [FeatureFastLZCNT, 989 FeatureFastBEXTR, 990 FeatureFastHorizontalOps, 991 FeatureFast15ByteNOP, 992 FeatureFastScalarShiftMasks, 993 FeatureFastVectorShiftMasks, 994 FeatureFastMOVBE, 995 FeatureSlowSHLD]; 996 list<SubtargetFeature> BtVer2Features = 997 !listconcat(BtVer1Features, BtVer2AdditionalFeatures); 998 999 // Bulldozer 1000 list<SubtargetFeature> BdVer1Features = [FeatureX87, 1001 FeatureCMPXCHG8B, 1002 FeatureCMOV, 1003 FeatureXOP, 1004 Feature64Bit, 1005 FeatureCMPXCHG16B, 1006 FeatureAES, 1007 FeaturePRFCHW, 1008 FeaturePCLMUL, 1009 FeatureMMX, 1010 FeatureFXSR, 1011 FeatureNOPL, 1012 FeatureLZCNT, 1013 FeaturePOPCNT, 1014 FeatureXSAVE, 1015 FeatureLWP, 1016 FeatureLAHFSAHF]; 1017 list<SubtargetFeature> BdVer1Tuning = [FeatureSlowSHLD, 1018 FeatureFast11ByteNOP, 1019 FeatureFastScalarShiftMasks, 1020 FeatureBranchFusion, 1021 FeatureInsertVZEROUPPER]; 1022 1023 // PileDriver 1024 list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C, 1025 FeatureBMI, 1026 FeatureTBM, 1027 FeatureFMA, 1028 FeatureFastBEXTR]; 1029 list<SubtargetFeature> BdVer2AdditionalTuning = [FeatureFastMOVBE]; 1030 list<SubtargetFeature> BdVer2Tuning = 1031 !listconcat(BdVer1Tuning, BdVer2AdditionalTuning); 1032 list<SubtargetFeature> BdVer2Features = 1033 !listconcat(BdVer1Features, BdVer2AdditionalFeatures); 1034 1035 // Steamroller 1036 list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT, 1037 FeatureFSGSBase]; 1038 list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning; 1039 list<SubtargetFeature> BdVer3Features = 1040 !listconcat(BdVer2Features, BdVer3AdditionalFeatures); 1041 1042 // Excavator 1043 list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2, 1044 FeatureBMI2, 1045 FeatureMOVBE, 1046 FeatureRDRAND, 1047 FeatureMWAITX]; 1048 list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning; 1049 list<SubtargetFeature> BdVer4Features = 1050 !listconcat(BdVer3Features, BdVer4AdditionalFeatures); 1051 1052 1053 // AMD Zen Processors common ISAs 1054 list<SubtargetFeature> ZNFeatures = [FeatureADX, 1055 FeatureAES, 1056 FeatureAVX2, 1057 FeatureBMI, 1058 FeatureBMI2, 1059 FeatureCLFLUSHOPT, 1060 FeatureCLZERO, 1061 FeatureCMOV, 1062 Feature64Bit, 1063 FeatureCMPXCHG16B, 1064 FeatureF16C, 1065 FeatureFMA, 1066 FeatureFSGSBase, 1067 FeatureFXSR, 1068 FeatureNOPL, 1069 FeatureLAHFSAHF, 1070 FeatureLZCNT, 1071 FeatureMMX, 1072 FeatureMOVBE, 1073 FeatureMWAITX, 1074 FeaturePCLMUL, 1075 FeaturePOPCNT, 1076 FeaturePRFCHW, 1077 FeatureRDRAND, 1078 FeatureRDSEED, 1079 FeatureSHA, 1080 FeatureSSE4A, 1081 FeatureX87, 1082 FeatureXSAVE, 1083 FeatureXSAVEC, 1084 FeatureXSAVEOPT, 1085 FeatureXSAVES]; 1086 list<SubtargetFeature> ZNTuning = [FeatureFastLZCNT, 1087 FeatureFastBEXTR, 1088 FeatureFast15ByteNOP, 1089 FeatureBranchFusion, 1090 FeatureFastScalarShiftMasks, 1091 FeatureFastMOVBE, 1092 FeatureSlowSHLD, 1093 FeatureInsertVZEROUPPER]; 1094 list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB, 1095 FeatureRDPID, 1096 FeatureWBNOINVD]; 1097 list<SubtargetFeature> ZN2Tuning = ZNTuning; 1098 list<SubtargetFeature> ZN2Features = 1099 !listconcat(ZNFeatures, ZN2AdditionalFeatures); 1100 list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM, 1101 FeatureINVPCID, 1102 FeaturePKU, 1103 FeatureVAES, 1104 FeatureVPCLMULQDQ]; 1105 list<SubtargetFeature> ZN3AdditionalTuning = [FeatureMacroFusion]; 1106 list<SubtargetFeature> ZN3Tuning = 1107 !listconcat(ZNTuning, ZN3AdditionalTuning); 1108 list<SubtargetFeature> ZN3Features = 1109 !listconcat(ZN2Features, ZN3AdditionalFeatures); 1110} 1111 1112//===----------------------------------------------------------------------===// 1113// X86 processors supported. 1114//===----------------------------------------------------------------------===// 1115 1116class Proc<string Name, list<SubtargetFeature> Features, 1117 list<SubtargetFeature> TuneFeatures> 1118 : ProcessorModel<Name, GenericModel, Features, TuneFeatures>; 1119 1120class ProcModel<string Name, SchedMachineModel Model, 1121 list<SubtargetFeature> Features, 1122 list<SubtargetFeature> TuneFeatures> 1123 : ProcessorModel<Name, Model, Features, TuneFeatures>; 1124 1125// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled 1126// if i386/i486 is specifically requested. 1127// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget 1128// constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled. 1129// It has no effect on code generation. 1130def : ProcModel<"generic", SandyBridgeModel, 1131 [FeatureX87, FeatureCMPXCHG8B, Feature64Bit], 1132 [FeatureSlow3OpsLEA, 1133 FeatureSlowDivide64, 1134 FeatureSlowIncDec, 1135 FeatureMacroFusion, 1136 FeatureInsertVZEROUPPER]>; 1137 1138def : Proc<"i386", [FeatureX87], 1139 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1140def : Proc<"i486", [FeatureX87], 1141 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1142def : Proc<"i586", [FeatureX87, FeatureCMPXCHG8B], 1143 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1144def : Proc<"pentium", [FeatureX87, FeatureCMPXCHG8B], 1145 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1146def : Proc<"pentium-mmx", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX], 1147 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1148 1149def : Proc<"i686", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV], 1150 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1151def : Proc<"pentiumpro", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, 1152 FeatureNOPL], 1153 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1154 1155def : Proc<"pentium2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV, 1156 FeatureFXSR, FeatureNOPL], 1157 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1158 1159foreach P = ["pentium3", "pentium3m"] in { 1160 def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, 1161 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV], 1162 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1163} 1164 1165// Enable the PostRAScheduler for SSE2 and SSE3 class cpus. 1166// The intent is to enable it for pentium4 which is the current default 1167// processor in a vanilla 32-bit clang compilation when no specific 1168// architecture is specified. This generally gives a nice performance 1169// increase on silvermont, with largely neutral behavior on other 1170// contemporary large core processors. 1171// pentium-m, pentium4m, prescott and nocona are included as a preventative 1172// measure to avoid performance surprises, in case clang's default cpu 1173// changes slightly. 1174 1175def : ProcModel<"pentium-m", GenericPostRAModel, 1176 [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, 1177 FeatureFXSR, FeatureNOPL, FeatureCMOV], 1178 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1179 1180foreach P = ["pentium4", "pentium4m"] in { 1181 def : ProcModel<P, GenericPostRAModel, 1182 [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, 1183 FeatureFXSR, FeatureNOPL, FeatureCMOV], 1184 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1185} 1186 1187// Intel Quark. 1188def : Proc<"lakemont", [FeatureCMPXCHG8B], 1189 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1190 1191// Intel Core Duo. 1192def : ProcModel<"yonah", SandyBridgeModel, 1193 [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, 1194 FeatureFXSR, FeatureNOPL, FeatureCMOV], 1195 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1196 1197// NetBurst. 1198def : ProcModel<"prescott", GenericPostRAModel, 1199 [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, 1200 FeatureFXSR, FeatureNOPL, FeatureCMOV], 1201 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1202def : ProcModel<"nocona", GenericPostRAModel, [ 1203 FeatureX87, 1204 FeatureCMPXCHG8B, 1205 FeatureCMOV, 1206 FeatureMMX, 1207 FeatureSSE3, 1208 FeatureFXSR, 1209 FeatureNOPL, 1210 Feature64Bit, 1211 FeatureCMPXCHG16B, 1212], 1213[ 1214 FeatureSlowUAMem16, 1215 FeatureInsertVZEROUPPER 1216]>; 1217 1218// Intel Core 2 Solo/Duo. 1219def : ProcModel<"core2", SandyBridgeModel, [ 1220 FeatureX87, 1221 FeatureCMPXCHG8B, 1222 FeatureCMOV, 1223 FeatureMMX, 1224 FeatureSSSE3, 1225 FeatureFXSR, 1226 FeatureNOPL, 1227 Feature64Bit, 1228 FeatureCMPXCHG16B, 1229 FeatureLAHFSAHF 1230], 1231[ 1232 FeatureMacroFusion, 1233 FeatureSlowUAMem16, 1234 FeatureInsertVZEROUPPER 1235]>; 1236def : ProcModel<"penryn", SandyBridgeModel, [ 1237 FeatureX87, 1238 FeatureCMPXCHG8B, 1239 FeatureCMOV, 1240 FeatureMMX, 1241 FeatureSSE41, 1242 FeatureFXSR, 1243 FeatureNOPL, 1244 Feature64Bit, 1245 FeatureCMPXCHG16B, 1246 FeatureLAHFSAHF 1247], 1248[ 1249 FeatureMacroFusion, 1250 FeatureSlowUAMem16, 1251 FeatureInsertVZEROUPPER 1252]>; 1253 1254// Atom CPUs. 1255foreach P = ["bonnell", "atom"] in { 1256 def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures, 1257 ProcessorFeatures.AtomTuning>; 1258} 1259 1260foreach P = ["silvermont", "slm"] in { 1261 def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures, 1262 ProcessorFeatures.SLMTuning>; 1263} 1264 1265def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures, 1266 ProcessorFeatures.GLMTuning>; 1267def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures, 1268 ProcessorFeatures.GLPTuning>; 1269def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures, 1270 ProcessorFeatures.TRMTuning>; 1271 1272// "Arrandale" along with corei3 and corei5 1273foreach P = ["nehalem", "corei7"] in { 1274 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures, 1275 ProcessorFeatures.NHMTuning>; 1276} 1277 1278// Westmere is the corei3/i5/i7 path from nehalem to sandybridge 1279def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures, 1280 ProcessorFeatures.WSMTuning>; 1281 1282foreach P = ["sandybridge", "corei7-avx"] in { 1283 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures, 1284 ProcessorFeatures.SNBTuning>; 1285} 1286 1287foreach P = ["ivybridge", "core-avx-i"] in { 1288 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures, 1289 ProcessorFeatures.IVBTuning>; 1290} 1291 1292foreach P = ["haswell", "core-avx2"] in { 1293 def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures, 1294 ProcessorFeatures.HSWTuning>; 1295} 1296 1297def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures, 1298 ProcessorFeatures.BDWTuning>; 1299 1300def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures, 1301 ProcessorFeatures.SKLTuning>; 1302 1303// FIXME: define KNL scheduler model 1304def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures, 1305 ProcessorFeatures.KNLTuning>; 1306def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures, 1307 ProcessorFeatures.KNLTuning>; 1308 1309foreach P = ["skylake-avx512", "skx"] in { 1310 def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures, 1311 ProcessorFeatures.SKXTuning>; 1312} 1313 1314def : ProcModel<"cascadelake", SkylakeServerModel, 1315 ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>; 1316def : ProcModel<"cooperlake", SkylakeServerModel, 1317 ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>; 1318def : ProcModel<"cannonlake", SkylakeServerModel, 1319 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>; 1320def : ProcModel<"icelake-client", SkylakeServerModel, 1321 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; 1322def : ProcModel<"rocketlake", SkylakeServerModel, 1323 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>; 1324def : ProcModel<"icelake-server", SkylakeServerModel, 1325 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>; 1326def : ProcModel<"tigerlake", SkylakeServerModel, 1327 ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>; 1328def : ProcModel<"sapphirerapids", SkylakeServerModel, 1329 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>; 1330def : ProcModel<"alderlake", SkylakeClientModel, 1331 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>; 1332 1333// AMD CPUs. 1334 1335def : Proc<"k6", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX], 1336 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1337def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow], 1338 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1339def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow], 1340 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1341 1342foreach P = ["athlon", "athlon-tbird"] in { 1343 def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, Feature3DNowA, 1344 FeatureNOPL], 1345 [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1346} 1347 1348foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { 1349 def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, 1350 FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL], 1351 [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1352} 1353 1354foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { 1355 def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE2, Feature3DNowA, 1356 FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMOV], 1357 [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16, 1358 FeatureInsertVZEROUPPER]>; 1359} 1360 1361foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { 1362 def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE3, Feature3DNowA, 1363 FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureCMOV, 1364 Feature64Bit], 1365 [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16, 1366 FeatureInsertVZEROUPPER]>; 1367} 1368 1369foreach P = ["amdfam10", "barcelona"] in { 1370 def : Proc<P, ProcessorFeatures.BarcelonaFeatures, 1371 ProcessorFeatures.BarcelonaTuning>; 1372} 1373 1374// Bobcat 1375def : Proc<"btver1", ProcessorFeatures.BtVer1Features, 1376 ProcessorFeatures.BtVer1Tuning>; 1377// Jaguar 1378def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features, 1379 ProcessorFeatures.BtVer2Tuning>; 1380 1381// Bulldozer 1382def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features, 1383 ProcessorFeatures.BdVer1Tuning>; 1384// Piledriver 1385def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features, 1386 ProcessorFeatures.BdVer2Tuning>; 1387// Steamroller 1388def : Proc<"bdver3", ProcessorFeatures.BdVer3Features, 1389 ProcessorFeatures.BdVer3Tuning>; 1390// Excavator 1391def : Proc<"bdver4", ProcessorFeatures.BdVer4Features, 1392 ProcessorFeatures.BdVer4Tuning>; 1393 1394def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures, 1395 ProcessorFeatures.ZNTuning>; 1396def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features, 1397 ProcessorFeatures.ZN2Tuning>; 1398def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features, 1399 ProcessorFeatures.ZN3Tuning>; 1400 1401def : Proc<"geode", [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA], 1402 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1403 1404def : Proc<"winchip-c6", [FeatureX87, FeatureMMX], 1405 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1406def : Proc<"winchip2", [FeatureX87, Feature3DNow], 1407 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1408def : Proc<"c3", [FeatureX87, Feature3DNow], 1409 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1410def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, 1411 FeatureSSE1, FeatureFXSR, FeatureCMOV], 1412 [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; 1413 1414// We also provide a generic 64-bit specific x86 processor model which tries to 1415// be good for modern chips without enabling instruction set encodings past the 1416// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and 1417// modern 64-bit x86 chip, and enables features that are generally beneficial. 1418// 1419// We currently use the Sandy Bridge model as the default scheduling model as 1420// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which 1421// covers a huge swath of x86 processors. If there are specific scheduling 1422// knobs which need to be tuned differently for AMD chips, we might consider 1423// forming a common base for them. 1424def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features, 1425[ 1426 FeatureSlow3OpsLEA, 1427 FeatureSlowDivide64, 1428 FeatureSlowIncDec, 1429 FeatureMacroFusion, 1430 FeatureInsertVZEROUPPER 1431]>; 1432 1433// x86-64 micro-architecture levels. 1434def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features, 1435 ProcessorFeatures.SNBTuning>; 1436// Close to Haswell. 1437def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features, 1438 ProcessorFeatures.HSWTuning>; 1439// Close to the AVX-512 level implemented by Xeon Scalable Processors. 1440def : ProcModel<"x86-64-v4", SkylakeServerModel, ProcessorFeatures.X86_64V4Features, 1441 ProcessorFeatures.SKXTuning>; 1442 1443//===----------------------------------------------------------------------===// 1444// Calling Conventions 1445//===----------------------------------------------------------------------===// 1446 1447include "X86CallingConv.td" 1448 1449 1450//===----------------------------------------------------------------------===// 1451// Assembly Parser 1452//===----------------------------------------------------------------------===// 1453 1454def ATTAsmParserVariant : AsmParserVariant { 1455 int Variant = 0; 1456 1457 // Variant name. 1458 string Name = "att"; 1459 1460 // Discard comments in assembly strings. 1461 string CommentDelimiter = "#"; 1462 1463 // Recognize hard coded registers. 1464 string RegisterPrefix = "%"; 1465} 1466 1467def IntelAsmParserVariant : AsmParserVariant { 1468 int Variant = 1; 1469 1470 // Variant name. 1471 string Name = "intel"; 1472 1473 // Discard comments in assembly strings. 1474 string CommentDelimiter = ";"; 1475 1476 // Recognize hard coded registers. 1477 string RegisterPrefix = ""; 1478} 1479 1480//===----------------------------------------------------------------------===// 1481// Assembly Printers 1482//===----------------------------------------------------------------------===// 1483 1484// The X86 target supports two different syntaxes for emitting machine code. 1485// This is controlled by the -x86-asm-syntax={att|intel} 1486def ATTAsmWriter : AsmWriter { 1487 string AsmWriterClassName = "ATTInstPrinter"; 1488 int Variant = 0; 1489} 1490def IntelAsmWriter : AsmWriter { 1491 string AsmWriterClassName = "IntelInstPrinter"; 1492 int Variant = 1; 1493} 1494 1495def X86 : Target { 1496 // Information about the instructions... 1497 let InstructionSet = X86InstrInfo; 1498 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; 1499 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 1500 let AllowRegisterRenaming = 1; 1501} 1502 1503//===----------------------------------------------------------------------===// 1504// Pfm Counters 1505//===----------------------------------------------------------------------===// 1506 1507include "X86PfmCounters.td" 1508