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/netbsd-src/external/gpl3/gdb/dist/cpu/
H A Dxstormy16.cpu199 (dnf f-Rd "general register destination" () 12 4)
200 (dnop Rd "general register destination" () h-gr f-Rd)
434 ; Update the PSW for destination register Rd, set Rd to value.
435 (define-pmacro (set-psw Rd index value ws)
443 ; Update the PSW for destination register Rd.
460 (define-pmacro (set-psw-carry Rd index value carry ws)
472 (define-pmacro (set-psw-add Rd index a b c)
486 ; Set the PSW for a subtraction of a-b into Rd, but don't actually
488 (define-pmacro (set-psw-cmp Rd index a b)
502 (define-pmacro (set-psw-sub Rd index a b c)
[all …]
/netbsd-src/external/gpl3/binutils/dist/cpu/
H A Dxstormy16.cpu199 (dnf f-Rd "general register destination" () 12 4)
200 (dnop Rd "general register destination" () h-gr f-Rd)
434 ; Update the PSW for destination register Rd, set Rd to value.
435 (define-pmacro (set-psw Rd index value ws)
443 ; Update the PSW for destination register Rd.
460 (define-pmacro (set-psw-carry Rd index value carry ws)
472 (define-pmacro (set-psw-add Rd index a b c)
486 ; Set the PSW for a subtraction of a-b into Rd, but don't actually
488 (define-pmacro (set-psw-cmp Rd index a b)
502 (define-pmacro (set-psw-sub Rd index a b c)
[all …]
H A Dcris.cpu154 ((Rd INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
292 ((Rd INT -1) (Rs INT -1))
293 ((Rd INT -1))
296 ; Special case of u-exec for movem: don't treat Rd as an incoming
300 ((Rd INT -1))
317 (define-pmacro (cris-timing-Rd-sfield)
318 (crisv32-timing-destreg ((out Rd Rd-sfield)))
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/netbsd-src/external/gpl3/binutils.old/dist/cpu/
H A Dxstormy16.cpu199 (dnf f-Rd "general register destination" () 12 4)
200 (dnop Rd "general register destination" () h-gr f-Rd)
434 ; Update the PSW for destination register Rd, set Rd to value.
435 (define-pmacro (set-psw Rd index value ws)
443 ; Update the PSW for destination register Rd.
460 (define-pmacro (set-psw-carry Rd index value carry ws)
472 (define-pmacro (set-psw-add Rd index a b c)
486 ; Set the PSW for a subtraction of a-b into Rd, but don't actually
488 (define-pmacro (set-psw-cmp Rd index a b)
502 (define-pmacro (set-psw-sub Rd index a b c)
[all …]
H A Dcris.cpu154 ((Rd INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
292 ((Rd INT -1) (Rs INT -1))
293 ((Rd INT -1))
296 ; Special case of u-exec for movem: don't treat Rd as an incoming
300 ((Rd INT -1))
317 (define-pmacro (cris-timing-Rd-sfield)
318 (crisv32-timing-destreg ((out Rd Rd-sfield)))
[all …]
/netbsd-src/external/gpl3/gdb.old/dist/cpu/
H A Dxstormy16.cpu199 (dnf f-Rd "general register destination" () 12 4)
200 (dnop Rd "general register destination" () h-gr f-Rd)
434 ; Update the PSW for destination register Rd, set Rd to value.
435 (define-pmacro (set-psw Rd index value ws)
443 ; Update the PSW for destination register Rd.
460 (define-pmacro (set-psw-carry Rd index value carry ws)
472 (define-pmacro (set-psw-add Rd index a b c)
486 ; Set the PSW for a subtraction of a-b into Rd, but don't actually
488 (define-pmacro (set-psw-cmp Rd index a b)
502 (define-pmacro (set-psw-sub Rd index a b c)
[all …]
H A Dcris.cpu154 ((Rd INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
292 ((Rd INT -1) (Rs INT -1))
293 ((Rd INT -1))
296 ; Special case of u-exec for movem: don't treat Rd as an incoming
300 ((Rd INT -1))
317 (define-pmacro (cris-timing-Rd-sfield)
318 (crisv32-timing-destreg ((out Rd Rd-sfield)))
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/netbsd-src/sys/arch/aarch64/aarch64/
H A Ddisasm.c799 uint64_t Rn, uint64_t Rd, in extendreg_common() argument
804 if ((z_op != NULL) && (Rd == 31)) { in extendreg_common()
807 PRINTF("%s\t%s, ", op, SREGNAME(sf, Rd)); in extendreg_common()
812 if ((Rd == 31) || (Rn == 31)) { in extendreg_common()
842 uint64_t Rn, uint64_t Rd, in shiftreg_common() argument
853 ZREGNAME(sf, Rd), in shiftreg_common()
855 } else if ((znm_op != NULL) && (Rd == 31)) { in shiftreg_common()
863 ZREGNAME(sf, Rd), in shiftreg_common()
1031 uint64_t sf, uint64_t shift, uint64_t imm12, uint64_t Rn, uint64_t Rd, in addsub_imm_common() argument
1039 if (Rd == 31) { in addsub_imm_common()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td49 // Rd - 64-bit registers.
50 class Rd<bits<5> num, string n, list<Register> subregs,
112 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
113 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
114 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
115 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
116 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
117 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
118 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
119 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td445 bits<4> Rd;
448 let Inst{11-8} = Rd;
458 bits<4> Rd;
462 let Inst{11-8} = Rd;
484 bits<4> Rd;
487 let Inst{11-8} = Rd;
497 bits<4> Rd;
500 let Inst{11-8} = Rd;
523 bits<4> Rd;
526 let Inst{11-8} = Rd;
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H A DARMInstrInfo.td1511 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1518 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1519 iii, opc, "\t$Rd, $Rn, $imm",
1520 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1522 bits<4> Rd;
1527 let Inst{15-12} = Rd;
1531 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1532 iir, opc, "\t$Rd, $Rn, $Rm",
1533 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1535 bits<4> Rd;
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H A DARMInstrThumb.td399 // ADD <Rd>, sp, #<imm8>
910 bits<3> Rd;
912 let Inst{2-0} = Rd;
920 bits<3> Rd;
923 let Inst{2-0} = Rd;
931 bits<3> Rd;
934 let Inst{2-0} = Rd;
940 bits<3> Rd;
943 let Inst{2-0} = Rd;
976 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
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H A DARMInstrCDE.td82 dag Rd;
116 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
119 bits<4> Rd;
123 let Inst{15-12} = Rd{3-0};
132 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
135 bits<4> Rd;
141 let Inst{15-12} = Rd{3-0};
150 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
153 bits<4> Rd;
163 let Inst{3-0} = Rd{3-0};
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td1879 def : InstAlias<asm # "\t$Rd, $imm, $target",
1880 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1925 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1926 [(set regtype:$Rd, (node regtype:$Rn))]>,
1928 bits<5> Rd;
1934 let Inst{4-0} = Rd;
1960 : I<(outs GPR64:$Rd), (ins GPR64:$src, GPR64sp:$Rn), asm, "\t$Rd, $Rn",
1961 "$Rd = $src",
1964 bits<5> Rd;
1970 let Inst{4-0} = Rd;
[all …]
H A DAArch64PBQPRegAlloc.cpp158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint() argument
160 if (Rd == Ra) in addIntraChainConstraint()
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) { in addIntraChainConstraint()
167 << Register::isPhysicalRegister(Rd) << '\n'); in addIntraChainConstraint()
173 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd); in addIntraChainConstraint()
186 const LiveInterval &ld = LIs.getInterval(Rd); in addIntraChainConstraint()
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint() argument
248 if (Rd != Ra) { in addInterChainConstraint()
250 << " to " << printReg(Rd, TRI) << '\n';); in addInterChainConstraint()
252 Chains.insert(Rd); in addInterChainConstraint()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
278 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
282 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
294 !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
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H A DLanaiInstrFormats.td34 // opcode Rd Rs1 constant (16)
37 // Rd <- Rs1 op constant
83 // A Jump is accomplished by `Rd' being `pc', and it has one shadow.
90 bits<5> Rd;
98 let Inst{27 - 23} = Rd;
112 // opcode Rd Rs1 Rs2 \ operation /
115 // `Rd <- Rs1 op Rs2' iff condition DDDI is true.
131 // instructions in *Note RI::). For the SELECT operation, Rd gets Rs1 if
145 // A Jump is accomplished by `Rd' being `pc', and it has one shadow.
150 bits<5> Rd;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td385 // ADD Rd, Rr
395 // ADDW Rd+1:Rd, Rr+1:Rr
399 // add Rd, Rr
400 // adc Rd+1, Rr+1
407 // ADC Rd, Rr
418 // ADCW Rd+1:Rd, Rr+1:Rr
423 // adc Rd, Rr
424 // adc Rd+1, Rr+1
432 // AIDW Rd, k
433 // Adds an immediate 6-bit value K to Rd, placing the result in Rd.
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Daarch64-tbl.h2741 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
2742 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
2743 …CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_AL…
2744 …CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS …
2745 …CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_AL…
2746 …CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS …
2749 …CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F…
2752 …CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F…
2757 …CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HA…
2760 …CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HA…
[all …]
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dft32.h290 unsigned int Rd = (op32 >> 20) & 31; in ft32_shortcode() local
298 if (Rd == R1) in ft32_shortcode()
304 r = Rd; in ft32_shortcode()
308 if ((find == NULL) && (Rd == R2)) in ft32_shortcode()
314 r = Rd; in ft32_shortcode()
334 r = Rd; in ft32_shortcode()
/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dft32.h290 unsigned int Rd = (op32 >> 20) & 31; in ft32_shortcode() local
298 if (Rd == R1) in ft32_shortcode()
304 r = Rd; in ft32_shortcode()
308 if ((find == NULL) && (Rd == R2)) in ft32_shortcode()
314 r = Rd; in ft32_shortcode()
334 r = Rd; in ft32_shortcode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td43 // Rd - Slots in the FP register file for 64-bit floating-point values.
44 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
197 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>;
198 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>;
199 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>;
200 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>;
201 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>;
202 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>;
203 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>;
204 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2217 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2225 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeQADDInstruction()
2443 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2452 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2454 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2467 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2475 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2478 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2494 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2503 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeSMLAInstruction()
[all …]
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Daarch64-tbl.h2949 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
2950 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
2951 …CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_AL…
2952 …CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS …
2953 …CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_AL…
2954 …CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS …
2957 …CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F…
2960 …CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F…
2965 …CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HA…
2968 …CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HA…
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp889 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
894 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
897 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
980 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
1008 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1029 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1042 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1054 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); in DecodeMoveImmInstruction()
1059 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeMoveImmInstruction()
1584 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
[all …]

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