Home
last modified time | relevance | path

Searched refs:Enable (Results 1 – 25 of 1725) sorted by relevance

12345678910>>...69

/netbsd-src/sys/external/bsd/compiler_rt/dist/lib/xray/
H A Dxray_AArch64.cc35 inline static bool patchSled(const bool Enable, const uint32_t FuncId, in patchSled() argument
67 if (Enable) { in patchSled()
93 bool patchFunctionEntry(const bool Enable, const uint32_t FuncId, in patchFunctionEntry() argument
96 return patchSled(Enable, FuncId, Sled, Trampoline); in patchFunctionEntry()
99 bool patchFunctionExit(const bool Enable, const uint32_t FuncId, in patchFunctionExit() argument
101 return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); in patchFunctionExit()
104 bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId, in patchFunctionTailExit() argument
106 return patchSled(Enable, FuncId, Sled, __xray_FunctionTailExit); in patchFunctionTailExit()
109 bool patchCustomEvent(const bool Enable, const uint32_t FuncId, in patchCustomEvent() argument
115 bool patchTypedEvent(const bool Enable, const uint32_t FuncId, in patchTypedEvent() argument
H A Dxray_arm.cc77 inline static bool patchSled(const bool Enable, const uint32_t FuncId, in patchSled() argument
108 if (Enable) { in patchSled()
130 bool patchFunctionEntry(const bool Enable, const uint32_t FuncId, in patchFunctionEntry() argument
133 return patchSled(Enable, FuncId, Sled, Trampoline); in patchFunctionEntry()
136 bool patchFunctionExit(const bool Enable, const uint32_t FuncId, in patchFunctionExit() argument
138 return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); in patchFunctionExit()
141 bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId, in patchFunctionTailExit() argument
143 return patchSled(Enable, FuncId, Sled, __xray_FunctionTailExit); in patchFunctionTailExit()
146 bool patchCustomEvent(const bool Enable, const uint32_t FuncId, in patchCustomEvent() argument
152 bool patchTypedEvent(const bool Enable, const uint32_t FuncId, in patchTypedEvent() argument
H A Dxray_powerpc64.cc53 bool patchFunctionEntry(const bool Enable, uint32_t FuncId, in patchFunctionEntry() argument
56 if (Enable) { in patchFunctionEntry()
71 bool patchFunctionExit(const bool Enable, uint32_t FuncId, in patchFunctionExit() argument
73 if (Enable) { in patchFunctionExit()
88 bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId, in patchFunctionTailExit() argument
90 return patchFunctionExit(Enable, FuncId, Sled); in patchFunctionTailExit()
96 bool patchCustomEvent(const bool Enable, const uint32_t FuncId, in patchCustomEvent() argument
102 bool patchTypedEvent(const bool Enable, const uint32_t FuncId, in patchTypedEvent() argument
H A Dxray_mips.cc53 inline static bool patchSled(const bool Enable, const uint32_t FuncId, in patchSled() argument
97 if (Enable) { in patchSled()
137 bool patchFunctionEntry(const bool Enable, const uint32_t FuncId, in patchFunctionEntry() argument
140 return patchSled(Enable, FuncId, Sled, Trampoline); in patchFunctionEntry()
143 bool patchFunctionExit(const bool Enable, const uint32_t FuncId, in patchFunctionExit() argument
145 return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); in patchFunctionExit()
148 bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId, in patchFunctionTailExit() argument
152 return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); in patchFunctionTailExit()
155 bool patchCustomEvent(const bool Enable, const uint32_t FuncId, in patchCustomEvent() argument
161 bool patchTypedEvent(const bool Enable, const uint32_t FuncId, in patchTypedEvent() argument
H A Dxray_mips64.cc54 inline static bool patchSled(const bool Enable, const uint32_t FuncId, in patchSled() argument
93 if (Enable) { in patchSled()
146 bool patchFunctionEntry(const bool Enable, const uint32_t FuncId, in patchFunctionEntry() argument
149 return patchSled(Enable, FuncId, Sled, Trampoline); in patchFunctionEntry()
152 bool patchFunctionExit(const bool Enable, const uint32_t FuncId, in patchFunctionExit() argument
154 return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); in patchFunctionExit()
157 bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId, in patchFunctionTailExit() argument
161 return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); in patchFunctionTailExit()
164 bool patchCustomEvent(const bool Enable, const uint32_t FuncId, in patchCustomEvent() argument
170 bool patchTypedEvent(const bool Enable, const uint32_t FuncId, in patchTypedEvent() argument
H A Dxray_interface.cc150 bool patchSled(const XRaySledEntry &Sled, bool Enable, in patchSled() argument
155 Success = patchFunctionEntry(Enable, FuncId, Sled, __xray_FunctionEntry); in patchSled()
158 Success = patchFunctionExit(Enable, FuncId, Sled); in patchSled()
161 Success = patchFunctionTailExit(Enable, FuncId, Sled); in patchSled()
164 Success = patchFunctionEntry(Enable, FuncId, Sled, __xray_ArgLoggerEntry); in patchSled()
167 Success = patchCustomEvent(Enable, FuncId, Sled); in patchSled()
170 Success = patchTypedEvent(Enable, FuncId, Sled); in patchSled()
180 bool Enable) XRAY_NEVER_INSTRUMENT { in patchFunction() argument
215 SucceedOnce |= patchSled(*f++, Enable, FuncId); in patchFunction()
231 XRayPatchingStatus controlPatching(bool Enable) XRAY_NEVER_INSTRUMENT { in controlPatching() argument
[all …]
H A Dxray_x86_64.cc130 bool patchFunctionEntry(const bool Enable, const uint32_t FuncId, in patchFunctionEntry() argument
161 if (Enable) { in patchFunctionEntry()
177 bool patchFunctionExit(const bool Enable, const uint32_t FuncId, in patchFunctionExit() argument
206 if (Enable) { in patchFunctionExit()
222 bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId, in patchFunctionTailExit() argument
234 if (Enable) { in patchFunctionTailExit()
250 bool patchCustomEvent(const bool Enable, const uint32_t FuncId, in patchCustomEvent() argument
275 if (Enable) { in patchCustomEvent()
297 bool patchTypedEvent(const bool Enable, const uint32_t FuncId, in patchTypedEvent() argument
316 if (Enable) { in patchTypedEvent()
/netbsd-src/external/gpl3/binutils/dist/gas/doc/
H A Dc-aarch64.texi163 @tab Enable the AES and PMULL cryptographic extensions.
165 @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2.
167 @tab Enable BFloat16 extension.
169 @tab Enable the Check Feature Status Extension.
171 @tab Enable the complex number SIMD extensions. An alias of @code{fcma}.
173 @tab Enable CRC instructions.
175 @tab Enable cryptographic extensions. This is equivalent to @code{aes+sha2}.
177 @tab Enable the Armv8.9-A Common Short Sequence Compression instructions.
179 @tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}.
181 @tab Enable the Dot Product extension.
[all …]
H A Dc-csky.texi61 Enable/disable transformation of the short branch instructions
86 Enable/disable transformation of @code{jbsr} instructions to @code{bsr}.
99 Enable/disable transformation of @code{jsri} instructions to @code{bsr}.
106 Enable/disable transformation of @code{lrw} instructions into a
113 Enable/disable extended @code{lrw} instructions.
124 Enable/disable placement of literal pools after each function.
134 Enable/disable placement of literal pools after unconditional branches.
141 Enable/disable interrupt stack instructions. This option is enabled by
153 Enable hard float instructions.
157 Enable multiprocessor instructions.
[all …]
H A Dc-pdp11.texi57 Enable all instruction set extensions.
66 Enable (or disable) the use of the commercial instruction set, which
82 Enable (or disable) the use of the @code{CSM} instruction.
87 Enable (or disable) the use of the extended instruction set, which
99 Enable (or disable) the use of the KEV11 floating-point instructions:
110 Enable (or disable) the use of FP-11 floating-point instructions:
121 Enable (or disable) the use of the limited extended instruction set:
129 Enable (or disable) the use of the @code{MFPT} instruction.
134 Enable (or disable) the use of multiprocessor instructions: @code{TSTSET} and
140 Enable (or disable) the use of the @code{MFPS} and @code{MTPS} instructions.
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPC.td59 "Enable 64-bit instructions">;
65 "Enable floating-point instructions">;
67 "Enable 64-bit registers usage for ppc32 [beta]">;
71 "Enable classic FPU instructions",
74 "Enable Altivec instructions",
77 "Enable SPE instructions",
80 "Enable Embedded Floating-Point APU 2 instructions",
83 "Enable the MFOCRF instruction">;
85 "Enable the fsqrt instruction",
88 "Enable the fcpsgn instruction",
[all …]
/netbsd-src/external/gpl3/gdb/dist/gnulib/import/m4/
H A Dextensions.m42 # Enable extensions on systems that normally disable them.
38 # Enable extensions on systems that normally disable them,
55 [/* Enable extensions on AIX 3, Interix. */
59 /* Enable general extensions on macOS. */
63 /* Enable general extensions on Solaris. */
67 /* Enable GNU extensions on systems that have them. */
71 /* Enable X/Open compliant socket functions that do not require linking
82 /* Enable general extensions on NetBSD.
83 Enable NetBSD compatibility extensions on Minix. */
87 /* Enable OpenBSD compatibility extensions on NetBSD.
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64.td23 "Enable ARMv8 FP">;
26 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
30 "Enable SM3 and SM4 support", [FeatureNEON]>;
34 "Enable SHA1 and SHA256 support", [FeatureNEON]>;
38 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
42 "Enable AES support", [FeatureNEON]>;
53 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
56 "Enable ARMv8 CRC-32 checksum instructions">;
59 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
62 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssembly.td26 "Enable 128-bit SIMD">;
29 "Enable Atomics">;
34 "Enable non-trapping float-to-int conversion operators">;
39 "Enable sign extension operators">;
44 "Enable tail call instructions">;
48 "Enable Wasm exception handling">;
52 "Enable bulk memory operations">;
57 "Enable multivalue blocks, instructions, and functions">;
61 "Enable mutable globals">;
65 "Enable reference types">;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepArch.td11 def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V…
13 def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexago…
15 def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexago…
17 def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexago…
19 def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexago…
21 def ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V66", "Enable Hexago…
23 def ArchV67: SubtargetFeature<"v67", "HexagonArchVersion", "Hexagon::ArchEnum::V67", "Enable Hexago…
25 def ArchV68: SubtargetFeature<"v68", "HexagonArchVersion", "Hexagon::ArchEnum::V68", "Enable Hexago…
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arc/
H A Darc.opt132 Enable DIV-REM instructions for ARCv2.
136 Enable code density instructions for ARCv2.
150 Enable cache bypass for volatile references.
210 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
230 Enable generation of ARC SIMD instructions via target-specific builtins.
281 Enable the use of indexed loads.
285 Enable the use of pre/post modify with register displacement.
309 Enable Rcq constraint handling - most short code generation depends on this.
313 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
317 Enable pre-reload use of cbranchsi pattern.
[all …]
/netbsd-src/external/bsd/openpam/dist/
H A Dconfig.h.in122 /* Enable extensions on AIX 3, Interix. */
126 /* Enable general extensions on macOS. */
130 /* Enable general extensions on Solaris. */
134 /* Enable GNU extensions on systems that have them. */
138 /* Enable X/Open compliant socket functions that do not require linking
149 /* Enable general extensions on NetBSD.
150 Enable NetBSD compatibility extensions on Minix. */
154 /* Enable OpenBSD compatibility extensions on NetBSD.
167 /* Enable POSIX-compatible threading on Solaris. */
171 /* Enable extensions specified by ISO/IEC TS 18661-5:2014. */
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arc/
H A Darc.opt132 Enable DIV-REM instructions for ARCv2.
136 Enable code density instructions for ARCv2.
154 Enable cache bypass for volatile references.
214 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
234 Enable generation of ARC SIMD instructions via target-specific builtins.
285 Enable the use of indexed loads.
289 Enable the use of pre/post modify with register displacement.
315 Enable Rcq constraint handling - most short code generation depends on this.
319 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
323 Enable pre-reload use of cbranchsi pattern.
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetMachine.h240 void setFastISel(bool Enable) { Options.EnableFastISel = Enable; } in setFastISel() argument
242 void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; } in setO0WantsFastISel() argument
243 void setGlobalISel(bool Enable) { Options.EnableGlobalISel = Enable; } in setGlobalISel() argument
247 void setMachineOutliner(bool Enable) { in setMachineOutliner() argument
248 Options.EnableMachineOutliner = Enable; in setMachineOutliner()
250 void setSupportsDefaultOutlining(bool Enable) { in setSupportsDefaultOutlining() argument
251 Options.SupportsDefaultOutlining = Enable; in setSupportsDefaultOutlining()
253 void setSupportsDebugEntryValues(bool Enable) { in setSupportsDebugEntryValues() argument
254 Options.SupportsDebugEntryValues = Enable; in setSupportsDebugEntryValues()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/or1k/
H A Dor1k.opt29 Enable generation of hardware divide (l.div, l.divu) instructions. This is the
34 Enable generation of binaries which use functions from libgcc to perform divide
39 Enable generation of hardware multiply instructions (l.mul, l.muli) instructions.
44 Enable generation of binaries which use functions from libgcc to perform
49 Enable generation of binaries which use functions from libgcc to perform
54 Enable generation of hardware floating point instructions. The default is
87 Enable generation of conditional move (l.cmov) instructions. By default the
92 Enable generation of rotate right (l.ror) instructions. By default functions
97 Enable generation of rotate right with immediate (l.rori) instructions. By
103 Enable generation of sign extension (l.ext*) instructions. By default memory
[all …]
/netbsd-src/external/bsd/libevent/dist/
H A Devconfig-private.h.cmake5 /* Enable extensions on AIX 3, Interix. */
8 /* Enable GNU extensions on systems that have them. */
11 /* Enable threading extensions on Solaris. */
14 /* Enable extensions on HP NonStop. */
17 /* Enable general extensions on Solaris. */
35 /* Enable POSIX.2 extensions on QNX for getopt */
/netbsd-src/external/gpl3/binutils.old/dist/gas/doc/
H A Dc-csky.texi61 Enable/disable transformation of the short branch instructions
86 Enable/disable transformation of @code{jbsr} instructions to @code{bsr}.
99 Enable/disable transformation of @code{jsri} instructions to @code{bsr}.
106 Enable/disable transformation of @code{lrw} instructions into a
113 Enable/disable extended @code{lrw} instructions.
124 Enable/disable placement of literal pools after each function.
134 Enable/disable placement of literal pools after unconditional branches.
141 Enable/disable interrupt stack instructions. This option is enabled by
153 Enable hard float instructions.
157 Enable multiprocessor instructions.
[all …]
H A Dc-aarch64.texi160 @tab Enable the AES cryptographic extensions. This implies @code{fp} and
163 @tab Enable BFloat16 extension.
165 @tab Enable the complex number SIMD extensions. This implies @code{fp16} and
168 @tab Enable CRC instructions.
170 @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd},
173 @tab Enable the Dot Product extension. This implies @code{simd}.
175 @tab Enable F32 Matrix Multiply extension. This implies @code{sve}.
177 @tab Enable F64 Matrix Multiply extension. This implies @code{sve}.
179 @tab Enable Flag Manipulation instructions.
181 @tab Enable ARMv8.2 16-bit floating-point multiplication variant support. This
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DCGLoopInfo.h44 enum LVEnableState { Unspecified, Enable, Disable, Full }; enumerator
232 void setParallel(bool Enable = true) { StagedAttrs.IsParallel = Enable; }
235 void setVectorizeEnable(bool Enable = true) {
237 Enable ? LoopAttributes::Enable : LoopAttributes::Disable;
241 void setDistributeState(bool Enable = true) {
243 Enable ? LoopAttributes::Enable : LoopAttributes::Disable;
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/csky/
H A Dcsky.opt61 Enable hardware floating-point instructions.
85 Enable the extended LRW instruction (default for CK801).
89 Enable interrupt stack instructions.
93 Enable multiprocessor instructions.
97 Enable coprocessor instructions.
101 Enable cache prefetch instructions.
105 Enable C-SKY SECURE instructions.
112 Enable C-SKY TRUST instructions.
116 Enable C-SKY DSP instructions.
120 Enable C-SKY Enhanced DSP instructions.
[all …]

12345678910>>...69