Home
last modified time | relevance | path

Searched refs:DwarfRegNum (Results 1 – 25 of 25) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td104 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
106 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
107 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
108 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
112 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
113 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
114 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
115 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
116 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
117 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td52 def R0 : CSKYReg<0, "r0", ["a0"]>, DwarfRegNum<[0]>;
53 def R1 : CSKYReg<1, "r1", ["a1"]>, DwarfRegNum<[1]>;
54 def R2 : CSKYReg<2, "r2", ["a2"]>, DwarfRegNum<[2]>;
55 def R3 : CSKYReg<3, "r3", ["a3"]>, DwarfRegNum<[3]>;
56 def R4 : CSKYReg<4, "r4", ["l0"]>, DwarfRegNum<[4]>;
57 def R5 : CSKYReg<5, "r5", ["l1"]>, DwarfRegNum<[5]>;
58 def R6 : CSKYReg<6, "r6", ["l2"]>, DwarfRegNum<[6]>;
59 def R7 : CSKYReg<7, "r7", ["l3"]>, DwarfRegNum<[7]>;
60 def R8 : CSKYReg<8, "r8", ["l4"]>, DwarfRegNum<[8]>;
61 def R9 : CSKYReg<9, "r9", ["l5"]>, DwarfRegNum<[9]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td28 def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>;
29 def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>;
30 def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
31 def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>;
33 def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
34 def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
35 def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>;
36 def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
37 def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
38 def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td44 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
45 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
46 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
47 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
48 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
49 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
50 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
51 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
52 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
53 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td71 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
129 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
130 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
131 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
132 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
133 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
134 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
135 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
136 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
137 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td87 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
88 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
89 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
90 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
91 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
92 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
93 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
94 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
95 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
96 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td25 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
26 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
27 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
28 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
29 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
30 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
31 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
34 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td80 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
82 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
83 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
84 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
85 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
86 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
87 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
88 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
90 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>;
91 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86RegisterInfo.td143 def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>;
144 def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
145 def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;
146 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
147 def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>;
148 def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>;
149 def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>;
150 def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;
151 def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;
169 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td60 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
61 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
62 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
63 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>;
64 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>;
65 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>;
66 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>;
67 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>;
68 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>;
69 def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>;
[all …]
H A DAArch64ISelLowering.cpp7546 unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false); in getRegisterByName() local
7547 if (!Subtarget->isXRegisterReserved(DwarfRegNum)) in getRegisterByName()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td124 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
130 DwarfRegNum<[Index, -2]>;
136 DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>;
142 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
150 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
156 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
176 DwarfRegNum<[0, 0]>;
184 DwarfRegNum<[0, 0]>;
236 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
237 def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td77 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
78 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
79 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
80 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
81 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
82 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
83 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
84 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
87 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
88 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVERegisterInfo.td105 def SW#I : VEReg<I, "sw"#I, [], ["s"#I]>, DwarfRegNum<[I]>;
112 DwarfRegNum<[I]>;
117 def SX8 : VEReg<8, "s8", [SW8, SF8], ["s8", "sl"]>, DwarfRegNum<[8]>;
118 def SX9 : VEReg<9, "s9", [SW9, SF9], ["s9", "fp"]>, DwarfRegNum<[9]>;
119 def SX10 : VEReg<10, "s10", [SW10, SF10], ["s10", "lr"]>, DwarfRegNum<[10]>;
120 def SX11 : VEReg<11, "s11", [SW11, SF11], ["s11", "sp"]>, DwarfRegNum<[11]>;
121 def SX14 : VEReg<14, "s14", [SW14, SF14], ["s14", "tp"]>, DwarfRegNum<[14]>;
122 def SX15 : VEReg<15, "s15", [SW15, SF15], ["s15", "got"]>, DwarfRegNum<[15]>;
123 def SX16 : VEReg<16, "s16", [SW16, SF16], ["s16", "plt"]>, DwarfRegNum<[16]>;
128 ["s"#I]>, DwarfRegNum<[I]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp234 uint64_t DwarfRegNum; in prettyPrintRegisterOp() local
239 DwarfRegNum = Operands[OpNum++]; in prettyPrintRegisterOp()
241 DwarfRegNum = Opcode - DW_OP_breg0; in prettyPrintRegisterOp()
243 DwarfRegNum = Opcode - DW_OP_reg0; in prettyPrintRegisterOp()
245 if (Optional<unsigned> LLVMRegNum = MRI->getLLVMRegNum(DwarfRegNum, isEH)) { in prettyPrintRegisterOp()
416 uint64_t DwarfRegNum = Op.getRawOperand(0); in printCompactDWARFExpr() local
417 Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false); in printCompactDWARFExpr()
419 OS << "<unknown register " << DwarfRegNum << ">"; in printCompactDWARFExpr()
427 int DwarfRegNum = Op.getRawOperand(0); in printCompactDWARFExpr() local
429 Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false); in printCompactDWARFExpr()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DStackMaps.cpp249 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); in parseOperand() local
250 unsigned LLVMRegNum = *TRI->getLLVMRegNum(DwarfRegNum, false); in parseOperand()
256 DwarfRegNum, Offset); in parseOperand()
330 OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte " in print()
340 unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI); in createLiveOutReg() local
342 return LiveOutReg(Reg, DwarfRegNum, Size); in createLiveOutReg()
364 return LHS.DwarfRegNum < RHS.DwarfRegNum; in parseRegisterLiveOutMask()
369 if (I->DwarfRegNum != II->DwarfRegNum) { in parseRegisterLiveOutMask()
698 OS.emitInt16(LO.DwarfRegNum); in emitCallsiteEntries()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DStackMaps.h274 unsigned short DwarfRegNum = 0; member
278 LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum, in LiveOutReg()
280 : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {} in LiveOutReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td33 def W#I : Wi<I, "w"#I>, DwarfRegNum<[I]>;
35 def R#I : Ri<I, "r"#I, [!cast<Wi>("W"#I)]>, DwarfRegNum<[I]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td87 DwarfRegNum<[I]>;
228 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
233 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
262 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
336 def A#I : ACR32<I, "a"#I>, DwarfRegNum<[!add(I, 48)]>;
346 def C#I : CREG64<I, "c"#I>, DwarfRegNum<[!add(I, 32)]>;
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp401 for (auto &DwarfRegNum : DwarfRegNums) in EmitRegMappingTables() local
402 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I) in EmitRegMappingTables()
403 DwarfRegNum.second.push_back(-1); in EmitRegMappingTables()
422 for (auto &DwarfRegNum : DwarfRegNums) { in EmitRegMappingTables() local
423 int DwarfRegNo = DwarfRegNum.second[I]; in EmitRegMappingTables()
426 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first; in EmitRegMappingTables()
483 for (auto &DwarfRegNum : DwarfRegNums) { in EmitRegMappingTables() local
484 int RegNo = DwarfRegNum.second[i]; in EmitRegMappingTables()
488 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo in EmitRegMappingTables()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td26 def R#i : LanaiReg<i, "r"#i>, DwarfRegNum<[i]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td167 def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> {
181 defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>;
184 def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
278 DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
286 DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>;
293 DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td19 : Register<N, ALTNAMES>, DwarfRegNum<DWREGS> {
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DWritingAnLLVMBackend.rst366 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
368 This defines the register ``AL`` and assigns it values (with ``DwarfRegNum``)
370 register. For register ``AL``, ``DwarfRegNum`` takes an array of 3 values
457 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
458 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
460 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>;
461 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>;
463 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
464 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTarget.td391 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
395 class DwarfRegNum<list<int> Numbers> {