[SystemZ] Add support for new cpu architecture - arch15

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new pr

[SystemZ] Add support for new cpu architecture - arch15

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture. Once new systems become available, the
official system name will be added as supported -march name.

show more ...

TargetParser: AArch64: Add part numbers for Apple CPUs.

Part numbers taken from:
https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c

Reviewers: ahmedbougacha, jroelofs

Reviewed By: jroelof

TargetParser: AArch64: Add part numbers for Apple CPUs.

Part numbers taken from:
https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c

Reviewers: ahmedbougacha, jroelofs

Reviewed By: jroelofs

Pull Request: https://github.com/llvm/llvm-project/pull/119777

show more ...

[AArch64] Add initial support for FUJITSU-MONAKA (#118432)

This patch adds initial support for FUJITSU-MONAKA CPU (-mcpu=fujitsu-monaka).

The scheduling model will be corrected in the future.

[AArch64] Add missing tests for Arm cpus (#106749)

[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (#99511)

This PR adds support for -mcpu=pwr11/power11 and -mtune=pwr11/power11 in
clang and llvm.

[AArch64] Add support for Qualcomm Oryon processor (#91022)

Oryon is an ARM V8 AArch64 CPU from Qualcomm.

---------

Co-authored-by: Wei Zhao <wezhao@qti.qualcomm.com>

[AArch64] Add the Ampere1B core (#81297)

The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-chan

[AArch64] Add the Ampere1B core (#81297)

The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-channel mitigation and architectural support for
defense against ROP/JOP style software attacks.

Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT
WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all
features of the second-generation Ampere1A, such as the Memory Tagging
Extension and SM3/SM4 cryptography instructions.

show more ...

[AArch64] Add native CPU detection for Microsoft Azure Cobalt 100. (#77793)

This patch extends the -mcpu/mtune=native support to handle the
Microsoft Azure Cobalt 100 CPU as a Neoverse N2. We expec

[AArch64] Add native CPU detection for Microsoft Azure Cobalt 100. (#77793)

This patch extends the -mcpu/mtune=native support to handle the
Microsoft Azure Cobalt 100 CPU as a Neoverse N2. We expect users to use
-mcpu=neoverse-n2 when targeting this CPU and all the architecture and
codegen decisions to be identical.

The only difference is that the Microsoft Azure Cobalt 100 has a
different Implementer ID in the /proc/cpuinfo entry that needs to be
detected in getHostCPUNameForARM appropriately.

show more ...

[AArch64] Add the Ampere1A core

The Ampere1A core improves on the Ampere1 with key differences being:
* memory tagging is supported
* SM3/SM4 are supported
* adds a new fusion pair for (A+B+1 and

[AArch64] Add the Ampere1A core

The Ampere1A core improves on the Ampere1 with key differences being:
* memory tagging is supported
* SM3/SM4 are supported
* adds a new fusion pair for (A+B+1 and A-B-1)
(added in a later commit)

Depends on D142395

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D142396

show more ...

[Support] Move TargetParsers to new component

This is a fairly large changeset, but it can be broken into a few
pieces:
- `llvm/Support/*TargetParser*` are all moved from the LLVM Support
componen

[Support] Move TargetParsers to new component

This is a fairly large changeset, but it can be broken into a few
pieces:
- `llvm/Support/*TargetParser*` are all moved from the LLVM Support
component into a new LLVM Component called "TargetParser". This
potentially enables using tablegen to maintain this information, as
is shown in https://reviews.llvm.org/D137517. This cannot currently
be done, as llvm-tblgen relies on LLVM's Support component.
- This also moves two files from Support which use and depend on
information in the TargetParser:
- `llvm/Support/Host.{h,cpp}` which contains functions for inspecting
the current Host machine for info about it, primarily to support
getting the host triple, but also for `-mcpu=native` support in e.g.
Clang. This is fairly tightly intertwined with the information in
`X86TargetParser.h`, so keeping them in the same component makes
sense.
- `llvm/ADT/Triple.h` and `llvm/Support/Triple.cpp`, which contains
the target triple parser and representation. This is very intertwined
with the Arm target parser, because the arm architecture version
appears in canonical triples on arm platforms.
- I moved the relevant unittests to their own directory.

And so, we end up with a single component that has all the information
about the following, which to me seems like a unified component:
- Triples that LLVM Knows about
- Architecture names and CPUs that LLVM knows about
- CPU detection logic for LLVM

Given this, I have also moved `RISCVISAInfo.h` into this component, as
it seems to me to be part of that same set of functionality.

If you get link errors in your components after this patch, you likely
need to add TargetParser into LLVM_LINK_COMPONENTS in CMake.

Differential Revision: https://reviews.llvm.org/D137838

show more ...