[X86] Add missing reg/imm attributes to VRNDSCALES instruction names (#117203)

More canonicalization of the instruction names to make the predictable - more closely matches VRNDSCALEP / VROUND equiv

[X86] Add missing reg/imm attributes to VRNDSCALES instruction names (#117203)

More canonicalization of the instruction names to make the predictable - more closely matches VRNDSCALEP / VROUND equivalent instructions

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[X86] Remove unused includes (NFC) (#115593)

Identified with misc-include-cleaner.

[X86] Add missing immediate qualifier to the (V)INSERT/EXTRACT/PERM2 instruction names (#108593)

Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm work

[X86] Add missing immediate qualifier to the (V)INSERT/EXTRACT/PERM2 instruction names (#108593)

Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on

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[X86][CodeGen] Share code between CompressEVEX pass and ND2NonND transform, NFCI

[X86][CodeGen] Disable NDD2NonNDD compression for CFCMOV

[X86][CodeGen] Extend X86CompressEVEX for NF transform

[X86][tablgen] Extend X86CompressEVEXTablesEmitter for NF transform

The generated table will be used in #93508

[X86][CodeGen] Fix compile crash in EVEX compression for corner case

The base register of OPmi_ND may be allocated to the same physic
register as the ND operand.

OPmi_ND is not compressible b/c it

[X86][CodeGen] Fix compile crash in EVEX compression for corner case

The base register of OPmi_ND may be allocated to the same physic
register as the ND operand.

OPmi_ND is not compressible b/c it has different semnatic from OPmi.
In this case, `isRedundantNewDataDest` should return false, otherwise
we would get error

Assertion `!IsNDLike && "Missing entry for ND-like instruction"' failed.

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[X86][NFC] X86CompressEVEX.cpp - Simplify code after 0c623b58e39cba7e67a0049dbcac87fdcc0103e1

[X86] X86CompressEVEX.cpp - ensure we tie the operands on MOVBErr instructions

Minor correction for #79775 - noticed in EXPENSIVE_CHECKS builds

[X86] Silence -Wlogical-op-parentheses in X86CompressEVEX.cpp (NFC)

llvm-project/llvm/lib/Target/X86/X86CompressEVEX.cpp:233:15:
error: '&&' within '||' [-Werror,-Wlogical-op-parentheses]
if (!I

[X86] Silence -Wlogical-op-parentheses in X86CompressEVEX.cpp (NFC)

llvm-project/llvm/lib/Target/X86/X86CompressEVEX.cpp:233:15:
error: '&&' within '||' [-Werror,-Wlogical-op-parentheses]
if (!IsND && !IsMovberr || !isRedundantNewDataDest(MI, ST))
~~~~~~^~~~~~~~~~~~~ ~~
llvm-project/llvm/lib/Target/X86/X86CompressEVEX.cpp:233:15:
note: place parentheses around the '&&' expression to silence this warning
if (!IsND && !IsMovberr || !isRedundantNewDataDest(MI, ST))
^
( )
1 error generated.

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[X86] Support EVEX compression from MOVBErr to BSWAP (#79775)

APX promoted MOVBE instructions were supported in #77431. The reg2reg
variants of MOVBE are newly introduced by APX and can be optimize

[X86] Support EVEX compression from MOVBErr to BSWAP (#79775)

APX promoted MOVBE instructions were supported in #77431. The reg2reg
variants of MOVBE are newly introduced by APX and can be optimized to
BSWAP instruction when the 2 register operands are same.

This patch adds manual entries for MOVBErr instructions when we do ndd
to non-ndd compression #77731.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

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[X86][CodeGen] Add entries for NDD SHLD/SHRD to the commuteInstructionImpl

[X86][NFC] Auto-generate the function to check predicate for EVEX compression

[X86] Correct the asm comment for compression NF_ND -> NF

[X86][CodeGen] Support EVEX compression: NDD to nonNDD (#77731)

[X86] Emit NDD2NonNDD entris in the EVEX comprerssion table, NFCI

This patch is a straightfoward change based on the design in #77202.
It does not have any effect since we haven't supported compress

[X86] Emit NDD2NonNDD entris in the EVEX comprerssion table, NFCI

This patch is a straightfoward change based on the design in #77202.
It does not have any effect since we haven't supported compressing ND
to non-ND in X86CompressEVEX.cpp.

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[X86] Support EVEX compression for EGPR (#77202)

Compress promoted instruction (EVEX) to pre-promotion instruction
(legacy/VEX) when R16-R31 is not used.

Alternative of #77065

[X86][NFC] Remove duplicate comments in X86CompressEVEX.cpp

[X86][NFC] Avoid uselss iterations when emitting EVEX compression table

BTW, we relax the condition for EVEX compression from
ST.hasAVX512() to ST.hasEGPR() || ST.hasAVX512(). It does not have any
e

[X86][NFC] Avoid uselss iterations when emitting EVEX compression table

BTW, we relax the condition for EVEX compression from
ST.hasAVX512() to ST.hasEGPR() || ST.hasAVX512(). It does not have any
effect now b/c no APX instruction is in the EVEX compression table so
far.

This patch is to extract NFC in #77065 into a separate commit.

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[X86][NFC] Use single table for EVEX compression

This patch is to address my review comments in #77065 to simplify the
implemention of EVEX2Legacy compression.

[X86][NFC] Rename variables/passes for EVEX compression optimization

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031

APX introduces EGPR, NDD and NF instruct

[X86][NFC] Rename variables/passes for EVEX compression optimization

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031

APX introduces EGPR, NDD and NF instructions. In addition to compressing
EVEX encoded AVX512 instructions into VEX encoding, we also have several
more possible optimizations.

a. Promoted instruction (EVEX space) -> pre-promotion instruction (legacy space)
b. NDD (EVEX space) -> non-NDD (legacy space)
c. NF_ND (EVEX space) -> NF (EVEX space)

The first two types of compression can usually reduce code size, while
the third type of compression can help hardware decode although the
instruction length remains unchanged.

So we do the renaming for the upcoming APX optimizations.

BTW, I clang-format the code in X86CompressEVEX.cpp,
X86CompressEVEXTablesEmitter.cpp.

This patch also extracts the NFC in #77065 into a separate commit.

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