[CodeGen] Use MCRegister instead of MCPhysReg in VirtRegMap. NFC

The callers of these methods already use MCRegister.

[CodeGen] Remove unused argument from getCoveringSubRegIndexes. NFC. (#122884)

RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)

Try to use DiagnosticInfo if every register in the class is reserved
by forcing assignment to a reserved register.

RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)

Try to use DiagnosticInfo if every register in the class is reserved
by forcing assignment to a reserved register. Also reduces the number
of redundant errors emitted, particularly with fast.

This is still broken in the case of undef uses. There are additional
complications in greedy and fast, so leave it for a separate fix.

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[CodeGen][PM] Initialize analyses with isAnalysis=true (#118779)

Analyses should be marked as analyses.

Otherwise they are prone to get ignored by the legacy analysis cache mechanism and get sche

[CodeGen][PM] Initialize analyses with isAnalysis=true (#118779)

Analyses should be marked as analyses.

Otherwise they are prone to get ignored by the legacy analysis cache mechanism and get scheduled redundantly.

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[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)

[CodeGen][NewPM] Port LiveDebugVariables to NPM (#115468)

The existing analysis was already a pimpl wrapper.

I have extracted legacy pass logic to a LDVImpl wrapper named
`LiveDebugVariables` wh

[CodeGen][NewPM] Port LiveDebugVariables to NPM (#115468)

The existing analysis was already a pimpl wrapper.

I have extracted legacy pass logic to a LDVImpl wrapper named
`LiveDebugVariables` which is the analysis::Result now. This controls
whether to activate the LDV (depending on `-live-debug-variables` and
DIsubprogram) itself.

The legacy and new analysis only construct the LiveDebugVariables.

VirtRegRewriter will test this.

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VirtRegRewriter: Add implicit register defs for live out undef lanes (#112679)

If an undef subregister def is live into another block, we need to
maintain a physreg def to track the liveness of tho

VirtRegRewriter: Add implicit register defs for live out undef lanes (#112679)

If an undef subregister def is live into another block, we need to
maintain a physreg def to track the liveness of those lanes. This
would manifest a verifier error after branch folding, when the cloned
tail block use no longer had a def.

We need to detect interference with other assigned intervals to avoid
clobbering the undef lanes defined in other intervals, since the undef
def didn't count as interference. This is pretty ugly and adds a new
dependency on LiveRegMatrix, keeping it live for one more pass. It also
adds a lot of implicit operand spam (we really should have a better
representation for this).

There is a missing verifier check for this situation. Added an xfailed
test that demonstrates this. We may also be able to revert the changes
in 47d3cbcf842a036c20c3f1c74255cdfc213f41c2.

It might be better to insert an IMPLICIT_DEF before the instruction
rather than using the implicit-def operand.

Fixes #98474

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[NewPM][CodeGen] Port VirtRegMap to NPM (#109936)

[VirtRegMap] Store MCRegister in Virt2PhysMap. (#108775)

Remove NO_PHYS_REG in favor of MCRegister() and converting MCRegister to
bool.

[VirtRegMap] Remove unnecessary calls to Register::id() accessing IndexMaps.

VirtReg2IndexFunctor already takes a Register.

[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use

[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.

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[CodeGen][NewPM] Port `SlotIndexes` to new pass manager (#97941)

- Add `SlotIndexesAnalysis`.
- Add `SlotIndexesPrinterPass`.
- Use `SlotIndexesWrapperPass` in legacy pass.

[NFC][LLVM][CodeGen] Move LiveDebugVariables.h into llvm/include/llvm/CodeGen (#88374)

This patch make `LiveDebugVariables` can be used by passes outside of
`lib/CodeGen`.

If we run a pass that

[NFC][LLVM][CodeGen] Move LiveDebugVariables.h into llvm/include/llvm/CodeGen (#88374)

This patch make `LiveDebugVariables` can be used by passes outside of
`lib/CodeGen`.

If we run a pass that occurs between the split register allocation pass
without preserving this pass, it will be freed and recomputed until it
encounters the next pass that needs LiveDebugVariables.

However, `LiveDebugVariables` will raise an assertion due to the pass
being freed without emitting a debug value.

This is reason we need `LiveDebugVariables` to be available for passes
outside of lib/Codegen.

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[SlotIndexes] Use upper/lower bound terminology for MBB searches. NFC. (#68802)

Rename advanceMBBIndex and findMBBIndex to getMBBLowerBound and add
getMBBUpperBound.

The motivations are:
- Make

[SlotIndexes] Use upper/lower bound terminology for MBB searches. NFC. (#68802)

Rename advanceMBBIndex and findMBBIndex to getMBBLowerBound and add
getMBBUpperBound.

The motivations are:
- Make it clear what kind of search is being done, using names inspired
by std::upper/lower_bound.
- Simplify getMBBFromIndex which really wants an upper bound search and
previously had to work hard to get the result it wanted from a lower
bound search.

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[VirtRegMap] Simplify condition after #65729

Clean up strange uses of getAnalysisIfAvailable (#65729)

After a pass calls addRequired<X>() it is strange to call
getAnalysisIfAvailable<X>() because analysis X should always be
available. Use ge

Clean up strange uses of getAnalysisIfAvailable (#65729)

After a pass calls addRequired<X>() it is strange to call
getAnalysisIfAvailable<X>() because analysis X should always be
available. Use getAnalysis<X>() instead.

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Fix typos in comments

[MC] Add MCRegisterInfo::regunits for iteration over register units

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098

Fix uninitialized pointer members in CodeGen

This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.

Reviewed By: LuoYuanke

Differentia

Fix uninitialized pointer members in CodeGen

This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D148303

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[CodeGen] Fix type of MachineRegisterInfo::RegAllocHints. NFC.

The first member of the pair should be unsigned instead of Register
because it is the hint type, 0 for simple (target independent) hint

[CodeGen] Fix type of MachineRegisterInfo::RegAllocHints. NFC.

The first member of the pair should be unsigned instead of Register
because it is the hint type, 0 for simple (target independent) hints and
other values for target dependent hints.

Differential Revision: https://reviews.llvm.org/D146646

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Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part

Use deduction guides instead of helper functions.

The only non-automatic changes have been:

1. ArrayRef(some_uint8_pointer, 0

Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part

Use deduction guides instead of helper functions.

The only non-automatic changes have been:

1. ArrayRef(some_uint8_pointer, 0) needs to be changed into ArrayRef(some_uint8_pointer, (size_t)0) to avoid an ambiguous call with ArrayRef((uint8_t*), (uint8_t*))
2. CVSymbol sym(makeArrayRef(symStorage)); needed to be rewritten as CVSymbol sym{ArrayRef(symStorage)}; otherwise the compiler is confused and thinks we have a (bad) function prototype. There was a few similar situation across the codebase.
3. ADL doesn't seem to work the same for deduction-guides and functions, so at some point the llvm namespace must be explicitly stated.
4. The "reference mode" of makeArrayRef(ArrayRef<T> &) that acts as no-op is not supported (a constructor cannot achieve that).

Per reviewers' comment, some useless makeArrayRef have been removed in the process.

This is a follow-up to https://reviews.llvm.org/D140896 that introduced
the deduction guides.

Differential Revision: https://reviews.llvm.org/D140955

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[NFC] Use Register instead of unsigned for variables that receive a Register object

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D139451

[CodeGen] Use MachineInstr::operands (NFC)

[llvm] Use make_early_inc_range (NFC)

[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned

Register allocation may spill virtual registers to the stack, which can
increase alignment requirements of the stack frame

[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned

Register allocation may spill virtual registers to the stack, which can
increase alignment requirements of the stack frame. If the the function
did not require stack realignment before register allocation, the
registers required to do so may not be reserved/available. This results
in a stack frame that requires realignment but can not be realigned.

Instead, only increase the alignment of the stack if we are still able
to realign.

The register SpillAlignment will be ignored if we can't realign, and the
backend will be responsible for emitting the correct unaligned loads and
stores. This seems to be the assumed behaviour already, e.g.
ARMBaseInstrInfo::storeRegToStackSlot and X86InstrInfo::storeRegToStackSlot
are both `canRealignStack` aware.

Differential Revision: https://reviews.llvm.org/D103602

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