lib: add new interface supporting AVX2 with GFNI

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

Remove all slver legacy segments

The relic slver is no longer used for individual versioning
on functions and is confusing tools looking for data in text
sections. This removes all instances instead

Remove all slver legacy segments

The relic slver is no longer used for individual versioning
on functions and is confusing tools looking for data in text
sections. This removes all instances instead of fixing since
its usefulness is waining. Fixes #221

Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Properly add .note.gnu.property section to assembly codes

1. Revert "x86: Generate .note.gnu.property section for ELF output"

This reverts commit 8074e3fe1b9398a9d3b717267790050fc5041594, which is

Properly add .note.gnu.property section to assembly codes

1. Revert "x86: Generate .note.gnu.property section for ELF output"

This reverts commit 8074e3fe1b9398a9d3b717267790050fc5041594, which is
a hack to work around the old nasm which doesn't support

section .note.gnu.property note alloc noexec align=8

This hack doesn't work for downstream, like:

https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=2040091

2. If Intel CET is enabled, require nasm with note section support to
add

section .note.gnu.property note alloc noexec align=N

to assembly codes.

Verified with

$ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
$ make -j8

on Tiger Lake.

Change-Id: I6d66fe6fd054420d7fde35b1508ca9f09defdeca
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

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x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to
funct

x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to
function entries in x86 assembly codes which are indirect branch
targets as discovered by running testsuite on Intel CET machine and
visual inspection.

Verified with

$ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
$ make -j8
$ make -j8 check

with both nasm and yasm on both CET and non-CET machines.

Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

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build: Fix for windows to allow nasm use

Previously windows build could only use yasm because some procedural items such
as proc_start were not supported by nasm. This adds a few macros and fixes s

build: Fix for windows to allow nasm use

Previously windows build could only use yasm because some procedural items such
as proc_start were not supported by nasm. This adds a few macros and fixes so
nasm can be used to build on windows.

Change-Id: Ia05dc3ff482f33b0f915bb1be3c7df5e4a753b3a
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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build: Add multi-binary checking for new arch

Change-Id: I8bb8d9e9ae28987ee583976871ff84ee205bdbdc
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>

build: Fix for mac nasm lack of symbol types

Change-Id: I9ee86a3e32876d3860477c8365fc459d94a8920e
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

build: Fix warnings on mac for objects defining no symbols

Change-Id: I13ef334ae23a3370cbf2a5409974fa0dc9fba7a5
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

multibinary: move WRT_OPT macro to common header

Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com>

Format only patch from iindent and remove_whitespace

Change-Id: I114bfcfa8750c7ba3a50ad2be9dd9e87cb7a1042
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

igzip: Avx512 version for encdode_df

Change-Id: I1625a3d7e016805791cfd09e31909562f432fd71
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>

Add crc unit

New crc unit adds three different polynomials: T10dif, ieee and iscsi.

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

Add avx512 versions of ec_encode_data

- Includes gf_nvect_dot_prod, gf_nvect_mad functions
- Change ec multibinary to use common macros
- Autoconf checks for nasm or yasm support and picks if ava

Add avx512 versions of ec_encode_data

- Includes gf_nvect_dot_prod, gf_nvect_mad functions
- Change ec multibinary to use common macros
- Autoconf checks for nasm or yasm support and picks if available
- Leave out compile of any avx512 code if assembler not available

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Initial commit isa-l v2.14.1

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>