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/llvm-project/llvm/lib/TargetParser/
H A DTargetParser.cpp1 //===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
9 // This file implements a target parser to recognise hardware features such as
27 unsigned Features; member
31 // Name Canonical Kind Features
62 // Don't bother listing the implicitly true features
65 // Name Canonical Kind Features
208 return Entry->Features; in getArchAttrR600()
214 return Entry->Features; in fillValidArchListAMDGCN()
291 // restricted in terms of features. in getIsaVersion()
323 StringMap<bool> &Features) { in fillAMDGPUFeatureMap()
316 fillAMDGPUFeatureMap(StringRef GPU,const Triple & T,StringMap<bool> & Features) fillAMDGPUFeatureMap() argument
620 insertWaveSizeFeature(StringRef GPU,const Triple & T,StringMap<bool> & Features,std::string & ErrorMsg) insertWaveSizeFeature() argument
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H A DCSKYTargetParser.cpp1 //===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
10 // This file implements a target parser to recognise CSKY hardware features
21 std::vector<StringRef> &Features) { in getFPUFeatures() argument
28 Features.push_back("+fpuv2_sf"); in getFPUFeatures()
29 Features.push_back("+fpuv2_df"); in getFPUFeatures()
30 Features.push_back("+fdivdu"); in getFPUFeatures()
33 Features.push_back("+fpuv2_sf"); in getFPUFeatures()
34 Features.push_back("+fpuv2_df"); in getFPUFeatures()
37 Features.push_back("+fpuv2_sf"); in getFPUFeatures()
38 Features.push_back("+fpuv2_df"); in getFPUFeatures()
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H A DHost.cpp444 // Look for the CPU features. in getHostCPUNameForRISCV()
447 if (Lines[I].starts_with("features")) { in getHostCPUNameForRISCV()
648 // Read control register 0 (XCR0). Used to detect features such as AVX. in getIntelProcessorTypeAndSubtype() argument
682 #define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0 in getIntelProcessorTypeAndSubtype()
686 const unsigned *Features, in getIntelProcessorTypeAndSubtype()
1087 const unsigned *Features, in getAMDProcessorTypeAndSubtype()
1261 unsigned *Features) { in getAvailableFeatures()
1265 Features[F / 32] |= 1U << (F % 32); in getAvailableFeatures()
1404 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; in getHostCPUName()
1406 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); in getHostCPUName()
1009 getAMDProcessorTypeAndSubtype(unsigned Family,unsigned Model,const unsigned * Features,unsigned * Type,unsigned * Subtype) getAMDProcessorTypeAndSubtype() argument
1163 getAvailableFeatures(unsigned ECX,unsigned EDX,unsigned MaxLeaf,unsigned * Features) getAvailableFeatures() argument
1306 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; getHostCPUName() local
1649 getHostCPUFeatures(StringMap<bool> & Features) getHostCPUFeatures() argument
1845 getHostCPUFeatures(StringMap<bool> & Features) getHostCPUFeatures() argument
1914 getHostCPUFeatures(StringMap<bool> & Features) getHostCPUFeatures() argument
1926 getHostCPUFeatures(StringMap<bool> & Features) getHostCPUFeatures() argument
1942 getHostCPUFeatures(StringMap<bool> & Features) getHostCPUFeatures() argument
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNProcessors.td24 FeatureISAVersion6_0_0.Features
28 FeatureISAVersion6_0_0.Features
32 FeatureISAVersion6_0_1.Features
36 FeatureISAVersion6_0_1.Features
40 FeatureISAVersion6_0_1.Features
44 FeatureISAVersion6_0_2.Features
48 FeatureISAVersion6_0_2.Features
52 FeatureISAVersion6_0_2.Features
60 FeatureISAVersion7_0_0.Features
64 FeatureISAVersion7_0_0.Features
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/llvm-project/compiler-rt/test/metadata/
H A Dcovered.cpp22 // CHECK-C: empty: features=0
25 // CHECK-CA: empty: features=0
26 // CHECK-CU: empty: features=0
28 // CHECK-CAU: empty: features=0
31 // CHECK-C: normal: features=0
32 // CHECK-A: normal: features=1
33 // CHECK-U: normal: features=2
34 // CHECK-CA: normal: features=1
35 // CHECK-CU: normal: features=2
36 // CHECK-AU: normal: features=3
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/llvm-project/clang/test/SemaOpenCL/
H A Dfeatures.cl2 // RUN: | FileCheck -match-full-lines %s --check-prefix=NO-FEATURES
4 // RUN: | FileCheck -match-full-lines %s --check-prefix=FEATURES
6 // RUN: | FileCheck -match-full-lines %s --check-prefix=NO-FEATURES
8 // RUN: | FileCheck -match-full-lines %s --check-prefix=FEATURES
10 // RUN: | FileCheck -match-full-lines %s --check-prefix=NO-FEATURES
12 // RUN: | FileCheck -match-full-lines %s --check-prefix=FEATURES
14 // RUN: | FileCheck -match-full-lines %s --check-prefix=NO-FEATURES
16 // RUN: | FileCheck -match-full-lines %s --check-prefix=FEATURES
21 // RUN: | FileCheck -match-full-lines %s --check-prefix=NO-FEATURES
23 // RUN: | FileCheck -match-full-lines %s --check-prefix=NO-FEATURES
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/llvm-project/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/
H A Dfuchsia.inc1 #include <zircon/features.h>
5 if (__atomic_load_n(&__aarch64_cpu_features.features, __ATOMIC_RELAXED))
11 uint32_t features;
12 zx_status_t status = _zx_system_get_features(ZX_FEATURE_KIND_CPU, &features);
19 if (features & ZX_ARM64_FEATURE_ISA_FP)
21 if (features & ZX_ARM64_FEATURE_ISA_ASIMD)
23 if (features & ZX_ARM64_FEATURE_ISA_PMULL)
25 if (features & ZX_ARM64_FEATURE_ISA_SHA256)
27 if (features & ZX_ARM64_FEATURE_ISA_CRC32)
29 if (features
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H A Dapple.inc33 static uint64_t deriveImplicitFeatures(uint64_t features) {
35 features |= (1ULL << FEAT_FP);
37 features |= (1ULL << FEAT_INIT);
39 return features;
48 if (__atomic_load_n(&__aarch64_cpu_features.features, __ATOMIC_RELAXED))
51 uint64_t features = 0;
64 features |= (1ULL << TO); \
98 features = deriveImplicitFeatures(features);
100 __atomic_store(&__aarch64_cpu_features.features,
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/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DAArch64.cpp73 // Decode AArch64 features from string like +[no]featureA+[no]featureB+...
140 llvm::AArch64::ExtensionSet &Extensions, std::vector<StringRef> &Features) { in getAArch64ArchFeaturesFromMcpu()
149 Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
159 std::vector<StringRef> &Features) { in getAArch64MicroArchFeaturesFromMtune()
174 Features.push_back("+zcm");
175 Features.push_back("+zcz");
184 std::vector<StringRef> &Features) { in getAArch64MicroArchFeaturesFromMcpu()
192 return getAArch64MicroArchFeaturesFromMtune(D, CPU, Args, Features); in getAArch64TargetFeatures() argument
198 std::vector<StringRef> &Features, in getAArch64TargetFeatures()
220 Features); in getAArch64TargetFeatures()
153 getAArch64MicroArchFeaturesFromMtune(const Driver & D,StringRef Mtune,const ArgList & Args,std::vector<StringRef> & Features) getAArch64MicroArchFeaturesFromMtune() argument
178 getAArch64MicroArchFeaturesFromMcpu(const Driver & D,StringRef Mcpu,const ArgList & Args,std::vector<StringRef> & Features) getAArch64MicroArchFeaturesFromMcpu() argument
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H A DSparc.cpp135 std::vector<StringRef> &Features) { in getSparcTargetFeatures()
138 Features.push_back("+soft-float"); in getSparcTargetFeatures()
142 Features.push_back("+fsmuld"); in getSparcTargetFeatures()
144 Features.push_back("-fsmuld"); in getSparcTargetFeatures()
149 Features.push_back("+popc"); in getSparcTargetFeatures()
151 Features.push_back("-popc"); in getSparcTargetFeatures()
156 Features.push_back("+vis"); in getSparcTargetFeatures()
158 Features.push_back("-vis"); in getSparcTargetFeatures()
163 Features.push_back("+vis2"); in getSparcTargetFeatures()
165 Features in getSparcTargetFeatures()
134 getSparcTargetFeatures(const Driver & D,const ArgList & Args,std::vector<StringRef> & Features) getSparcTargetFeatures() argument
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H A DRISCV.cpp30 std::vector<StringRef> &Features, in getArchFeatures() argument
47 Features.push_back(Args.MakeArgString(Str)); in getArchFeatures()
50 Features.push_back(Args.MakeArgString("+experimental")); in getArchFeatures()
55 // Get features except standard extension feature
59 std::vector<StringRef> &Features) { in getRISCFeaturesFromMcpu() argument
74 std::vector<StringRef> &Features) { in getRISCVTargetFeatures() argument
77 if (!getArchFeatures(D, MArch, Features, Args)) in getRISCVTargetFeatures()
84 // and other features (ex. mirco architecture feature) from mcpu in getRISCVTargetFeatures()
90 getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features); in getRISCVTargetFeatures()
98 // Handle features correspondin in getRISCVTargetFeatures()
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H A DM68k.cpp69 std::vector<llvm::StringRef> &Features) { in addFloatABIFeatures() argument
74 Features.push_back("-isa-68881"); in addFloatABIFeatures()
75 Features.push_back("-isa-68882"); in addFloatABIFeatures()
84 Features.push_back("+isa-68881"); in addFloatABIFeatures()
90 Features.push_back("+isa-68882"); in addFloatABIFeatures()
95 std::vector<StringRef> &Features) { in getM68kTargetFeatures() argument
96 addFloatABIFeatures(Args, Features); in getM68kTargetFeatures()
100 Features.push_back("+reserve-a0"); in getM68kTargetFeatures()
102 Features.push_back("+reserve-a1"); in getM68kTargetFeatures()
104 Features.push_back("+reserve-a2"); in getM68kTargetFeatures()
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H A DX86.cpp121 std::vector<StringRef> &Features) { in getX86TargetFeatures() argument
135 Features.push_back( in getX86TargetFeatures()
141 // x86_64h implies quite a few of the more modern subtarget features in getX86TargetFeatures()
143 Features.push_back("-rdrnd"); in getX86TargetFeatures()
144 Features.push_back("-aes"); in getX86TargetFeatures()
145 Features.push_back("-pclmul"); in getX86TargetFeatures()
146 Features.push_back("-rtm"); in getX86TargetFeatures()
147 Features.push_back("-fsgsbase"); in getX86TargetFeatures()
151 // Add features to be compatible with gcc for Android. in getX86TargetFeatures()
154 Features in getX86TargetFeatures()
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H A DLoongArch.cpp132 std::vector<StringRef> &Features) { in getLoongArchTargetFeatures()
136 Features.push_back("+lsx"); in getLoongArchTargetFeatures()
143 Features.push_back("+relax"); in getLoongArchTargetFeatures()
152 Features.push_back("-relax"); in getLoongArchTargetFeatures()
161 llvm::LoongArch::getArchFeatures(ArchName, Features); in getLoongArchTargetFeatures()
164 Features.push_back( in getLoongArchTargetFeatures()
167 // Select floating-point features determined by -mdouble-float, in getLoongArchTargetFeatures()
174 Features.push_back("+f"); in getLoongArchTargetFeatures()
175 Features.push_back("+d"); in getLoongArchTargetFeatures()
177 Features in getLoongArchTargetFeatures()
129 getLoongArchTargetFeatures(const Driver & D,const llvm::Triple & Triple,const ArgList & Args,std::vector<StringRef> & Features) getLoongArchTargetFeatures() argument
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H A DARM.cpp102 std::vector<StringRef> &Features) { in DecodeARMFeatures()
104 if (!llvm::ARM::getHWDivFeatures(HWDivID, Features)) in DecodeARMFeatures()
111 std::vector<StringRef> &Features) { in DecodeARMFeatures()
113 if (!llvm::ARM::getFPUFeatures(FPUKind, Features)) in DecodeARMFeaturesFromCPU()
118 // Decode ARM features from string like +[no]featureA+[no]featureB+... in DecodeARMFeaturesFromCPU()
121 std::vector<StringRef> &Features, in DecodeARMFeaturesFromCPU()
127 if (!appendArchExtFeatures(CPU, ArchKind, Feature, Features, ArgFPUKind)) in checkARMArchName()
134 std::vector<StringRef> &Features) { in checkARMArchName()
139 llvm::ARM::getExtensionFeatures(Extension, Features); in checkARMArchName()
148 std::vector<StringRef> &Features, in checkARMCPUName()
82 getARMHWDivFeatures(const Driver & D,const Arg * A,const ArgList & Args,StringRef HWDiv,std::vector<StringRef> & Features) getARMHWDivFeatures() argument
91 getARMFPUFeatures(const Driver & D,const Arg * A,const ArgList & Args,StringRef FPU,std::vector<StringRef> & Features) getARMFPUFeatures() argument
101 DecodeARMFeatures(const Driver & D,StringRef text,StringRef CPU,llvm::ARM::ArchKind ArchKind,std::vector<StringRef> & Features,llvm::ARM::FPUKind & ArgFPUKind) DecodeARMFeatures() argument
114 DecodeARMFeaturesFromCPU(const Driver & D,StringRef CPU,std::vector<StringRef> & Features) DecodeARMFeaturesFromCPU() argument
128 checkARMArchName(const Driver & D,const Arg * A,const ArgList & Args,llvm::StringRef ArchName,llvm::StringRef CPUName,std::vector<StringRef> & Features,const llvm::Triple & Triple,llvm::ARM::FPUKind & ArgFPUKind) checkARMArchName() argument
146 checkARMCPUName(const Driver & D,const Arg * A,const ArgList & Args,llvm::StringRef CPUName,llvm::StringRef ArchName,std::vector<StringRef> & Features,const llvm::Triple & Triple,llvm::ARM::FPUKind & ArgFPUKind) checkARMCPUName() argument
490 getARMTargetFeatures(const Driver & D,const llvm::Triple & Triple,const ArgList & Args,std::vector<StringRef> & Features,bool ForAS,bool ForMultilib) getARMTargetFeatures() argument
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H A DMips.cpp187 std::vector<StringRef> &Features) { in getMIPSTargetFeatures() argument
257 Features.push_back("+noabicalls"); in getMIPSTargetFeatures()
259 Features.push_back("-noabicalls"); in getMIPSTargetFeatures()
264 Features.push_back("-long-calls"); in getMIPSTargetFeatures()
266 Features.push_back("+long-calls"); in getMIPSTargetFeatures()
273 Features.push_back("+xgot"); in getMIPSTargetFeatures()
275 Features.push_back("-xgot"); in getMIPSTargetFeatures()
283 Features.push_back("+soft-float"); in getMIPSTargetFeatures()
290 Features.push_back("+nan2008"); in getMIPSTargetFeatures()
293 Features in getMIPSTargetFeatures()
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/llvm-project/llvm/test/CodeGen/X86/
H A Dnorex-subreg.ll55 %Features.6.or35 = select i1 %cmp33, i32 0, i32 undef
57 %or40 = or i32 %Features.6.or35, 4
58 %Features.8 = select i1 %cmp38, i32 %Features.6.or35, i32 %or40
60 %or45 = or i32 %Features.8, 2
62 %Features.8.or45 = select i1 %cmp43, i32 %Features.8, i32 %or45
65 %or50 = or i32 %Features.8.or45, 32
66 %Features.10 = select i1 %cmp48, i32 %Features.8.or45, i32 %or50
67 %or55 = or i32 %Features.10, 64
68 %Features.10.or55 = select i1 undef, i32 %Features.10, i32 %or55
72 %Features.12 = or i32 %Features.10.or55, %or60
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/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRELFStreamer.cpp10 static unsigned getEFlagsForFeatureSet(const FeatureBitset &Features) {
14 if (Features[AVR::ELFArchAVR1]) in getEFlagsForFeatureSet()
16 else if (Features[AVR::ELFArchAVR2]) in getEFlagsForFeatureSet()
18 else if (Features[AVR::ELFArchAVR25]) in getEFlagsForFeatureSet()
20 else if (Features[AVR::ELFArchAVR3]) in getEFlagsForFeatureSet()
22 else if (Features[AVR::ELFArchAVR31]) in getEFlagsForFeatureSet()
24 else if (Features[AVR::ELFArchAVR35]) in getEFlagsForFeatureSet()
26 else if (Features[AVR::ELFArchAVR4]) in getEFlagsForFeatureSet()
28 else if (Features[AVR::ELFArchAVR5]) in getEFlagsForFeatureSet()
30 else if (Features[AV in getEFlagsForFeatureSet()
13 getEFlagsForFeatureSet(const FeatureBitset & Features) getEFlagsForFeatureSet() argument
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/llvm-project/llvm/lib/Support/BLAKE3/
H A Dblake3_dispatch.c95 enum cpu_feature features = 0; in get_cpu_features() local
100 features |= SSE2; in get_cpu_features()
103 features |= SSE2; in get_cpu_features()
106 features |= SSSE3; in get_cpu_features()
108 features |= SSE41; in get_cpu_features()
114 features |= AVX; in get_cpu_features()
118 features |= AVX2; in get_cpu_features()
121 features |= AVX512VL; in get_cpu_features()
123 features |= AVX512F; in get_cpu_features()
128 g_cpu_features = features; in get_cpu_features()
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/llvm-project/llvm/lib/Object/
H A DELFObjectFile.cpp101 SubtargetFeatures Features; in getMIPSFeatures()
108 Features.AddFeature("mips2"); in getMIPSFeatures()
111 Features.AddFeature("mips3"); in getMIPSFeatures()
114 Features.AddFeature("mips4"); in getMIPSFeatures()
117 Features.AddFeature("mips5"); in getMIPSFeatures()
120 Features.AddFeature("mips32"); in getMIPSFeatures()
123 Features.AddFeature("mips64"); in getMIPSFeatures()
126 Features.AddFeature("mips32r2"); in getMIPSFeatures()
129 Features.AddFeature("mips64r2"); in getMIPSFeatures()
132 Features in getMIPSFeatures()
102 SubtargetFeatures Features; getMIPSFeatures() local
162 SubtargetFeatures Features; getARMFeatures() local
319 SubtargetFeatures Features; getHexagonFeatures() local
367 SubtargetFeatures Features; getRISCVFeatures() local
401 SubtargetFeatures Features; getLoongArchFeatures() local
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/llvm-project/clang/lib/Basic/Targets/
H A DWebAssembly.cpp119 void WebAssemblyTargetInfo::setSIMDLevel(llvm::StringMap<bool> &Features, in setSIMDLevel()
124 Features["relaxed-simd"] = true; in setSIMDLevel()
127 Features["simd128"] = true; in setSIMDLevel()
138 Features["simd128"] = false;
141 Features["relaxed-simd"] = false; in setFeatureEnabled()
146 void WebAssemblyTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, in setFeatureEnabled()
150 setSIMDLevel(Features, SIMD128, Enabled); in initFeatureMap()
152 setSIMDLevel(Features, RelaxedSIMD, Enabled); in initFeatureMap()
154 Features[Name] = Enabled; in initFeatureMap()
158 llvm::StringMap<bool> &Features, DiagnosticsEngin in initFeatureMap()
112 setSIMDLevel(llvm::StringMap<bool> & Features,SIMDEnum Level,bool Enabled) setSIMDLevel() argument
139 setFeatureEnabled(llvm::StringMap<bool> & Features,StringRef Name,bool Enabled) const setFeatureEnabled() argument
151 initFeatureMap(llvm::StringMap<bool> & Features,DiagnosticsEngine & Diags,StringRef CPU,const std::vector<std::string> & FeaturesVec) const initFeatureMap() argument
181 handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags) handleTargetFeatures() argument
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H A DPPC.cpp33 /// configured set of features. in handleTargetFeatures() argument
34 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, in handleTargetFeatures()
37 for (const auto &Feature : Features) { in handleTargetFeatures()
538 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, in initFeatureMap()
540 Features["altivec"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
555 Features["power9-vector"] = (CPU == "pwr9"); in initFeatureMap()
556 Features["crypto"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
561 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
566 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
572 Features["extdi in initFeatureMap()
515 initFeatureMap(llvm::StringMap<bool> & Features,DiagnosticsEngine & Diags,StringRef CPU,const std::vector<std::string> & FeaturesVec) const initFeatureMap() argument
737 setFeatureEnabled(llvm::StringMap<bool> & Features,StringRef Name,bool Enabled) const setFeatureEnabled() argument
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/llvm-project/clang/test/CodeGen/
H A Daarch64-fmv-dependencies.c
/llvm-project/clang/test/CodeGenOpenCL/
H A Damdgpu-features.cl3 // Check that appropriate features are defined for every supported AMDGPU
62 // NOCPU-NOT: "target-features"
63 // NOCPU-WAVE32: "target-features"="+wavefrontsize32"
64 // NOCPU-WAVE64: "target-features"="+wavefrontsize64"
66 // GFX600: "target-features"="+s-memtime-inst,+wavefrontsize64"
67 // GFX601: "target-features"="+s-memtime-inst,+wavefrontsize64"
68 // GFX602: "target-features"="+s-memtime-inst,+wavefrontsize64"
69 // GFX700: "target-features"="+ci-insts,+s-memtime-inst,+wavefrontsize64"
70 // GFX701: "target-features"="+ci-insts,+s-memtime-inst,+wavefrontsize64"
71 // GFX702: "target-features"
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/llvm-project/compiler-rt/lib/fuzzer/
H A DFuzzerMerge.cpp109 Files[CurrentFileIdx].Features = TmpFeatures; in Parse()
133 Res += sizeof(F) + F.Features.size() * sizeof(F.Features[0]); in ApproximateMemoryConsumption()
138 // Returns the number of new features added.
150 // What features are in the initial corpus? in Merge()
152 auto &Cur = Files[i].Features; in Merge()
155 // Remove all features that we already know from all other inputs. in Merge()
157 auto &Cur = Files[i].Features; in Merge()
166 // * files with more features. in Merge()
171 return a.Features.size() > b.Features.size(); in Merge()
174 // One greedy pass: add the file's features to AllFeatures. in Merge()
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