Lines Matching full:features
33 /// configured set of features.
34 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
37 for (const auto &Feature : Features) {
538 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
540 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
555 Features["power9-vector"] = (CPU == "pwr9");
556 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
561 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
566 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
572 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
578 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
583 Features["crbits"] = llvm::StringSwitch<bool>(CPU)
588 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
594 Features["htm"] = llvm::StringSwitch<bool>(CPU)
601 Features["rop-protect"] = false;
603 Features["privileged"] = false;
607 Features["aix-small-local-exec-tls"] = false;
608 Features["aix-small-local-dynamic-tls"] = false;
611 Features["aix-shared-lib-tls-model-opt"] = false;
613 Features["spe"] = llvm::StringSwitch<bool>(CPU)
618 Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
626 Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
632 Features["isa-v30-instructions"] =
635 Features["quadword-atomics"] =
641 // Power10 includes all the same features as Power9 plus any features specific
644 initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
645 addP10SpecificFeatures(Features);
648 // Power11 includes all the same features as Power10 plus any features
651 initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
652 addP11SpecificFeatures(Features);
655 // Future CPU should include all of the features of Power 11 as well as any
656 // additional features (yet to be determined) specific to it.
658 initFeatureMap(Features, Diags, "pwr11", FeaturesVec);
659 addFutureSpecificFeatures(Features);
713 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
716 // Add any Power10 specific features.
718 llvm::StringMap<bool> &Features) const {
719 Features["htm"] = false; // HTM was removed for P10.
720 Features["paired-vector-memops"] = true;
721 Features["mma"] = true;
722 Features["power10-vector"] = true;
723 Features["pcrelative-memops"] = true;
724 Features["prefix-instrs"] = true;
725 Features["isa-v31-instructions"] = true;
728 // Add any Power11 specific features.
730 llvm::StringMap<bool> &Features) const {}
732 // Add features specific to the "Future" CPU.
734 llvm::StringMap<bool> &Features) const {}
770 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
774 Features["spe"] = true;
775 // If we're enabling any of the vsx based features then enable vsx and
788 Features["vsx"] = Features["altivec"] = true;
790 Features["power8-vector"] = true;
792 Features["power8-vector"] = Features["power9-vector"] = true;
794 Features["pcrelative-memops"] = true;
796 Features["prefix-instrs"] = true;
798 Features[Name] = true;
801 Features["efpu2"] = false;
803 // of the vsx features.
806 Features["altivec"] = Features["crypto"] = false;
807 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
808 Features["float128"] = Features["power9-vector"] =
809 Features["paired-vector-memops"] = Features["mma"] =
810 Features["power10-vector"] = false;
813 Features["power9-vector"] = Features["paired-vector-memops"] =
814 Features["mma"] = Features["power10-vector"] = false;
816 Features["paired-vector-memops"] = Features["mma"] =
817 Features["power10-vector"] = false;
819 Features["pcrelative-memops"] = false;
821 Features["prefix-instrs"] = false;
823 Features[Name] = false;