/llvm-project/llvm/lib/CodeGen/ |
H A D | IntrinsicLowering.cpp | 65 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local 75 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local 104 Value* Tmp2 = Builder.CreateLShr(V, in LowerBSWAP() local [all...] |
/llvm-project/clang/test/CodeGenCXX/ |
H A D | matrix-type.cpp | 54 float Tmp2; member 95 long Tmp2; member in MatrixClass 121 long Tmp2; member in MatrixClassTemplate
|
/llvm-project/clang/test/CodeGen/ |
H A D | matrix-type.c | 129 float Tmp2; member
|
/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | IntegerDivision.cpp | 123 Value *Tmp2 = Builder.CreateXor(Tmp, Dividend); in generateSignedDivisionCode() local 252 Value *Tmp2 = Builder.CreateSub(MSB, SR); in generateUnsignedDivisionCode() local
|
/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 4189 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; matchBEXTRFromAndImm() local 4226 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; emitPCMPISTR() local 4259 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; emitPCMPESTR() local 4552 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; matchVPTERNLOG() local 4938 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; tryVPTESTM() local 5514 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local 5567 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local 5653 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local 5787 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local 5795 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain; Select() local 6158 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local [all...] |
/llvm-project/clang-tools-extra/modularize/ |
H A D | ModularizeUtilities.cpp | 456 StringRef Tmp2(Tmp); getCanonicalPath() local
|
/llvm-project/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 2031 Register Tmp2 = MRI.createVirtualRegister(RC); prepareMBB() local 2095 Register Tmp2 = MRI.createVirtualRegister(RC); prepareSymbol() local 2113 Register Tmp2 = MRI.createVirtualRegister(RC); prepareSymbol() local 2138 Register Tmp2 = MRI.createVirtualRegister(RC); prepareSymbol() local 2524 Register Tmp2 = MRI.createVirtualRegister(RC); emitSjLjDispatchBlock() local [all...] |
/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2465 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); LowerShiftRightParts() local 2525 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); LowerShiftLeftParts() local 2829 SDValue Tmp2 = Node->getOperand(1); LowerVAARG() local 3093 SDValue Tmp2 = ST->getBasePtr(); LowerSTOREi1() local
|
/llvm-project/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineC.cpp | 49 ExplodedNodeSet Tmp2; in VisitBinaryOperator() local
|
H A D | CheckerManager.cpp | 123 ExplodedNodeSet Tmp1, Tmp2; expandGraphWithCheckers() local
|
/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitDouble.cpp | 689 auto *Tmp2 = in splitMemRef() local
|
H A D | HexagonHardwareLoops.cpp | 1942 SmallVector<MachineOperand,1> Tmp2; createPreheaderForLoop() local
|
H A D | HexagonISelLoweringHVX.cpp | 2465 SDValue Tmp2 = DAG.getNode(ShRight, dl, IntTy, Tmp0, AmtM1); emitHvxShiftRightRnd() local
|
/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 5876 unsigned Tmp2 = DAG.ComputeNumSignBits(Op.getOperand(2), Depth + 1); in computeNumSignBitsForTargetInstr() local 2451 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); LowerFTRUNC() local 2470 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); LowerFROUNDEVEN() local 5836 unsigned Tmp2 = DAG.ComputeNumSignBits(Op.getOperand(2), Depth + 1); ComputeNumSignBitsForTargetNode() local [all...] |
H A D | AMDGPULegalizerInfo.cpp | 2436 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); legalizeFroundeven() local 4868 auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X); legalizeFastUnsafeFDIV64() local
|
/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 1739 SDValue Tmp2 = SDValue(Node, 1); ExpandDYNAMIC_STACKALLOC() local 3057 SDValue Tmp1, Tmp2, Tmp3, Tmp4; ExpandNode() local 5081 SDValue Tmp1, Tmp2, Tmp3, Tmp4; PromoteNode() local [all...] |
H A D | TargetLowering.cpp | 8075 SDValue Tmp2, Tmp3; expandShiftParts() local 8862 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; expandVPCTPOP() local 9302 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; expandBSWAP() local 9362 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; expandVPBSWAP() local 9434 SDValue Tmp, Tmp2, Tmp3; expandBITREVERSE() local 9499 SDValue Tmp, Tmp2, Tmp3; expandVPBITREVERSE() local [all...] |
H A D | LegalizeFloatTypes.cpp | 2014 SDValue Tmp1, Tmp2, Tmp3, OutputChain; FloatExpandSetCCOperands() local
|
/llvm-project/llvm/unittests/IR/ |
H A D | PassManagerTest.cpp | 371 auto Tmp2 = PreservedAnalyses::all(); in TEST() local
|
/llvm-project/clang/lib/CodeGen/ |
H A D | CGExprComplex.cpp | 1079 llvm::Value *Tmp2 = Builder.CreateMul(LHSi, RHSi); // b*d EmitBinDiv() local
|
/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 6270 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); Select() local 6284 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); Select() local
|
H A D | PPCISelLowering.cpp | 9126 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); LowerSHL_PARTS() local 9155 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); LowerSRL_PARTS() local 9183 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); LowerSRA_PARTS() local
|
/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelLowering.cpp | 1971 SDValue Tmp1, Tmp2; ReplaceNodeResults() local
|
/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 4184 SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32); Select() local
|
/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6923 SDValue Tmp2 = Op.getOperand(1); LowerOperation() local 11024 SDValue Tmp2 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op2, lowerVectorStrictFSetcc() local 17900 unsigned Tmp2 = ComputeNumSignBitsForTargetNode() local
|