| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 164 bool OffsetIsScalable; in runOnMachineFunction() local
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| H A D | AArch64InstrInfo.cpp | 2701 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
2723 bool OffsetIsScalable; getAddrModeFromMemoryOp() local
3492 getMemOperandWithOffsetWidth(const MachineInstr & LdSt,const MachineOperand * & BaseOp,int64_t & Offset,bool & OffsetIsScalable,TypeSize & Width,const TargetRegisterInfo * TRI) const getMemOperandWithOffsetWidth() argument
8463 bool OffsetIsScalable; getOutliningCandidateInfo() local
9007 bool OffsetIsScalable; fixupPostOutline() local
[all...] |
| /llvm-project/llvm/unittests/Target/RISCV/ |
| H A D | RISCVInstrInfoTest.cpp | 169 bool OffsetIsScalable; in TEST_P() local
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| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 797 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, in getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1426 getMemOperandWithOffset(const MachineInstr & MI,const MachineOperand * & BaseOp,int64_t & Offset,bool & OffsetIsScalable,const TargetRegisterInfo * TRI) const getMemOperandWithOffset() argument
1554 bool OffsetIsScalable; describeLoadedValue() local
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| H A D | MachineSink.cpp | 1308 bool OffsetIsScalable; SinkingPreventsImplicitNullCheck() local
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| H A D | MachineScheduler.cpp | 1741 bool OffsetIsScalable; global() member
1951 bool OffsetIsScalable; collectMemOpRecords() local
[all...] |
| H A D | ModuloSchedule.cpp | 928 bool OffsetIsScalable; computeDelta() local
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| H A D | MachinePipeliner.cpp | 2562 bool OffsetIsScalable; computeDelta() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1918 bool OffsetIsScalable; schedule() local
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| H A D | SIInstrInfo.cpp | 361 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1485 getMemOperandsWithOffsetWidth(const MachineInstr & MI,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2609 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 3074 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2839 getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4616 getMemOperandsWithOffsetWidth(const MachineInstr & MemOp,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,LocationSize & Width,const TargetRegisterInfo * TRI) const getMemOperandsWithOffsetWidth() argument
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