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Searched refs:vm_manager (Results 1 – 25 of 37) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vm.c136 adev->vm_manager.block_size; in amdgpu_vm_level_shift()
161 adev->vm_manager.root_level); in amdgpu_vm_num_entries()
163 if (level == adev->vm_manager.root_level) in amdgpu_vm_num_entries()
165 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) in amdgpu_vm_num_entries()
187 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_num_ats_entries()
203 if (level <= adev->vm_manager.root_level) in amdgpu_vm_entries_mask()
404 cursor->level = adev->vm_manager.root_level; in amdgpu_vm_pt_start()
754 unsigned level = adev->vm_manager.root_level; in amdgpu_vm_clear_bo()
1043 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
1082 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
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H A Damdgpu_ids.c214 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
237 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
238 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
350 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
423 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
485 id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_alloc_reserved()
512 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_free_reserved()
535 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_reset()
562 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_reset_all()
582 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_mgr_init()
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H A Damdgpu_gfxhub_v2_0.c102 + adev->vm_manager.vram_base_offset; in gfxhub_v2_0_init_system_aperture_regs()
218 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
235 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
244 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
246 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
H A Damdgpu_gfxhub_v1_0.c107 adev->vm_manager.vram_base_offset; in gfxhub_v1_0_init_system_aperture_regs()
219 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
220 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
257 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
259 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
H A Damdgpu_vm.h53 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
365 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
366 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
367 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
H A Damdgpu_mmhub_v2_0.c88 adev->vm_manager.vram_base_offset; in mmhub_v2_0_init_system_aperture_regs()
208 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
226 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
235 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
237 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
H A Damdgpu_gmc_v6_0.c465 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
524 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
548 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
569 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
905 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v6_0_sw_init()
913 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
915 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
H A Damdgpu_gmc_v9_0.c741 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v9_0_get_vm_pde()
943 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
946 adev->vm_manager.vram_base_offset += in gmc_v9_0_vram_gtt_location()
1128 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1230 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v9_0_sw_init()
1231 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v9_0_sw_init()
1232 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v9_0_sw_init()
H A Damdgpu_mmhub_v1_0.c123 adev->vm_manager.vram_base_offset; in mmhub_v1_0_init_system_aperture_regs()
242 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
243 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
280 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
282 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
H A Damdgpu_gmc_v7_0.c588 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
660 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
689 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
707 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1072 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v7_0_sw_init()
1080 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1082 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
H A Damdgpu_gmc_v8_0.c809 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
882 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
926 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
951 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1192 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v8_0_sw_init()
1200 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1202 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
H A Damdgpu_gmc_v10_0.c573 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v10_0_get_vm_pde()
670 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); in gmc_v10_0_vram_gtt_location()
857 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v10_0_sw_init()
858 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v10_0_sw_init()
H A Damdgpu_csa.c34 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; in amdgpu_csa_vaddr()
H A Damdgpu_si_dma.c844 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; in si_dma_set_vm_pte_funcs()
846 adev->vm_manager.vm_pte_scheds[i] = in si_dma_set_vm_pte_funcs()
849 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
H A Damdgpu_mmhub_v9_4.c149 adev->vm_manager.vram_base_offset; in mmhub_v9_4_init_system_aperture_regs()
319 adev->vm_manager.num_level); in mmhub_v9_4_setup_vmid_config()
337 adev->vm_manager.block_size - 9); in mmhub_v9_4_setup_vmid_config()
354 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v9_4_setup_vmid_config()
358 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v9_4_setup_vmid_config()
H A Damdgpu_vm_sdma.c250 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * in amdgpu_vm_sdma_update()
H A Damdgpu_sdma_v2_4.c1271 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; in sdma_v2_4_set_vm_pte_funcs()
1273 adev->vm_manager.vm_pte_scheds[i] = in sdma_v2_4_set_vm_pte_funcs()
1276 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v2_4_set_vm_pte_funcs()
H A Damdgpu_cik_sdma.c1382 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; in cik_sdma_set_vm_pte_funcs()
1384 adev->vm_manager.vm_pte_scheds[i] = in cik_sdma_set_vm_pte_funcs()
1387 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in cik_sdma_set_vm_pte_funcs()
H A Damdgpu_sdma_v5_0.c1730 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v5_0_set_vm_pte_funcs()
1731 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; in sdma_v5_0_set_vm_pte_funcs()
1733 adev->vm_manager.vm_pte_scheds[i] = in sdma_v5_0_set_vm_pte_funcs()
1736 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_0_set_vm_pte_funcs()
H A Damdgpu_sdma_v3_0.c1709 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; in sdma_v3_0_set_vm_pte_funcs()
1711 adev->vm_manager.vm_pte_scheds[i] = in sdma_v3_0_set_vm_pte_funcs()
1714 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v3_0_set_vm_pte_funcs()
H A Damdgpu_amdkfd.c123 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
H A Damdgpu_kms.c727 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; in amdgpu_info_ioctl()
744 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; in amdgpu_info_ioctl()
H A Damdgpu_sdma_v4_0.c2525 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; in sdma_v4_0_set_vm_pte_funcs()
2531 adev->vm_manager.vm_pte_scheds[i] = sched; in sdma_v4_0_set_vm_pte_funcs()
2533 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v4_0_set_vm_pte_funcs()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_vm.c69 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
96 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
101 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
117 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
121 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
123 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
195 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
202 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
203 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
222 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
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H A Dradeon_ni.c1333 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1335 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1370 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2516 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2521 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2523 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()

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