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Searched refs:tiling_flags (Results 1 – 25 of 27) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_object.c609 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
614 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate()
630 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
669 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
691 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
699 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
700 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
701 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
702 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags()
703 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags()
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H A Dradeon_fb.c147 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
174 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
179 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
182 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
188 if (tiling_flags) { in radeonfb_create_pinned_object()
190 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
H A Dradeon_r200.c226 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
228 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
298 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
300 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
H A Dradeon_object.h149 u32 tiling_flags, u32 pitch);
151 u32 *tiling_flags, u32 *pitch);
H A Dradeon_legacy_crtc.c391 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
438 tiling_flags = 0; in radeon_crtc_do_set_base()
479 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
482 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
515 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
H A Dradeon_r300.c752 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
754 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
756 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
821 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
823 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
825 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
906 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
908 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
910 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
H A Dradeon_atombios_crtc.c1160 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1188 tiling_flags = 0; in dce4_crtc_do_set_base()
1198 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1282 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1283 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1356 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1483 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1510 tiling_flags = 0; in avivo_crtc_do_set_base()
1520 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1597 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
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H A Dradeon_evergreen_cs.c102 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
104 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
106 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1209 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1210 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1211 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1214 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1395 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1396 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1413 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
[all …]
H A Dradeon_r100.c1302 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1304 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1644 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1646 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1725 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1727 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3113 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3120 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
3123 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3126 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
[all …]
H A Dradeon_r600_cs.c1047 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1146 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1149 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1477 u32 tiling_flags) in r600_check_texture_resource() argument
1499 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1501 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1970 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1972 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1988 reloc->tiling_flags); in r600_packet3_check()
H A Dradeon_gem.c534 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
555 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
H A Dradeon_display.c498 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local
544 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target()
552 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
H A Dradeon_vm.c153 list[0].tiling_flags = 0; in radeon_vm_get_bos()
165 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
H A Dradeon.h368 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
483 uint32_t tiling_flags; member
515 u32 tiling_flags; member
1982 uint32_t tiling_flags, uint32_t pitch,
H A Dradeon_asic.h93 uint32_t tiling_flags, uint32_t pitch,
341 uint32_t tiling_flags, uint32_t pitch,
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_fb.c144 u32 tiling_flags = 0, domain; in amdgpufb_create_pinned_object() local
173 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); in amdgpufb_create_pinned_object()
179 if (tiling_flags) { in amdgpufb_create_pinned_object()
181 tiling_flags); in amdgpufb_create_pinned_object()
H A Damdgpu_object.h95 u64 tiling_flags; member
270 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
271 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
H A Damdgpu_object.c1160 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
1165 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1168 bo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
1180 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
1184 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
1185 *tiling_flags = bo->tiling_flags; in amdgpu_bo_get_tiling_flags()
H A Damdgpu_dce_v8_0.c1791 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
1829 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
1832 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1914 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1917 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1918 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1919 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1920 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1921 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1930 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
H A Damdgpu_dce_v6_0.c1822 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local
1859 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base()
1942 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1945 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
1946 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1947 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1948 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1949 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
1957 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1961 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
H A Damdgpu_dce_v10_0.c1862 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
1900 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
1903 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
H A Damdgpu_dce_v11_0.c1904 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
1942 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2035 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2039 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2041 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2042 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2055 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
H A Damdgpu_display.c166 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local
221 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c3113 uint64_t *tiling_flags) in get_fb_info() argument
3125 if (tiling_flags) in get_fb_info()
3126 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); in get_fb_info()
3133 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) in get_dcc_address() argument
3135 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); in get_dcc_address()
3206 const uint64_t tiling_flags, in fill_plane_buffer_attributes() argument
3262 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in fill_plane_buffer_attributes()
3265 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_buffer_attributes()
3266 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_plane_buffer_attributes()
3267 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_plane_buffer_attributes()
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/netbsd-src/sys/external/bsd/drm2/dist/include/uapi/drm/
H A Dradeon_drm.h860 __u32 tiling_flags; member
866 __u32 tiling_flags; member

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