| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| H A D | intel_overlay.c | 818 params->src_width); in intel_overlay_do_put_image()
820 tmp_width = params->src_width; in intel_overlay_do_put_image()
822 swidth = params->src_width; in intel_overlay_do_put_image()
833 swidth |= (params->src_width / uv_hscale) << 16; in intel_overlay_do_put_image()
837 params->src_width / uv_hscale); in intel_overlay_do_put_image()
839 params->src_width / uv_hscale); in intel_overlay_do_put_image()
978 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) in check_overlay_src()
982 rec->src_width > IMAGE_MAX_WIDTH) in check_overlay_src()
988 rec->src_width < N_HORIZ_Y_TAPS*4) in check_overlay_src()
1024 if (rec->src_width % uv_hscale) in check_overlay_src()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_dwb.c | 83 REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width, in dwb2_config_dwb_cnv()
109 if ((params->cnv_params.src_width != params->dest_width) || in dwb2_enable()
169 if ((params->cnv_params.src_width != params->dest_width) || in dwb2_update()
295 dwb_program_horz_scalar(dwbc20, params->cnv_params.src_width, in dwb2_set_scaler()
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| H A D | amdgpu_dcn20_dwb_scl.c | 725 uint32_t src_width, in dwb_program_horz_scalar() argument
748 src_width, dest_width); in dwb_program_horz_scalar()
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| H A D | dcn20_dwb.h | 453 uint32_t src_width,
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| /netbsd-src/external/mit/xorg/lib/libxcb/files/ |
| H A D | shm.c | 217 uint16_t src_width, in xcb_shm_put_image_checked() argument
244 xcb_out.src_width = src_width; in xcb_shm_put_image_checked()
272 uint16_t src_width, in xcb_shm_put_image() argument
299 xcb_out.src_width = src_width; in xcb_shm_put_image()
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| H A D | shm.h | 141 uint16_t src_width; member
459 uint16_t src_width,
511 uint16_t src_width,
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| H A D | xinput.h | 2348 uint16_t src_width; member
7765 uint16_t src_width,
7785 uint16_t src_width,
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| H A D | xproto.h | 2602 uint16_t src_width; member
8300 uint16_t src_width,
8338 uint16_t src_width,
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| H A D | xproto.c | 5150 uint16_t src_width, in xcb_warp_pointer_checked() argument
5171 xcb_out.src_width = src_width; in xcb_warp_pointer_checked()
5191 uint16_t src_width, in xcb_warp_pointer() argument
5212 xcb_out.src_width = src_width; in xcb_warp_pointer()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | dm_services_types.h | 130 uint32_t src_width; member
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| H A D | dc_types.h | 487 unsigned int src_width; /* input active width */ member
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_dce_v8_0.c | 640 u32 src_width; /* viewport width */ member
805 fixed20_12 src_width; in dce_v8_0_average_bandwidth() local
813 src_width.full = dfixed_const(wm->src_width); in dce_v8_0_average_bandwidth()
814 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v8_0_average_bandwidth()
866 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v8_0_latency_watermark()
931 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v8_0_check_latency_hiding()
996 wm_high.src_width = mode->crtc_hdisplay; in dce_v8_0_program_watermarks()
1035 wm_low.src_width = mode->crtc_hdisplay; in dce_v8_0_program_watermarks()
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| H A D | amdgpu_dce_v6_0.c | 503 u32 src_width; /* viewport width */ member
668 fixed20_12 src_width; in dce_v6_0_average_bandwidth() local
676 src_width.full = dfixed_const(wm->src_width); in dce_v6_0_average_bandwidth()
677 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v6_0_average_bandwidth()
729 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v6_0_latency_watermark()
794 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v6_0_check_latency_hiding()
868 wm_high.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
895 wm_low.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
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| H A D | amdgpu_dce_v10_0.c | 705 u32 src_width; /* viewport width */ member
870 fixed20_12 src_width; in dce_v10_0_average_bandwidth() local
878 src_width.full = dfixed_const(wm->src_width); in dce_v10_0_average_bandwidth()
879 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v10_0_average_bandwidth()
931 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v10_0_latency_watermark()
996 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v10_0_check_latency_hiding()
1061 wm_high.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
1100 wm_low.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
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| H A D | amdgpu_dce_v11_0.c | 731 u32 src_width; /* viewport width */ member
896 fixed20_12 src_width; in dce_v11_0_average_bandwidth() local
904 src_width.full = dfixed_const(wm->src_width); in dce_v11_0_average_bandwidth()
905 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v11_0_average_bandwidth()
957 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v11_0_latency_watermark()
1022 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v11_0_check_latency_hiding()
1087 wm_high.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
1126 wm_low.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| H A D | amdgpu_dce_calcs.c | 393 data->src_width[maximum_number_of_surfaces - 2] = data->src_width[5]; in calculate_bandwidth()
394 data->src_width[maximum_number_of_surfaces - 1] = data->src_width[5]; in calculate_bandwidth()
397 data->pitch_in_pixels[maximum_number_of_surfaces - 2] = data->src_width[5]; in calculate_bandwidth()
398 data->pitch_in_pixels[maximum_number_of_surfaces - 1] = data->src_width[5]; in calculate_bandwidth()
431 data->src_width_after_surface_type = bw_div(data->src_width[i], bw_int_to_fixed(2)); in calculate_bandwidth()
438 data->src_width_after_surface_type = data->src_width[i]; in calculate_bandwidth()
2804 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2805 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; in populate_initial_data()
2859 …data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.vi… in populate_initial_data()
2906 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
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| H A D | calcs_logger.h | 425 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width[%d]:%d", i, bw_fixed_to_int(data->src_width[i])); in print_bw_calcs_data()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | amdgpu_dce110_clk_mgr.c | 155 cfg->src_width = stream->src.width; in dce110_fill_display_configs()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_evergreen.c | 1941 u32 src_width; /* viewport width */ member
2050 fixed20_12 src_width; in evergreen_average_bandwidth() local
2058 src_width.full = dfixed_const(wm->src_width); in evergreen_average_bandwidth()
2059 bandwidth.full = dfixed_mul(src_width, bpp); in evergreen_average_bandwidth()
2099 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in evergreen_latency_watermark()
2133 u32 lb_partitions = wm->lb_size / wm->src_width; in evergreen_check_latency_hiding()
2196 wm_high.src_width = mode->crtc_hdisplay; in evergreen_program_watermarks()
2223 wm_low.src_width = mode->crtc_hdisplay; in evergreen_program_watermarks()
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| H A D | radeon_si.c | 2069 u32 src_width; /* viewport width */ member
2195 fixed20_12 src_width; in dce6_average_bandwidth() local
2203 src_width.full = dfixed_const(wm->src_width); in dce6_average_bandwidth()
2204 bandwidth.full = dfixed_mul(src_width, bpp); in dce6_average_bandwidth()
2247 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce6_latency_watermark()
2281 u32 lb_partitions = wm->lb_size / wm->src_width; in dce6_check_latency_hiding()
2347 wm_high.src_width = mode->crtc_hdisplay; in dce6_program_watermarks()
2374 wm_low.src_width = mode->crtc_hdisplay; in dce6_program_watermarks()
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| H A D | radeon_cik.c | 8986 u32 src_width; /* viewport width */ member
9151 fixed20_12 src_width; in dce8_average_bandwidth() local
9159 src_width.full = dfixed_const(wm->src_width); in dce8_average_bandwidth()
9160 bandwidth.full = dfixed_mul(src_width, bpp); in dce8_average_bandwidth()
9212 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce8_latency_watermark()
9277 u32 lb_partitions = wm->lb_size / wm->src_width; in dce8_check_latency_hiding()
9343 wm_high.src_width = mode->crtc_hdisplay; in dce8_program_watermarks()
9383 wm_low.src_width = mode->crtc_hdisplay; in dce8_program_watermarks()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| H A D | dce_calcs.h | 393 struct bw_fixed src_width[maximum_number_of_surfaces]; member
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/brig/brigfrontend/ |
| H A D | brig-code-entry-handler.cc | 1062 size_t src_width = int_size_in_bytes (input_type); in build_output_assignment() local
1067 if (INTEGRAL_TYPE_P (TREE_TYPE (input)) && src_width != dst_width) in build_output_assignment()
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| /netbsd-src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| H A D | i915_drm.h | 1448 __u16 src_width; member
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | dce_clk_mgr.c | 527 cfg->src_width = stream->src.width; in dce110_fill_display_configs()
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