Home
last modified time | relevance | path

Searched refs:se_num (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_nv.c215 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
221 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
222 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
226 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
233 bool indexed, u32 se_num, in nv_get_register_value() argument
237 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
245 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
260 se_num, sh_num, reg_offset); in nv_read_register()
H A Damdgpu_cik.c1054 bool indexed, u32 se_num, in cik_get_register_value() argument
1059 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in cik_get_register_value()
1074 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1075 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in cik_get_register_value()
1079 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1149 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, in cik_read_register() argument
1161 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
H A Damdgpu_vi.c559 bool indexed, u32 se_num, in vi_get_register_value() argument
564 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in vi_get_register_value()
579 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
580 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
584 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
654 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
666 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
H A Damdgpu_soc15.c363 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
369 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
370 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
374 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
381 bool indexed, u32 se_num, in soc15_get_register_value() argument
385 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
395 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
410 se_num, sh_num, reg_offset); in soc15_read_register()
H A Damdgpu_si.c1036 bool indexed, u32 se_num, in si_get_register_value() argument
1041 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in si_get_register_value()
1054 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1055 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in si_get_register_value()
1059 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1110 static int si_read_register(struct amdgpu_device *adev, u32 se_num, in si_read_register() argument
1122 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
H A Dgfx_v9_0.h31 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
H A Damdgpu_gfx_v9_4.c98 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_select_se_sh() argument
110 if (se_num == 0xffffffff) in gfx_v9_4_select_se_sh()
114 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
875 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_query_ras_error_count()
907 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_clear_ras_edc_counter()
H A Dsoc15.h53 uint32_t se_num; member
H A Damdgpu_kms.c657 unsigned se_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
666 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) in amdgpu_info_ioctl()
667 se_num = 0xffffffff; in amdgpu_info_ioctl()
681 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Damdgpu_gfx.h195 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
H A Damdgpu_gfx_v6_0.c1306 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v6_0_select_se_sh() argument
1316 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1319 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1324 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1327 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
H A Damdgpu_gfx_v7_0.c1597 u32 se_num, u32 sh_num, u32 instance) in gfx_v7_0_select_se_sh() argument
1606 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1609 else if (se_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1614 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1617 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
H A Damdgpu_gfx_v9_0.c743 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
2337 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) in gfx_v9_0_select_se_sh() argument
2346 if (se_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2349 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
6338 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_clear_ras_edc_counter()
6400 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_query_ras_error_count()
H A Damdgpu.h573 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
H A Damdgpu_gfx_v10_0.c256 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1495 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v10_0_select_se_sh() argument
1507 if (se_num == 0xffffffff) in gfx_v10_0_select_se_sh()
1511 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v10_0_select_se_sh()
H A Damdgpu_gfx_v8_0.c3423 u32 se_num, u32 sh_num, u32 instance) in gfx_v8_0_select_se_sh() argument
3432 if (se_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3435 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_si.c2959 u32 se_num, u32 sh_num) in si_select_se_sh() argument
2963 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2965 else if (se_num == 0xffffffff) in si_select_se_sh()
2968 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); in si_select_se_sh()
2970 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in si_select_se_sh()
3004 u32 se_num, u32 sh_per_se, in si_setup_spi() argument
3010 for (i = 0; i < se_num; i++) { in si_setup_spi()
3051 u32 se_num, u32 sh_per_se, in si_setup_rb() argument
3059 for (i = 0; i < se_num; i++) { in si_setup_rb()
3069 for (i = 0; i < max_rb_num_per_se * se_num; i++) { in si_setup_rb()
[all …]
H A Dradeon_cik.c3053 u32 se_num, u32 sh_num) in cik_select_se_sh() argument
3057 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in cik_select_se_sh()
3059 else if (se_num == 0xffffffff) in cik_select_se_sh()
3062 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); in cik_select_se_sh()
3064 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in cik_select_se_sh()
3129 u32 se_num, u32 sh_per_se, in cik_setup_rb() argument
3137 for (i = 0; i < se_num; i++) { in cik_setup_rb()
3150 for (i = 0; i < max_rb_num_per_se * se_num; i++) { in cik_setup_rb()
3158 for (i = 0; i < se_num; i++) { in cik_setup_rb()