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Searched refs:mmUVD_RB_BASE_HI2 (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h42 #define mmUVD_RB_BASE_HI2 0x3c22 macro
H A Duvd_7_0_offset.h88 #define mmUVD_RB_BASE_HI2 … macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h210 #define mmUVD_RB_BASE_HI2 … macro
H A Dvcn_2_5_offset.h565 #define mmUVD_RB_BASE_HI2 … macro
H A Dvcn_2_0_0_offset.h922 #define mmUVD_RB_BASE_HI2 … macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v2_0.c1036 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1178 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
H A Damdgpu_vcn_v1_0.c951 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1252 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
H A Damdgpu_vcn_v2_5.c1067 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1408 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
H A Damdgpu_uvd_v6_0.c857 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
H A Damdgpu_uvd_v7_0.c1111 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()