| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_2_d.h | 49 #define mmUVD_MASTINT_EN 0x3d40 macro
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| H A D | uvd_4_0_d.h | 54 #define mmUVD_MASTINT_EN 0x3D40 macro
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| H A D | uvd_5_0_d.h | 55 #define mmUVD_MASTINT_EN 0x3d40 macro
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| H A D | uvd_6_0_d.h | 71 #define mmUVD_MASTINT_EN 0x3d40 macro
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| H A D | uvd_7_0_offset.h | 154 #define mmUVD_MASTINT_EN … macro
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_uvd_v4_2.c | 283 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
348 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start()
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| H A D | amdgpu_uvd_v5_0.c | 315 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
392 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
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| H A D | amdgpu_vcn_v2_0.c | 778 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
834 UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start_dpg_mode()
903 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v2_0_start()
993 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start()
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| H A D | amdgpu_uvd_v7_0.c | 855 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
892 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
968 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, in uvd_v7_0_start()
1059 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), in uvd_v7_0_start()
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| H A D | amdgpu_vcn_v1_0.c | 804 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v1_0_start_spg_mode()
894 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v1_0_start_spg_mode()
986 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
1040 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
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| H A D | amdgpu_vcn_v2_5.c | 786 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
846 UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
929 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1024 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
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| H A D | amdgpu_uvd_v6_0.c | 808 WREG32_P(mmUVD_MASTINT_EN, in uvd_v6_0_start()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 332 #define mmUVD_MASTINT_EN … macro
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| H A D | vcn_2_5_offset.h | 535 #define mmUVD_MASTINT_EN … macro
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| H A D | vcn_2_0_0_offset.h | 540 #define mmUVD_MASTINT_EN … macro
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