Searched refs:interrupt_status_offsets (Results 1 – 4 of 4) sorted by relevance
95 } interrupt_status_offsets[6] = { { variable3048 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq()3054 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()3065 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()3169 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()3170 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
98 } interrupt_status_offsets[6] = { { variable2958 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq()2964 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()2975 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()3079 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()3080 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
95 } interrupt_status_offsets[] = { { variable3237 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()3242 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()3254 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()3283 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()3284 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
97 } interrupt_status_offsets[] = { { variable3363 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq()3369 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()3381 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()3411 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()