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Searched refs:VC_AND_TC (Results 1 – 20 of 20) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv770d.h619 #define VC_AND_TC 2 macro
H A Dnid.h336 #define VC_AND_TC 2 macro
H A Dsid.h1056 #define VC_AND_TC 2 macro
H A Dcikd.h1131 #define VC_AND_TC 2 macro
H A Dradeon_rv770.c1549 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | in rv770_gpu_init()
H A Devergreend.h1125 #define VC_AND_TC 2 macro
H A Dr600d.h536 #define VC_AND_TC 2 macro
H A Dradeon_ni.c1232 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in cayman_gpu_init()
H A Dradeon_r600.c2327 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); in r600_gpu_init()
H A Dradeon_evergreen.c3660 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); in evergreen_gpu_init()
H A Dradeon_si.c3339 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in si_gpu_init()
H A Dradeon_cik.c3417 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in cik_gpu_init()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h1055 #define VC_AND_TC 2 macro
H A Damdgpu_gfx_v6_0.c1762 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | in gfx_v6_0_constants_init()
H A Damdgpu_gfx_v7_0.c2042 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | in gfx_v7_0_constants_init()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_enum.h4919 VC_AND_TC = 0x2, enumerator
H A Dgfx_8_0_enum.h5405 VC_AND_TC = 0x2, enumerator
H A Dgfx_8_1_enum.h5474 VC_AND_TC = 0x2, enumerator
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/
H A Dvega10_enum.h15655 VC_AND_TC = 0x00000002, enumerator
H A Dnavi10_enum.h14366 VC_AND_TC = 0x00000002, enumerator