xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/navi10_enum.h (revision e4a580baf2598beeaae98d953ac7635b8700b80c)
1 /*	$NetBSD: navi10_enum.h,v 1.3 2021/12/19 10:59:02 riastradh Exp $	*/
2 
3 /*
4  * Copyright (C) 2019  Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included
14  * in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #if !defined (_navi10_ENUM_HEADER)
24 #define _navi10_ENUM_HEADER
25 
26 #ifndef _DRIVER_BUILD
27 #ifndef GL_ZERO
28 #define GL__ZERO                      BLEND_ZERO
29 #define GL__ONE                       BLEND_ONE
30 #define GL__SRC_COLOR                 BLEND_SRC_COLOR
31 #define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
32 #define GL__DST_COLOR                 BLEND_DST_COLOR
33 #define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
34 #define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
35 #define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
36 #define GL__DST_ALPHA                 BLEND_DST_ALPHA
37 #define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
38 #define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
39 #define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
40 #define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
41 #define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
42 #define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
43 #endif
44 #endif
45 
46 /*******************************************************
47  * GDS DATA_TYPE Enums
48  *******************************************************/
49 
50 #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
51 #define ENUMS_GDS_PERFCOUNT_SELECT_H
52 typedef enum GDS_PERFCOUNT_SELECT {
53  GDS_PERF_SEL_DS_ADDR_CONFL = 0,
54  GDS_PERF_SEL_DS_BANK_CONFL = 1,
55  GDS_PERF_SEL_WBUF_FLUSH = 2,
56  GDS_PERF_SEL_WR_COMP = 3,
57  GDS_PERF_SEL_WBUF_WR = 4,
58  GDS_PERF_SEL_RBUF_HIT = 5,
59  GDS_PERF_SEL_RBUF_MISS = 6,
60  GDS_PERF_SEL_SE0_SH0_NORET = 7,
61  GDS_PERF_SEL_SE0_SH0_RET = 8,
62  GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
63  GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
64  GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
65  GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
66  GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
67  GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
68  GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
69  GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
70  GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
71  GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
72  GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
73  GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
74  GDS_PERF_SEL_SE0_SH1_NORET = 21,
75  GDS_PERF_SEL_SE0_SH1_RET = 22,
76  GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
77  GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
78  GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
79  GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
80  GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
81  GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
82  GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
83  GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
84  GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
85  GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
86  GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
87  GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
88  GDS_PERF_SEL_SE1_SH0_NORET = 35,
89  GDS_PERF_SEL_SE1_SH0_RET = 36,
90  GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
91  GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
92  GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
93  GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
94  GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
95  GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
96  GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
97  GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
98  GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
99  GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
100  GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
101  GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
102  GDS_PERF_SEL_SE1_SH1_NORET = 49,
103  GDS_PERF_SEL_SE1_SH1_RET = 50,
104  GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
105  GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
106  GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
107  GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
108  GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
109  GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
110  GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
111  GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
112  GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
113  GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
114  GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
115  GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
116  GDS_PERF_SEL_SE2_SH0_NORET = 63,
117  GDS_PERF_SEL_SE2_SH0_RET = 64,
118  GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
119  GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
120  GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
121  GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
122  GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
123  GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
124  GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
125  GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
126  GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
127  GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
128  GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
129  GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
130  GDS_PERF_SEL_SE2_SH1_NORET = 77,
131  GDS_PERF_SEL_SE2_SH1_RET = 78,
132  GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
133  GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
134  GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
135  GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
136  GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
137  GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
138  GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
139  GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
140  GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
141  GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
142  GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
143  GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
144  GDS_PERF_SEL_SE3_SH0_NORET = 91,
145  GDS_PERF_SEL_SE3_SH0_RET = 92,
146  GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
147  GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
148  GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
149  GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
150  GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
151  GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
152  GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
153  GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
154  GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
155  GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
156  GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
157  GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
158  GDS_PERF_SEL_SE3_SH1_NORET = 105,
159  GDS_PERF_SEL_SE3_SH1_RET = 106,
160  GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
161  GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
162  GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
163  GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
164  GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
165  GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
166  GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
167  GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
168  GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
169  GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
170  GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
171  GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
172  GDS_PERF_SEL_GWS_RELEASED = 119,
173  GDS_PERF_SEL_GWS_BYPASS = 120,
174 } GDS_PERFCOUNT_SELECT;
175 #endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
176 
177 /*******************************************************
178  * Chip Enums
179  *******************************************************/
180 
181 /*
182  * GATCL1RequestType enum
183  */
184 
185 typedef enum GATCL1RequestType {
186 GATCL1_TYPE_NORMAL                       = 0x00000000,
187 GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
188 GATCL1_TYPE_BYPASS                       = 0x00000002,
189 } GATCL1RequestType;
190 
191 /*
192  * UTCL1RequestType enum
193  */
194 
195 typedef enum UTCL1RequestType {
196 UTCL1_TYPE_NORMAL                        = 0x00000000,
197 UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
198 UTCL1_TYPE_BYPASS                        = 0x00000002,
199 } UTCL1RequestType;
200 
201 /*
202  * UTCL1FaultType enum
203  */
204 
205 typedef enum UTCL1FaultType {
206 UTCL1_XNACK_SUCCESS                      = 0x00000000,
207 UTCL1_XNACK_RETRY                        = 0x00000001,
208 UTCL1_XNACK_PRT                          = 0x00000002,
209 UTCL1_XNACK_NO_RETRY                     = 0x00000003,
210 } UTCL1FaultType;
211 
212 /*
213  * UTCL0RequestType enum
214  */
215 
216 typedef enum UTCL0RequestType {
217 UTCL0_TYPE_NORMAL                        = 0x00000000,
218 UTCL0_TYPE_SHOOTDOWN                     = 0x00000001,
219 UTCL0_TYPE_BYPASS                        = 0x00000002,
220 } UTCL0RequestType;
221 
222 /*
223  * UTCL0FaultType enum
224  */
225 
226 typedef enum UTCL0FaultType {
227 UTCL0_XNACK_SUCCESS                      = 0x00000000,
228 UTCL0_XNACK_RETRY                        = 0x00000001,
229 UTCL0_XNACK_PRT                          = 0x00000002,
230 UTCL0_XNACK_NO_RETRY                     = 0x00000003,
231 } UTCL0FaultType;
232 
233 /*
234  * VMEMCMD_RETURN_ORDER enum
235  */
236 
237 typedef enum VMEMCMD_RETURN_ORDER {
238 VMEMCMD_RETURN_OUT_OF_ORDER              = 0x00000000,
239 VMEMCMD_RETURN_IN_ORDER                  = 0x00000001,
240 VMEMCMD_RETURN_IN_ORDER_READ             = 0x00000002,
241 } VMEMCMD_RETURN_ORDER;
242 
243 /*
244  * GL0V_CACHE_POLICIES enum
245  */
246 
247 typedef enum GL0V_CACHE_POLICIES {
248 GL0V_CACHE_POLICY_MISS_LRU               = 0x00000000,
249 GL0V_CACHE_POLICY_MISS_EVICT             = 0x00000001,
250 GL0V_CACHE_POLICY_HIT_LRU                = 0x00000002,
251 GL0V_CACHE_POLICY_HIT_EVICT              = 0x00000003,
252 } GL0V_CACHE_POLICIES;
253 
254 /*
255  * GL1_CACHE_POLICIES enum
256  */
257 
258 typedef enum GL1_CACHE_POLICIES {
259 GL1_CACHE_POLICY_MISS_LRU                = 0x00000000,
260 GL1_CACHE_POLICY_MISS_EVICT              = 0x00000001,
261 GL1_CACHE_POLICY_HIT_LRU                 = 0x00000002,
262 GL1_CACHE_POLICY_HIT_EVICT               = 0x00000003,
263 } GL1_CACHE_POLICIES;
264 
265 /*
266  * GL1_CACHE_STORE_POLICIES enum
267  */
268 
269 typedef enum GL1_CACHE_STORE_POLICIES {
270 GL1_CACHE_STORE_POLICY_BYPASS            = 0x00000000,
271 } GL1_CACHE_STORE_POLICIES;
272 
273 /*
274  * TCC_CACHE_POLICIES enum
275  */
276 
277 typedef enum TCC_CACHE_POLICIES {
278 TCC_CACHE_POLICY_LRU                     = 0x00000000,
279 TCC_CACHE_POLICY_STREAM                  = 0x00000001,
280 } TCC_CACHE_POLICIES;
281 
282 /*
283  * TCC_MTYPE enum
284  */
285 
286 typedef enum TCC_MTYPE {
287 MTYPE_NC                                 = 0x00000000,
288 MTYPE_WC                                 = 0x00000001,
289 MTYPE_CC                                 = 0x00000002,
290 } TCC_MTYPE;
291 
292 /*
293  * GL2_CACHE_POLICIES enum
294  */
295 
296 typedef enum GL2_CACHE_POLICIES {
297 GL2_CACHE_POLICY_LRU                     = 0x00000000,
298 GL2_CACHE_POLICY_STREAM                  = 0x00000001,
299 GL2_CACHE_POLICY_NOA                     = 0x00000002,
300 GL2_CACHE_POLICY_BYPASS                  = 0x00000003,
301 } GL2_CACHE_POLICIES;
302 
303 /*
304  * MTYPE enum
305  */
306 
307 typedef enum MTYPE {
308 MTYPE_C_RW_US                            = 0x00000000,
309 MTYPE_RESERVED_1                         = 0x00000001,
310 MTYPE_C_RO_S                             = 0x00000002,
311 MTYPE_UC                                 = 0x00000003,
312 MTYPE_C_RW_S                             = 0x00000004,
313 MTYPE_RESERVED_5                         = 0x00000005,
314 MTYPE_C_RO_US                            = 0x00000006,
315 MTYPE_RESERVED_7                         = 0x00000007,
316 } MTYPE;
317 
318 /*
319  * RMI_CID enum
320  */
321 
322 typedef enum RMI_CID {
323 RMI_CID_CC                               = 0x00000000,
324 RMI_CID_FC                               = 0x00000001,
325 RMI_CID_CM                               = 0x00000002,
326 RMI_CID_DC                               = 0x00000003,
327 RMI_CID_Z                                = 0x00000004,
328 RMI_CID_S                                = 0x00000005,
329 RMI_CID_TILE                             = 0x00000006,
330 RMI_CID_ZPCPSD                           = 0x00000007,
331 } RMI_CID;
332 
333 /*
334  * WritePolicy enum
335  */
336 
337 typedef enum WritePolicy {
338 CACHE_LRU_WR                             = 0x00000000,
339 CACHE_STREAM                             = 0x00000001,
340 CACHE_BYPASS                             = 0x00000002,
341 UNCACHED_WR                              = 0x00000003,
342 } WritePolicy;
343 
344 /*
345  * ReadPolicy enum
346  */
347 
348 typedef enum ReadPolicy {
349 CACHE_LRU_RD                             = 0x00000000,
350 CACHE_NOA                                = 0x00000001,
351 UNCACHED_RD                              = 0x00000002,
352 RESERVED_RDPOLICY                        = 0x00000003,
353 } ReadPolicy;
354 
355 /*
356  * PERFMON_COUNTER_MODE enum
357  */
358 
359 typedef enum PERFMON_COUNTER_MODE {
360 PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
361 PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
362 PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
363 PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
364 PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
365 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT  = 0x00000005,
366 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT  = 0x00000006,
367 PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
368 PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
369 PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
370 PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
371 } PERFMON_COUNTER_MODE;
372 
373 /*
374  * PERFMON_SPM_MODE enum
375  */
376 
377 typedef enum PERFMON_SPM_MODE {
378 PERFMON_SPM_MODE_OFF                     = 0x00000000,
379 PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
380 PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
381 PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
382 PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
383 PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
384 PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
385 PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
386 PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
387 PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
388 PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
389 } PERFMON_SPM_MODE;
390 
391 /*
392  * SurfaceTiling enum
393  */
394 
395 typedef enum SurfaceTiling {
396 ARRAY_LINEAR                             = 0x00000000,
397 ARRAY_TILED                              = 0x00000001,
398 } SurfaceTiling;
399 
400 /*
401  * SurfaceArray enum
402  */
403 
404 typedef enum SurfaceArray {
405 ARRAY_1D                                 = 0x00000000,
406 ARRAY_2D                                 = 0x00000001,
407 ARRAY_3D                                 = 0x00000002,
408 ARRAY_3D_SLICE                           = 0x00000003,
409 } SurfaceArray;
410 
411 /*
412  * ColorArray enum
413  */
414 
415 typedef enum ColorArray {
416 ARRAY_2D_ALT_COLOR                       = 0x00000000,
417 ARRAY_2D_COLOR                           = 0x00000001,
418 ARRAY_3D_SLICE_COLOR                     = 0x00000003,
419 } ColorArray;
420 
421 /*
422  * DepthArray enum
423  */
424 
425 typedef enum DepthArray {
426 ARRAY_2D_ALT_DEPTH                       = 0x00000000,
427 ARRAY_2D_DEPTH                           = 0x00000001,
428 } DepthArray;
429 
430 /*
431  * ENUM_NUM_SIMD_PER_CU enum
432  */
433 
434 typedef enum ENUM_NUM_SIMD_PER_CU {
435 NUM_SIMD_PER_CU                          = 0x00000004,
436 } ENUM_NUM_SIMD_PER_CU;
437 
438 /*
439  * DSM_ENABLE_ERROR_INJECT enum
440  */
441 
442 typedef enum DSM_ENABLE_ERROR_INJECT {
443 DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,
444 DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,
445 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE    = 0x00000002,
446 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED  = 0x00000003,
447 } DSM_ENABLE_ERROR_INJECT;
448 
449 /*
450  * DSM_SELECT_INJECT_DELAY enum
451  */
452 
453 typedef enum DSM_SELECT_INJECT_DELAY {
454 DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,
455 DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,
456 } DSM_SELECT_INJECT_DELAY;
457 
458 /*
459  * DSM_DATA_SEL enum
460  */
461 
462 typedef enum DSM_DATA_SEL {
463 DSM_DATA_SEL_DISABLE                     = 0x00000000,
464 DSM_DATA_SEL_0                           = 0x00000001,
465 DSM_DATA_SEL_1                           = 0x00000002,
466 DSM_DATA_SEL_BOTH                        = 0x00000003,
467 } DSM_DATA_SEL;
468 
469 /*
470  * DSM_SINGLE_WRITE enum
471  */
472 
473 typedef enum DSM_SINGLE_WRITE {
474 DSM_SINGLE_WRITE_DIS                     = 0x00000000,
475 DSM_SINGLE_WRITE_EN                      = 0x00000001,
476 } DSM_SINGLE_WRITE;
477 
478 /*
479  * Hdp_SurfaceEndian enum
480  */
481 
482 typedef enum Hdp_SurfaceEndian {
483 HDP_ENDIAN_NONE                          = 0x00000000,
484 HDP_ENDIAN_8IN16                         = 0x00000001,
485 HDP_ENDIAN_8IN32                         = 0x00000002,
486 HDP_ENDIAN_8IN64                         = 0x00000003,
487 } Hdp_SurfaceEndian;
488 
489 /*******************************************************
490  * CNVC_CFG Enums
491  *******************************************************/
492 
493 /*
494  * CNVC_ENABLE enum
495  */
496 
497 typedef enum CNVC_ENABLE {
498 CNVC_DIS                                 = 0x00000000,
499 CNVC_EN                                  = 0x00000001,
500 } CNVC_ENABLE;
501 
502 /*
503  * CNVC_BYPASS enum
504  */
505 
506 typedef enum CNVC_BYPASS {
507 CNVC_BYPASS_DISABLE                      = 0x00000000,
508 CNVC_BYPASS_EN                           = 0x00000001,
509 } CNVC_BYPASS;
510 
511 /*
512  * CNVC_PENDING enum
513  */
514 
515 typedef enum CNVC_PENDING {
516 CNVC_NOT_PENDING                         = 0x00000000,
517 CNVC_YES_PENDING                         = 0x00000001,
518 } CNVC_PENDING;
519 
520 /*
521  * DENORM_TRUNCATE enum
522  */
523 
524 typedef enum DENORM_TRUNCATE {
525 CNVC_ROUND                               = 0x00000000,
526 CNVC_TRUNCATE                            = 0x00000001,
527 } DENORM_TRUNCATE;
528 
529 /*
530  * PIX_EXPAND_MODE enum
531  */
532 
533 typedef enum PIX_EXPAND_MODE {
534 PIX_DYNAMIC_EXPANSION                    = 0x00000000,
535 PIX_ZERO_EXPANSION                       = 0x00000001,
536 } PIX_EXPAND_MODE;
537 
538 /*
539  * SURFACE_PIXEL_FORMAT enum
540  */
541 
542 typedef enum SURFACE_PIXEL_FORMAT {
543 ARGB1555                                 = 0x00000001,
544 RGBA5551                                 = 0x00000002,
545 RGB565                                   = 0x00000003,
546 BGR565                                   = 0x00000004,
547 ARGB4444                                 = 0x00000005,
548 RGBA4444                                 = 0x00000006,
549 ARGB8888                                 = 0x00000008,
550 RGBA8888                                 = 0x00000009,
551 ARGB2101010                              = 0x0000000a,
552 RGBA1010102                              = 0x0000000b,
553 AYCrCb8888                               = 0x0000000c,
554 YCrCbA8888                               = 0x0000000d,
555 ACrYCb8888                               = 0x0000000e,
556 CrYCbA8888                               = 0x0000000f,
557 ARGB16161616_10MSB                       = 0x00000010,
558 RGBA16161616_10MSB                       = 0x00000011,
559 ARGB16161616_10LSB                       = 0x00000012,
560 RGBA16161616_10LSB                       = 0x00000013,
561 ARGB16161616_12MSB                       = 0x00000014,
562 RGBA16161616_12MSB                       = 0x00000015,
563 ARGB16161616_12LSB                       = 0x00000016,
564 RGBA16161616_12LSB                       = 0x00000017,
565 ARGB16161616_FLOAT                       = 0x00000018,
566 RGBA16161616_FLOAT                       = 0x00000019,
567 ARGB16161616_UNORM                       = 0x0000001a,
568 RGBA16161616_UNORM                       = 0x0000001b,
569 ARGB16161616_SNORM                       = 0x0000001c,
570 RGBA16161616_SNORM                       = 0x0000001d,
571 AYCrCb16161616_10MSB                     = 0x00000020,
572 AYCrCb16161616_10LSB                     = 0x00000021,
573 YCrCbA16161616_10MSB                     = 0x00000022,
574 YCrCbA16161616_10LSB                     = 0x00000023,
575 ACrYCb16161616_10MSB                     = 0x00000024,
576 ACrYCb16161616_10LSB                     = 0x00000025,
577 CrYCbA16161616_10MSB                     = 0x00000026,
578 CrYCbA16161616_10LSB                     = 0x00000027,
579 AYCrCb16161616_12MSB                     = 0x00000028,
580 AYCrCb16161616_12LSB                     = 0x00000029,
581 YCrCbA16161616_12MSB                     = 0x0000002a,
582 YCrCbA16161616_12LSB                     = 0x0000002b,
583 ACrYCb16161616_12MSB                     = 0x0000002c,
584 ACrYCb16161616_12LSB                     = 0x0000002d,
585 CrYCbA16161616_12MSB                     = 0x0000002e,
586 CrYCbA16161616_12LSB                     = 0x0000002f,
587 Y8_CrCb88_420_PLANAR                     = 0x00000040,
588 Y8_CbCr88_420_PLANAR                     = 0x00000041,
589 Y10_CrCb1010_420_PLANAR                  = 0x00000042,
590 Y10_CbCr1010_420_PLANAR                  = 0x00000043,
591 Y12_CrCb1212_420_PLANAR                  = 0x00000044,
592 Y12_CbCr1212_420_PLANAR                  = 0x00000045,
593 YCrYCb8888_422_PACKED                    = 0x00000048,
594 YCbYCr8888_422_PACKED                    = 0x00000049,
595 CrYCbY8888_422_PACKED                    = 0x0000004a,
596 CbYCrY8888_422_PACKED                    = 0x0000004b,
597 YCrYCb10101010_422_PACKED                = 0x0000004c,
598 YCbYCr10101010_422_PACKED                = 0x0000004d,
599 CrYCbY10101010_422_PACKED                = 0x0000004e,
600 CbYCrY10101010_422_PACKED                = 0x0000004f,
601 YCrYCb12121212_422_PACKED                = 0x00000050,
602 YCbYCr12121212_422_PACKED                = 0x00000051,
603 CrYCbY12121212_422_PACKED                = 0x00000052,
604 CbYCrY12121212_422_PACKED                = 0x00000053,
605 RGB111110_FIX                            = 0x00000070,
606 BGR101111_FIX                            = 0x00000071,
607 ACrYCb2101010                            = 0x00000072,
608 CrYCbA1010102                            = 0x00000073,
609 RGB111110_FLOAT                          = 0x00000076,
610 BGR101111_FLOAT                          = 0x00000077,
611 MONO_8                                   = 0x00000078,
612 MONO_10MSB                               = 0x00000079,
613 MONO_10LSB                               = 0x0000007a,
614 MONO_12MSB                               = 0x0000007b,
615 MONO_12LSB                               = 0x0000007c,
616 MONO_16                                  = 0x0000007d,
617 } SURFACE_PIXEL_FORMAT;
618 
619 /*
620  * XNORM enum
621  */
622 
623 typedef enum XNORM {
624 XNORM_A                                  = 0x00000000,
625 XNORM_B                                  = 0x00000001,
626 } XNORM;
627 
628 /*
629  * COLOR_KEYER_MODE enum
630  */
631 
632 typedef enum COLOR_KEYER_MODE {
633 FORCE_00                                 = 0x00000000,
634 FORCE_FF                                 = 0x00000001,
635 RANGE_00                                 = 0x00000002,
636 RANGE_FF                                 = 0x00000003,
637 } COLOR_KEYER_MODE;
638 
639 /*******************************************************
640  * CNVC_CUR Enums
641  *******************************************************/
642 
643 /*
644  * CUR_ENABLE enum
645  */
646 
647 typedef enum CUR_ENABLE {
648 CUR_DIS                                  = 0x00000000,
649 CUR_EN                                   = 0x00000001,
650 } CUR_ENABLE;
651 
652 /*
653  * CUR_PENDING enum
654  */
655 
656 typedef enum CUR_PENDING {
657 CUR_NOT_PENDING                          = 0x00000000,
658 CUR_YES_PENDING                          = 0x00000001,
659 } CUR_PENDING;
660 
661 /*
662  * CUR_EXPAND_MODE enum
663  */
664 
665 typedef enum CUR_EXPAND_MODE {
666 CUR_DYNAMIC_EXPANSION                    = 0x00000000,
667 CUR_ZERO_EXPANSION                       = 0x00000001,
668 } CUR_EXPAND_MODE;
669 
670 /*
671  * CUR_ROM_EN enum
672  */
673 
674 typedef enum CUR_ROM_EN {
675 CUR_FP_NO_ROM                            = 0x00000000,
676 CUR_FP_USE_ROM                           = 0x00000001,
677 } CUR_ROM_EN;
678 
679 /*
680  * CUR_MODE enum
681  */
682 
683 typedef enum CUR_MODE {
684 MONO_2BIT                                = 0x00000000,
685 COLOR_24BIT_1BIT_AND                     = 0x00000001,
686 COLOR_24BIT_8BIT_ALPHA_PREMULT           = 0x00000002,
687 COLOR_24BIT_8BIT_ALPHA_UNPREMULT         = 0x00000003,
688 COLOR_64BIT_FP_PREMULT                   = 0x00000004,
689 COLOR_64BIT_FP_UNPREMULT                 = 0x00000005,
690 } CUR_MODE;
691 
692 /*
693  * CUR_INV_CLAMP enum
694  */
695 
696 typedef enum CUR_INV_CLAMP {
697 CUR_CLAMP_DIS                            = 0x00000000,
698 CUR_CLAMP_EN                             = 0x00000001,
699 } CUR_INV_CLAMP;
700 
701 /*******************************************************
702  * DSCL Enums
703  *******************************************************/
704 
705 /*
706  * SCL_COEF_FILTER_TYPE_SEL enum
707  */
708 
709 typedef enum SCL_COEF_FILTER_TYPE_SEL {
710 SCL_COEF_LUMA_VERT_FILTER                = 0x00000000,
711 SCL_COEF_LUMA_HORZ_FILTER                = 0x00000001,
712 SCL_COEF_CHROMA_VERT_FILTER              = 0x00000002,
713 SCL_COEF_CHROMA_HORZ_FILTER              = 0x00000003,
714 SCL_COEF_ALPHA_VERT_FILTER               = 0x00000004,
715 SCL_COEF_ALPHA_HORZ_FILTER               = 0x00000005,
716 } SCL_COEF_FILTER_TYPE_SEL;
717 
718 /*
719  * DSCL_MODE_SEL enum
720  */
721 
722 typedef enum DSCL_MODE_SEL {
723 DSCL_MODE_SCALING_444_BYPASS             = 0x00000000,
724 DSCL_MODE_SCALING_444_RGB_ENABLE         = 0x00000001,
725 DSCL_MODE_SCALING_444_YCBCR_ENABLE       = 0x00000002,
726 DSCL_MODE_SCALING_YCBCR_ENABLE           = 0x00000003,
727 DSCL_MODE_LUMA_SCALING_BYPASS            = 0x00000004,
728 DSCL_MODE_CHROMA_SCALING_BYPASS          = 0x00000005,
729 DSCL_MODE_DSCL_BYPASS                    = 0x00000006,
730 } DSCL_MODE_SEL;
731 
732 /*
733  * SCL_AUTOCAL_MODE enum
734  */
735 
736 typedef enum SCL_AUTOCAL_MODE {
737 AUTOCAL_MODE_OFF                         = 0x00000000,
738 AUTOCAL_MODE_AUTOSCALE                   = 0x00000001,
739 AUTOCAL_MODE_AUTOCENTER                  = 0x00000002,
740 AUTOCAL_MODE_AUTOREPLICATE               = 0x00000003,
741 } SCL_AUTOCAL_MODE;
742 
743 /*
744  * SCL_COEF_RAM_SEL enum
745  */
746 
747 typedef enum SCL_COEF_RAM_SEL {
748 SCL_COEF_RAM_SEL_0                       = 0x00000000,
749 SCL_COEF_RAM_SEL_1                       = 0x00000001,
750 } SCL_COEF_RAM_SEL;
751 
752 /*
753  * SCL_CHROMA_COEF enum
754  */
755 
756 typedef enum SCL_CHROMA_COEF {
757 SCL_CHROMA_COEF_LUMA                     = 0x00000000,
758 SCL_CHROMA_COEF_CHROMA                   = 0x00000001,
759 } SCL_CHROMA_COEF;
760 
761 /*
762  * SCL_ALPHA_COEF enum
763  */
764 
765 typedef enum SCL_ALPHA_COEF {
766 SCL_ALPHA_COEF_LUMA                      = 0x00000000,
767 SCL_ALPHA_COEF_ALPHA                     = 0x00000001,
768 } SCL_ALPHA_COEF;
769 
770 /*
771  * COEF_RAM_SELECT_RD enum
772  */
773 
774 typedef enum COEF_RAM_SELECT_RD {
775 COEF_RAM_SELECT_BACK                     = 0x00000000,
776 COEF_RAM_SELECT_CURRENT                  = 0x00000001,
777 } COEF_RAM_SELECT_RD;
778 
779 /*
780  * SCL_2TAP_HARDCODE enum
781  */
782 
783 typedef enum SCL_2TAP_HARDCODE {
784 SCL_COEF_2TAP_HARDCODE_OFF               = 0x00000000,
785 SCL_COEF_2TAP_HARDCODE_ON                = 0x00000001,
786 } SCL_2TAP_HARDCODE;
787 
788 /*
789  * SCL_SHARP_EN enum
790  */
791 
792 typedef enum SCL_SHARP_EN {
793 SCL_SHARP_DISABLE                        = 0x00000000,
794 SCL_SHARP_ENABLE                         = 0x00000001,
795 } SCL_SHARP_EN;
796 
797 /*
798  * SCL_BOUNDARY enum
799  */
800 
801 typedef enum SCL_BOUNDARY {
802 SCL_BOUNDARY_EDGE                        = 0x00000000,
803 SCL_BOUNDARY_BLACK                       = 0x00000001,
804 } SCL_BOUNDARY;
805 
806 /*
807  * LB_INTERLEAVE_EN enum
808  */
809 
810 typedef enum LB_INTERLEAVE_EN {
811 LB_INTERLEAVE_DISABLE                    = 0x00000000,
812 LB_INTERLEAVE_ENABLE                     = 0x00000001,
813 } LB_INTERLEAVE_EN;
814 
815 /*
816  * LB_ALPHA_EN enum
817  */
818 
819 typedef enum LB_ALPHA_EN {
820 LB_ALPHA_DISABLE                         = 0x00000000,
821 LB_ALPHA_ENABLE                          = 0x00000001,
822 } LB_ALPHA_EN;
823 
824 /*
825  * OBUF_BYPASS_SEL enum
826  */
827 
828 typedef enum OBUF_BYPASS_SEL {
829 OBUF_BYPASS_DIS                          = 0x00000000,
830 OBUF_BYPASS_EN                           = 0x00000001,
831 } OBUF_BYPASS_SEL;
832 
833 /*
834  * OBUF_USE_FULL_BUFFER_SEL enum
835  */
836 
837 typedef enum OBUF_USE_FULL_BUFFER_SEL {
838 OBUF_RECOUT                              = 0x00000000,
839 OBUF_FULL                                = 0x00000001,
840 } OBUF_USE_FULL_BUFFER_SEL;
841 
842 /*
843  * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
844  */
845 
846 typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
847 OBUF_FULL_RECOUT                         = 0x00000000,
848 OBUF_HALF_RECOUT                         = 0x00000001,
849 } OBUF_IS_HALF_RECOUT_WIDTH_SEL;
850 
851 /*******************************************************
852  * CM Enums
853  *******************************************************/
854 
855 /*
856  * CM_BYPASS enum
857  */
858 
859 typedef enum CM_BYPASS {
860 NON_BYPASS                               = 0x00000000,
861 BYPASS_EN                                = 0x00000001,
862 } CM_BYPASS;
863 
864 /*
865  * CM_EN enum
866  */
867 
868 typedef enum CM_EN {
869 CM_DISABLE                               = 0x00000000,
870 CM_ENABLE                                = 0x00000001,
871 } CM_EN;
872 
873 /*
874  * CM_PENDING enum
875  */
876 
877 typedef enum CM_PENDING {
878 CM_NOT_PENDING                           = 0x00000000,
879 CM_YES_PENDING                           = 0x00000001,
880 } CM_PENDING;
881 
882 /*
883  * CM_DATA_SIGNED enum
884  */
885 
886 typedef enum CM_DATA_SIGNED {
887 UNSIGNED                                 = 0x00000000,
888 SIGNED                                   = 0x00000001,
889 } CM_DATA_SIGNED;
890 
891 /*
892  * CM_WRITE_BASE_ONLY enum
893  */
894 
895 typedef enum CM_WRITE_BASE_ONLY {
896 WRITE_BOTH                               = 0x00000000,
897 WRITE_BASE_ONLY                          = 0x00000001,
898 } CM_WRITE_BASE_ONLY;
899 
900 /*
901  * CM_LUT_4_CONFIG_ENUM enum
902  */
903 
904 typedef enum CM_LUT_4_CONFIG_ENUM {
905 LUT_4CFG_NO_MEMORY                       = 0x00000000,
906 LUT_4CFG_ROM_A                           = 0x00000001,
907 LUT_4CFG_ROM_B                           = 0x00000002,
908 LUT_4CFG_MEMORY_A                        = 0x00000003,
909 LUT_4CFG_MEMORY_B                        = 0x00000004,
910 } CM_LUT_4_CONFIG_ENUM;
911 
912 /*
913  * CM_LUT_2_CONFIG_ENUM enum
914  */
915 
916 typedef enum CM_LUT_2_CONFIG_ENUM {
917 LUT_2CFG_NO_MEMORY                       = 0x00000000,
918 LUT_2CFG_MEMORY_A                        = 0x00000001,
919 LUT_2CFG_MEMORY_B                        = 0x00000002,
920 } CM_LUT_2_CONFIG_ENUM;
921 
922 /*
923  * CM_LUT_4_MODE_ENUM enum
924  */
925 
926 typedef enum CM_LUT_4_MODE_ENUM {
927 LUT_4_MODE_BYPASS                        = 0x00000000,
928 LUT_4_MODE_ROMA_LUT                      = 0x00000001,
929 LUT_4_MODE_ROMB_LUT                      = 0x00000002,
930 LUT_4_MODE_RAMA_LUT                      = 0x00000003,
931 LUT_4_MODE_RAMB_LUT                      = 0x00000004,
932 } CM_LUT_4_MODE_ENUM;
933 
934 /*
935  * CM_LUT_2_MODE_ENUM enum
936  */
937 
938 typedef enum CM_LUT_2_MODE_ENUM {
939 LUT_2_MODE_BYPASS                        = 0x00000000,
940 LUT_2_MODE_RAMA_LUT                      = 0x00000001,
941 LUT_2_MODE_RAMB_LUT                      = 0x00000002,
942 } CM_LUT_2_MODE_ENUM;
943 
944 /*
945  * CM_LUT_RAM_SEL enum
946  */
947 
948 typedef enum CM_LUT_RAM_SEL {
949 RAMA_ACCESS                              = 0x00000000,
950 RAMB_ACCESS                              = 0x00000001,
951 } CM_LUT_RAM_SEL;
952 
953 /*
954  * CM_LUT_NUM_SEG enum
955  */
956 
957 typedef enum CM_LUT_NUM_SEG {
958 SEGMENTS_1                               = 0x00000000,
959 SEGMENTS_2                               = 0x00000001,
960 SEGMENTS_4                               = 0x00000002,
961 SEGMENTS_8                               = 0x00000003,
962 SEGMENTS_16                              = 0x00000004,
963 SEGMENTS_32                              = 0x00000005,
964 SEGMENTS_64                              = 0x00000006,
965 SEGMENTS_128                             = 0x00000007,
966 } CM_LUT_NUM_SEG;
967 
968 /*
969  * CM_ICSC_MODE_ENUM enum
970  */
971 
972 typedef enum CM_ICSC_MODE_ENUM {
973 BYPASS_ICSC                              = 0x00000000,
974 COEF_ICSC                                = 0x00000001,
975 COEF_ICSC_B                              = 0x00000002,
976 } CM_ICSC_MODE_ENUM;
977 
978 /*
979  * CM_GAMUT_REMAP_MODE_ENUM enum
980  */
981 
982 typedef enum CM_GAMUT_REMAP_MODE_ENUM {
983 BYPASS_GAMUT                             = 0x00000000,
984 GAMUT_COEF                               = 0x00000001,
985 GAMUT_COEF_B                             = 0x00000002,
986 } CM_GAMUT_REMAP_MODE_ENUM;
987 
988 /*
989  * CM_COEF_FORMAT_ENUM enum
990  */
991 
992 typedef enum CM_COEF_FORMAT_ENUM {
993 FIX_S2_13                                = 0x00000000,
994 FIX_S3_12                                = 0x00000001,
995 } CM_COEF_FORMAT_ENUM;
996 
997 /*
998  * CMC_LUT_2_CONFIG_ENUM enum
999  */
1000 
1001 typedef enum CMC_LUT_2_CONFIG_ENUM {
1002 CMC_LUT_2CFG_NO_MEMORY                   = 0x00000000,
1003 CMC_LUT_2CFG_MEMORY_A                    = 0x00000001,
1004 CMC_LUT_2CFG_MEMORY_B                    = 0x00000002,
1005 } CMC_LUT_2_CONFIG_ENUM;
1006 
1007 /*
1008  * CMC_LUT_2_MODE_ENUM enum
1009  */
1010 
1011 typedef enum CMC_LUT_2_MODE_ENUM {
1012 CMC_LUT_2_MODE_BYPASS                    = 0x00000000,
1013 CMC_LUT_2_MODE_RAMA_LUT                  = 0x00000001,
1014 CMC_LUT_2_MODE_RAMB_LUT                  = 0x00000002,
1015 } CMC_LUT_2_MODE_ENUM;
1016 
1017 /*
1018  * CMC_LUT_RAM_SEL enum
1019  */
1020 
1021 typedef enum CMC_LUT_RAM_SEL {
1022 CMC_RAMA_ACCESS                          = 0x00000000,
1023 CMC_RAMB_ACCESS                          = 0x00000001,
1024 } CMC_LUT_RAM_SEL;
1025 
1026 /*
1027  * CMC_3DLUT_RAM_SEL enum
1028  */
1029 
1030 typedef enum CMC_3DLUT_RAM_SEL {
1031 CMC_RAM0_ACCESS                          = 0x00000000,
1032 CMC_RAM1_ACCESS                          = 0x00000001,
1033 CMC_RAM2_ACCESS                          = 0x00000002,
1034 CMC_RAM3_ACCESS                          = 0x00000003,
1035 } CMC_3DLUT_RAM_SEL;
1036 
1037 /*
1038  * CMC_LUT_NUM_SEG enum
1039  */
1040 
1041 typedef enum CMC_LUT_NUM_SEG {
1042 CMC_SEGMENTS_1                           = 0x00000000,
1043 CMC_SEGMENTS_2                           = 0x00000001,
1044 CMC_SEGMENTS_4                           = 0x00000002,
1045 CMC_SEGMENTS_8                           = 0x00000003,
1046 CMC_SEGMENTS_16                          = 0x00000004,
1047 CMC_SEGMENTS_32                          = 0x00000005,
1048 CMC_SEGMENTS_64                          = 0x00000006,
1049 CMC_SEGMENTS_128                         = 0x00000007,
1050 } CMC_LUT_NUM_SEG;
1051 
1052 /*
1053  * CMC_3DLUT_30BIT_ENUM enum
1054  */
1055 
1056 typedef enum CMC_3DLUT_30BIT_ENUM {
1057 CMC_3DLUT_36BIT                          = 0x00000000,
1058 CMC_3DLUT_30BIT                          = 0x00000001,
1059 } CMC_3DLUT_30BIT_ENUM;
1060 
1061 /*
1062  * CMC_3DLUT_SIZE_ENUM enum
1063  */
1064 
1065 typedef enum CMC_3DLUT_SIZE_ENUM {
1066 CMC_3DLUT_17CUBE                         = 0x00000000,
1067 CMC_3DLUT_9CUBE                          = 0x00000001,
1068 } CMC_3DLUT_SIZE_ENUM;
1069 
1070 /*******************************************************
1071  * DPP_TOP Enums
1072  *******************************************************/
1073 
1074 /*
1075  * TEST_CLK_SEL enum
1076  */
1077 
1078 typedef enum TEST_CLK_SEL {
1079 TEST_CLK_SEL_0                           = 0x00000000,
1080 TEST_CLK_SEL_1                           = 0x00000001,
1081 TEST_CLK_SEL_2                           = 0x00000002,
1082 TEST_CLK_SEL_3                           = 0x00000003,
1083 TEST_CLK_SEL_4                           = 0x00000004,
1084 TEST_CLK_SEL_5                           = 0x00000005,
1085 TEST_CLK_SEL_6                           = 0x00000006,
1086 TEST_CLK_SEL_7                           = 0x00000007,
1087 TEST_CLK_SEL_8                           = 0x00000008,
1088 } TEST_CLK_SEL;
1089 
1090 /*
1091  * CRC_SRC_SEL enum
1092  */
1093 
1094 typedef enum CRC_SRC_SEL {
1095 CRC_SRC_0                                = 0x00000000,
1096 CRC_SRC_1                                = 0x00000001,
1097 CRC_SRC_2                                = 0x00000002,
1098 CRC_SRC_3                                = 0x00000003,
1099 } CRC_SRC_SEL;
1100 
1101 /*
1102  * CRC_IN_PIX_SEL enum
1103  */
1104 
1105 typedef enum CRC_IN_PIX_SEL {
1106 CRC_IN_PIX_0                             = 0x00000000,
1107 CRC_IN_PIX_1                             = 0x00000001,
1108 CRC_IN_PIX_2                             = 0x00000002,
1109 CRC_IN_PIX_3                             = 0x00000003,
1110 CRC_IN_PIX_4                             = 0x00000004,
1111 CRC_IN_PIX_5                             = 0x00000005,
1112 CRC_IN_PIX_6                             = 0x00000006,
1113 CRC_IN_PIX_7                             = 0x00000007,
1114 } CRC_IN_PIX_SEL;
1115 
1116 /*
1117  * CRC_CUR_BITS_SEL enum
1118  */
1119 
1120 typedef enum CRC_CUR_BITS_SEL {
1121 CRC_CUR_BITS_0                           = 0x00000000,
1122 CRC_CUR_BITS_1                           = 0x00000001,
1123 } CRC_CUR_BITS_SEL;
1124 
1125 /*
1126  * CRC_IN_CUR_SEL enum
1127  */
1128 
1129 typedef enum CRC_IN_CUR_SEL {
1130 CRC_IN_CUR_0                             = 0x00000000,
1131 CRC_IN_CUR_1                             = 0x00000001,
1132 } CRC_IN_CUR_SEL;
1133 
1134 /*
1135  * CRC_CUR_SEL enum
1136  */
1137 
1138 typedef enum CRC_CUR_SEL {
1139 CRC_CUR_0                                = 0x00000000,
1140 CRC_CUR_1                                = 0x00000001,
1141 } CRC_CUR_SEL;
1142 
1143 /*
1144  * CRC_STEREO_SEL enum
1145  */
1146 
1147 typedef enum CRC_STEREO_SEL {
1148 CRC_STEREO_0                             = 0x00000000,
1149 CRC_STEREO_1                             = 0x00000001,
1150 CRC_STEREO_2                             = 0x00000002,
1151 CRC_STEREO_3                             = 0x00000003,
1152 } CRC_STEREO_SEL;
1153 
1154 /*
1155  * CRC_INTERLACE_SEL enum
1156  */
1157 
1158 typedef enum CRC_INTERLACE_SEL {
1159 CRC_INTERLACE_0                          = 0x00000000,
1160 CRC_INTERLACE_1                          = 0x00000001,
1161 CRC_INTERLACE_2                          = 0x00000002,
1162 CRC_INTERLACE_3                          = 0x00000003,
1163 } CRC_INTERLACE_SEL;
1164 
1165 /*******************************************************
1166  * DC_PERFMON Enums
1167  *******************************************************/
1168 
1169 /*
1170  * PERFCOUNTER_CVALUE_SEL enum
1171  */
1172 
1173 typedef enum PERFCOUNTER_CVALUE_SEL {
1174 PERFCOUNTER_CVALUE_SEL_47_0              = 0x00000000,
1175 PERFCOUNTER_CVALUE_SEL_15_0              = 0x00000001,
1176 PERFCOUNTER_CVALUE_SEL_31_16             = 0x00000002,
1177 PERFCOUNTER_CVALUE_SEL_47_32             = 0x00000003,
1178 PERFCOUNTER_CVALUE_SEL_11_0              = 0x00000004,
1179 PERFCOUNTER_CVALUE_SEL_23_12             = 0x00000005,
1180 PERFCOUNTER_CVALUE_SEL_35_24             = 0x00000006,
1181 PERFCOUNTER_CVALUE_SEL_47_36             = 0x00000007,
1182 } PERFCOUNTER_CVALUE_SEL;
1183 
1184 /*
1185  * PERFCOUNTER_INC_MODE enum
1186  */
1187 
1188 typedef enum PERFCOUNTER_INC_MODE {
1189 PERFCOUNTER_INC_MODE_MULTI_BIT           = 0x00000000,
1190 PERFCOUNTER_INC_MODE_BOTH_EDGE           = 0x00000001,
1191 PERFCOUNTER_INC_MODE_LSB                 = 0x00000002,
1192 PERFCOUNTER_INC_MODE_POS_EDGE            = 0x00000003,
1193 PERFCOUNTER_INC_MODE_NEG_EDGE            = 0x00000004,
1194 } PERFCOUNTER_INC_MODE;
1195 
1196 /*
1197  * PERFCOUNTER_HW_CNTL_SEL enum
1198  */
1199 
1200 typedef enum PERFCOUNTER_HW_CNTL_SEL {
1201 PERFCOUNTER_HW_CNTL_SEL_RUNEN            = 0x00000000,
1202 PERFCOUNTER_HW_CNTL_SEL_CNTOFF           = 0x00000001,
1203 } PERFCOUNTER_HW_CNTL_SEL;
1204 
1205 /*
1206  * PERFCOUNTER_RUNEN_MODE enum
1207  */
1208 
1209 typedef enum PERFCOUNTER_RUNEN_MODE {
1210 PERFCOUNTER_RUNEN_MODE_LEVEL             = 0x00000000,
1211 PERFCOUNTER_RUNEN_MODE_EDGE              = 0x00000001,
1212 } PERFCOUNTER_RUNEN_MODE;
1213 
1214 /*
1215  * PERFCOUNTER_CNTOFF_START_DIS enum
1216  */
1217 
1218 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1219 PERFCOUNTER_CNTOFF_START_ENABLE          = 0x00000000,
1220 PERFCOUNTER_CNTOFF_START_DISABLE         = 0x00000001,
1221 } PERFCOUNTER_CNTOFF_START_DIS;
1222 
1223 /*
1224  * PERFCOUNTER_RESTART_EN enum
1225  */
1226 
1227 typedef enum PERFCOUNTER_RESTART_EN {
1228 PERFCOUNTER_RESTART_DISABLE              = 0x00000000,
1229 PERFCOUNTER_RESTART_ENABLE               = 0x00000001,
1230 } PERFCOUNTER_RESTART_EN;
1231 
1232 /*
1233  * PERFCOUNTER_INT_EN enum
1234  */
1235 
1236 typedef enum PERFCOUNTER_INT_EN {
1237 PERFCOUNTER_INT_DISABLE                  = 0x00000000,
1238 PERFCOUNTER_INT_ENABLE                   = 0x00000001,
1239 } PERFCOUNTER_INT_EN;
1240 
1241 /*
1242  * PERFCOUNTER_OFF_MASK enum
1243  */
1244 
1245 typedef enum PERFCOUNTER_OFF_MASK {
1246 PERFCOUNTER_OFF_MASK_DISABLE             = 0x00000000,
1247 PERFCOUNTER_OFF_MASK_ENABLE              = 0x00000001,
1248 } PERFCOUNTER_OFF_MASK;
1249 
1250 /*
1251  * PERFCOUNTER_ACTIVE enum
1252  */
1253 
1254 typedef enum PERFCOUNTER_ACTIVE {
1255 PERFCOUNTER_IS_IDLE                      = 0x00000000,
1256 PERFCOUNTER_IS_ACTIVE                    = 0x00000001,
1257 } PERFCOUNTER_ACTIVE;
1258 
1259 /*
1260  * PERFCOUNTER_INT_TYPE enum
1261  */
1262 
1263 typedef enum PERFCOUNTER_INT_TYPE {
1264 PERFCOUNTER_INT_TYPE_LEVEL               = 0x00000000,
1265 PERFCOUNTER_INT_TYPE_PULSE               = 0x00000001,
1266 } PERFCOUNTER_INT_TYPE;
1267 
1268 /*
1269  * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1270  */
1271 
1272 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1273 PERFCOUNTER_COUNTED_VALUE_TYPE_ACC       = 0x00000000,
1274 PERFCOUNTER_COUNTED_VALUE_TYPE_MAX       = 0x00000001,
1275 PERFCOUNTER_COUNTED_VALUE_TYPE_MIN       = 0x00000002,
1276 } PERFCOUNTER_COUNTED_VALUE_TYPE;
1277 
1278 /*
1279  * PERFCOUNTER_HW_STOP1_SEL enum
1280  */
1281 
1282 typedef enum PERFCOUNTER_HW_STOP1_SEL {
1283 PERFCOUNTER_HW_STOP1_0                   = 0x00000000,
1284 PERFCOUNTER_HW_STOP1_1                   = 0x00000001,
1285 } PERFCOUNTER_HW_STOP1_SEL;
1286 
1287 /*
1288  * PERFCOUNTER_HW_STOP2_SEL enum
1289  */
1290 
1291 typedef enum PERFCOUNTER_HW_STOP2_SEL {
1292 PERFCOUNTER_HW_STOP2_0                   = 0x00000000,
1293 PERFCOUNTER_HW_STOP2_1                   = 0x00000001,
1294 } PERFCOUNTER_HW_STOP2_SEL;
1295 
1296 /*
1297  * PERFCOUNTER_CNTL_SEL enum
1298  */
1299 
1300 typedef enum PERFCOUNTER_CNTL_SEL {
1301 PERFCOUNTER_CNTL_SEL_0                   = 0x00000000,
1302 PERFCOUNTER_CNTL_SEL_1                   = 0x00000001,
1303 PERFCOUNTER_CNTL_SEL_2                   = 0x00000002,
1304 PERFCOUNTER_CNTL_SEL_3                   = 0x00000003,
1305 PERFCOUNTER_CNTL_SEL_4                   = 0x00000004,
1306 PERFCOUNTER_CNTL_SEL_5                   = 0x00000005,
1307 PERFCOUNTER_CNTL_SEL_6                   = 0x00000006,
1308 PERFCOUNTER_CNTL_SEL_7                   = 0x00000007,
1309 } PERFCOUNTER_CNTL_SEL;
1310 
1311 /*
1312  * PERFCOUNTER_CNT0_STATE enum
1313  */
1314 
1315 typedef enum PERFCOUNTER_CNT0_STATE {
1316 PERFCOUNTER_CNT0_STATE_RESET             = 0x00000000,
1317 PERFCOUNTER_CNT0_STATE_START             = 0x00000001,
1318 PERFCOUNTER_CNT0_STATE_FREEZE            = 0x00000002,
1319 PERFCOUNTER_CNT0_STATE_HW                = 0x00000003,
1320 } PERFCOUNTER_CNT0_STATE;
1321 
1322 /*
1323  * PERFCOUNTER_STATE_SEL0 enum
1324  */
1325 
1326 typedef enum PERFCOUNTER_STATE_SEL0 {
1327 PERFCOUNTER_STATE_SEL0_GLOBAL            = 0x00000000,
1328 PERFCOUNTER_STATE_SEL0_LOCAL             = 0x00000001,
1329 } PERFCOUNTER_STATE_SEL0;
1330 
1331 /*
1332  * PERFCOUNTER_CNT1_STATE enum
1333  */
1334 
1335 typedef enum PERFCOUNTER_CNT1_STATE {
1336 PERFCOUNTER_CNT1_STATE_RESET             = 0x00000000,
1337 PERFCOUNTER_CNT1_STATE_START             = 0x00000001,
1338 PERFCOUNTER_CNT1_STATE_FREEZE            = 0x00000002,
1339 PERFCOUNTER_CNT1_STATE_HW                = 0x00000003,
1340 } PERFCOUNTER_CNT1_STATE;
1341 
1342 /*
1343  * PERFCOUNTER_STATE_SEL1 enum
1344  */
1345 
1346 typedef enum PERFCOUNTER_STATE_SEL1 {
1347 PERFCOUNTER_STATE_SEL1_GLOBAL            = 0x00000000,
1348 PERFCOUNTER_STATE_SEL1_LOCAL             = 0x00000001,
1349 } PERFCOUNTER_STATE_SEL1;
1350 
1351 /*
1352  * PERFCOUNTER_CNT2_STATE enum
1353  */
1354 
1355 typedef enum PERFCOUNTER_CNT2_STATE {
1356 PERFCOUNTER_CNT2_STATE_RESET             = 0x00000000,
1357 PERFCOUNTER_CNT2_STATE_START             = 0x00000001,
1358 PERFCOUNTER_CNT2_STATE_FREEZE            = 0x00000002,
1359 PERFCOUNTER_CNT2_STATE_HW                = 0x00000003,
1360 } PERFCOUNTER_CNT2_STATE;
1361 
1362 /*
1363  * PERFCOUNTER_STATE_SEL2 enum
1364  */
1365 
1366 typedef enum PERFCOUNTER_STATE_SEL2 {
1367 PERFCOUNTER_STATE_SEL2_GLOBAL            = 0x00000000,
1368 PERFCOUNTER_STATE_SEL2_LOCAL             = 0x00000001,
1369 } PERFCOUNTER_STATE_SEL2;
1370 
1371 /*
1372  * PERFCOUNTER_CNT3_STATE enum
1373  */
1374 
1375 typedef enum PERFCOUNTER_CNT3_STATE {
1376 PERFCOUNTER_CNT3_STATE_RESET             = 0x00000000,
1377 PERFCOUNTER_CNT3_STATE_START             = 0x00000001,
1378 PERFCOUNTER_CNT3_STATE_FREEZE            = 0x00000002,
1379 PERFCOUNTER_CNT3_STATE_HW                = 0x00000003,
1380 } PERFCOUNTER_CNT3_STATE;
1381 
1382 /*
1383  * PERFCOUNTER_STATE_SEL3 enum
1384  */
1385 
1386 typedef enum PERFCOUNTER_STATE_SEL3 {
1387 PERFCOUNTER_STATE_SEL3_GLOBAL            = 0x00000000,
1388 PERFCOUNTER_STATE_SEL3_LOCAL             = 0x00000001,
1389 } PERFCOUNTER_STATE_SEL3;
1390 
1391 /*
1392  * PERFCOUNTER_CNT4_STATE enum
1393  */
1394 
1395 typedef enum PERFCOUNTER_CNT4_STATE {
1396 PERFCOUNTER_CNT4_STATE_RESET             = 0x00000000,
1397 PERFCOUNTER_CNT4_STATE_START             = 0x00000001,
1398 PERFCOUNTER_CNT4_STATE_FREEZE            = 0x00000002,
1399 PERFCOUNTER_CNT4_STATE_HW                = 0x00000003,
1400 } PERFCOUNTER_CNT4_STATE;
1401 
1402 /*
1403  * PERFCOUNTER_STATE_SEL4 enum
1404  */
1405 
1406 typedef enum PERFCOUNTER_STATE_SEL4 {
1407 PERFCOUNTER_STATE_SEL4_GLOBAL            = 0x00000000,
1408 PERFCOUNTER_STATE_SEL4_LOCAL             = 0x00000001,
1409 } PERFCOUNTER_STATE_SEL4;
1410 
1411 /*
1412  * PERFCOUNTER_CNT5_STATE enum
1413  */
1414 
1415 typedef enum PERFCOUNTER_CNT5_STATE {
1416 PERFCOUNTER_CNT5_STATE_RESET             = 0x00000000,
1417 PERFCOUNTER_CNT5_STATE_START             = 0x00000001,
1418 PERFCOUNTER_CNT5_STATE_FREEZE            = 0x00000002,
1419 PERFCOUNTER_CNT5_STATE_HW                = 0x00000003,
1420 } PERFCOUNTER_CNT5_STATE;
1421 
1422 /*
1423  * PERFCOUNTER_STATE_SEL5 enum
1424  */
1425 
1426 typedef enum PERFCOUNTER_STATE_SEL5 {
1427 PERFCOUNTER_STATE_SEL5_GLOBAL            = 0x00000000,
1428 PERFCOUNTER_STATE_SEL5_LOCAL             = 0x00000001,
1429 } PERFCOUNTER_STATE_SEL5;
1430 
1431 /*
1432  * PERFCOUNTER_CNT6_STATE enum
1433  */
1434 
1435 typedef enum PERFCOUNTER_CNT6_STATE {
1436 PERFCOUNTER_CNT6_STATE_RESET             = 0x00000000,
1437 PERFCOUNTER_CNT6_STATE_START             = 0x00000001,
1438 PERFCOUNTER_CNT6_STATE_FREEZE            = 0x00000002,
1439 PERFCOUNTER_CNT6_STATE_HW                = 0x00000003,
1440 } PERFCOUNTER_CNT6_STATE;
1441 
1442 /*
1443  * PERFCOUNTER_STATE_SEL6 enum
1444  */
1445 
1446 typedef enum PERFCOUNTER_STATE_SEL6 {
1447 PERFCOUNTER_STATE_SEL6_GLOBAL            = 0x00000000,
1448 PERFCOUNTER_STATE_SEL6_LOCAL             = 0x00000001,
1449 } PERFCOUNTER_STATE_SEL6;
1450 
1451 /*
1452  * PERFCOUNTER_CNT7_STATE enum
1453  */
1454 
1455 typedef enum PERFCOUNTER_CNT7_STATE {
1456 PERFCOUNTER_CNT7_STATE_RESET             = 0x00000000,
1457 PERFCOUNTER_CNT7_STATE_START             = 0x00000001,
1458 PERFCOUNTER_CNT7_STATE_FREEZE            = 0x00000002,
1459 PERFCOUNTER_CNT7_STATE_HW                = 0x00000003,
1460 } PERFCOUNTER_CNT7_STATE;
1461 
1462 /*
1463  * PERFCOUNTER_STATE_SEL7 enum
1464  */
1465 
1466 typedef enum PERFCOUNTER_STATE_SEL7 {
1467 PERFCOUNTER_STATE_SEL7_GLOBAL            = 0x00000000,
1468 PERFCOUNTER_STATE_SEL7_LOCAL             = 0x00000001,
1469 } PERFCOUNTER_STATE_SEL7;
1470 
1471 /*
1472  * PERFMON_STATE enum
1473  */
1474 
1475 typedef enum PERFMON_STATE {
1476 PERFMON_STATE_RESET                      = 0x00000000,
1477 PERFMON_STATE_START                      = 0x00000001,
1478 PERFMON_STATE_FREEZE                     = 0x00000002,
1479 PERFMON_STATE_HW                         = 0x00000003,
1480 } PERFMON_STATE;
1481 
1482 /*
1483  * PERFMON_CNTOFF_AND_OR enum
1484  */
1485 
1486 typedef enum PERFMON_CNTOFF_AND_OR {
1487 PERFMON_CNTOFF_OR                        = 0x00000000,
1488 PERFMON_CNTOFF_AND                       = 0x00000001,
1489 } PERFMON_CNTOFF_AND_OR;
1490 
1491 /*
1492  * PERFMON_CNTOFF_INT_EN enum
1493  */
1494 
1495 typedef enum PERFMON_CNTOFF_INT_EN {
1496 PERFMON_CNTOFF_INT_DISABLE               = 0x00000000,
1497 PERFMON_CNTOFF_INT_ENABLE                = 0x00000001,
1498 } PERFMON_CNTOFF_INT_EN;
1499 
1500 /*
1501  * PERFMON_CNTOFF_INT_TYPE enum
1502  */
1503 
1504 typedef enum PERFMON_CNTOFF_INT_TYPE {
1505 PERFMON_CNTOFF_INT_TYPE_LEVEL            = 0x00000000,
1506 PERFMON_CNTOFF_INT_TYPE_PULSE            = 0x00000001,
1507 } PERFMON_CNTOFF_INT_TYPE;
1508 
1509 /*******************************************************
1510  * HUBP Enums
1511  *******************************************************/
1512 
1513 /*
1514  * ROTATION_ANGLE enum
1515  */
1516 
1517 typedef enum ROTATION_ANGLE {
1518 ROTATE_0_DEGREES                         = 0x00000000,
1519 ROTATE_90_DEGREES                        = 0x00000001,
1520 ROTATE_180_DEGREES                       = 0x00000002,
1521 ROTATE_270_DEGREES                       = 0x00000003,
1522 } ROTATION_ANGLE;
1523 
1524 /*
1525  * H_MIRROR_EN enum
1526  */
1527 
1528 typedef enum H_MIRROR_EN {
1529 HW_MIRRORING_DISABLE                     = 0x00000000,
1530 HW_MIRRORING_ENABLE                      = 0x00000001,
1531 } H_MIRROR_EN;
1532 
1533 /*
1534  * NUM_PIPES enum
1535  */
1536 
1537 typedef enum NUM_PIPES {
1538 ONE_PIPE                                 = 0x00000000,
1539 TWO_PIPES                                = 0x00000001,
1540 FOUR_PIPES                               = 0x00000002,
1541 EIGHT_PIPES                              = 0x00000003,
1542 SIXTEEN_PIPES                            = 0x00000004,
1543 THIRTY_TWO_PIPES                         = 0x00000005,
1544 SIXTY_FOUR_PIPES                         = 0x00000006,
1545 } NUM_PIPES;
1546 
1547 /*
1548  * NUM_BANKS enum
1549  */
1550 
1551 typedef enum NUM_BANKS {
1552 ONE_BANK                                 = 0x00000000,
1553 TWO_BANKS                                = 0x00000001,
1554 FOUR_BANKS                               = 0x00000002,
1555 EIGHT_BANKS                              = 0x00000003,
1556 SIXTEEN_BANKS                            = 0x00000004,
1557 } NUM_BANKS;
1558 
1559 /*
1560  * SW_MODE enum
1561  */
1562 
1563 typedef enum SW_MODE {
1564 SWIZZLE_LINEAR                           = 0x00000000,
1565 SWIZZLE_4KB_S                            = 0x00000005,
1566 SWIZZLE_4KB_D                            = 0x00000006,
1567 SWIZZLE_64KB_S                           = 0x00000009,
1568 SWIZZLE_64KB_D                           = 0x0000000a,
1569 SWIZZLE_VAR_S                            = 0x0000000d,
1570 SWIZZLE_VAR_D                            = 0x0000000e,
1571 SWIZZLE_64KB_S_T                         = 0x00000011,
1572 SWIZZLE_64KB_D_T                         = 0x00000012,
1573 SWIZZLE_4KB_S_X                          = 0x00000015,
1574 SWIZZLE_4KB_D_X                          = 0x00000016,
1575 SWIZZLE_64KB_S_X                         = 0x00000019,
1576 SWIZZLE_64KB_D_X                         = 0x0000001a,
1577 SWIZZLE_64KB_R_X                         = 0x0000001b,
1578 SWIZZLE_VAR_S_X                          = 0x0000001d,
1579 SWIZZLE_VAR_D_X                          = 0x0000001e,
1580 } SW_MODE;
1581 
1582 /*
1583  * PIPE_INTERLEAVE enum
1584  */
1585 
1586 typedef enum PIPE_INTERLEAVE {
1587 PIPE_INTERLEAVE_256B                     = 0x00000000,
1588 PIPE_INTERLEAVE_512B                     = 0x00000001,
1589 PIPE_INTERLEAVE_1KB                      = 0x00000002,
1590 } PIPE_INTERLEAVE;
1591 
1592 /*
1593  * LEGACY_PIPE_INTERLEAVE enum
1594  */
1595 
1596 typedef enum LEGACY_PIPE_INTERLEAVE {
1597 LEGACY_PIPE_INTERLEAVE_256B              = 0x00000000,
1598 LEGACY_PIPE_INTERLEAVE_512B              = 0x00000001,
1599 } LEGACY_PIPE_INTERLEAVE;
1600 
1601 /*
1602  * NUM_SE enum
1603  */
1604 
1605 typedef enum NUM_SE {
1606 ONE_SHADER_ENGIN                         = 0x00000000,
1607 TWO_SHADER_ENGINS                        = 0x00000001,
1608 FOUR_SHADER_ENGINS                       = 0x00000002,
1609 EIGHT_SHADER_ENGINS                      = 0x00000003,
1610 } NUM_SE;
1611 
1612 /*
1613  * NUM_RB_PER_SE enum
1614  */
1615 
1616 typedef enum NUM_RB_PER_SE {
1617 ONE_RB_PER_SE                            = 0x00000000,
1618 TWO_RB_PER_SE                            = 0x00000001,
1619 FOUR_RB_PER_SE                           = 0x00000002,
1620 } NUM_RB_PER_SE;
1621 
1622 /*
1623  * MAX_COMPRESSED_FRAGS enum
1624  */
1625 
1626 typedef enum MAX_COMPRESSED_FRAGS {
1627 ONE_FRAGMENT                             = 0x00000000,
1628 TWO_FRAGMENTS                            = 0x00000001,
1629 FOUR_FRAGMENTS                           = 0x00000002,
1630 EIGHT_FRAGMENTS                          = 0x00000003,
1631 } MAX_COMPRESSED_FRAGS;
1632 
1633 /*
1634  * DIM_TYPE enum
1635  */
1636 
1637 typedef enum DIM_TYPE {
1638 DIM_TYPE_1D                              = 0x00000000,
1639 DIM_TYPE_2D                              = 0x00000001,
1640 DIM_TYPE_3D                              = 0x00000002,
1641 DIM_TYPE_RESERVED                        = 0x00000003,
1642 } DIM_TYPE;
1643 
1644 /*
1645  * META_LINEAR enum
1646  */
1647 
1648 typedef enum META_LINEAR {
1649 META_SURF_TILED                          = 0x00000000,
1650 META_SURF_LINEAR                         = 0x00000001,
1651 } META_LINEAR;
1652 
1653 /*
1654  * RB_ALIGNED enum
1655  */
1656 
1657 typedef enum RB_ALIGNED {
1658 RB_UNALIGNED_META_SURF                   = 0x00000000,
1659 RB_ALIGNED_META_SURF                     = 0x00000001,
1660 } RB_ALIGNED;
1661 
1662 /*
1663  * PIPE_ALIGNED enum
1664  */
1665 
1666 typedef enum PIPE_ALIGNED {
1667 PIPE_UNALIGNED_SURF                      = 0x00000000,
1668 PIPE_ALIGNED_SURF                        = 0x00000001,
1669 } PIPE_ALIGNED;
1670 
1671 /*
1672  * ARRAY_MODE enum
1673  */
1674 
1675 typedef enum ARRAY_MODE {
1676 AM_LINEAR_GENERAL                        = 0x00000000,
1677 AM_LINEAR_ALIGNED                        = 0x00000001,
1678 AM_1D_TILED_THIN1                        = 0x00000002,
1679 AM_1D_TILED_THICK                        = 0x00000003,
1680 AM_2D_TILED_THIN1                        = 0x00000004,
1681 AM_PRT_TILED_THIN1                       = 0x00000005,
1682 AM_PRT_2D_TILED_THIN1                    = 0x00000006,
1683 AM_2D_TILED_THICK                        = 0x00000007,
1684 AM_2D_TILED_XTHICK                       = 0x00000008,
1685 AM_PRT_TILED_THICK                       = 0x00000009,
1686 AM_PRT_2D_TILED_THICK                    = 0x0000000a,
1687 AM_PRT_3D_TILED_THIN1                    = 0x0000000b,
1688 AM_3D_TILED_THIN1                        = 0x0000000c,
1689 AM_3D_TILED_THICK                        = 0x0000000d,
1690 AM_3D_TILED_XTHICK                       = 0x0000000e,
1691 AM_PRT_3D_TILED_THICK                    = 0x0000000f,
1692 } ARRAY_MODE;
1693 
1694 /*
1695  * PIPE_CONFIG enum
1696  */
1697 
1698 typedef enum PIPE_CONFIG {
1699 P2                                       = 0x00000000,
1700 P4_8x16                                  = 0x00000004,
1701 P4_16x16                                 = 0x00000005,
1702 P4_16x32                                 = 0x00000006,
1703 P4_32x32                                 = 0x00000007,
1704 P8_16x16_8x16                            = 0x00000008,
1705 P8_16x32_8x16                            = 0x00000009,
1706 P8_32x32_8x16                            = 0x0000000a,
1707 P8_16x32_16x16                           = 0x0000000b,
1708 P8_32x32_16x16                           = 0x0000000c,
1709 P8_32x32_16x32                           = 0x0000000d,
1710 P8_32x64_32x32                           = 0x0000000e,
1711 P16_32x32_8x16                           = 0x00000010,
1712 P16_32x32_16x16                          = 0x00000011,
1713 P16_ADDR_SURF                            = 0x00000012,
1714 } PIPE_CONFIG;
1715 
1716 /*
1717  * MICRO_TILE_MODE_NEW enum
1718  */
1719 
1720 typedef enum MICRO_TILE_MODE_NEW {
1721 DISPLAY_MICRO_TILING                     = 0x00000000,
1722 THIN_MICRO_TILING                        = 0x00000001,
1723 DEPTH_MICRO_TILING                       = 0x00000002,
1724 ROTATED_MICRO_TILING                     = 0x00000003,
1725 THICK_MICRO_TILING                       = 0x00000004,
1726 } MICRO_TILE_MODE_NEW;
1727 
1728 /*
1729  * TILE_SPLIT enum
1730  */
1731 
1732 typedef enum TILE_SPLIT {
1733 SURF_TILE_SPLIT_64B                      = 0x00000000,
1734 SURF_TILE_SPLIT_128B                     = 0x00000001,
1735 SURF_TILE_SPLIT_256B                     = 0x00000002,
1736 SURF_TILE_SPLIT_512B                     = 0x00000003,
1737 SURF_TILE_SPLIT_1KB                      = 0x00000004,
1738 SURF_TILE_SPLIT_2KB                      = 0x00000005,
1739 SURF_TILE_SPLIT_4KB                      = 0x00000006,
1740 } TILE_SPLIT;
1741 
1742 /*
1743  * BANK_WIDTH enum
1744  */
1745 
1746 typedef enum BANK_WIDTH {
1747 SURF_BANK_WIDTH_1                        = 0x00000000,
1748 SURF_BANK_WIDTH_2                        = 0x00000001,
1749 SURF_BANK_WIDTH_4                        = 0x00000002,
1750 SURF_BANK_WIDTH_8                        = 0x00000003,
1751 } BANK_WIDTH;
1752 
1753 /*
1754  * BANK_HEIGHT enum
1755  */
1756 
1757 typedef enum BANK_HEIGHT {
1758 SURF_BANK_HEIGHT_1                       = 0x00000000,
1759 SURF_BANK_HEIGHT_2                       = 0x00000001,
1760 SURF_BANK_HEIGHT_4                       = 0x00000002,
1761 SURF_BANK_HEIGHT_8                       = 0x00000003,
1762 } BANK_HEIGHT;
1763 
1764 /*
1765  * MACRO_TILE_ASPECT enum
1766  */
1767 
1768 typedef enum MACRO_TILE_ASPECT {
1769 SURF_MACRO_ASPECT_1                      = 0x00000000,
1770 SURF_MACRO_ASPECT_2                      = 0x00000001,
1771 SURF_MACRO_ASPECT_4                      = 0x00000002,
1772 SURF_MACRO_ASPECT_8                      = 0x00000003,
1773 } MACRO_TILE_ASPECT;
1774 
1775 /*
1776  * LEGACY_NUM_BANKS enum
1777  */
1778 
1779 typedef enum LEGACY_NUM_BANKS {
1780 SURF_2_BANK                              = 0x00000000,
1781 SURF_4_BANK                              = 0x00000001,
1782 SURF_8_BANK                              = 0x00000002,
1783 SURF_16_BANK                             = 0x00000003,
1784 } LEGACY_NUM_BANKS;
1785 
1786 /*
1787  * SWATH_HEIGHT enum
1788  */
1789 
1790 typedef enum SWATH_HEIGHT {
1791 SWATH_HEIGHT_1L                          = 0x00000000,
1792 SWATH_HEIGHT_2L                          = 0x00000001,
1793 SWATH_HEIGHT_4L                          = 0x00000002,
1794 SWATH_HEIGHT_8L                          = 0x00000003,
1795 SWATH_HEIGHT_16L                         = 0x00000004,
1796 } SWATH_HEIGHT;
1797 
1798 /*
1799  * PTE_ROW_HEIGHT_LINEAR enum
1800  */
1801 
1802 typedef enum PTE_ROW_HEIGHT_LINEAR {
1803 PTE_ROW_HEIGHT_LINEAR_8L                 = 0x00000000,
1804 PTE_ROW_HEIGHT_LINEAR_16L                = 0x00000001,
1805 PTE_ROW_HEIGHT_LINEAR_32L                = 0x00000002,
1806 PTE_ROW_HEIGHT_LINEAR_64L                = 0x00000003,
1807 PTE_ROW_HEIGHT_LINEAR_128L               = 0x00000004,
1808 PTE_ROW_HEIGHT_LINEAR_256L               = 0x00000005,
1809 PTE_ROW_HEIGHT_LINEAR_512L               = 0x00000006,
1810 PTE_ROW_HEIGHT_LINEAR_1024L              = 0x00000007,
1811 } PTE_ROW_HEIGHT_LINEAR;
1812 
1813 /*
1814  * CHUNK_SIZE enum
1815  */
1816 
1817 typedef enum CHUNK_SIZE {
1818 CHUNK_SIZE_1KB                           = 0x00000000,
1819 CHUNK_SIZE_2KB                           = 0x00000001,
1820 CHUNK_SIZE_4KB                           = 0x00000002,
1821 CHUNK_SIZE_8KB                           = 0x00000003,
1822 CHUNK_SIZE_16KB                          = 0x00000004,
1823 CHUNK_SIZE_32KB                          = 0x00000005,
1824 CHUNK_SIZE_64KB                          = 0x00000006,
1825 } CHUNK_SIZE;
1826 
1827 /*
1828  * MIN_CHUNK_SIZE enum
1829  */
1830 
1831 typedef enum MIN_CHUNK_SIZE {
1832 NO_MIN_CHUNK_SIZE                        = 0x00000000,
1833 MIN_CHUNK_SIZE_256B                      = 0x00000001,
1834 MIN_CHUNK_SIZE_512B                      = 0x00000002,
1835 MIN_CHUNK_SIZE_1024B                     = 0x00000003,
1836 } MIN_CHUNK_SIZE;
1837 
1838 /*
1839  * META_CHUNK_SIZE enum
1840  */
1841 
1842 typedef enum META_CHUNK_SIZE {
1843 META_CHUNK_SIZE_1KB                      = 0x00000000,
1844 META_CHUNK_SIZE_2KB                      = 0x00000001,
1845 META_CHUNK_SIZE_4KB                      = 0x00000002,
1846 META_CHUNK_SIZE_8KB                      = 0x00000003,
1847 } META_CHUNK_SIZE;
1848 
1849 /*
1850  * MIN_META_CHUNK_SIZE enum
1851  */
1852 
1853 typedef enum MIN_META_CHUNK_SIZE {
1854 NO_MIN_META_CHUNK_SIZE                   = 0x00000000,
1855 MIN_META_CHUNK_SIZE_64B                  = 0x00000001,
1856 MIN_META_CHUNK_SIZE_128B                 = 0x00000002,
1857 MIN_META_CHUNK_SIZE_256B                 = 0x00000003,
1858 } MIN_META_CHUNK_SIZE;
1859 
1860 /*
1861  * DPTE_GROUP_SIZE enum
1862  */
1863 
1864 typedef enum DPTE_GROUP_SIZE {
1865 DPTE_GROUP_SIZE_64B                      = 0x00000000,
1866 DPTE_GROUP_SIZE_128B                     = 0x00000001,
1867 DPTE_GROUP_SIZE_256B                     = 0x00000002,
1868 DPTE_GROUP_SIZE_512B                     = 0x00000003,
1869 DPTE_GROUP_SIZE_1024B                    = 0x00000004,
1870 DPTE_GROUP_SIZE_2048B                    = 0x00000005,
1871 DPTE_GROUP_SIZE_4096B                    = 0x00000006,
1872 DPTE_GROUP_SIZE_8192B                    = 0x00000007,
1873 } DPTE_GROUP_SIZE;
1874 
1875 /*
1876  * MPTE_GROUP_SIZE enum
1877  */
1878 
1879 typedef enum MPTE_GROUP_SIZE {
1880 MPTE_GROUP_SIZE_64B                      = 0x00000000,
1881 MPTE_GROUP_SIZE_128B                     = 0x00000001,
1882 MPTE_GROUP_SIZE_256B                     = 0x00000002,
1883 MPTE_GROUP_SIZE_512B                     = 0x00000003,
1884 MPTE_GROUP_SIZE_1024B                    = 0x00000004,
1885 MPTE_GROUP_SIZE_2048B                    = 0x00000005,
1886 MPTE_GROUP_SIZE_4096B                    = 0x00000006,
1887 MPTE_GROUP_SIZE_8192B                    = 0x00000007,
1888 } MPTE_GROUP_SIZE;
1889 
1890 /*
1891  * HUBP_BLANK_EN enum
1892  */
1893 
1894 typedef enum HUBP_BLANK_EN {
1895 HUBP_BLANK_SW_DEASSERT                   = 0x00000000,
1896 HUBP_BLANK_SW_ASSERT                     = 0x00000001,
1897 } HUBP_BLANK_EN;
1898 
1899 /*
1900  * HUBP_DISABLE enum
1901  */
1902 
1903 typedef enum HUBP_DISABLE {
1904 HUBP_ENABLED                             = 0x00000000,
1905 HUBP_DISABLED                            = 0x00000001,
1906 } HUBP_DISABLE;
1907 
1908 /*
1909  * HUBP_TTU_DISABLE enum
1910  */
1911 
1912 typedef enum HUBP_TTU_DISABLE {
1913 HUBP_TTU_ENABLED                         = 0x00000000,
1914 HUBP_TTU_DISABLED                        = 0x00000001,
1915 } HUBP_TTU_DISABLE;
1916 
1917 /*
1918  * HUBP_NO_OUTSTANDING_REQ enum
1919  */
1920 
1921 typedef enum HUBP_NO_OUTSTANDING_REQ {
1922 OUTSTANDING_REQ                          = 0x00000000,
1923 NO_OUTSTANDING_REQ                       = 0x00000001,
1924 } HUBP_NO_OUTSTANDING_REQ;
1925 
1926 /*
1927  * HUBP_IN_BLANK enum
1928  */
1929 
1930 typedef enum HUBP_IN_BLANK {
1931 HUBP_IN_ACTIVE                           = 0x00000000,
1932 HUBP_IN_VBLANK                           = 0x00000001,
1933 } HUBP_IN_BLANK;
1934 
1935 /*
1936  * HUBP_VTG_SEL enum
1937  */
1938 
1939 typedef enum HUBP_VTG_SEL {
1940 VTG_SEL_0                                = 0x00000000,
1941 VTG_SEL_1                                = 0x00000001,
1942 VTG_SEL_2                                = 0x00000002,
1943 VTG_SEL_3                                = 0x00000003,
1944 VTG_SEL_4                                = 0x00000004,
1945 VTG_SEL_5                                = 0x00000005,
1946 } HUBP_VTG_SEL;
1947 
1948 /*
1949  * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1950  */
1951 
1952 typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1953 VREADY_BEFORE_VSYNC                      = 0x00000000,
1954 VREADY_AT_OR_AFTER_VSYNC                 = 0x00000001,
1955 } HUBP_VREADY_AT_OR_AFTER_VSYNC;
1956 
1957 /*
1958  * VMPG_SIZE enum
1959  */
1960 
1961 typedef enum VMPG_SIZE {
1962 VMPG_SIZE_4KB                            = 0x00000000,
1963 VMPG_SIZE_64KB                           = 0x00000001,
1964 } VMPG_SIZE;
1965 
1966 /*
1967  * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1968  */
1969 
1970 typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1971 HUBP_MEASURE_WIN_MODE_DCFCLK_0           = 0x00000000,
1972 HUBP_MEASURE_WIN_MODE_DCFCLK_1           = 0x00000001,
1973 HUBP_MEASURE_WIN_MODE_DCFCLK_2           = 0x00000002,
1974 HUBP_MEASURE_WIN_MODE_DCFCLK_3           = 0x00000003,
1975 } HUBP_MEASURE_WIN_MODE_DCFCLK;
1976 
1977 /*******************************************************
1978  * HUBPREQ Enums
1979  *******************************************************/
1980 
1981 /*
1982  * SURFACE_TMZ enum
1983  */
1984 
1985 typedef enum SURFACE_TMZ {
1986 SURFACE_IS_NOT_TMZ                       = 0x00000000,
1987 SURFACE_IS_TMZ                           = 0x00000001,
1988 } SURFACE_TMZ;
1989 
1990 /*
1991  * SURFACE_DCC enum
1992  */
1993 
1994 typedef enum SURFACE_DCC {
1995 SURFACE_IS_NOT_DCC                       = 0x00000000,
1996 SURFACE_IS_DCC                           = 0x00000001,
1997 } SURFACE_DCC;
1998 
1999 /*
2000  * SURFACE_DCC_IND_64B enum
2001  */
2002 
2003 typedef enum SURFACE_DCC_IND_64B {
2004 SURFACE_DCC_IS_NOT_IND_64B               = 0x00000000,
2005 SURFACE_DCC_IS_IND_64B                   = 0x00000001,
2006 } SURFACE_DCC_IND_64B;
2007 
2008 /*
2009  * SURFACE_FLIP_TYPE enum
2010  */
2011 
2012 typedef enum SURFACE_FLIP_TYPE {
2013 SURFACE_V_FLIP                           = 0x00000000,
2014 SURFACE_I_FLIP                           = 0x00000001,
2015 } SURFACE_FLIP_TYPE;
2016 
2017 /*
2018  * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2019  */
2020 
2021 typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2022 FLIP_ANY_FRAME                           = 0x00000000,
2023 FLIP_LEFT_EYE                            = 0x00000001,
2024 FLIP_RIGHT_EYE                           = 0x00000002,
2025 SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED  = 0x00000003,
2026 } SURFACE_FLIP_MODE_FOR_STEREOSYNC;
2027 
2028 /*
2029  * SURFACE_UPDATE_LOCK enum
2030  */
2031 
2032 typedef enum SURFACE_UPDATE_LOCK {
2033 SURFACE_UPDATE_IS_UNLOCKED               = 0x00000000,
2034 SURFACE_UPDATE_IS_LOCKED                 = 0x00000001,
2035 } SURFACE_UPDATE_LOCK;
2036 
2037 /*
2038  * SURFACE_FLIP_IN_STEREOSYNC enum
2039  */
2040 
2041 typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2042 SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE      = 0x00000000,
2043 SURFACE_FLIP_IN_STEREOSYNC_MODE          = 0x00000001,
2044 } SURFACE_FLIP_IN_STEREOSYNC;
2045 
2046 /*
2047  * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2048  */
2049 
2050 typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2051 SURFACE_FLIP_STEREO_SELECT_ENABLED       = 0x00000000,
2052 SURFACE_FLIP_STEREO_SELECT_DISABLED      = 0x00000001,
2053 } SURFACE_FLIP_STEREO_SELECT_DISABLE;
2054 
2055 /*
2056  * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2057  */
2058 
2059 typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2060 SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT  = 0x00000000,
2061 SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT  = 0x00000001,
2062 } SURFACE_FLIP_STEREO_SELECT_POLARITY;
2063 
2064 /*
2065  * SURFACE_INUSE_RAED_NO_LATCH enum
2066  */
2067 
2068 typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2069 SURFACE_INUSE_IS_LATCHED                 = 0x00000000,
2070 SURFACE_INUSE_IS_NOT_LATCHED             = 0x00000001,
2071 } SURFACE_INUSE_RAED_NO_LATCH;
2072 
2073 /*
2074  * INT_MASK enum
2075  */
2076 
2077 typedef enum INT_MASK {
2078 INT_DISABLED                             = 0x00000000,
2079 INT_ENABLED                              = 0x00000001,
2080 } INT_MASK;
2081 
2082 /*
2083  * SURFACE_FLIP_INT_TYPE enum
2084  */
2085 
2086 typedef enum SURFACE_FLIP_INT_TYPE {
2087 SURFACE_FLIP_INT_LEVEL                   = 0x00000000,
2088 SURFACE_FLIP_INT_PULSE                   = 0x00000001,
2089 } SURFACE_FLIP_INT_TYPE;
2090 
2091 /*
2092  * SURFACE_FLIP_AWAY_INT_TYPE enum
2093  */
2094 
2095 typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2096 SURFACE_FLIP_AWAY_INT_LEVEL              = 0x00000000,
2097 SURFACE_FLIP_AWAY_INT_PULSE              = 0x00000001,
2098 } SURFACE_FLIP_AWAY_INT_TYPE;
2099 
2100 /*
2101  * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2102  */
2103 
2104 typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2105 SURFACE_FLIP_VUPDATE_SKIP_NUM_0          = 0x00000000,
2106 SURFACE_FLIP_VUPDATE_SKIP_NUM_1          = 0x00000001,
2107 SURFACE_FLIP_VUPDATE_SKIP_NUM_2          = 0x00000002,
2108 SURFACE_FLIP_VUPDATE_SKIP_NUM_3          = 0x00000003,
2109 SURFACE_FLIP_VUPDATE_SKIP_NUM_4          = 0x00000004,
2110 SURFACE_FLIP_VUPDATE_SKIP_NUM_5          = 0x00000005,
2111 SURFACE_FLIP_VUPDATE_SKIP_NUM_6          = 0x00000006,
2112 SURFACE_FLIP_VUPDATE_SKIP_NUM_7          = 0x00000007,
2113 SURFACE_FLIP_VUPDATE_SKIP_NUM_8          = 0x00000008,
2114 SURFACE_FLIP_VUPDATE_SKIP_NUM_9          = 0x00000009,
2115 SURFACE_FLIP_VUPDATE_SKIP_NUM_10         = 0x0000000a,
2116 SURFACE_FLIP_VUPDATE_SKIP_NUM_11         = 0x0000000b,
2117 SURFACE_FLIP_VUPDATE_SKIP_NUM_12         = 0x0000000c,
2118 SURFACE_FLIP_VUPDATE_SKIP_NUM_13         = 0x0000000d,
2119 SURFACE_FLIP_VUPDATE_SKIP_NUM_14         = 0x0000000e,
2120 SURFACE_FLIP_VUPDATE_SKIP_NUM_15         = 0x0000000f,
2121 } SURFACE_FLIP_VUPDATE_SKIP_NUM;
2122 
2123 /*
2124  * DFQ_SIZE enum
2125  */
2126 
2127 typedef enum DFQ_SIZE {
2128 DFQ_SIZE_0                               = 0x00000000,
2129 DFQ_SIZE_1                               = 0x00000001,
2130 DFQ_SIZE_2                               = 0x00000002,
2131 DFQ_SIZE_3                               = 0x00000003,
2132 DFQ_SIZE_4                               = 0x00000004,
2133 DFQ_SIZE_5                               = 0x00000005,
2134 DFQ_SIZE_6                               = 0x00000006,
2135 DFQ_SIZE_7                               = 0x00000007,
2136 } DFQ_SIZE;
2137 
2138 /*
2139  * DFQ_MIN_FREE_ENTRIES enum
2140  */
2141 
2142 typedef enum DFQ_MIN_FREE_ENTRIES {
2143 DFQ_MIN_FREE_ENTRIES_0                   = 0x00000000,
2144 DFQ_MIN_FREE_ENTRIES_1                   = 0x00000001,
2145 DFQ_MIN_FREE_ENTRIES_2                   = 0x00000002,
2146 DFQ_MIN_FREE_ENTRIES_3                   = 0x00000003,
2147 DFQ_MIN_FREE_ENTRIES_4                   = 0x00000004,
2148 DFQ_MIN_FREE_ENTRIES_5                   = 0x00000005,
2149 DFQ_MIN_FREE_ENTRIES_6                   = 0x00000006,
2150 DFQ_MIN_FREE_ENTRIES_7                   = 0x00000007,
2151 } DFQ_MIN_FREE_ENTRIES;
2152 
2153 /*
2154  * DFQ_NUM_ENTRIES enum
2155  */
2156 
2157 typedef enum DFQ_NUM_ENTRIES {
2158 DFQ_NUM_ENTRIES_0                        = 0x00000000,
2159 DFQ_NUM_ENTRIES_1                        = 0x00000001,
2160 DFQ_NUM_ENTRIES_2                        = 0x00000002,
2161 DFQ_NUM_ENTRIES_3                        = 0x00000003,
2162 DFQ_NUM_ENTRIES_4                        = 0x00000004,
2163 DFQ_NUM_ENTRIES_5                        = 0x00000005,
2164 DFQ_NUM_ENTRIES_6                        = 0x00000006,
2165 DFQ_NUM_ENTRIES_7                        = 0x00000007,
2166 DFQ_NUM_ENTRIES_8                        = 0x00000008,
2167 } DFQ_NUM_ENTRIES;
2168 
2169 /*
2170  * FLIP_RATE enum
2171  */
2172 
2173 typedef enum FLIP_RATE {
2174 FLIP_RATE_0                              = 0x00000000,
2175 FLIP_RATE_1                              = 0x00000001,
2176 FLIP_RATE_2                              = 0x00000002,
2177 FLIP_RATE_3                              = 0x00000003,
2178 FLIP_RATE_4                              = 0x00000004,
2179 FLIP_RATE_5                              = 0x00000005,
2180 FLIP_RATE_6                              = 0x00000006,
2181 FLIP_RATE_7                              = 0x00000007,
2182 } FLIP_RATE;
2183 
2184 /*******************************************************
2185  * HUBPRET Enums
2186  *******************************************************/
2187 
2188 /*
2189  * DETILE_BUFFER_PACKER_ENABLE enum
2190  */
2191 
2192 typedef enum DETILE_BUFFER_PACKER_ENABLE {
2193 DETILE_BUFFER_PACKER_IS_DISABLE          = 0x00000000,
2194 DETILE_BUFFER_PACKER_IS_ENABLE           = 0x00000001,
2195 } DETILE_BUFFER_PACKER_ENABLE;
2196 
2197 /*
2198  * CROSSBAR_FOR_ALPHA enum
2199  */
2200 
2201 typedef enum CROSSBAR_FOR_ALPHA {
2202 ALPHA_DATA_ON_ALPHA_PORT                 = 0x00000000,
2203 ALPHA_DATA_ON_Y_G_PORT                   = 0x00000001,
2204 ALPHA_DATA_ON_CB_B_PORT                  = 0x00000002,
2205 ALPHA_DATA_ON_CR_R_PORT                  = 0x00000003,
2206 } CROSSBAR_FOR_ALPHA;
2207 
2208 /*
2209  * CROSSBAR_FOR_Y_G enum
2210  */
2211 
2212 typedef enum CROSSBAR_FOR_Y_G {
2213 Y_G_DATA_ON_ALPHA_PORT                   = 0x00000000,
2214 Y_G_DATA_ON_Y_G_PORT                     = 0x00000001,
2215 Y_G_DATA_ON_CB_B_PORT                    = 0x00000002,
2216 Y_G_DATA_ON_CR_R_PORT                    = 0x00000003,
2217 } CROSSBAR_FOR_Y_G;
2218 
2219 /*
2220  * CROSSBAR_FOR_CB_B enum
2221  */
2222 
2223 typedef enum CROSSBAR_FOR_CB_B {
2224 CB_B_DATA_ON_ALPHA_PORT                  = 0x00000000,
2225 CB_B_DATA_ON_Y_G_PORT                    = 0x00000001,
2226 CB_B_DATA_ON_CB_B_PORT                   = 0x00000002,
2227 CB_B_DATA_ON_CR_R_PORT                   = 0x00000003,
2228 } CROSSBAR_FOR_CB_B;
2229 
2230 /*
2231  * CROSSBAR_FOR_CR_R enum
2232  */
2233 
2234 typedef enum CROSSBAR_FOR_CR_R {
2235 CR_R_DATA_ON_ALPHA_PORT                  = 0x00000000,
2236 CR_R_DATA_ON_Y_G_PORT                    = 0x00000001,
2237 CR_R_DATA_ON_CB_B_PORT                   = 0x00000002,
2238 CR_R_DATA_ON_CR_R_PORT                   = 0x00000003,
2239 } CROSSBAR_FOR_CR_R;
2240 
2241 /*
2242  * DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2243  */
2244 
2245 typedef enum DET_MEM_PWR_LIGHT_SLEEP_MODE {
2246 DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF       = 0x00000000,
2247 DET_MEM_POWER_LIGHT_SLEEP_MODE_1         = 0x00000001,
2248 DET_MEM_POWER_LIGHT_SLEEP_MODE_2         = 0x00000002,
2249 } DET_MEM_PWR_LIGHT_SLEEP_MODE;
2250 
2251 /*
2252  * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2253  */
2254 
2255 typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2256 PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF    = 0x00000000,
2257 PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1      = 0x00000001,
2258 } PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE;
2259 
2260 /*******************************************************
2261  * CURSOR Enums
2262  *******************************************************/
2263 
2264 /*
2265  * CURSOR_ENABLE enum
2266  */
2267 
2268 typedef enum CURSOR_ENABLE {
2269 CURSOR_IS_DISABLE                        = 0x00000000,
2270 CURSOR_IS_ENABLE                         = 0x00000001,
2271 } CURSOR_ENABLE;
2272 
2273 /*
2274  * CURSOR_2X_MAGNIFY enum
2275  */
2276 
2277 typedef enum CURSOR_2X_MAGNIFY {
2278 CURSOR_2X_MAGNIFY_IS_DISABLE             = 0x00000000,
2279 CURSOR_2X_MAGNIFY_IS_ENABLE              = 0x00000001,
2280 } CURSOR_2X_MAGNIFY;
2281 
2282 /*
2283  * CURSOR_MODE enum
2284  */
2285 
2286 typedef enum CURSOR_MODE {
2287 CURSOR_MONO_2BIT                         = 0x00000000,
2288 CURSOR_COLOR_24BIT_1BIT_AND              = 0x00000001,
2289 CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT    = 0x00000002,
2290 CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT  = 0x00000003,
2291 CURSOR_COLOR_64BIT_FP_PREMULT            = 0x00000004,
2292 CURSOR_COLOR_64BIT_FP_UNPREMULT          = 0x00000005,
2293 } CURSOR_MODE;
2294 
2295 /*
2296  * CURSOR_SURFACE_TMZ enum
2297  */
2298 
2299 typedef enum CURSOR_SURFACE_TMZ {
2300 CURSOR_SURFACE_IS_NOT_TMZ                = 0x00000000,
2301 CURSOR_SURFACE_IS_TMZ                    = 0x00000001,
2302 } CURSOR_SURFACE_TMZ;
2303 
2304 /*
2305  * CURSOR_SNOOP enum
2306  */
2307 
2308 typedef enum CURSOR_SNOOP {
2309 CURSOR_IS_NOT_SNOOP                      = 0x00000000,
2310 CURSOR_IS_SNOOP                          = 0x00000001,
2311 } CURSOR_SNOOP;
2312 
2313 /*
2314  * CURSOR_SYSTEM enum
2315  */
2316 
2317 typedef enum CURSOR_SYSTEM {
2318 CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS        = 0x00000000,
2319 CURSOR_IN_GUEST_PHYSICAL_ADDRESS         = 0x00000001,
2320 } CURSOR_SYSTEM;
2321 
2322 /*
2323  * CURSOR_PITCH enum
2324  */
2325 
2326 typedef enum CURSOR_PITCH {
2327 CURSOR_PITCH_64_PIXELS                   = 0x00000000,
2328 CURSOR_PITCH_128_PIXELS                  = 0x00000001,
2329 CURSOR_PITCH_256_PIXELS                  = 0x00000002,
2330 } CURSOR_PITCH;
2331 
2332 /*
2333  * CURSOR_LINES_PER_CHUNK enum
2334  */
2335 
2336 typedef enum CURSOR_LINES_PER_CHUNK {
2337 CURSOR_LINE_PER_CHUNK_1                  = 0x00000000,
2338 CURSOR_LINE_PER_CHUNK_2                  = 0x00000001,
2339 CURSOR_LINE_PER_CHUNK_4                  = 0x00000002,
2340 CURSOR_LINE_PER_CHUNK_8                  = 0x00000003,
2341 CURSOR_LINE_PER_CHUNK_16                 = 0x00000004,
2342 } CURSOR_LINES_PER_CHUNK;
2343 
2344 /*
2345  * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2346  */
2347 
2348 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2349 CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED  = 0x00000000,
2350 CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED  = 0x00000001,
2351 } CURSOR_PERFMON_LATENCY_MEASURE_EN;
2352 
2353 /*
2354  * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2355  */
2356 
2357 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2358 CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY  = 0x00000000,
2359 CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY  = 0x00000001,
2360 } CURSOR_PERFMON_LATENCY_MEASURE_SEL;
2361 
2362 /*
2363  * CURSOR_STEREO_EN enum
2364  */
2365 
2366 typedef enum CURSOR_STEREO_EN {
2367 CURSOR_STEREO_IS_DISABLED                = 0x00000000,
2368 CURSOR_STEREO_IS_ENABLED                 = 0x00000001,
2369 } CURSOR_STEREO_EN;
2370 
2371 /*
2372  * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2373  */
2374 
2375 typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2376 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0  = 0x00000000,
2377 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1  = 0x00000001,
2378 } CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS;
2379 
2380 /*
2381  * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2382  */
2383 
2384 typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2385 CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF      = 0x00000000,
2386 CROB_MEM_POWER_LIGHT_SLEEP_MODE_1        = 0x00000001,
2387 CROB_MEM_POWER_LIGHT_SLEEP_MODE_2        = 0x00000002,
2388 } CROB_MEM_PWR_LIGHT_SLEEP_MODE;
2389 
2390 /*
2391  * DMDATA_UPDATED enum
2392  */
2393 
2394 typedef enum DMDATA_UPDATED {
2395 DMDATA_NOT_UPDATED                       = 0x00000000,
2396 DMDATA_WAS_UPDATED                       = 0x00000001,
2397 } DMDATA_UPDATED;
2398 
2399 /*
2400  * DMDATA_REPEAT enum
2401  */
2402 
2403 typedef enum DMDATA_REPEAT {
2404 DMDATA_USE_FOR_CURRENT_FRAME_ONLY        = 0x00000000,
2405 DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES  = 0x00000001,
2406 } DMDATA_REPEAT;
2407 
2408 /*
2409  * DMDATA_MODE enum
2410  */
2411 
2412 typedef enum DMDATA_MODE {
2413 DMDATA_SOFTWARE_UPDATE_MODE              = 0x00000000,
2414 DMDATA_HARDWARE_UPDATE_MODE              = 0x00000001,
2415 } DMDATA_MODE;
2416 
2417 /*
2418  * DMDATA_QOS_MODE enum
2419  */
2420 
2421 typedef enum DMDATA_QOS_MODE {
2422 DMDATA_QOS_LEVEL_FROM_TTU                = 0x00000000,
2423 DMDATA_QOS_LEVEL_FROM_SOFTWARE           = 0x00000001,
2424 } DMDATA_QOS_MODE;
2425 
2426 /*
2427  * DMDATA_DONE enum
2428  */
2429 
2430 typedef enum DMDATA_DONE {
2431 DMDATA_NOT_SENT_TO_DIG                   = 0x00000000,
2432 DMDATA_SENT_TO_DIG                       = 0x00000001,
2433 } DMDATA_DONE;
2434 
2435 /*
2436  * DMDATA_UNDERFLOW enum
2437  */
2438 
2439 typedef enum DMDATA_UNDERFLOW {
2440 DMDATA_NOT_UNDERFLOW                     = 0x00000000,
2441 DMDATA_UNDERFLOWED                       = 0x00000001,
2442 } DMDATA_UNDERFLOW;
2443 
2444 /*
2445  * DMDATA_UNDERFLOW_CLEAR enum
2446  */
2447 
2448 typedef enum DMDATA_UNDERFLOW_CLEAR {
2449 DMDATA_DONT_CLEAR                        = 0x00000000,
2450 DMDATA_CLEAR_UNDERFLOW_STATUS            = 0x00000001,
2451 } DMDATA_UNDERFLOW_CLEAR;
2452 
2453 /*******************************************************
2454  * HUBPXFC Enums
2455  *******************************************************/
2456 
2457 /*
2458  * HUBP_XFC_PIXEL_FORMAT_ENUM enum
2459  */
2460 
2461 typedef enum HUBP_XFC_PIXEL_FORMAT_ENUM {
2462 HUBP_XFC_PIXEL_IS_32BPP                  = 0x00000000,
2463 HUBP_XFC_PIXEL_IS_64BPP                  = 0x00000001,
2464 } HUBP_XFC_PIXEL_FORMAT_ENUM;
2465 
2466 /*
2467  * HUBP_XFC_FRAME_MODE_ENUM enum
2468  */
2469 
2470 typedef enum HUBP_XFC_FRAME_MODE_ENUM {
2471 HUBP_XFC_PARTIAL_FRAME_MODE              = 0x00000000,
2472 HUBP_XFC_FULL_FRAME_MODE                 = 0x00000001,
2473 } HUBP_XFC_FRAME_MODE_ENUM;
2474 
2475 /*
2476  * HUBP_XFC_CHUNK_SIZE_ENUM enum
2477  */
2478 
2479 typedef enum HUBP_XFC_CHUNK_SIZE_ENUM {
2480 HUBP_XFC_CHUNK_SIZE_256B                 = 0x00000000,
2481 HUBP_XFC_CHUNK_SIZE_512B                 = 0x00000001,
2482 HUBP_XFC_CHUNK_SIZE_1KB                  = 0x00000002,
2483 HUBP_XFC_CHUNK_SIZE_2KB                  = 0x00000003,
2484 HUBP_XFC_CHUNK_SIZE_4KB                  = 0x00000004,
2485 HUBP_XFC_CHUNK_SIZE_8KB                  = 0x00000005,
2486 HUBP_XFC_CHUNK_SIZE_16KB                 = 0x00000006,
2487 HUBP_XFC_CHUNK_SIZE_32KB                 = 0x00000007,
2488 } HUBP_XFC_CHUNK_SIZE_ENUM;
2489 
2490 /*******************************************************
2491  * XFC Enums
2492  *******************************************************/
2493 
2494 /*
2495  * MMHUBBUB_XFC_XFCMON_MODE_ENUM enum
2496  */
2497 
2498 typedef enum MMHUBBUB_XFC_XFCMON_MODE_ENUM {
2499 MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT        = 0x00000000,
2500 MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS      = 0x00000001,
2501 MMHUBBUB_XFC_XFCMON_MODE_PERIODS         = 0x00000002,
2502 } MMHUBBUB_XFC_XFCMON_MODE_ENUM;
2503 
2504 /*
2505  * MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM enum
2506  */
2507 
2508 typedef enum MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM {
2509 MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB  = 0x00000000,
2510 MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB  = 0x00000001,
2511 } MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM;
2512 
2513 /*******************************************************
2514  * XFCP Enums
2515  *******************************************************/
2516 
2517 /*
2518  * MMHUBBUB_XFC_PIXEL_FORMAT_ENUM enum
2519  */
2520 
2521 typedef enum MMHUBBUB_XFC_PIXEL_FORMAT_ENUM {
2522 MMHUBBUB_XFC_PIXEL_IS_32BPP              = 0x00000000,
2523 MMHUBBUB_XFC_PIXEL_IS_64BPP              = 0x00000001,
2524 } MMHUBBUB_XFC_PIXEL_FORMAT_ENUM;
2525 
2526 /*
2527  * MMHUBBUB_XFC_FRAME_MODE_ENUM enum
2528  */
2529 
2530 typedef enum MMHUBBUB_XFC_FRAME_MODE_ENUM {
2531 MMHUBBUB_XFC_PARTIAL_FRAME_MODE          = 0x00000000,
2532 MMHUBBUB_XFC_FULL_FRAME_MODE             = 0x00000001,
2533 } MMHUBBUB_XFC_FRAME_MODE_ENUM;
2534 
2535 /*******************************************************
2536  * MPC_CFG Enums
2537  *******************************************************/
2538 
2539 /*
2540  * MPC_CFG_MPC_TEST_CLK_SEL enum
2541  */
2542 
2543 typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2544 MPC_CFG_MPC_TEST_CLK_SEL_0               = 0x00000000,
2545 MPC_CFG_MPC_TEST_CLK_SEL_1               = 0x00000001,
2546 MPC_CFG_MPC_TEST_CLK_SEL_2               = 0x00000002,
2547 MPC_CFG_MPC_TEST_CLK_SEL_3               = 0x00000003,
2548 } MPC_CFG_MPC_TEST_CLK_SEL;
2549 
2550 /*
2551  * MPC_CRC_CALC_MODE enum
2552  */
2553 
2554 typedef enum MPC_CRC_CALC_MODE {
2555 MPC_CRC_ONE_SHOT_MODE                    = 0x00000000,
2556 MPC_CRC_CONTINUOUS_MODE                  = 0x00000001,
2557 } MPC_CRC_CALC_MODE;
2558 
2559 /*
2560  * MPC_CRC_CALC_STEREO_MODE enum
2561  */
2562 
2563 typedef enum MPC_CRC_CALC_STEREO_MODE {
2564 MPC_CRC_STEREO_MODE_LEFT                 = 0x00000000,
2565 MPC_CRC_STEREO_MODE_RIGHT                = 0x00000001,
2566 MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT     = 0x00000002,
2567 MPC_CRC_STEREO_MODE_BOTH_RESET_EACH      = 0x00000003,
2568 } MPC_CRC_CALC_STEREO_MODE;
2569 
2570 /*
2571  * MPC_CRC_CALC_INTERLACE_MODE enum
2572  */
2573 
2574 typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2575 MPC_CRC_INTERLACE_MODE_TOP               = 0x00000000,
2576 MPC_CRC_INTERLACE_MODE_BOTTOM            = 0x00000001,
2577 MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM  = 0x00000002,
2578 MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH   = 0x00000003,
2579 } MPC_CRC_CALC_INTERLACE_MODE;
2580 
2581 /*
2582  * MPC_CRC_SOURCE_SELECT enum
2583  */
2584 
2585 typedef enum MPC_CRC_SOURCE_SELECT {
2586 MPC_CRC_SOURCE_SEL_DPP                   = 0x00000000,
2587 MPC_CRC_SOURCE_SEL_OPP                   = 0x00000001,
2588 MPC_CRC_SOURCE_SEL_DWB                   = 0x00000002,
2589 MPC_CRC_SOURCE_SEL_OTHER                 = 0x00000003,
2590 } MPC_CRC_SOURCE_SELECT;
2591 
2592 /*
2593  * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2594  */
2595 
2596 typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2597 MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE  = 0x00000000,
2598 MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE  = 0x00000001,
2599 } MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET;
2600 
2601 /*
2602  * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2603  */
2604 
2605 typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2606 MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE   = 0x00000000,
2607 MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE    = 0x00000001,
2608 } MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET;
2609 
2610 /*
2611  * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2612  */
2613 
2614 typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2615 MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
2616 MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
2617 } MPC_CFG_CFG_VUPDATE_LOCK_SET;
2618 
2619 /*
2620  * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2621  */
2622 
2623 typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2624 MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
2625 MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
2626 } MPC_CFG_ADR_VUPDATE_LOCK_SET;
2627 
2628 /*
2629  * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2630  */
2631 
2632 typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2633 MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE       = 0x00000000,
2634 MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE        = 0x00000001,
2635 } MPC_CFG_CUR_VUPDATE_LOCK_SET;
2636 
2637 /*
2638  * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2639  */
2640 
2641 typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2642 MPC_OUT_RATE_CONTROL_SET_ENABLE          = 0x00000000,
2643 MPC_OUT_RATE_CONTROL_SET_DISABLE         = 0x00000001,
2644 } MPC_OUT_RATE_CONTROL_DISABLE_SET;
2645 
2646 /*
2647  * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2648  */
2649 
2650 typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2651 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS  = 0x00000000,
2652 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS  = 0x00000001,
2653 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS  = 0x00000002,
2654 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS  = 0x00000003,
2655 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS  = 0x00000004,
2656 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS  = 0x00000005,
2657 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS  = 0x00000006,
2658 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH  = 0x00000007,
2659 } MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE;
2660 
2661 /*******************************************************
2662  * MPC_OCSC Enums
2663  *******************************************************/
2664 
2665 /*
2666  * MPC_OCSC_COEF_FORMAT enum
2667  */
2668 
2669 typedef enum MPC_OCSC_COEF_FORMAT {
2670 MPC_OCSC_COEF_FORMAT_S2_13               = 0x00000000,
2671 MPC_OCSC_COEF_FORMAT_S3_12               = 0x00000001,
2672 } MPC_OCSC_COEF_FORMAT;
2673 
2674 /*
2675  * MPC_OUT_CSC_MODE enum
2676  */
2677 
2678 typedef enum MPC_OUT_CSC_MODE {
2679 MPC_OUT_CSC_MODE_0                       = 0x00000000,
2680 MPC_OUT_CSC_MODE_1                       = 0x00000001,
2681 MPC_OUT_CSC_MODE_2                       = 0x00000002,
2682 MPC_OUT_CSC_MODE_RSV                     = 0x00000003,
2683 } MPC_OUT_CSC_MODE;
2684 
2685 /*******************************************************
2686  * MPCC Enums
2687  *******************************************************/
2688 
2689 /*
2690  * MPCC_CONTROL_MPCC_MODE enum
2691  */
2692 
2693 typedef enum MPCC_CONTROL_MPCC_MODE {
2694 MPCC_CONTROL_MPCC_MODE_BYPASS            = 0x00000000,
2695 MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH  = 0x00000001,
2696 MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY    = 0x00000002,
2697 MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING  = 0x00000003,
2698 } MPCC_CONTROL_MPCC_MODE;
2699 
2700 /*
2701  * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2702  */
2703 
2704 typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2705 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA  = 0x00000000,
2706 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN  = 0x00000001,
2707 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA  = 0x00000002,
2708 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED  = 0x00000003,
2709 } MPCC_CONTROL_MPCC_ALPHA_BLND_MODE;
2710 
2711 /*
2712  * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2713  */
2714 
2715 typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2716 MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE  = 0x00000000,
2717 MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE  = 0x00000001,
2718 } MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE;
2719 
2720 /*
2721  * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2722  */
2723 
2724 typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2725 MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE  = 0x00000000,
2726 MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE  = 0x00000001,
2727 } MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY;
2728 
2729 /*
2730  * MPCC_SM_CONTROL_MPCC_SM_EN enum
2731  */
2732 
2733 typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
2734 MPCC_SM_CONTROL_MPCC_SM_EN_FALSE         = 0x00000000,
2735 MPCC_SM_CONTROL_MPCC_SM_EN_TRUE          = 0x00000001,
2736 } MPCC_SM_CONTROL_MPCC_SM_EN;
2737 
2738 /*
2739  * MPCC_SM_CONTROL_MPCC_SM_MODE enum
2740  */
2741 
2742 typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
2743 MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE  = 0x00000000,
2744 MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING  = 0x00000002,
2745 MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING  = 0x00000004,
2746 MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING  = 0x00000006,
2747 } MPCC_SM_CONTROL_MPCC_SM_MODE;
2748 
2749 /*
2750  * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
2751  */
2752 
2753 typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
2754 MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE  = 0x00000000,
2755 MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE   = 0x00000001,
2756 } MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT;
2757 
2758 /*
2759  * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
2760  */
2761 
2762 typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
2763 MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE  = 0x00000000,
2764 MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE   = 0x00000001,
2765 } MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT;
2766 
2767 /*
2768  * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
2769  */
2770 
2771 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
2772 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE  = 0x00000000,
2773 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED  = 0x00000001,
2774 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW  = 0x00000002,
2775 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH  = 0x00000003,
2776 } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL;
2777 
2778 /*
2779  * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
2780  */
2781 
2782 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
2783 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE  = 0x00000000,
2784 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED  = 0x00000001,
2785 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW  = 0x00000002,
2786 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH  = 0x00000003,
2787 } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL;
2788 
2789 /*
2790  * MPCC_STALL_STATUS_MPCC_STALL_INT_ACK enum
2791  */
2792 
2793 typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_ACK {
2794 MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0x00000000,
2795 MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 0x00000001,
2796 } MPCC_STALL_STATUS_MPCC_STALL_INT_ACK;
2797 
2798 /*
2799  * MPCC_STALL_STATUS_MPCC_STALL_INT_MASK enum
2800  */
2801 
2802 typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_MASK {
2803 MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE  = 0x00000000,
2804 MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE  = 0x00000001,
2805 } MPCC_STALL_STATUS_MPCC_STALL_INT_MASK;
2806 
2807 /*
2808  * MPCC_BG_COLOR_BPC enum
2809  */
2810 
2811 typedef enum MPCC_BG_COLOR_BPC {
2812 MPCC_BG_COLOR_BPC_8bit                   = 0x00000000,
2813 MPCC_BG_COLOR_BPC_9bit                   = 0x00000001,
2814 MPCC_BG_COLOR_BPC_10bit                  = 0x00000002,
2815 MPCC_BG_COLOR_BPC_11bit                  = 0x00000003,
2816 MPCC_BG_COLOR_BPC_12bit                  = 0x00000004,
2817 } MPCC_BG_COLOR_BPC;
2818 
2819 /*
2820  * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2821  */
2822 
2823 typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2824 MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0        = 0x00000000,
2825 MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1        = 0x00000001,
2826 } MPCC_CONTROL_MPCC_BOT_GAIN_MODE;
2827 
2828 /*******************************************************
2829  * MPCC_OGAM Enums
2830  *******************************************************/
2831 
2832 /*
2833  * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
2834  */
2835 
2836 typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
2837 MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA  = 0x00000000,
2838 MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB  = 0x00000001,
2839 } MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL;
2840 
2841 /*
2842  * MPCC_OGAM_MODE_MPCC_OGAM_MODE enum
2843  */
2844 
2845 typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE {
2846 MPCC_OGAM_MODE_0                         = 0x00000000,
2847 MPCC_OGAM_MODE_1                         = 0x00000001,
2848 MPCC_OGAM_MODE_2                         = 0x00000002,
2849 MPCC_OGAM_MODE_RSV                       = 0x00000003,
2850 } MPCC_OGAM_MODE_MPCC_OGAM_MODE;
2851 
2852 /*******************************************************
2853  * DPG Enums
2854  *******************************************************/
2855 
2856 /*
2857  * ENUM_DPG_EN enum
2858  */
2859 
2860 typedef enum ENUM_DPG_EN {
2861 ENUM_DPG_DISABLE                         = 0x00000000,
2862 ENUM_DPG_ENABLE                          = 0x00000001,
2863 } ENUM_DPG_EN;
2864 
2865 /*
2866  * ENUM_DPG_MODE enum
2867  */
2868 
2869 typedef enum ENUM_DPG_MODE {
2870 ENUM_DPG_MODE_RGB_COLOUR_BLOCK           = 0x00000000,
2871 ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK     = 0x00000001,
2872 ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK     = 0x00000002,
2873 ENUM_DPG_MODE_VERTICAL_BAR               = 0x00000003,
2874 ENUM_DPG_MODE_HORIZONTAL_BAR             = 0x00000004,
2875 ENUM_DPG_MODE_RGB_SINGLE_RAMP            = 0x00000005,
2876 ENUM_DPG_MODE_RGB_DUAL_RAMP              = 0x00000006,
2877 ENUM_DPG_MODE_RGB_XR_BIAS                = 0x00000007,
2878 } ENUM_DPG_MODE;
2879 
2880 /*
2881  * ENUM_DPG_DYNAMIC_RANGE enum
2882  */
2883 
2884 typedef enum ENUM_DPG_DYNAMIC_RANGE {
2885 ENUM_DPG_DYNAMIC_RANGE_VESA              = 0x00000000,
2886 ENUM_DPG_DYNAMIC_RANGE_CEA               = 0x00000001,
2887 } ENUM_DPG_DYNAMIC_RANGE;
2888 
2889 /*
2890  * ENUM_DPG_BIT_DEPTH enum
2891  */
2892 
2893 typedef enum ENUM_DPG_BIT_DEPTH {
2894 ENUM_DPG_BIT_DEPTH_6BPC                  = 0x00000000,
2895 ENUM_DPG_BIT_DEPTH_8BPC                  = 0x00000001,
2896 ENUM_DPG_BIT_DEPTH_10BPC                 = 0x00000002,
2897 ENUM_DPG_BIT_DEPTH_12BPC                 = 0x00000003,
2898 } ENUM_DPG_BIT_DEPTH;
2899 
2900 /*
2901  * ENUM_DPG_FIELD_POLARITY enum
2902  */
2903 
2904 typedef enum ENUM_DPG_FIELD_POLARITY {
2905 ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD  = 0x00000000,
2906 ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN  = 0x00000001,
2907 } ENUM_DPG_FIELD_POLARITY;
2908 
2909 /*******************************************************
2910  * FMT Enums
2911  *******************************************************/
2912 
2913 /*
2914  * FMT_CONTROL_PIXEL_ENCODING enum
2915  */
2916 
2917 typedef enum FMT_CONTROL_PIXEL_ENCODING {
2918 FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444  = 0x00000000,
2919 FMT_CONTROL_PIXEL_ENCODING_YCBCR422      = 0x00000001,
2920 FMT_CONTROL_PIXEL_ENCODING_YCBCR420      = 0x00000002,
2921 FMT_CONTROL_PIXEL_ENCODING_RESERVED      = 0x00000003,
2922 } FMT_CONTROL_PIXEL_ENCODING;
2923 
2924 /*
2925  * FMT_CONTROL_SUBSAMPLING_MODE enum
2926  */
2927 
2928 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
2929 FMT_CONTROL_SUBSAMPLING_MODE_DROP        = 0x00000000,
2930 FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE     = 0x00000001,
2931 FMT_CONTROL_SUBSAMPLING_MOME_3_TAP       = 0x00000002,
2932 FMT_CONTROL_SUBSAMPLING_MOME_RESERVED    = 0x00000003,
2933 } FMT_CONTROL_SUBSAMPLING_MODE;
2934 
2935 /*
2936  * FMT_CONTROL_SUBSAMPLING_ORDER enum
2937  */
2938 
2939 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
2940 FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR  = 0x00000000,
2941 FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB  = 0x00000001,
2942 } FMT_CONTROL_SUBSAMPLING_ORDER;
2943 
2944 /*
2945  * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
2946  */
2947 
2948 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
2949 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE  = 0x00000000,
2950 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE  = 0x00000001,
2951 } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
2952 
2953 /*
2954  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
2955  */
2956 
2957 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
2958 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION  = 0x00000000,
2959 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING  = 0x00000001,
2960 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
2961 
2962 /*
2963  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
2964  */
2965 
2966 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
2967 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP  = 0x00000000,
2968 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP  = 0x00000001,
2969 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP  = 0x00000002,
2970 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
2971 
2972 /*
2973  * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
2974  */
2975 
2976 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
2977 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP  = 0x00000000,
2978 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP  = 0x00000001,
2979 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP  = 0x00000002,
2980 } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
2981 
2982 /*
2983  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
2984  */
2985 
2986 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
2987 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP  = 0x00000000,
2988 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP  = 0x00000001,
2989 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP  = 0x00000002,
2990 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
2991 
2992 /*
2993  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
2994  */
2995 
2996 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
2997 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2  = 0x00000000,
2998 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4  = 0x00000001,
2999 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3000 
3001 /*
3002  * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3003  */
3004 
3005 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3006 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei       = 0x00000000,
3007 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi       = 0x00000001,
3008 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi       = 0x00000002,
3009 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED  = 0x00000003,
3010 } FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3011 
3012 /*
3013  * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3014  */
3015 
3016 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3017 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A        = 0x00000000,
3018 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B        = 0x00000001,
3019 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C        = 0x00000002,
3020 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D        = 0x00000003,
3021 } FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3022 
3023 /*
3024  * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3025  */
3026 
3027 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3028 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E        = 0x00000000,
3029 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F        = 0x00000001,
3030 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G        = 0x00000002,
3031 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED  = 0x00000003,
3032 } FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3033 
3034 /*
3035  * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3036  */
3037 
3038 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3039 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR  = 0x00000000,
3040 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB  = 0x00000001,
3041 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3042 
3043 /*
3044  * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3045  */
3046 
3047 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3048 FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC         = 0x00000000,
3049 FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC         = 0x00000001,
3050 FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC        = 0x00000002,
3051 FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC        = 0x00000003,
3052 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1    = 0x00000004,
3053 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2    = 0x00000005,
3054 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3    = 0x00000006,
3055 FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE  = 0x00000007,
3056 } FMT_CLAMP_CNTL_COLOR_FORMAT;
3057 
3058 /*
3059  * FMT_SPATIAL_DITHER_MODE enum
3060  */
3061 
3062 typedef enum FMT_SPATIAL_DITHER_MODE {
3063 FMT_SPATIAL_DITHER_MODE_0                = 0x00000000,
3064 FMT_SPATIAL_DITHER_MODE_1                = 0x00000001,
3065 FMT_SPATIAL_DITHER_MODE_2                = 0x00000002,
3066 FMT_SPATIAL_DITHER_MODE_3                = 0x00000003,
3067 } FMT_SPATIAL_DITHER_MODE;
3068 
3069 /*
3070  * FMT_DYNAMIC_EXP_MODE enum
3071  */
3072 
3073 typedef enum FMT_DYNAMIC_EXP_MODE {
3074 FMT_DYNAMIC_EXP_MODE_10to12              = 0x00000000,
3075 FMT_DYNAMIC_EXP_MODE_8to12               = 0x00000001,
3076 } FMT_DYNAMIC_EXP_MODE;
3077 
3078 /*
3079  * FMTMEM_PWR_FORCE_CTRL enum
3080  */
3081 
3082 typedef enum FMTMEM_PWR_FORCE_CTRL {
3083 FMTMEM_NO_FORCE_REQUEST                  = 0x00000000,
3084 FMTMEM_FORCE_LIGHT_SLEEP_REQUEST         = 0x00000001,
3085 FMTMEM_FORCE_DEEP_SLEEP_REQUEST          = 0x00000002,
3086 FMTMEM_FORCE_SHUT_DOWN_REQUEST           = 0x00000003,
3087 } FMTMEM_PWR_FORCE_CTRL;
3088 
3089 /*
3090  * FMTMEM_PWR_DIS_CTRL enum
3091  */
3092 
3093 typedef enum FMTMEM_PWR_DIS_CTRL {
3094 FMTMEM_ENABLE_MEM_PWR_CTRL               = 0x00000000,
3095 FMTMEM_DISABLE_MEM_PWR_CTRL              = 0x00000001,
3096 } FMTMEM_PWR_DIS_CTRL;
3097 
3098 /*
3099  * FMT_POWER_STATE_ENUM enum
3100  */
3101 
3102 typedef enum FMT_POWER_STATE_ENUM {
3103 FMT_POWER_STATE_ENUM_ON                  = 0x00000000,
3104 FMT_POWER_STATE_ENUM_LS                  = 0x00000001,
3105 FMT_POWER_STATE_ENUM_DS                  = 0x00000002,
3106 FMT_POWER_STATE_ENUM_SD                  = 0x00000003,
3107 } FMT_POWER_STATE_ENUM;
3108 
3109 /*
3110  * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3111  */
3112 
3113 typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3114 FMT_STEREOSYNC_OVERRIDE_CONTROL_0        = 0x00000000,
3115 FMT_STEREOSYNC_OVERRIDE_CONTROL_1        = 0x00000001,
3116 } FMT_STEREOSYNC_OVERRIDE_CONTROL;
3117 
3118 /*
3119  * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3120  */
3121 
3122 typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3123 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP  = 0x00000000,
3124 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1  = 0x00000001,
3125 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2  = 0x00000002,
3126 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED  = 0x00000003,
3127 } FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL;
3128 
3129 /*
3130  * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3131  */
3132 
3133 typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3134 FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME  = 0x00000000,
3135 FMT_FRAME_RANDOM_ENABLE_RESET_ONCE       = 0x00000001,
3136 } FMT_FRAME_RANDOM_ENABLE_CONTROL;
3137 
3138 /*
3139  * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3140  */
3141 
3142 typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3143 FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE    = 0x00000000,
3144 FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE     = 0x00000001,
3145 } FMT_RGB_RANDOM_ENABLE_CONTROL;
3146 
3147 /*
3148  * ENUM_FMT_PTI_FIELD_POLARITY enum
3149  */
3150 
3151 typedef enum ENUM_FMT_PTI_FIELD_POLARITY {
3152 ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD  = 0x00000000,
3153 ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN  = 0x00000001,
3154 } ENUM_FMT_PTI_FIELD_POLARITY;
3155 
3156 /*******************************************************
3157  * OPP_PIPE Enums
3158  *******************************************************/
3159 
3160 /*
3161  * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3162  */
3163 
3164 typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3165 OPP_PIPE_CLOCK_DISABLE                   = 0x00000000,
3166 OPP_PIPE_CLOCK_ENABLE                    = 0x00000001,
3167 } OPP_PIPE_CLOCK_ENABLE_CONTROL;
3168 
3169 /*
3170  * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3171  */
3172 
3173 typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3174 OPP_PIPE_DIGTIAL_BYPASS_DISABLE          = 0x00000000,
3175 OPP_PIPE_DIGTIAL_BYPASS_ENABLE           = 0x00000001,
3176 } OPP_PIPE_DIGTIAL_BYPASS_CONTROL;
3177 
3178 /*******************************************************
3179  * OPP_PIPE_CRC Enums
3180  *******************************************************/
3181 
3182 /*
3183  * OPP_PIPE_CRC_EN enum
3184  */
3185 
3186 typedef enum OPP_PIPE_CRC_EN {
3187 OPP_PIPE_CRC_DISABLE                     = 0x00000000,
3188 OPP_PIPE_CRC_ENABLE                      = 0x00000001,
3189 } OPP_PIPE_CRC_EN;
3190 
3191 /*
3192  * OPP_PIPE_CRC_CONT_EN enum
3193  */
3194 
3195 typedef enum OPP_PIPE_CRC_CONT_EN {
3196 OPP_PIPE_CRC_MODE_ONE_SHOT               = 0x00000000,
3197 OPP_PIPE_CRC_MODE_CONTINUOUS             = 0x00000001,
3198 } OPP_PIPE_CRC_CONT_EN;
3199 
3200 /*
3201  * OPP_PIPE_CRC_STEREO_MODE enum
3202  */
3203 
3204 typedef enum OPP_PIPE_CRC_STEREO_MODE {
3205 OPP_PIPE_CRC_STEREO_MODE_LEFT            = 0x00000000,
3206 OPP_PIPE_CRC_STEREO_MODE_RIGHT           = 0x00000001,
3207 OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE  = 0x00000002,
3208 OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE  = 0x00000003,
3209 } OPP_PIPE_CRC_STEREO_MODE;
3210 
3211 /*
3212  * OPP_PIPE_CRC_STEREO_EN enum
3213  */
3214 
3215 typedef enum OPP_PIPE_CRC_STEREO_EN {
3216 OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO  = 0x00000000,
3217 OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO  = 0x00000001,
3218 } OPP_PIPE_CRC_STEREO_EN;
3219 
3220 /*
3221  * OPP_PIPE_CRC_INTERLACE_MODE enum
3222  */
3223 
3224 typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3225 OPP_PIPE_CRC_INTERLACE_MODE_TOP          = 0x00000000,
3226 OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM       = 0x00000001,
3227 OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD  = 0x00000002,
3228 OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD  = 0x00000003,
3229 } OPP_PIPE_CRC_INTERLACE_MODE;
3230 
3231 /*
3232  * OPP_PIPE_CRC_INTERLACE_EN enum
3233  */
3234 
3235 typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3236 OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE  = 0x00000000,
3237 OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED  = 0x00000001,
3238 } OPP_PIPE_CRC_INTERLACE_EN;
3239 
3240 /*
3241  * OPP_PIPE_CRC_PIXEL_SELECT enum
3242  */
3243 
3244 typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3245 OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS     = 0x00000000,
3246 OPP_PIPE_CRC_PIXEL_SELECT_RESERVED       = 0x00000001,
3247 OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS    = 0x00000002,
3248 OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS     = 0x00000003,
3249 } OPP_PIPE_CRC_PIXEL_SELECT;
3250 
3251 /*
3252  * OPP_PIPE_CRC_SOURCE_SELECT enum
3253  */
3254 
3255 typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3256 OPP_PIPE_CRC_SOURCE_SELECT_FMT           = 0x00000000,
3257 OPP_PIPE_CRC_SOURCE_SELECT_SFT           = 0x00000001,
3258 } OPP_PIPE_CRC_SOURCE_SELECT;
3259 
3260 /*
3261  * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3262  */
3263 
3264 typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3265 OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING  = 0x00000000,
3266 OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING    = 0x00000001,
3267 } OPP_PIPE_CRC_ONE_SHOT_PENDING;
3268 
3269 /*******************************************************
3270  * OPP_TOP Enums
3271  *******************************************************/
3272 
3273 /*
3274  * OPP_TOP_CLOCK_GATING_CONTROL enum
3275  */
3276 
3277 typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3278 OPP_TOP_CLOCK_GATING_ENABLED             = 0x00000000,
3279 OPP_TOP_CLOCK_GATING_DISABLED            = 0x00000001,
3280 } OPP_TOP_CLOCK_GATING_CONTROL;
3281 
3282 /*
3283  * OPP_TOP_CLOCK_ENABLE_STATUS enum
3284  */
3285 
3286 typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3287 OPP_TOP_CLOCK_DISABLED_STATUS            = 0x00000000,
3288 OPP_TOP_CLOCK_ENABLED_STATUS             = 0x00000001,
3289 } OPP_TOP_CLOCK_ENABLE_STATUS;
3290 
3291 /*
3292  * OPP_TEST_CLK_SEL_CONTROL enum
3293  */
3294 
3295 typedef enum OPP_TEST_CLK_SEL_CONTROL {
3296 OPP_TEST_CLK_SEL_DISPCLK_P               = 0x00000000,
3297 OPP_TEST_CLK_SEL_DISPCLK_R               = 0x00000001,
3298 OPP_TEST_CLK_SEL_DISPCLK_ABM0            = 0x00000002,
3299 OPP_TEST_CLK_SEL_RESERVED0               = 0x00000003,
3300 OPP_TEST_CLK_SEL_DISPCLK_OPP0            = 0x00000004,
3301 OPP_TEST_CLK_SEL_DISPCLK_OPP1            = 0x00000005,
3302 OPP_TEST_CLK_SEL_DISPCLK_OPP2            = 0x00000006,
3303 OPP_TEST_CLK_SEL_DISPCLK_OPP3            = 0x00000007,
3304 OPP_TEST_CLK_SEL_DISPCLK_OPP4            = 0x00000008,
3305 OPP_TEST_CLK_SEL_DISPCLK_OPP5            = 0x00000009,
3306 } OPP_TEST_CLK_SEL_CONTROL;
3307 
3308 /*******************************************************
3309  * OTG Enums
3310  *******************************************************/
3311 
3312 /*
3313  * OTG_CONTROL_OTG_START_POINT_CNTL enum
3314  */
3315 
3316 typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3317 OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL  = 0x00000000,
3318 OTG_CONTROL_OTG_START_POINT_CNTL_DP      = 0x00000001,
3319 } OTG_CONTROL_OTG_START_POINT_CNTL;
3320 
3321 /*
3322  * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3323  */
3324 
3325 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3326 OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
3327 OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP     = 0x00000001,
3328 } OTG_CONTROL_OTG_FIELD_NUMBER_CNTL;
3329 
3330 /*
3331  * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3332  */
3333 
3334 typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3335 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE  = 0x00000000,
3336 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT  = 0x00000001,
3337 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED  = 0x00000002,
3338 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST  = 0x00000003,
3339 } OTG_CONTROL_OTG_DISABLE_POINT_CNTL;
3340 
3341 /*
3342  * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3343  */
3344 
3345 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3346 OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE  = 0x00000000,
3347 OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE  = 0x00000001,
3348 } OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY;
3349 
3350 /*
3351  * OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE enum
3352  */
3353 
3354 typedef enum OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE {
3355 OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE  = 0x00000000,
3356 OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE  = 0x00000001,
3357 } OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE;
3358 
3359 /*
3360  * OTG_CONTROL_OTG_SOF_PULL_EN enum
3361  */
3362 
3363 typedef enum OTG_CONTROL_OTG_SOF_PULL_EN {
3364 OTG_CONTROL_OTG_SOF_PULL_EN_FALSE        = 0x00000000,
3365 OTG_CONTROL_OTG_SOF_PULL_EN_TRUE         = 0x00000001,
3366 } OTG_CONTROL_OTG_SOF_PULL_EN;
3367 
3368 /*
3369  * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
3370  */
3371 
3372 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
3373 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE  = 0x00000000,
3374 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE  = 0x00000001,
3375 } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL;
3376 
3377 /*
3378  * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
3379  */
3380 
3381 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
3382 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE  = 0x00000000,
3383 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE  = 0x00000001,
3384 } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL;
3385 
3386 /*
3387  * OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN enum
3388  */
3389 
3390 typedef enum OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN {
3391 OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE  = 0x00000000,
3392 OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE  = 0x00000001,
3393 } OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN;
3394 
3395 /*
3396  * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
3397  */
3398 
3399 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
3400 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
3401 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE  = 0x00000001,
3402 } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC;
3403 
3404 /*
3405  * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
3406  */
3407 
3408 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
3409 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
3410 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE  = 0x00000001,
3411 } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT;
3412 
3413 /*
3414  * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
3415  */
3416 
3417 typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
3418 OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0  = 0x00000000,
3419 OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1  = 0x00000001,
3420 } OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD;
3421 
3422 /*
3423  * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
3424  */
3425 
3426 typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
3427 OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
3428 OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE  = 0x00000001,
3429 } OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
3430 
3431 /*
3432  * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
3433  */
3434 
3435 typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
3436 OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
3437 OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE  = 0x00000001,
3438 } OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR;
3439 
3440 /*
3441  * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
3442  */
3443 
3444 typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
3445 OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE  = 0x00000000,
3446 OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE  = 0x00000001,
3447 } OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN;
3448 
3449 /*
3450  * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
3451  */
3452 
3453 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
3454 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0  = 0x00000000,
3455 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN  = 0x00000001,
3456 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN  = 0x00000002,
3457 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN  = 0x00000003,
3458 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN  = 0x00000004,
3459 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN  = 0x00000005,
3460 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN  = 0x00000006,
3461 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN  = 0x00000007,
3462 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN  = 0x00000008,
3463 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN  = 0x00000009,
3464 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN  = 0x0000000a,
3465 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1  = 0x0000000b,
3466 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2  = 0x0000000c,
3467 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN  = 0x0000000d,
3468 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL  = 0x0000000e,
3469 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK  = 0x0000000f,
3470 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP  = 0x00000010,
3471 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING  = 0x00000011,
3472 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF  = 0x00000012,
3473 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC  = 0x00000013,
3474 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC  = 0x00000014,
3475 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL  = 0x00000015,
3476 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL  = 0x00000016,
3477 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1  = 0x00000017,
3478 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING  = 0x00000018,
3479 } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT;
3480 
3481 /*
3482  * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
3483  */
3484 
3485 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
3486 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0  = 0x00000000,
3487 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE  = 0x00000001,
3488 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA  = 0x00000002,
3489 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB  = 0x00000003,
3490 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA  = 0x00000004,
3491 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1  = 0x00000005,
3492 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC  = 0x00000006,
3493 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD  = 0x00000007,
3494 } OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT;
3495 
3496 /*
3497  * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
3498  */
3499 
3500 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
3501 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0  = 0x00000000,
3502 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN  = 0x00000001,
3503 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN  = 0x00000002,
3504 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN  = 0x00000003,
3505 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN  = 0x00000004,
3506 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN  = 0x00000005,
3507 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN  = 0x00000006,
3508 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN  = 0x00000007,
3509 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN  = 0x00000008,
3510 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN  = 0x00000009,
3511 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN  = 0x0000000a,
3512 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1  = 0x0000000b,
3513 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2  = 0x0000000c,
3514 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN  = 0x0000000d,
3515 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL  = 0x0000000e,
3516 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK  = 0x0000000f,
3517 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP  = 0x00000010,
3518 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING  = 0x00000011,
3519 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF  = 0x00000012,
3520 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC  = 0x00000013,
3521 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC  = 0x00000014,
3522 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL  = 0x00000015,
3523 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL  = 0x00000016,
3524 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1  = 0x00000017,
3525 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING  = 0x00000018,
3526 } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT;
3527 
3528 /*
3529  * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
3530  */
3531 
3532 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
3533 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0  = 0x00000000,
3534 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1  = 0x00000001,
3535 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2  = 0x00000002,
3536 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3  = 0x00000003,
3537 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4  = 0x00000004,
3538 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5  = 0x00000005,
3539 } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT;
3540 
3541 /*
3542  * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
3543  */
3544 
3545 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
3546 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0  = 0x00000000,
3547 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE  = 0x00000001,
3548 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA  = 0x00000002,
3549 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB  = 0x00000003,
3550 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA  = 0x00000004,
3551 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1  = 0x00000005,
3552 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC  = 0x00000006,
3553 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD  = 0x00000007,
3554 } OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT;
3555 
3556 /*
3557  * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
3558  */
3559 
3560 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
3561 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0  = 0x00000000,
3562 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1  = 0x00000001,
3563 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2  = 0x00000002,
3564 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3  = 0x00000003,
3565 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4  = 0x00000004,
3566 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5  = 0x00000005,
3567 } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT;
3568 
3569 /*
3570  * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
3571  */
3572 
3573 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
3574 OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
3575 OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
3576 } OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN;
3577 
3578 /*
3579  * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
3580  */
3581 
3582 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
3583 OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE     = 0x00000000,
3584 OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE      = 0x00000001,
3585 } OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR;
3586 
3587 /*
3588  * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
3589  */
3590 
3591 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
3592 OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
3593 OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
3594 } OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN;
3595 
3596 /*
3597  * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
3598  */
3599 
3600 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
3601 OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE     = 0x00000000,
3602 OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE      = 0x00000001,
3603 } OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR;
3604 
3605 /*
3606  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
3607  */
3608 
3609 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
3610 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE  = 0x00000000,
3611 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT  = 0x00000001,
3612 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT  = 0x00000002,
3613 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED  = 0x00000003,
3614 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE;
3615 
3616 /*
3617  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
3618  */
3619 
3620 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
3621 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE  = 0x00000000,
3622 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE  = 0x00000001,
3623 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK;
3624 
3625 /*
3626  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
3627  */
3628 
3629 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
3630 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE  = 0x00000000,
3631 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE  = 0x00000001,
3632 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL;
3633 
3634 /*
3635  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
3636  */
3637 
3638 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
3639 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
3640 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE  = 0x00000001,
3641 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR;
3642 
3643 /*
3644  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
3645  */
3646 
3647 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
3648 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0  = 0x00000000,
3649 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1  = 0x00000001,
3650 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA  = 0x00000002,
3651 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB  = 0x00000003,
3652 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC  = 0x00000004,
3653 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD  = 0x00000005,
3654 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE  = 0x00000006,
3655 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF  = 0x00000007,
3656 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1  = 0x00000008,
3657 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2  = 0x00000009,
3658 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA  = 0x0000000a,
3659 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK  = 0x0000000b,
3660 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA  = 0x0000000c,
3661 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK  = 0x0000000d,
3662 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL  = 0x0000000e,
3663 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE  = 0x0000000f,
3664 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK  = 0x00000010,
3665 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC  = 0x00000011,
3666 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA  = 0x00000012,
3667 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB  = 0x00000013,
3668 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT;
3669 
3670 /*
3671  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
3672  */
3673 
3674 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
3675 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE  = 0x00000000,
3676 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE  = 0x00000001,
3677 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY;
3678 
3679 /*
3680  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
3681  */
3682 
3683 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
3684 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE  = 0x00000000,
3685 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE  = 0x00000001,
3686 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY;
3687 
3688 /*
3689  * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
3690  */
3691 
3692 typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
3693 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO  = 0x00000000,
3694 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT  = 0x00000001,
3695 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT  = 0x00000002,
3696 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED  = 0x00000003,
3697 } OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE;
3698 
3699 /*
3700  * OTG_CONTROL_OTG_MASTER_EN enum
3701  */
3702 
3703 typedef enum OTG_CONTROL_OTG_MASTER_EN {
3704 OTG_CONTROL_OTG_MASTER_EN_FALSE          = 0x00000000,
3705 OTG_CONTROL_OTG_MASTER_EN_TRUE           = 0x00000001,
3706 } OTG_CONTROL_OTG_MASTER_EN;
3707 
3708 /*
3709  * OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN enum
3710  */
3711 
3712 typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN {
3713 OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE  = 0x00000000,
3714 OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE  = 0x00000001,
3715 } OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN;
3716 
3717 /*
3718  * OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE enum
3719  */
3720 
3721 typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE {
3722 OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE  = 0x00000000,
3723 OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE  = 0x00000001,
3724 } OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE;
3725 
3726 /*
3727  * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
3728  */
3729 
3730 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
3731 OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE  = 0x00000000,
3732 OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE  = 0x00000001,
3733 } OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE;
3734 
3735 /*
3736  * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
3737  */
3738 
3739 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
3740 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT  = 0x00000000,
3741 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM  = 0x00000001,
3742 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP  = 0x00000002,
3743 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2  = 0x00000003,
3744 } OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD;
3745 
3746 /*
3747  * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY enum
3748  */
3749 
3750 typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY {
3751 OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE  = 0x00000000,
3752 OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE  = 0x00000001,
3753 } OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY;
3754 
3755 /*
3756  * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT enum
3757  */
3758 
3759 typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT {
3760 OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE  = 0x00000000,
3761 OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE  = 0x00000001,
3762 } OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT;
3763 
3764 /*
3765  * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3766  */
3767 
3768 typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3769 OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE  = 0x00000000,
3770 OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE  = 0x00000001,
3771 } OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN;
3772 
3773 /*
3774  * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
3775  */
3776 
3777 typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
3778 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
3779 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE  = 0x00000001,
3780 } OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE;
3781 
3782 /*
3783  * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
3784  */
3785 
3786 typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
3787 OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
3788 OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE  = 0x00000001,
3789 } OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;
3790 
3791 /*
3792  * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
3793  */
3794 
3795 typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
3796 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE  = 0x00000000,
3797 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA  = 0x00000001,
3798 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB  = 0x00000002,
3799 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED  = 0x00000003,
3800 } OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE;
3801 
3802 /*
3803  * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
3804  */
3805 
3806 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
3807 OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE  = 0x00000000,
3808 OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE  = 0x00000001,
3809 } OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY;
3810 
3811 /*
3812  * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
3813  */
3814 
3815 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
3816 OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE  = 0x00000000,
3817 OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE  = 0x00000001,
3818 } OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY;
3819 
3820 /*
3821  * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
3822  */
3823 
3824 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
3825 OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE   = 0x00000000,
3826 OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE    = 0x00000001,
3827 } OTG_STEREO_CONTROL_OTG_STEREO_EN;
3828 
3829 /*
3830  * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
3831  */
3832 
3833 typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
3834 OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000,
3835 OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE  = 0x00000001,
3836 } OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR;
3837 
3838 /*
3839  * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
3840  */
3841 
3842 typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
3843 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE  = 0x00000000,
3844 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA  = 0x00000001,
3845 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB  = 0x00000002,
3846 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED  = 0x00000003,
3847 } OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL;
3848 
3849 /*
3850  * OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY enum
3851  */
3852 
3853 typedef enum OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY {
3854 OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
3855 OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE  = 0x00000001,
3856 } OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY;
3857 
3858 /*
3859  * OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY enum
3860  */
3861 
3862 typedef enum OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY {
3863 OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
3864 OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE  = 0x00000001,
3865 } OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY;
3866 
3867 /*
3868  * OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN enum
3869  */
3870 
3871 typedef enum OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN {
3872 OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE  = 0x00000000,
3873 OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE  = 0x00000001,
3874 } OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN;
3875 
3876 /*
3877  * OTG_START_LINE_CONTROL_OTG_PREFETCH_EN enum
3878  */
3879 
3880 typedef enum OTG_START_LINE_CONTROL_OTG_PREFETCH_EN {
3881 OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE  = 0x00000000,
3882 OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE  = 0x00000001,
3883 } OTG_START_LINE_CONTROL_OTG_PREFETCH_EN;
3884 
3885 /*
3886  * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
3887  */
3888 
3889 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
3890 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE  = 0x00000000,
3891 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE  = 0x00000001,
3892 } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK;
3893 
3894 /*
3895  * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
3896  */
3897 
3898 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
3899 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE  = 0x00000000,
3900 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE  = 0x00000001,
3901 } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE;
3902 
3903 /*
3904  * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK enum
3905  */
3906 
3907 typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK {
3908 OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE  = 0x00000000,
3909 OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE  = 0x00000001,
3910 } OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK;
3911 
3912 /*
3913  * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE enum
3914  */
3915 
3916 typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE {
3917 OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE  = 0x00000000,
3918 OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE  = 0x00000001,
3919 } OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE;
3920 
3921 /*
3922  * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
3923  */
3924 
3925 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
3926 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE  = 0x00000000,
3927 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE  = 0x00000001,
3928 } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK;
3929 
3930 /*
3931  * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
3932  */
3933 
3934 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
3935 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE  = 0x00000000,
3936 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE  = 0x00000001,
3937 } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE;
3938 
3939 /*
3940  * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
3941  */
3942 
3943 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
3944 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE  = 0x00000000,
3945 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE  = 0x00000001,
3946 } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK;
3947 
3948 /*
3949  * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
3950  */
3951 
3952 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
3953 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE  = 0x00000000,
3954 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE  = 0x00000001,
3955 } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
3956 
3957 /*
3958  * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
3959  */
3960 
3961 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
3962 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE  = 0x00000000,
3963 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE  = 0x00000001,
3964 } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK;
3965 
3966 /*
3967  * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
3968  */
3969 
3970 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
3971 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE  = 0x00000000,
3972 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE  = 0x00000001,
3973 } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE;
3974 
3975 /*
3976  * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
3977  */
3978 
3979 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
3980 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE  = 0x00000000,
3981 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE  = 0x00000001,
3982 } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK;
3983 
3984 /*
3985  * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
3986  */
3987 
3988 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
3989 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE  = 0x00000000,
3990 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE  = 0x00000001,
3991 } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE;
3992 
3993 /*
3994  * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
3995  */
3996 
3997 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
3998 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE  = 0x00000000,
3999 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE  = 0x00000001,
4000 } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK;
4001 
4002 /*
4003  * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4004  */
4005 
4006 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4007 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE  = 0x00000000,
4008 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE  = 0x00000001,
4009 } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE;
4010 
4011 /*
4012  * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4013  */
4014 
4015 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4016 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE  = 0x00000000,
4017 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE  = 0x00000001,
4018 } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK;
4019 
4020 /*
4021  * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4022  */
4023 
4024 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4025 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE  = 0x00000000,
4026 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE  = 0x00000001,
4027 } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE;
4028 
4029 /*
4030  * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4031  */
4032 
4033 typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4034 OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE    = 0x00000000,
4035 OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE     = 0x00000001,
4036 } OTG_UPDATE_LOCK_OTG_UPDATE_LOCK;
4037 
4038 /*
4039  * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4040  */
4041 
4042 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4043 OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE  = 0x00000000,
4044 OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE  = 0x00000001,
4045 } OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY;
4046 
4047 /*
4048  * OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN enum
4049  */
4050 
4051 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN {
4052 OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE  = 0x00000000,
4053 OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE  = 0x00000001,
4054 } OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN;
4055 
4056 /*
4057  * OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE enum
4058  */
4059 
4060 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE {
4061 OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0  = 0x00000000,
4062 OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1  = 0x00000001,
4063 OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2  = 0x00000002,
4064 OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3  = 0x00000003,
4065 } OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE;
4066 
4067 /*
4068  * OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE enum
4069  */
4070 
4071 typedef enum OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE {
4072 OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE  = 0x00000000,
4073 OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE  = 0x00000001,
4074 } OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE;
4075 
4076 /*
4077  * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
4078  */
4079 
4080 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
4081 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
4082 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
4083 } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
4084 
4085 /*
4086  * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4087  */
4088 
4089 typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4090 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME  = 0x00000000,
4091 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME  = 0x00000001,
4092 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME  = 0x00000002,
4093 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME  = 0x00000003,
4094 } OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME;
4095 
4096 /*
4097  * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
4098  */
4099 
4100 typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
4101 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE  = 0x00000000,
4102 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE  = 0x00000001,
4103 } MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
4104 
4105 /*
4106  * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
4107  */
4108 
4109 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
4110 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH  = 0x00000000,
4111 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP  = 0x00000001,
4112 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM  = 0x00000002,
4113 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED  = 0x00000003,
4114 } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
4115 
4116 /*
4117  * OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE enum
4118  */
4119 
4120 typedef enum OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE {
4121 OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE  = 0x00000000,
4122 OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG  = 0x00000001,
4123 OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL  = 0x00000002,
4124 } OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE;
4125 
4126 /*
4127  * OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR enum
4128  */
4129 
4130 typedef enum OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR {
4131 OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE  = 0x00000000,
4132 OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE   = 0x00000001,
4133 } OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR;
4134 
4135 /*
4136  * OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR enum
4137  */
4138 
4139 typedef enum OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR {
4140 OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
4141 OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE  = 0x00000001,
4142 } OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR;
4143 
4144 /*
4145  * OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR enum
4146  */
4147 
4148 typedef enum OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR {
4149 OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
4150 OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE  = 0x00000001,
4151 } OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR;
4152 
4153 /*
4154  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4155  */
4156 
4157 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4158 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE  = 0x00000000,
4159 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE  = 0x00000001,
4160 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
4161 
4162 /*
4163  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4164  */
4165 
4166 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4167 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
4168 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE  = 0x00000001,
4169 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE;
4170 
4171 /*
4172  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4173  */
4174 
4175 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4176 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
4177 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE  = 0x00000001,
4178 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR;
4179 
4180 /*
4181  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4182  */
4183 
4184 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4185 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE  = 0x00000000,
4186 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE  = 0x00000001,
4187 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE;
4188 
4189 /*
4190  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4191  */
4192 
4193 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4194 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
4195 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE  = 0x00000001,
4196 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR;
4197 
4198 /*
4199  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4200  */
4201 
4202 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4203 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
4204 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE  = 0x00000001,
4205 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE;
4206 
4207 /*
4208  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4209  */
4210 
4211 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4212 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE  = 0x00000000,
4213 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE  = 0x00000001,
4214 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE;
4215 
4216 /*
4217  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4218  */
4219 
4220 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4221 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
4222 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE  = 0x00000001,
4223 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR;
4224 
4225 /*
4226  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4227  */
4228 
4229 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4230 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
4231 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE  = 0x00000001,
4232 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE;
4233 
4234 /*
4235  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4236  */
4237 
4238 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4239 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE  = 0x00000000,
4240 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE  = 0x00000001,
4241 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE;
4242 
4243 /*
4244  * OTG_CRC_CNTL_OTG_CRC_EN enum
4245  */
4246 
4247 typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4248 OTG_CRC_CNTL_OTG_CRC_EN_FALSE            = 0x00000000,
4249 OTG_CRC_CNTL_OTG_CRC_EN_TRUE             = 0x00000001,
4250 } OTG_CRC_CNTL_OTG_CRC_EN;
4251 
4252 /*
4253  * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
4254  */
4255 
4256 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
4257 OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE       = 0x00000000,
4258 OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE        = 0x00000001,
4259 } OTG_CRC_CNTL_OTG_CRC_CONT_EN;
4260 
4261 /*
4262  * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4263  */
4264 
4265 typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4266 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT    = 0x00000000,
4267 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT   = 0x00000001,
4268 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES  = 0x00000002,
4269 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS  = 0x00000003,
4270 } OTG_CRC_CNTL_OTG_CRC_STEREO_MODE;
4271 
4272 /*
4273  * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4274  */
4275 
4276 typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4277 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP  = 0x00000000,
4278 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM  = 0x00000001,
4279 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
4280 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD  = 0x00000003,
4281 } OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE;
4282 
4283 /*
4284  * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4285  */
4286 
4287 typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4288 OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
4289 OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE  = 0x00000001,
4290 } OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS;
4291 
4292 /*
4293  * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4294  */
4295 
4296 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4297 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB     = 0x00000000,
4298 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B    = 0x00000001,
4299 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB    = 0x00000002,
4300 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B   = 0x00000003,
4301 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB     = 0x00000004,
4302 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B    = 0x00000005,
4303 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB    = 0x00000006,
4304 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B   = 0x00000007,
4305 } OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT;
4306 
4307 /*
4308  * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4309  */
4310 
4311 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4312 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB     = 0x00000000,
4313 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B    = 0x00000001,
4314 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB    = 0x00000002,
4315 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B   = 0x00000003,
4316 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB     = 0x00000004,
4317 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B    = 0x00000005,
4318 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB    = 0x00000006,
4319 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B   = 0x00000007,
4320 } OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT;
4321 
4322 /*
4323  * OTG_CRC_CNTL2_OTG_CRC_DSC_MODE enum
4324  */
4325 
4326 typedef enum OTG_CRC_CNTL2_OTG_CRC_DSC_MODE {
4327 OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE     = 0x00000000,
4328 OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE      = 0x00000001,
4329 } OTG_CRC_CNTL2_OTG_CRC_DSC_MODE;
4330 
4331 /*
4332  * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE enum
4333  */
4334 
4335 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE {
4336 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE  = 0x00000000,
4337 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE  = 0x00000001,
4338 } OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE;
4339 
4340 /*
4341  * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE enum
4342  */
4343 
4344 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE {
4345 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE  = 0x00000000,
4346 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1  = 0x00000001,
4347 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2  = 0x00000002,
4348 OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3  = 0x00000003,
4349 } OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE;
4350 
4351 /*
4352  * OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT enum
4353  */
4354 
4355 typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT {
4356 OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0      = 0x00000000,
4357 OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1      = 0x00000001,
4358 OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2      = 0x00000002,
4359 OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3      = 0x00000003,
4360 } OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT;
4361 
4362 /*
4363  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE enum
4364  */
4365 
4366 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE {
4367 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE  = 0x00000000,
4368 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT  = 0x00000001,
4369 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS  = 0x00000002,
4370 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED  = 0x00000003,
4371 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE;
4372 
4373 /*
4374  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
4375  */
4376 
4377 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
4378 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE  = 0x00000000,
4379 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE  = 0x00000001,
4380 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
4381 
4382 /*
4383  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
4384  */
4385 
4386 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
4387 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE  = 0x00000000,
4388 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE  = 0x00000001,
4389 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
4390 
4391 /*
4392  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
4393  */
4394 
4395 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
4396 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel  = 0x00000000,
4397 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel  = 0x00000001,
4398 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel  = 0x00000002,
4399 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel  = 0x00000003,
4400 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
4401 
4402 /*
4403  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE enum
4404  */
4405 
4406 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE {
4407 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE  = 0x00000000,
4408 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE  = 0x00000001,
4409 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE;
4410 
4411 /*
4412  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE enum
4413  */
4414 
4415 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE {
4416 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
4417 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE  = 0x00000001,
4418 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE;
4419 
4420 /*
4421  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY enum
4422  */
4423 
4424 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY {
4425 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE  = 0x00000000,
4426 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE  = 0x00000001,
4427 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY;
4428 
4429 /*
4430  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY enum
4431  */
4432 
4433 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY {
4434 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE  = 0x00000000,
4435 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE  = 0x00000001,
4436 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY;
4437 
4438 /*
4439  * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE enum
4440  */
4441 
4442 typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE {
4443 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE  = 0x00000000,
4444 OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE  = 0x00000001,
4445 } OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE;
4446 
4447 /*
4448  * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
4449  */
4450 
4451 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
4452 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE  = 0x00000000,
4453 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE  = 0x00000001,
4454 } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
4455 
4456 /*
4457  * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR enum
4458  */
4459 
4460 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR {
4461 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
4462 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE  = 0x00000001,
4463 } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR;
4464 
4465 /*
4466  * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
4467  */
4468 
4469 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE {
4470 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE  = 0x00000000,
4471 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE  = 0x00000001,
4472 } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE;
4473 
4474 /*
4475  * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
4476  */
4477 
4478 typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
4479 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME  = 0x00000000,
4480 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME  = 0x00000001,
4481 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME  = 0x00000002,
4482 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME  = 0x00000003,
4483 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME  = 0x00000004,
4484 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME  = 0x00000005,
4485 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME  = 0x00000006,
4486 OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME  = 0x00000007,
4487 } OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
4488 
4489 /*
4490  * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE enum
4491  */
4492 
4493 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE {
4494 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE  = 0x00000000,
4495 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE  = 0x00000001,
4496 } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE;
4497 
4498 /*
4499  * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR enum
4500  */
4501 
4502 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR {
4503 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
4504 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE  = 0x00000001,
4505 } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR;
4506 
4507 /*
4508  * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE enum
4509  */
4510 
4511 typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE {
4512 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE  = 0x00000000,
4513 OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE  = 0x00000001,
4514 } OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE;
4515 
4516 /*
4517  * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
4518  */
4519 
4520 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
4521 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE  = 0x00000000,
4522 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE  = 0x00000001,
4523 } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
4524 
4525 /*
4526  * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
4527  */
4528 
4529 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR {
4530 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
4531 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE  = 0x00000001,
4532 } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR;
4533 
4534 /*
4535  * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
4536  */
4537 
4538 typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
4539 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE  = 0x00000000,
4540 OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE  = 0x00000001,
4541 } OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
4542 
4543 /*
4544  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4545  */
4546 
4547 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4548 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE  = 0x00000000,
4549 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE  = 0x00000001,
4550 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE;
4551 
4552 /*
4553  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4554  */
4555 
4556 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4557 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
4558 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE  = 0x00000001,
4559 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR;
4560 
4561 /*
4562  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4563  */
4564 
4565 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4566 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE  = 0x00000000,
4567 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE  = 0x00000001,
4568 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE;
4569 
4570 /*
4571  * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4572  */
4573 
4574 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4575 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE  = 0x00000000,
4576 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE  = 0x00000001,
4577 } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE;
4578 
4579 /*
4580  * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4581  */
4582 
4583 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4584 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF  = 0x00000000,
4585 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON  = 0x00000001,
4586 } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE;
4587 
4588 /*
4589  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
4590  */
4591 
4592 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
4593 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE  = 0x00000000,
4594 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE  = 0x00000001,
4595 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN;
4596 
4597 /*
4598  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
4599  */
4600 
4601 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
4602 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE  = 0x00000000,
4603 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE  = 0x00000001,
4604 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB;
4605 
4606 /*
4607  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
4608  */
4609 
4610 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
4611 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH  = 0x00000000,
4612 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE  = 0x00000001,
4613 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE  = 0x00000002,
4614 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED  = 0x00000003,
4615 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE;
4616 
4617 /*
4618  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
4619  */
4620 
4621 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
4622 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE  = 0x00000000,
4623 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE  = 0x00000001,
4624 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR;
4625 
4626 /*
4627  * OTG_V_SYNC_A_POL enum
4628  */
4629 
4630 typedef enum OTG_V_SYNC_A_POL {
4631 OTG_V_SYNC_A_POL_HIGH                    = 0x00000000,
4632 OTG_V_SYNC_A_POL_LOW                     = 0x00000001,
4633 } OTG_V_SYNC_A_POL;
4634 
4635 /*
4636  * OTG_H_SYNC_A_POL enum
4637  */
4638 
4639 typedef enum OTG_H_SYNC_A_POL {
4640 OTG_H_SYNC_A_POL_HIGH                    = 0x00000000,
4641 OTG_H_SYNC_A_POL_LOW                     = 0x00000001,
4642 } OTG_H_SYNC_A_POL;
4643 
4644 /*
4645  * OTG_HORZ_REPETITION_COUNT enum
4646  */
4647 
4648 typedef enum OTG_HORZ_REPETITION_COUNT {
4649 OTG_HORZ_REPETITION_COUNT_0              = 0x00000000,
4650 OTG_HORZ_REPETITION_COUNT_1              = 0x00000001,
4651 OTG_HORZ_REPETITION_COUNT_2              = 0x00000002,
4652 OTG_HORZ_REPETITION_COUNT_3              = 0x00000003,
4653 OTG_HORZ_REPETITION_COUNT_4              = 0x00000004,
4654 OTG_HORZ_REPETITION_COUNT_5              = 0x00000005,
4655 OTG_HORZ_REPETITION_COUNT_6              = 0x00000006,
4656 OTG_HORZ_REPETITION_COUNT_7              = 0x00000007,
4657 OTG_HORZ_REPETITION_COUNT_8              = 0x00000008,
4658 OTG_HORZ_REPETITION_COUNT_9              = 0x00000009,
4659 OTG_HORZ_REPETITION_COUNT_10             = 0x0000000a,
4660 OTG_HORZ_REPETITION_COUNT_11             = 0x0000000b,
4661 OTG_HORZ_REPETITION_COUNT_12             = 0x0000000c,
4662 OTG_HORZ_REPETITION_COUNT_13             = 0x0000000d,
4663 OTG_HORZ_REPETITION_COUNT_14             = 0x0000000e,
4664 OTG_HORZ_REPETITION_COUNT_15             = 0x0000000f,
4665 } OTG_HORZ_REPETITION_COUNT;
4666 
4667 /*
4668  * MASTER_UPDATE_LOCK_SEL enum
4669  */
4670 
4671 typedef enum MASTER_UPDATE_LOCK_SEL {
4672 MASTER_UPDATE_LOCK_SEL_0                 = 0x00000000,
4673 MASTER_UPDATE_LOCK_SEL_1                 = 0x00000001,
4674 MASTER_UPDATE_LOCK_SEL_2                 = 0x00000002,
4675 MASTER_UPDATE_LOCK_SEL_3                 = 0x00000003,
4676 MASTER_UPDATE_LOCK_SEL_4                 = 0x00000004,
4677 MASTER_UPDATE_LOCK_SEL_5                 = 0x00000005,
4678 } MASTER_UPDATE_LOCK_SEL;
4679 
4680 /*
4681  * DRR_UPDATE_LOCK_SEL enum
4682  */
4683 
4684 typedef enum DRR_UPDATE_LOCK_SEL {
4685 DRR_UPDATE_LOCK_SEL_0                    = 0x00000000,
4686 DRR_UPDATE_LOCK_SEL_1                    = 0x00000001,
4687 DRR_UPDATE_LOCK_SEL_2                    = 0x00000002,
4688 DRR_UPDATE_LOCK_SEL_3                    = 0x00000003,
4689 DRR_UPDATE_LOCK_SEL_4                    = 0x00000004,
4690 DRR_UPDATE_LOCK_SEL_5                    = 0x00000005,
4691 } DRR_UPDATE_LOCK_SEL;
4692 
4693 /*
4694  * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4695  */
4696 
4697 typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4698 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0  = 0x00000000,
4699 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1  = 0x00000001,
4700 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2  = 0x00000002,
4701 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3  = 0x00000003,
4702 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4  = 0x00000004,
4703 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5  = 0x00000005,
4704 } OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL;
4705 
4706 /*
4707  * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4708  */
4709 
4710 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4711 MASTER_UPDATE_LOCK_DB_FIELD_BOTH         = 0x00000000,
4712 MASTER_UPDATE_LOCK_DB_FIELD_TOP          = 0x00000001,
4713 MASTER_UPDATE_LOCK_DB_FIELD_RESERVED     = 0x00000002,
4714 } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD;
4715 
4716 /*
4717  * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4718  */
4719 
4720 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4721 MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH    = 0x00000000,
4722 MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT    = 0x00000001,
4723 MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT   = 0x00000002,
4724 MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED  = 0x00000003,
4725 } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL;
4726 
4727 /*
4728  * OTG_H_TIMING_DIV_BY2 enum
4729  */
4730 
4731 typedef enum OTG_H_TIMING_DIV_BY2 {
4732 OTG_H_TIMING_DIV_BY2_FALSE               = 0x00000000,
4733 OTG_H_TIMING_DIV_BY2_TRUE                = 0x00000001,
4734 } OTG_H_TIMING_DIV_BY2;
4735 
4736 /*
4737  * OTG_H_TIMING_DIV_BY2_UPDATE_MODE enum
4738  */
4739 
4740 typedef enum OTG_H_TIMING_DIV_BY2_UPDATE_MODE {
4741 OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0       = 0x00000000,
4742 OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1       = 0x00000001,
4743 } OTG_H_TIMING_DIV_BY2_UPDATE_MODE;
4744 
4745 /*
4746  * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4747  */
4748 
4749 typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4750 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0      = 0x00000000,
4751 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1      = 0x00000001,
4752 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2      = 0x00000002,
4753 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3      = 0x00000003,
4754 } OTG_TRIGA_RISING_EDGE_DETECT_CNTL;
4755 
4756 /*
4757  * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4758  */
4759 
4760 typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4761 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0     = 0x00000000,
4762 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1     = 0x00000001,
4763 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2     = 0x00000002,
4764 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3     = 0x00000003,
4765 } OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;
4766 
4767 /*
4768  * OTG_TRIGA_FREQUENCY_SELECT enum
4769  */
4770 
4771 typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4772 OTG_TRIGA_FREQUENCY_SELECT_0             = 0x00000000,
4773 OTG_TRIGA_FREQUENCY_SELECT_1             = 0x00000001,
4774 OTG_TRIGA_FREQUENCY_SELECT_2             = 0x00000002,
4775 OTG_TRIGA_FREQUENCY_SELECT_3             = 0x00000003,
4776 } OTG_TRIGA_FREQUENCY_SELECT;
4777 
4778 /*
4779  * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4780  */
4781 
4782 typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4783 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0      = 0x00000000,
4784 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1      = 0x00000001,
4785 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2      = 0x00000002,
4786 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3      = 0x00000003,
4787 } OTG_TRIGB_RISING_EDGE_DETECT_CNTL;
4788 
4789 /*
4790  * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4791  */
4792 
4793 typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4794 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0     = 0x00000000,
4795 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1     = 0x00000001,
4796 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2     = 0x00000002,
4797 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3     = 0x00000003,
4798 } OTG_TRIGB_FALLING_EDGE_DETECT_CNTL;
4799 
4800 /*
4801  * OTG_TRIGB_FREQUENCY_SELECT enum
4802  */
4803 
4804 typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4805 OTG_TRIGB_FREQUENCY_SELECT_0             = 0x00000000,
4806 OTG_TRIGB_FREQUENCY_SELECT_1             = 0x00000001,
4807 OTG_TRIGB_FREQUENCY_SELECT_2             = 0x00000002,
4808 OTG_TRIGB_FREQUENCY_SELECT_3             = 0x00000003,
4809 } OTG_TRIGB_FREQUENCY_SELECT;
4810 
4811 /*
4812  * OTG_PIPE_ABORT enum
4813  */
4814 
4815 typedef enum OTG_PIPE_ABORT {
4816 OTG_PIPE_ABORT_0                         = 0x00000000,
4817 OTG_PIPE_ABORT_1                         = 0x00000001,
4818 } OTG_PIPE_ABORT;
4819 
4820 /*
4821  * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4822  */
4823 
4824 typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4825 OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE      = 0x00000000,
4826 OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE       = 0x00000001,
4827 } OTG_MASTER_UPDATE_LOCK_GSL_EN;
4828 
4829 /*
4830  * OTG_PTI_CONTROL_OTG_PIT_EN enum
4831  */
4832 
4833 typedef enum OTG_PTI_CONTROL_OTG_PIT_EN {
4834 OTG_PTI_CONTROL_OTG_PIT_EN_FALSE         = 0x00000000,
4835 OTG_PTI_CONTROL_OTG_PIT_EN_TRUE          = 0x00000001,
4836 } OTG_PTI_CONTROL_OTG_PIT_EN;
4837 
4838 /*
4839  * OTG_GSL_MASTER_MODE enum
4840  */
4841 
4842 typedef enum OTG_GSL_MASTER_MODE {
4843 OTG_GSL_MASTER_MODE_0                    = 0x00000000,
4844 OTG_GSL_MASTER_MODE_1                    = 0x00000001,
4845 OTG_GSL_MASTER_MODE_2                    = 0x00000002,
4846 OTG_GSL_MASTER_MODE_3                    = 0x00000003,
4847 } OTG_GSL_MASTER_MODE;
4848 
4849 /*******************************************************
4850  * DMCUB Enums
4851  *******************************************************/
4852 
4853 /*
4854  * DC_DMCUB_TIMER_WINDOW enum
4855  */
4856 
4857 typedef enum DC_DMCUB_TIMER_WINDOW {
4858 BITS_31_0                                = 0x00000000,
4859 BITS_32_1                                = 0x00000001,
4860 BITS_33_2                                = 0x00000002,
4861 BITS_34_3                                = 0x00000003,
4862 BITS_35_4                                = 0x00000004,
4863 BITS_36_5                                = 0x00000005,
4864 BITS_37_6                                = 0x00000006,
4865 BITS_38_7                                = 0x00000007,
4866 } DC_DMCUB_TIMER_WINDOW;
4867 
4868 /*
4869  * DC_DMCUB_INT_TYPE enum
4870  */
4871 
4872 typedef enum DC_DMCUB_INT_TYPE {
4873 INT_LEVEL                                = 0x00000000,
4874 INT_PULSE                                = 0x00000001,
4875 } DC_DMCUB_INT_TYPE;
4876 
4877 /*******************************************************
4878  * RBBMIF Enums
4879  *******************************************************/
4880 
4881 /*
4882  * INVALID_REG_ACCESS_TYPE enum
4883  */
4884 
4885 typedef enum INVALID_REG_ACCESS_TYPE {
4886 REG_UNALLOCATED_ADDR_WRITE               = 0x00000000,
4887 REG_UNALLOCATED_ADDR_READ                = 0x00000001,
4888 REG_VIRTUAL_WRITE                        = 0x00000002,
4889 REG_VIRTUAL_READ                         = 0x00000003,
4890 } INVALID_REG_ACCESS_TYPE;
4891 
4892 /*******************************************************
4893  * IHC Enums
4894  *******************************************************/
4895 
4896 /*
4897  * DMU_DC_GPU_TIMER_START_POSITION enum
4898  */
4899 
4900 typedef enum DMU_DC_GPU_TIMER_START_POSITION {
4901 DMU_GPU_TIMER_START_0_END_27             = 0x00000000,
4902 DMU_GPU_TIMER_START_1_END_28             = 0x00000001,
4903 DMU_GPU_TIMER_START_2_END_29             = 0x00000002,
4904 DMU_GPU_TIMER_START_3_END_30             = 0x00000003,
4905 DMU_GPU_TIMER_START_4_END_31             = 0x00000004,
4906 DMU_GPU_TIMER_START_6_END_33             = 0x00000005,
4907 DMU_GPU_TIMER_START_8_END_35             = 0x00000006,
4908 DMU_GPU_TIMER_START_10_END_37            = 0x00000007,
4909 } DMU_DC_GPU_TIMER_START_POSITION;
4910 
4911 /*
4912  * DMU_DC_GPU_TIMER_READ_SELECT enum
4913  */
4914 
4915 typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
4916 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0  = 0x00000000,
4917 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1  = 0x00000001,
4918 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2  = 0x00000002,
4919 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3  = 0x00000003,
4920 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4  = 0x00000004,
4921 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5  = 0x00000005,
4922 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6  = 0x00000006,
4923 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7  = 0x00000007,
4924 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8  = 0x00000008,
4925 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9  = 0x00000009,
4926 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10  = 0x0000000a,
4927 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11  = 0x0000000b,
4928 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12  = 0x0000000c,
4929 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13  = 0x0000000d,
4930 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14  = 0x0000000e,
4931 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15  = 0x0000000f,
4932 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16  = 0x00000010,
4933 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17  = 0x00000011,
4934 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18  = 0x00000012,
4935 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19  = 0x00000013,
4936 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20  = 0x00000014,
4937 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21  = 0x00000015,
4938 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22  = 0x00000016,
4939 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23  = 0x00000017,
4940 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24  = 0x00000018,
4941 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25  = 0x00000019,
4942 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26  = 0x0000001a,
4943 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27  = 0x0000001b,
4944 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28  = 0x0000001c,
4945 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29  = 0x0000001d,
4946 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30  = 0x0000001e,
4947 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31  = 0x0000001f,
4948 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32  = 0x00000020,
4949 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33  = 0x00000021,
4950 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34  = 0x00000022,
4951 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35  = 0x00000023,
4952 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36  = 0x00000024,
4953 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37  = 0x00000025,
4954 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38  = 0x00000026,
4955 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39  = 0x00000027,
4956 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40  = 0x00000028,
4957 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41  = 0x00000029,
4958 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42  = 0x0000002a,
4959 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43  = 0x0000002b,
4960 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44  = 0x0000002c,
4961 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45  = 0x0000002d,
4962 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46  = 0x0000002e,
4963 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47  = 0x0000002f,
4964 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48  = 0x00000030,
4965 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49  = 0x00000031,
4966 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50  = 0x00000032,
4967 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51  = 0x00000033,
4968 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52  = 0x00000034,
4969 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53  = 0x00000035,
4970 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54  = 0x00000036,
4971 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55  = 0x00000037,
4972 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56  = 0x00000038,
4973 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57  = 0x00000039,
4974 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58  = 0x0000003a,
4975 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59  = 0x0000003b,
4976 RESERVED_60                              = 0x0000003c,
4977 RESERVED_61                              = 0x0000003d,
4978 RESERVED_62                              = 0x0000003e,
4979 RESERVED_63                              = 0x0000003f,
4980 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64  = 0x00000040,
4981 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65  = 0x00000041,
4982 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66  = 0x00000042,
4983 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67  = 0x00000043,
4984 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68  = 0x00000044,
4985 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69  = 0x00000045,
4986 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70  = 0x00000046,
4987 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71  = 0x00000047,
4988 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72  = 0x00000048,
4989 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73  = 0x00000049,
4990 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74  = 0x0000004a,
4991 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75  = 0x0000004b,
4992 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76  = 0x0000004c,
4993 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77  = 0x0000004d,
4994 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78  = 0x0000004e,
4995 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79  = 0x0000004f,
4996 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80  = 0x00000050,
4997 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81  = 0x00000051,
4998 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82  = 0x00000052,
4999 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83  = 0x00000053,
5000 DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84  = 0x00000054,
5001 DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85  = 0x00000055,
5002 DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86  = 0x00000056,
5003 DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87  = 0x00000057,
5004 RESERVED_88                              = 0x00000058,
5005 RESERVED_89                              = 0x00000059,
5006 RESERVED_90                              = 0x0000005a,
5007 RESERVED_91                              = 0x0000005b,
5008 } DMU_DC_GPU_TIMER_READ_SELECT;
5009 
5010 /*
5011  * IHC_INTERRUPT_LINE_STATUS enum
5012  */
5013 
5014 typedef enum IHC_INTERRUPT_LINE_STATUS {
5015 INTERRUPT_LINE_NOT_ASSERTED              = 0x00000000,
5016 INTERRUPT_LINE_ASSERTED                  = 0x00000001,
5017 } IHC_INTERRUPT_LINE_STATUS;
5018 
5019 /*******************************************************
5020  * DMU_MISC Enums
5021  *******************************************************/
5022 
5023 /*
5024  * DMU_CLOCK_GATING_DISABLE enum
5025  */
5026 
5027 typedef enum DMU_CLOCK_GATING_DISABLE {
5028 DMU_ENABLE_CLOCK_GATING                  = 0x00000000,
5029 DMU_DISABLE_CLOCK_GATING                 = 0x00000001,
5030 } DMU_CLOCK_GATING_DISABLE;
5031 
5032 /*
5033  * DMU_CLOCK_ON enum
5034  */
5035 
5036 typedef enum DMU_CLOCK_ON {
5037 DMU_CLOCK_STATUS_ON                      = 0x00000000,
5038 DMU_CLOCK_STATUS_OFF                     = 0x00000001,
5039 } DMU_CLOCK_ON;
5040 
5041 /*
5042  * DC_SMU_INTERRUPT_ENABLE enum
5043  */
5044 
5045 typedef enum DC_SMU_INTERRUPT_ENABLE {
5046 DISABLE_THE_INTERRUPT                    = 0x00000000,
5047 ENABLE_THE_INTERRUPT                     = 0x00000001,
5048 } DC_SMU_INTERRUPT_ENABLE;
5049 
5050 /*
5051  * STATIC_SCREEN_SMU_INTR enum
5052  */
5053 
5054 typedef enum STATIC_SCREEN_SMU_INTR {
5055 STATIC_SCREEN_SMU_INTR_NOOP              = 0x00000000,
5056 SET_STATIC_SCREEN_SMU_INTR               = 0x00000001,
5057 } STATIC_SCREEN_SMU_INTR;
5058 
5059 /*******************************************************
5060  * DCCG Enums
5061  *******************************************************/
5062 
5063 /*
5064  * ENABLE enum
5065  */
5066 
5067 typedef enum ENABLE {
5068 DISABLE_THE_FEATURE                      = 0x00000000,
5069 ENABLE_THE_FEATURE                       = 0x00000001,
5070 } ENABLE;
5071 
5072 /*
5073  * DS_HW_CAL_ENABLE enum
5074  */
5075 
5076 typedef enum DS_HW_CAL_ENABLE {
5077 DS_HW_CAL_DIS                            = 0x00000000,
5078 DS_HW_CAL_EN                             = 0x00000001,
5079 } DS_HW_CAL_ENABLE;
5080 
5081 /*
5082  * ENABLE_CLOCK enum
5083  */
5084 
5085 typedef enum ENABLE_CLOCK {
5086 DISABLE_THE_CLOCK                        = 0x00000000,
5087 ENABLE_THE_CLOCK                         = 0x00000001,
5088 } ENABLE_CLOCK;
5089 
5090 /*
5091  * CLEAR_SMU_INTR enum
5092  */
5093 
5094 typedef enum CLEAR_SMU_INTR {
5095 SMU_INTR_STATUS_NOOP                     = 0x00000000,
5096 SMU_INTR_STATUS_CLEAR                    = 0x00000001,
5097 } CLEAR_SMU_INTR;
5098 
5099 /*
5100  * JITTER_REMOVE_DISABLE enum
5101  */
5102 
5103 typedef enum JITTER_REMOVE_DISABLE {
5104 ENABLE_JITTER_REMOVAL                    = 0x00000000,
5105 DISABLE_JITTER_REMOVAL                   = 0x00000001,
5106 } JITTER_REMOVE_DISABLE;
5107 
5108 /*
5109  * DS_REF_SRC enum
5110  */
5111 
5112 typedef enum DS_REF_SRC {
5113 DS_REF_IS_XTALIN                         = 0x00000000,
5114 DS_REF_IS_EXT_GENLOCK                    = 0x00000001,
5115 DS_REF_IS_PCIE                           = 0x00000002,
5116 } DS_REF_SRC;
5117 
5118 /*
5119  * DISABLE_CLOCK_GATING enum
5120  */
5121 
5122 typedef enum DISABLE_CLOCK_GATING {
5123 CLOCK_GATING_ENABLED                     = 0x00000000,
5124 CLOCK_GATING_DISABLED                    = 0x00000001,
5125 } DISABLE_CLOCK_GATING;
5126 
5127 /*
5128  * DISABLE_CLOCK_GATING_IN_DCO enum
5129  */
5130 
5131 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5132 CLOCK_GATING_ENABLED_IN_DCO              = 0x00000000,
5133 CLOCK_GATING_DISABLED_IN_DCO             = 0x00000001,
5134 } DISABLE_CLOCK_GATING_IN_DCO;
5135 
5136 /*
5137  * DCCG_DEEP_COLOR_CNTL enum
5138  */
5139 
5140 typedef enum DCCG_DEEP_COLOR_CNTL {
5141 DCCG_DEEP_COLOR_DTO_DISABLE              = 0x00000000,
5142 DCCG_DEEP_COLOR_DTO_5_4_RATIO            = 0x00000001,
5143 DCCG_DEEP_COLOR_DTO_3_2_RATIO            = 0x00000002,
5144 DCCG_DEEP_COLOR_DTO_2_1_RATIO            = 0x00000003,
5145 } DCCG_DEEP_COLOR_CNTL;
5146 
5147 /*
5148  * REFCLK_CLOCK_EN enum
5149  */
5150 
5151 typedef enum REFCLK_CLOCK_EN {
5152 REFCLK_CLOCK_EN_XTALIN_CLK               = 0x00000000,
5153 REFCLK_CLOCK_EN_ALLOW_SRC_SEL            = 0x00000001,
5154 } REFCLK_CLOCK_EN;
5155 
5156 /*
5157  * REFCLK_SRC_SEL enum
5158  */
5159 
5160 typedef enum REFCLK_SRC_SEL {
5161 REFCLK_SRC_SEL_PCIE_REFCLK               = 0x00000000,
5162 REFCLK_SRC_SEL_CPL_REFCLK                = 0x00000001,
5163 } REFCLK_SRC_SEL;
5164 
5165 /*
5166  * DPREFCLK_SRC_SEL enum
5167  */
5168 
5169 typedef enum DPREFCLK_SRC_SEL {
5170 DPREFCLK_SRC_SEL_CK                      = 0x00000000,
5171 DPREFCLK_SRC_SEL_P0PLL                   = 0x00000001,
5172 DPREFCLK_SRC_SEL_P1PLL                   = 0x00000002,
5173 DPREFCLK_SRC_SEL_P2PLL                   = 0x00000003,
5174 } DPREFCLK_SRC_SEL;
5175 
5176 /*
5177  * XTAL_REF_SEL enum
5178  */
5179 
5180 typedef enum XTAL_REF_SEL {
5181 XTAL_REF_SEL_1X                          = 0x00000000,
5182 XTAL_REF_SEL_2X                          = 0x00000001,
5183 } XTAL_REF_SEL;
5184 
5185 /*
5186  * XTAL_REF_CLOCK_SOURCE_SEL enum
5187  */
5188 
5189 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5190 XTAL_REF_CLOCK_SOURCE_SEL_XTALIN         = 0x00000000,
5191 XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK     = 0x00000001,
5192 } XTAL_REF_CLOCK_SOURCE_SEL;
5193 
5194 /*
5195  * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5196  */
5197 
5198 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5199 MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
5200 MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK  = 0x00000001,
5201 } MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5202 
5203 /*
5204  * ALLOW_SR_ON_TRANS_REQ enum
5205  */
5206 
5207 typedef enum ALLOW_SR_ON_TRANS_REQ {
5208 ALLOW_SR_ON_TRANS_REQ_ENABLE             = 0x00000000,
5209 ALLOW_SR_ON_TRANS_REQ_DISABLE            = 0x00000001,
5210 } ALLOW_SR_ON_TRANS_REQ;
5211 
5212 /*
5213  * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5214  */
5215 
5216 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5217 MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
5218 MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK  = 0x00000001,
5219 } MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5220 
5221 /*
5222  * PIPE_PIXEL_RATE_SOURCE enum
5223  */
5224 
5225 typedef enum PIPE_PIXEL_RATE_SOURCE {
5226 PIPE_PIXEL_RATE_SOURCE_P0PLL             = 0x00000000,
5227 PIPE_PIXEL_RATE_SOURCE_P1PLL             = 0x00000001,
5228 PIPE_PIXEL_RATE_SOURCE_P2PLL             = 0x00000002,
5229 } PIPE_PIXEL_RATE_SOURCE;
5230 
5231 /*
5232  * TEST_CLK_DIV_SEL enum
5233  */
5234 
5235 typedef enum TEST_CLK_DIV_SEL {
5236 NO_DIV                                   = 0x00000000,
5237 DIV_2                                    = 0x00000001,
5238 DIV_4                                    = 0x00000002,
5239 DIV_8                                    = 0x00000003,
5240 } TEST_CLK_DIV_SEL;
5241 
5242 /*
5243  * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5244  */
5245 
5246 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5247 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA    = 0x00000000,
5248 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB    = 0x00000001,
5249 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC    = 0x00000002,
5250 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD    = 0x00000003,
5251 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE    = 0x00000004,
5252 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF    = 0x00000005,
5253 PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED   = 0x00000006,
5254 } PIPE_PHYPLL_PIXEL_RATE_SOURCE;
5255 
5256 /*
5257  * PIPE_PIXEL_RATE_PLL_SOURCE enum
5258  */
5259 
5260 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5261 PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL        = 0x00000000,
5262 PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL       = 0x00000001,
5263 } PIPE_PIXEL_RATE_PLL_SOURCE;
5264 
5265 /*
5266  * DP_DTO_DS_DISABLE enum
5267  */
5268 
5269 typedef enum DP_DTO_DS_DISABLE {
5270 DP_DTO_DESPREAD_DISABLE                  = 0x00000000,
5271 DP_DTO_DESPREAD_ENABLE                   = 0x00000001,
5272 } DP_DTO_DS_DISABLE;
5273 
5274 /*
5275  * OTG_ADD_PIXEL enum
5276  */
5277 
5278 typedef enum OTG_ADD_PIXEL {
5279 OTG_ADD_PIXEL_NOOP                       = 0x00000000,
5280 OTG_ADD_PIXEL_FORCE                      = 0x00000001,
5281 } OTG_ADD_PIXEL;
5282 
5283 /*
5284  * OTG_DROP_PIXEL enum
5285  */
5286 
5287 typedef enum OTG_DROP_PIXEL {
5288 OTG_DROP_PIXEL_NOOP                      = 0x00000000,
5289 OTG_DROP_PIXEL_FORCE                     = 0x00000001,
5290 } OTG_DROP_PIXEL;
5291 
5292 /*
5293  * SYMCLK_FE_FORCE_EN enum
5294  */
5295 
5296 typedef enum SYMCLK_FE_FORCE_EN {
5297 SYMCLK_FE_FORCE_EN_DISABLE               = 0x00000000,
5298 SYMCLK_FE_FORCE_EN_ENABLE                = 0x00000001,
5299 } SYMCLK_FE_FORCE_EN;
5300 
5301 /*
5302  * SYMCLK_FE_FORCE_SRC enum
5303  */
5304 
5305 typedef enum SYMCLK_FE_FORCE_SRC {
5306 SYMCLK_FE_FORCE_SRC_UNIPHYA              = 0x00000000,
5307 SYMCLK_FE_FORCE_SRC_UNIPHYB              = 0x00000001,
5308 SYMCLK_FE_FORCE_SRC_UNIPHYC              = 0x00000002,
5309 SYMCLK_FE_FORCE_SRC_UNIPHYD              = 0x00000003,
5310 SYMCLK_FE_FORCE_SRC_UNIPHYE              = 0x00000004,
5311 SYMCLK_FE_FORCE_SRC_UNIPHYF              = 0x00000005,
5312 SYMCLK_FE_FORCE_SRC_RESERVED             = 0x00000006,
5313 } SYMCLK_FE_FORCE_SRC;
5314 
5315 /*
5316  * DVOACLK_COARSE_SKEW_CNTL enum
5317  */
5318 
5319 typedef enum DVOACLK_COARSE_SKEW_CNTL {
5320 DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT   = 0x00000000,
5321 DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP    = 0x00000001,
5322 DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS   = 0x00000002,
5323 DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS   = 0x00000003,
5324 DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS   = 0x00000004,
5325 DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS   = 0x00000005,
5326 DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS   = 0x00000006,
5327 DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS   = 0x00000007,
5328 DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS   = 0x00000008,
5329 DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS   = 0x00000009,
5330 DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS  = 0x0000000a,
5331 DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS  = 0x0000000b,
5332 DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS  = 0x0000000c,
5333 DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS  = 0x0000000d,
5334 DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS  = 0x0000000e,
5335 DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS  = 0x0000000f,
5336 DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP    = 0x00000010,
5337 DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS   = 0x00000011,
5338 DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS   = 0x00000012,
5339 DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS   = 0x00000013,
5340 DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS   = 0x00000014,
5341 DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS   = 0x00000015,
5342 DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS   = 0x00000016,
5343 DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS   = 0x00000017,
5344 DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS   = 0x00000018,
5345 DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS  = 0x00000019,
5346 DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS  = 0x0000001a,
5347 DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS  = 0x0000001b,
5348 DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS  = 0x0000001c,
5349 DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS  = 0x0000001d,
5350 DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS  = 0x0000001e,
5351 } DVOACLK_COARSE_SKEW_CNTL;
5352 
5353 /*
5354  * DVOACLK_FINE_SKEW_CNTL enum
5355  */
5356 
5357 typedef enum DVOACLK_FINE_SKEW_CNTL {
5358 DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT     = 0x00000000,
5359 DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP      = 0x00000001,
5360 DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS     = 0x00000002,
5361 DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS     = 0x00000003,
5362 DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP      = 0x00000004,
5363 DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS     = 0x00000005,
5364 DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS     = 0x00000006,
5365 DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS     = 0x00000007,
5366 } DVOACLK_FINE_SKEW_CNTL;
5367 
5368 /*
5369  * DVOACLKD_IN_PHASE enum
5370  */
5371 
5372 typedef enum DVOACLKD_IN_PHASE {
5373 DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
5374 DVOACLKD_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
5375 } DVOACLKD_IN_PHASE;
5376 
5377 /*
5378  * DVOACLKC_IN_PHASE enum
5379  */
5380 
5381 typedef enum DVOACLKC_IN_PHASE {
5382 DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
5383 DVOACLKC_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
5384 } DVOACLKC_IN_PHASE;
5385 
5386 /*
5387  * DVOACLKC_MVP_IN_PHASE enum
5388  */
5389 
5390 typedef enum DVOACLKC_MVP_IN_PHASE {
5391 DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
5392 DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO      = 0x00000001,
5393 } DVOACLKC_MVP_IN_PHASE;
5394 
5395 /*
5396  * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
5397  */
5398 
5399 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
5400 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE  = 0x00000000,
5401 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE  = 0x00000001,
5402 } DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
5403 
5404 /*
5405  * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5406  */
5407 
5408 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5409 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0          = 0x00000000,
5410 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1          = 0x00000001,
5411 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2          = 0x00000002,
5412 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3          = 0x00000003,
5413 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4          = 0x00000004,
5414 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5          = 0x00000005,
5415 DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED      = 0x00000006,
5416 } DCCG_AUDIO_DTO0_SOURCE_SEL;
5417 
5418 /*
5419  * DCCG_AUDIO_DTO_SEL enum
5420  */
5421 
5422 typedef enum DCCG_AUDIO_DTO_SEL {
5423 DCCG_AUDIO_DTO_SEL_AUDIO_DTO0            = 0x00000000,
5424 DCCG_AUDIO_DTO_SEL_AUDIO_DTO1            = 0x00000001,
5425 DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO          = 0x00000002,
5426 } DCCG_AUDIO_DTO_SEL;
5427 
5428 /*
5429  * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5430  */
5431 
5432 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5433 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0        = 0x00000000,
5434 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1        = 0x00000001,
5435 } DCCG_AUDIO_DTO2_SOURCE_SEL;
5436 
5437 /*
5438  * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5439  */
5440 
5441 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5442 DCCG_AUDIO_DTO_USE_128FBR_FOR_DP         = 0x00000000,
5443 DCCG_AUDIO_DTO_USE_512FBR_FOR_DP         = 0x00000001,
5444 } DCCG_AUDIO_DTO_USE_512FBR_DTO;
5445 
5446 /*
5447  * DISPCLK_FREQ_RAMP_DONE enum
5448  */
5449 
5450 typedef enum DISPCLK_FREQ_RAMP_DONE {
5451 DISPCLK_FREQ_RAMP_IN_PROGRESS            = 0x00000000,
5452 DISPCLK_FREQ_RAMP_COMPLETED              = 0x00000001,
5453 } DISPCLK_FREQ_RAMP_DONE;
5454 
5455 /*
5456  * DCCG_FIFO_ERRDET_RESET enum
5457  */
5458 
5459 typedef enum DCCG_FIFO_ERRDET_RESET {
5460 DCCG_FIFO_ERRDET_RESET_NOOP              = 0x00000000,
5461 DCCG_FIFO_ERRDET_RESET_FORCE             = 0x00000001,
5462 } DCCG_FIFO_ERRDET_RESET;
5463 
5464 /*
5465  * DCCG_FIFO_ERRDET_STATE enum
5466  */
5467 
5468 typedef enum DCCG_FIFO_ERRDET_STATE {
5469 DCCG_FIFO_ERRDET_STATE_CALIBRATION       = 0x00000000,
5470 DCCG_FIFO_ERRDET_STATE_DETECTION         = 0x00000001,
5471 } DCCG_FIFO_ERRDET_STATE;
5472 
5473 /*
5474  * DCCG_FIFO_ERRDET_OVR_EN enum
5475  */
5476 
5477 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5478 DCCG_FIFO_ERRDET_OVR_DISABLE             = 0x00000000,
5479 DCCG_FIFO_ERRDET_OVR_ENABLE              = 0x00000001,
5480 } DCCG_FIFO_ERRDET_OVR_EN;
5481 
5482 /*
5483  * DISPCLK_CHG_FWD_CORR_DISABLE enum
5484  */
5485 
5486 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5487 DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING  = 0x00000000,
5488 DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING  = 0x00000001,
5489 } DISPCLK_CHG_FWD_CORR_DISABLE;
5490 
5491 /*
5492  * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5493  */
5494 
5495 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5496 DC_MEM_GLOBAL_PWR_REQ_ENABLE             = 0x00000000,
5497 DC_MEM_GLOBAL_PWR_REQ_DISABLE            = 0x00000001,
5498 } DC_MEM_GLOBAL_PWR_REQ_DIS;
5499 
5500 /*
5501  * DCCG_PERF_RUN enum
5502  */
5503 
5504 typedef enum DCCG_PERF_RUN {
5505 DCCG_PERF_RUN_NOOP                       = 0x00000000,
5506 DCCG_PERF_RUN_START                      = 0x00000001,
5507 } DCCG_PERF_RUN;
5508 
5509 /*
5510  * DCCG_PERF_MODE_VSYNC enum
5511  */
5512 
5513 typedef enum DCCG_PERF_MODE_VSYNC {
5514 DCCG_PERF_MODE_VSYNC_NOOP                = 0x00000000,
5515 DCCG_PERF_MODE_VSYNC_START               = 0x00000001,
5516 } DCCG_PERF_MODE_VSYNC;
5517 
5518 /*
5519  * DCCG_PERF_MODE_HSYNC enum
5520  */
5521 
5522 typedef enum DCCG_PERF_MODE_HSYNC {
5523 DCCG_PERF_MODE_HSYNC_NOOP                = 0x00000000,
5524 DCCG_PERF_MODE_HSYNC_START               = 0x00000001,
5525 } DCCG_PERF_MODE_HSYNC;
5526 
5527 /*
5528  * DCCG_PERF_OTG_SELECT enum
5529  */
5530 
5531 typedef enum DCCG_PERF_OTG_SELECT {
5532 DCCG_PERF_SEL_OTG0                       = 0x00000000,
5533 DCCG_PERF_SEL_OTG1                       = 0x00000001,
5534 DCCG_PERF_SEL_OTG2                       = 0x00000002,
5535 DCCG_PERF_SEL_OTG3                       = 0x00000003,
5536 DCCG_PERF_SEL_OTG4                       = 0x00000004,
5537 DCCG_PERF_SEL_OTG5                       = 0x00000005,
5538 DCCG_PERF_SEL_RESERVED                   = 0x00000006,
5539 } DCCG_PERF_OTG_SELECT;
5540 
5541 /*
5542  * CLOCK_BRANCH_SOFT_RESET enum
5543  */
5544 
5545 typedef enum CLOCK_BRANCH_SOFT_RESET {
5546 CLOCK_BRANCH_SOFT_RESET_NOOP             = 0x00000000,
5547 CLOCK_BRANCH_SOFT_RESET_FORCE            = 0x00000001,
5548 } CLOCK_BRANCH_SOFT_RESET;
5549 
5550 /*
5551  * PLL_CFG_IF_SOFT_RESET enum
5552  */
5553 
5554 typedef enum PLL_CFG_IF_SOFT_RESET {
5555 PLL_CFG_IF_SOFT_RESET_NOOP               = 0x00000000,
5556 PLL_CFG_IF_SOFT_RESET_FORCE              = 0x00000001,
5557 } PLL_CFG_IF_SOFT_RESET;
5558 
5559 /*
5560  * DVO_ENABLE_RST enum
5561  */
5562 
5563 typedef enum DVO_ENABLE_RST {
5564 DVO_ENABLE_RST_DISABLE                   = 0x00000000,
5565 DVO_ENABLE_RST_ENABLE                    = 0x00000001,
5566 } DVO_ENABLE_RST;
5567 
5568 /*
5569  * DS_JITTER_COUNT_SRC_SEL enum
5570  */
5571 
5572 typedef enum DS_JITTER_COUNT_SRC_SEL {
5573 DS_JITTER_COUNT_SRC_SEL0                 = 0x00000000,
5574 DS_JITTER_COUNT_SRC_SEL1                 = 0x00000001,
5575 } DS_JITTER_COUNT_SRC_SEL;
5576 
5577 /*
5578  * DIO_FIFO_ERROR enum
5579  */
5580 
5581 typedef enum DIO_FIFO_ERROR {
5582 DIO_FIFO_ERROR_00                        = 0x00000000,
5583 DIO_FIFO_ERROR_01                        = 0x00000001,
5584 DIO_FIFO_ERROR_10                        = 0x00000002,
5585 DIO_FIFO_ERROR_11                        = 0x00000003,
5586 } DIO_FIFO_ERROR;
5587 
5588 /*
5589  * VSYNC_CNT_REFCLK_SEL enum
5590  */
5591 
5592 typedef enum VSYNC_CNT_REFCLK_SEL {
5593 VSYNC_CNT_REFCLK_SEL_0                   = 0x00000000,
5594 VSYNC_CNT_REFCLK_SEL_1                   = 0x00000001,
5595 } VSYNC_CNT_REFCLK_SEL;
5596 
5597 /*
5598  * VSYNC_CNT_RESET_SEL enum
5599  */
5600 
5601 typedef enum VSYNC_CNT_RESET_SEL {
5602 VSYNC_CNT_RESET_SEL_0                    = 0x00000000,
5603 VSYNC_CNT_RESET_SEL_1                    = 0x00000001,
5604 } VSYNC_CNT_RESET_SEL;
5605 
5606 /*
5607  * VSYNC_CNT_LATCH_MASK enum
5608  */
5609 
5610 typedef enum VSYNC_CNT_LATCH_MASK {
5611 VSYNC_CNT_LATCH_MASK_0                   = 0x00000000,
5612 VSYNC_CNT_LATCH_MASK_1                   = 0x00000001,
5613 } VSYNC_CNT_LATCH_MASK;
5614 
5615 /*******************************************************
5616  * HPD Enums
5617  *******************************************************/
5618 
5619 /*
5620  * HPD_INT_CONTROL_ACK enum
5621  */
5622 
5623 typedef enum HPD_INT_CONTROL_ACK {
5624 HPD_INT_CONTROL_ACK_0                    = 0x00000000,
5625 HPD_INT_CONTROL_ACK_1                    = 0x00000001,
5626 } HPD_INT_CONTROL_ACK;
5627 
5628 /*
5629  * HPD_INT_CONTROL_POLARITY enum
5630  */
5631 
5632 typedef enum HPD_INT_CONTROL_POLARITY {
5633 HPD_INT_CONTROL_GEN_INT_ON_DISCON        = 0x00000000,
5634 HPD_INT_CONTROL_GEN_INT_ON_CON           = 0x00000001,
5635 } HPD_INT_CONTROL_POLARITY;
5636 
5637 /*
5638  * HPD_INT_CONTROL_RX_INT_ACK enum
5639  */
5640 
5641 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5642 HPD_INT_CONTROL_RX_INT_ACK_0             = 0x00000000,
5643 HPD_INT_CONTROL_RX_INT_ACK_1             = 0x00000001,
5644 } HPD_INT_CONTROL_RX_INT_ACK;
5645 
5646 /*******************************************************
5647  * DP Enums
5648  *******************************************************/
5649 
5650 /*
5651  * DP_MSO_NUM_OF_SST_LINKS enum
5652  */
5653 
5654 typedef enum DP_MSO_NUM_OF_SST_LINKS {
5655 DP_MSO_ONE_SSTLINK                       = 0x00000000,
5656 DP_MSO_TWO_SSTLINK                       = 0x00000001,
5657 DP_MSO_FOUR_SSTLINK                      = 0x00000002,
5658 } DP_MSO_NUM_OF_SST_LINKS;
5659 
5660 /*
5661  * DP_SYNC_POLARITY enum
5662  */
5663 
5664 typedef enum DP_SYNC_POLARITY {
5665 DP_SYNC_POLARITY_ACTIVE_HIGH             = 0x00000000,
5666 DP_SYNC_POLARITY_ACTIVE_LOW              = 0x00000001,
5667 } DP_SYNC_POLARITY;
5668 
5669 /*
5670  * DP_COMBINE_PIXEL_NUM enum
5671  */
5672 
5673 typedef enum DP_COMBINE_PIXEL_NUM {
5674 DP_COMBINE_ONE_PIXEL                     = 0x00000000,
5675 DP_COMBINE_TWO_PIXEL                     = 0x00000001,
5676 DP_COMBINE_FOUR_PIXEL                    = 0x00000002,
5677 } DP_COMBINE_PIXEL_NUM;
5678 
5679 /*
5680  * DP_LINK_TRAINING_COMPLETE enum
5681  */
5682 
5683 typedef enum DP_LINK_TRAINING_COMPLETE {
5684 DP_LINK_TRAINING_NOT_COMPLETE            = 0x00000000,
5685 DP_LINK_TRAINING_ALREADY_COMPLETE        = 0x00000001,
5686 } DP_LINK_TRAINING_COMPLETE;
5687 
5688 /*
5689  * DP_EMBEDDED_PANEL_MODE enum
5690  */
5691 
5692 typedef enum DP_EMBEDDED_PANEL_MODE {
5693 DP_EXTERNAL_PANEL                        = 0x00000000,
5694 DP_EMBEDDED_PANEL                        = 0x00000001,
5695 } DP_EMBEDDED_PANEL_MODE;
5696 
5697 /*
5698  * DP_PIXEL_ENCODING enum
5699  */
5700 
5701 typedef enum DP_PIXEL_ENCODING {
5702 DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
5703 DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
5704 DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
5705 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
5706 DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
5707 DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
5708 DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
5709 } DP_PIXEL_ENCODING;
5710 
5711 /*
5712  * DP_COMPONENT_DEPTH enum
5713  */
5714 
5715 typedef enum DP_COMPONENT_DEPTH {
5716 DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
5717 DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
5718 DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
5719 DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
5720 DP_COMPONENT_DEPTH_16BPC_RESERVED        = 0x00000004,
5721 DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
5722 } DP_COMPONENT_DEPTH;
5723 
5724 /*
5725  * DP_UDI_LANES enum
5726  */
5727 
5728 typedef enum DP_UDI_LANES {
5729 DP_UDI_1_LANE                            = 0x00000000,
5730 DP_UDI_2_LANES                           = 0x00000001,
5731 DP_UDI_LANES_RESERVED                    = 0x00000002,
5732 DP_UDI_4_LANES                           = 0x00000003,
5733 } DP_UDI_LANES;
5734 
5735 /*
5736  * DP_VID_STREAM_DIS_DEFER enum
5737  */
5738 
5739 typedef enum DP_VID_STREAM_DIS_DEFER {
5740 DP_VID_STREAM_DIS_NO_DEFER               = 0x00000000,
5741 DP_VID_STREAM_DIS_DEFER_TO_HBLANK        = 0x00000001,
5742 DP_VID_STREAM_DIS_DEFER_TO_VBLANK        = 0x00000002,
5743 } DP_VID_STREAM_DIS_DEFER;
5744 
5745 /*
5746  * DP_STEER_OVERFLOW_ACK enum
5747  */
5748 
5749 typedef enum DP_STEER_OVERFLOW_ACK {
5750 DP_STEER_OVERFLOW_ACK_NO_EFFECT          = 0x00000000,
5751 DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT      = 0x00000001,
5752 } DP_STEER_OVERFLOW_ACK;
5753 
5754 /*
5755  * DP_STEER_OVERFLOW_MASK enum
5756  */
5757 
5758 typedef enum DP_STEER_OVERFLOW_MASK {
5759 DP_STEER_OVERFLOW_MASKED                 = 0x00000000,
5760 DP_STEER_OVERFLOW_UNMASK                 = 0x00000001,
5761 } DP_STEER_OVERFLOW_MASK;
5762 
5763 /*
5764  * DP_TU_OVERFLOW_ACK enum
5765  */
5766 
5767 typedef enum DP_TU_OVERFLOW_ACK {
5768 DP_TU_OVERFLOW_ACK_NO_EFFECT             = 0x00000000,
5769 DP_TU_OVERFLOW_ACK_CLR_INTERRUPT         = 0x00000001,
5770 } DP_TU_OVERFLOW_ACK;
5771 
5772 /*
5773  * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
5774  */
5775 
5776 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
5777 DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE  = 0x00000000,
5778 DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START  = 0x00000001,
5779 } DP_VID_M_N_DOUBLE_BUFFER_MODE;
5780 
5781 /*
5782  * DP_VID_M_N_GEN_EN enum
5783  */
5784 
5785 typedef enum DP_VID_M_N_GEN_EN {
5786 DP_VID_M_N_PROGRAMMED_VIA_REG            = 0x00000000,
5787 DP_VID_M_N_CALC_AUTO                     = 0x00000001,
5788 } DP_VID_M_N_GEN_EN;
5789 
5790 /*
5791  * DP_VID_N_MUL enum
5792  */
5793 
5794 typedef enum DP_VID_N_MUL {
5795 DP_VID_M_1X_INPUT_PIXEL_RATE             = 0x00000000,
5796 DP_VID_M_2X_INPUT_PIXEL_RATE             = 0x00000001,
5797 DP_VID_M_4X_INPUT_PIXEL_RATE             = 0x00000002,
5798 DP_VID_M_8X_INPUT_PIXEL_RATE             = 0x00000003,
5799 } DP_VID_N_MUL;
5800 
5801 /*
5802  * DP_VID_ENHANCED_FRAME_MODE enum
5803  */
5804 
5805 typedef enum DP_VID_ENHANCED_FRAME_MODE {
5806 VID_NORMAL_FRAME_MODE                    = 0x00000000,
5807 VID_ENHANCED_MODE                        = 0x00000001,
5808 } DP_VID_ENHANCED_FRAME_MODE;
5809 
5810 /*
5811  * DP_VID_VBID_FIELD_POL enum
5812  */
5813 
5814 typedef enum DP_VID_VBID_FIELD_POL {
5815 DP_VID_VBID_FIELD_POL_NORMAL             = 0x00000000,
5816 DP_VID_VBID_FIELD_POL_INV                = 0x00000001,
5817 } DP_VID_VBID_FIELD_POL;
5818 
5819 /*
5820  * DP_VID_STREAM_DISABLE_ACK enum
5821  */
5822 
5823 typedef enum DP_VID_STREAM_DISABLE_ACK {
5824 ID_STREAM_DISABLE_NO_ACK                 = 0x00000000,
5825 ID_STREAM_DISABLE_ACKED                  = 0x00000001,
5826 } DP_VID_STREAM_DISABLE_ACK;
5827 
5828 /*
5829  * DP_VID_STREAM_DISABLE_MASK enum
5830  */
5831 
5832 typedef enum DP_VID_STREAM_DISABLE_MASK {
5833 VID_STREAM_DISABLE_MASKED                = 0x00000000,
5834 VID_STREAM_DISABLE_UNMASK                = 0x00000001,
5835 } DP_VID_STREAM_DISABLE_MASK;
5836 
5837 /*
5838  * DPHY_ATEST_SEL_LANE0 enum
5839  */
5840 
5841 typedef enum DPHY_ATEST_SEL_LANE0 {
5842 DPHY_ATEST_LANE0_PRBS_PATTERN            = 0x00000000,
5843 DPHY_ATEST_LANE0_REG_PATTERN             = 0x00000001,
5844 } DPHY_ATEST_SEL_LANE0;
5845 
5846 /*
5847  * DPHY_ATEST_SEL_LANE1 enum
5848  */
5849 
5850 typedef enum DPHY_ATEST_SEL_LANE1 {
5851 DPHY_ATEST_LANE1_PRBS_PATTERN            = 0x00000000,
5852 DPHY_ATEST_LANE1_REG_PATTERN             = 0x00000001,
5853 } DPHY_ATEST_SEL_LANE1;
5854 
5855 /*
5856  * DPHY_ATEST_SEL_LANE2 enum
5857  */
5858 
5859 typedef enum DPHY_ATEST_SEL_LANE2 {
5860 DPHY_ATEST_LANE2_PRBS_PATTERN            = 0x00000000,
5861 DPHY_ATEST_LANE2_REG_PATTERN             = 0x00000001,
5862 } DPHY_ATEST_SEL_LANE2;
5863 
5864 /*
5865  * DPHY_ATEST_SEL_LANE3 enum
5866  */
5867 
5868 typedef enum DPHY_ATEST_SEL_LANE3 {
5869 DPHY_ATEST_LANE3_PRBS_PATTERN            = 0x00000000,
5870 DPHY_ATEST_LANE3_REG_PATTERN             = 0x00000001,
5871 } DPHY_ATEST_SEL_LANE3;
5872 
5873 /*
5874  * DPHY_BYPASS enum
5875  */
5876 
5877 typedef enum DPHY_BYPASS {
5878 DPHY_8B10B_OUTPUT                        = 0x00000000,
5879 DPHY_DBG_OUTPUT                          = 0x00000001,
5880 } DPHY_BYPASS;
5881 
5882 /*
5883  * DPHY_SKEW_BYPASS enum
5884  */
5885 
5886 typedef enum DPHY_SKEW_BYPASS {
5887 DPHY_WITH_SKEW                           = 0x00000000,
5888 DPHY_NO_SKEW                             = 0x00000001,
5889 } DPHY_SKEW_BYPASS;
5890 
5891 /*
5892  * DPHY_TRAINING_PATTERN_SEL enum
5893  */
5894 
5895 typedef enum DPHY_TRAINING_PATTERN_SEL {
5896 DPHY_TRAINING_PATTERN_1                  = 0x00000000,
5897 DPHY_TRAINING_PATTERN_2                  = 0x00000001,
5898 DPHY_TRAINING_PATTERN_3                  = 0x00000002,
5899 DPHY_TRAINING_PATTERN_4                  = 0x00000003,
5900 } DPHY_TRAINING_PATTERN_SEL;
5901 
5902 /*
5903  * DPHY_8B10B_RESET enum
5904  */
5905 
5906 typedef enum DPHY_8B10B_RESET {
5907 DPHY_8B10B_NOT_RESET                     = 0x00000000,
5908 DPHY_8B10B_RESETET                       = 0x00000001,
5909 } DPHY_8B10B_RESET;
5910 
5911 /*
5912  * DP_DPHY_8B10B_EXT_DISP enum
5913  */
5914 
5915 typedef enum DP_DPHY_8B10B_EXT_DISP {
5916 DP_DPHY_8B10B_EXT_DISP_ZERO              = 0x00000000,
5917 DP_DPHY_8B10B_EXT_DISP_ONE               = 0x00000001,
5918 } DP_DPHY_8B10B_EXT_DISP;
5919 
5920 /*
5921  * DPHY_8B10B_CUR_DISP enum
5922  */
5923 
5924 typedef enum DPHY_8B10B_CUR_DISP {
5925 DPHY_8B10B_CUR_DISP_ZERO                 = 0x00000000,
5926 DPHY_8B10B_CUR_DISP_ONE                  = 0x00000001,
5927 } DPHY_8B10B_CUR_DISP;
5928 
5929 /*
5930  * DPHY_PRBS_EN enum
5931  */
5932 
5933 typedef enum DPHY_PRBS_EN {
5934 DPHY_PRBS_DISABLE                        = 0x00000000,
5935 DPHY_PRBS_ENABLE                         = 0x00000001,
5936 } DPHY_PRBS_EN;
5937 
5938 /*
5939  * DPHY_PRBS_SEL enum
5940  */
5941 
5942 typedef enum DPHY_PRBS_SEL {
5943 DPHY_PRBS7_SELECTED                      = 0x00000000,
5944 DPHY_PRBS23_SELECTED                     = 0x00000001,
5945 DPHY_PRBS11_SELECTED                     = 0x00000002,
5946 } DPHY_PRBS_SEL;
5947 
5948 /*
5949  * DPHY_FEC_ENABLE enum
5950  */
5951 
5952 typedef enum DPHY_FEC_ENABLE {
5953 DPHY_FEC_DISABLED                        = 0x00000000,
5954 DPHY_FEC_ENABLED                         = 0x00000001,
5955 } DPHY_FEC_ENABLE;
5956 
5957 /*
5958  * FEC_ACTIVE_STATUS enum
5959  */
5960 
5961 typedef enum FEC_ACTIVE_STATUS {
5962 DPHY_FEC_NOT_ACTIVE                      = 0x00000000,
5963 DPHY_FEC_ACTIVE                          = 0x00000001,
5964 } FEC_ACTIVE_STATUS;
5965 
5966 /*
5967  * DPHY_FEC_READY enum
5968  */
5969 
5970 typedef enum DPHY_FEC_READY {
5971 DPHY_FEC_READY_EN                        = 0x00000000,
5972 DPHY_FEC_READY_DIS                       = 0x00000001,
5973 } DPHY_FEC_READY;
5974 
5975 /*
5976  * DPHY_LOAD_BS_COUNT_START enum
5977  */
5978 
5979 typedef enum DPHY_LOAD_BS_COUNT_START {
5980 DPHY_LOAD_BS_COUNT_STARTED               = 0x00000000,
5981 DPHY_LOAD_BS_COUNT_NOT_STARTED           = 0x00000001,
5982 } DPHY_LOAD_BS_COUNT_START;
5983 
5984 /*
5985  * DPHY_CRC_EN enum
5986  */
5987 
5988 typedef enum DPHY_CRC_EN {
5989 DPHY_CRC_DISABLED                        = 0x00000000,
5990 DPHY_CRC_ENABLED                         = 0x00000001,
5991 } DPHY_CRC_EN;
5992 
5993 /*
5994  * DPHY_CRC_CONT_EN enum
5995  */
5996 
5997 typedef enum DPHY_CRC_CONT_EN {
5998 DPHY_CRC_ONE_SHOT                        = 0x00000000,
5999 DPHY_CRC_CONTINUOUS                      = 0x00000001,
6000 } DPHY_CRC_CONT_EN;
6001 
6002 /*
6003  * DPHY_CRC_FIELD enum
6004  */
6005 
6006 typedef enum DPHY_CRC_FIELD {
6007 DPHY_CRC_START_FROM_TOP_FIELD            = 0x00000000,
6008 DPHY_CRC_START_FROM_BOTTOM_FIELD         = 0x00000001,
6009 } DPHY_CRC_FIELD;
6010 
6011 /*
6012  * DPHY_CRC_SEL enum
6013  */
6014 
6015 typedef enum DPHY_CRC_SEL {
6016 DPHY_CRC_LANE0_SELECTED                  = 0x00000000,
6017 DPHY_CRC_LANE1_SELECTED                  = 0x00000001,
6018 DPHY_CRC_LANE2_SELECTED                  = 0x00000002,
6019 DPHY_CRC_LANE3_SELECTED                  = 0x00000003,
6020 } DPHY_CRC_SEL;
6021 
6022 /*
6023  * DPHY_RX_FAST_TRAINING_CAPABLE enum
6024  */
6025 
6026 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
6027 DPHY_FAST_TRAINING_NOT_CAPABLE_0         = 0x00000000,
6028 DPHY_FAST_TRAINING_CAPABLE               = 0x00000001,
6029 } DPHY_RX_FAST_TRAINING_CAPABLE;
6030 
6031 /*
6032  * DP_SEC_COLLISION_ACK enum
6033  */
6034 
6035 typedef enum DP_SEC_COLLISION_ACK {
6036 DP_SEC_COLLISION_ACK_NO_EFFECT           = 0x00000000,
6037 DP_SEC_COLLISION_ACK_CLR_FLAG            = 0x00000001,
6038 } DP_SEC_COLLISION_ACK;
6039 
6040 /*
6041  * DP_SEC_AUDIO_MUTE enum
6042  */
6043 
6044 typedef enum DP_SEC_AUDIO_MUTE {
6045 DP_SEC_AUDIO_MUTE_HW_CTRL                = 0x00000000,
6046 DP_SEC_AUDIO_MUTE_SW_CTRL                = 0x00000001,
6047 } DP_SEC_AUDIO_MUTE;
6048 
6049 /*
6050  * DP_SEC_TIMESTAMP_MODE enum
6051  */
6052 
6053 typedef enum DP_SEC_TIMESTAMP_MODE {
6054 DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE       = 0x00000000,
6055 DP_SEC_TIMESTAMP_AUTO_CALC_MODE          = 0x00000001,
6056 } DP_SEC_TIMESTAMP_MODE;
6057 
6058 /*
6059  * DP_SEC_ASP_PRIORITY enum
6060  */
6061 
6062 typedef enum DP_SEC_ASP_PRIORITY {
6063 DP_SEC_ASP_LOW_PRIORITY                  = 0x00000000,
6064 DP_SEC_ASP_HIGH_PRIORITY                 = 0x00000001,
6065 } DP_SEC_ASP_PRIORITY;
6066 
6067 /*
6068  * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
6069  */
6070 
6071 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
6072 DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ         = 0x00000000,
6073 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED  = 0x00000001,
6074 } DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
6075 
6076 /*
6077  * DP_MSE_SAT_UPDATE_ACT enum
6078  */
6079 
6080 typedef enum DP_MSE_SAT_UPDATE_ACT {
6081 DP_MSE_SAT_UPDATE_NO_ACTION              = 0x00000000,
6082 DP_MSE_SAT_UPDATE_WITH_TRIGGER           = 0x00000001,
6083 DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER        = 0x00000002,
6084 } DP_MSE_SAT_UPDATE_ACT;
6085 
6086 /*
6087  * DP_MSE_LINK_LINE enum
6088  */
6089 
6090 typedef enum DP_MSE_LINK_LINE {
6091 DP_MSE_LINK_LINE_32_MTP_LONG             = 0x00000000,
6092 DP_MSE_LINK_LINE_64_MTP_LONG             = 0x00000001,
6093 DP_MSE_LINK_LINE_128_MTP_LONG            = 0x00000002,
6094 DP_MSE_LINK_LINE_256_MTP_LONG            = 0x00000003,
6095 } DP_MSE_LINK_LINE;
6096 
6097 /*
6098  * DP_MSE_BLANK_CODE enum
6099  */
6100 
6101 typedef enum DP_MSE_BLANK_CODE {
6102 DP_MSE_BLANK_CODE_SF_FILLED              = 0x00000000,
6103 DP_MSE_BLANK_CODE_ZERO_FILLED            = 0x00000001,
6104 } DP_MSE_BLANK_CODE;
6105 
6106 /*
6107  * DP_MSE_TIMESTAMP_MODE enum
6108  */
6109 
6110 typedef enum DP_MSE_TIMESTAMP_MODE {
6111 DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE  = 0x00000000,
6112 DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE   = 0x00000001,
6113 } DP_MSE_TIMESTAMP_MODE;
6114 
6115 /*
6116  * DP_MSE_ZERO_ENCODER enum
6117  */
6118 
6119 typedef enum DP_MSE_ZERO_ENCODER {
6120 DP_MSE_NOT_ZERO_FE_ENCODER               = 0x00000000,
6121 DP_MSE_ZERO_FE_ENCODER                   = 0x00000001,
6122 } DP_MSE_ZERO_ENCODER;
6123 
6124 /*
6125  * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
6126  */
6127 
6128 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
6129 DP_DPHY_HBR2_PASS_THROUGH                = 0x00000000,
6130 DP_DPHY_HBR2_PATTERN_1                   = 0x00000001,
6131 DP_DPHY_HBR2_PATTERN_2_NEG               = 0x00000002,
6132 DP_DPHY_HBR2_PATTERN_3                   = 0x00000003,
6133 DP_DPHY_HBR2_PATTERN_2_POS               = 0x00000006,
6134 } DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
6135 
6136 /*
6137  * DPHY_CRC_MST_PHASE_ERROR_ACK enum
6138  */
6139 
6140 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
6141 DPHY_CRC_MST_PHASE_ERROR_NO_ACK          = 0x00000000,
6142 DPHY_CRC_MST_PHASE_ERROR_ACKED           = 0x00000001,
6143 } DPHY_CRC_MST_PHASE_ERROR_ACK;
6144 
6145 /*
6146  * DPHY_SW_FAST_TRAINING_START enum
6147  */
6148 
6149 typedef enum DPHY_SW_FAST_TRAINING_START {
6150 DPHY_SW_FAST_TRAINING_NOT_STARTED        = 0x00000000,
6151 DPHY_SW_FAST_TRAINING_STARTED            = 0x00000001,
6152 } DPHY_SW_FAST_TRAINING_START;
6153 
6154 /*
6155  * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
6156  */
6157 
6158 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
6159 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED  = 0x00000000,
6160 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED  = 0x00000001,
6161 } DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
6162 
6163 /*
6164  * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
6165  */
6166 
6167 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
6168 DP_DPHY_FAST_TRAINING_COMPLETE_MASKED    = 0x00000000,
6169 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED  = 0x00000001,
6170 } DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
6171 
6172 /*
6173  * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
6174  */
6175 
6176 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
6177 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED  = 0x00000000,
6178 DP_DPHY_FAST_TRAINING_COMPLETE_ACKED     = 0x00000001,
6179 } DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
6180 
6181 /*
6182  * DP_MSA_V_TIMING_OVERRIDE_EN enum
6183  */
6184 
6185 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
6186 MSA_V_TIMING_OVERRIDE_DISABLED           = 0x00000000,
6187 MSA_V_TIMING_OVERRIDE_ENABLED            = 0x00000001,
6188 } DP_MSA_V_TIMING_OVERRIDE_EN;
6189 
6190 /*
6191  * DP_SEC_GSP0_PRIORITY enum
6192  */
6193 
6194 typedef enum DP_SEC_GSP0_PRIORITY {
6195 SEC_GSP0_PRIORITY_LOW                    = 0x00000000,
6196 SEC_GSP0_PRIORITY_HIGH                   = 0x00000001,
6197 } DP_SEC_GSP0_PRIORITY;
6198 
6199 /*
6200  * DP_SEC_GSP_SEND enum
6201  */
6202 
6203 typedef enum DP_SEC_GSP_SEND {
6204 NOT_SENT                                 = 0x00000000,
6205 FORCE_SENT                               = 0x00000001,
6206 } DP_SEC_GSP_SEND;
6207 
6208 /*
6209  * DP_SEC_GSP_SEND_ANY_LINE enum
6210  */
6211 
6212 typedef enum DP_SEC_GSP_SEND_ANY_LINE {
6213 SEND_AT_LINK_NUMBER                      = 0x00000000,
6214 SEND_AT_EARLIEST_TIME                    = 0x00000001,
6215 } DP_SEC_GSP_SEND_ANY_LINE;
6216 
6217 /*
6218  * DP_SEC_LINE_REFERENCE enum
6219  */
6220 
6221 typedef enum DP_SEC_LINE_REFERENCE {
6222 REFER_TO_DP_SOF                          = 0x00000000,
6223 REFER_TO_OTG_SOF                         = 0x00000001,
6224 } DP_SEC_LINE_REFERENCE;
6225 
6226 /*
6227  * DP_SEC_GSP_SEND_PPS enum
6228  */
6229 
6230 typedef enum DP_SEC_GSP_SEND_PPS {
6231 SEND_NORMAL_PACKET                       = 0x00000000,
6232 SEND_PPS_PACKET                          = 0x00000001,
6233 } DP_SEC_GSP_SEND_PPS;
6234 
6235 /*
6236  * DP_ML_PHY_SEQ_MODE enum
6237  */
6238 
6239 typedef enum DP_ML_PHY_SEQ_MODE {
6240 DP_ML_PHY_SEQ_LINE_NUM                   = 0x00000000,
6241 DP_ML_PHY_SEQ_IMMEDIATE                  = 0x00000001,
6242 } DP_ML_PHY_SEQ_MODE;
6243 
6244 /*
6245  * DP_LINK_TRAINING_SWITCH_MODE enum
6246  */
6247 
6248 typedef enum DP_LINK_TRAINING_SWITCH_MODE {
6249 DP_LINK_TRAINING_SWITCH_TO_IDLE          = 0x00000000,
6250 DP_LINK_TRAINING_SWITCH_TO_VIDEO         = 0x00000001,
6251 } DP_LINK_TRAINING_SWITCH_MODE;
6252 
6253 /*
6254  * DP_DSC_MODE enum
6255  */
6256 
6257 typedef enum DP_DSC_MODE {
6258 DP_DSC_DISABLE                           = 0x00000000,
6259 DP_DSC_444_SIMPLE_422                    = 0x00000001,
6260 DP_DSC_NATIVE_422_420                    = 0x00000002,
6261 } DP_DSC_MODE;
6262 
6263 /*******************************************************
6264  * DIG Enums
6265  *******************************************************/
6266 
6267 /*
6268  * HDMI_KEEPOUT_MODE enum
6269  */
6270 
6271 typedef enum HDMI_KEEPOUT_MODE {
6272 HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC        = 0x00000000,
6273 HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC      = 0x00000001,
6274 } HDMI_KEEPOUT_MODE;
6275 
6276 /*
6277  * HDMI_CLOCK_CHANNEL_RATE enum
6278  */
6279 
6280 typedef enum HDMI_CLOCK_CHANNEL_RATE {
6281 HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE  = 0x00000000,
6282 HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE  = 0x00000001,
6283 } HDMI_CLOCK_CHANNEL_RATE;
6284 
6285 /*
6286  * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
6287  */
6288 
6289 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
6290 HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE     = 0x00000000,
6291 HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE    = 0x00000001,
6292 } HDMI_NO_EXTRA_NULL_PACKET_FILLED;
6293 
6294 /*
6295  * HDMI_PACKET_GEN_VERSION enum
6296  */
6297 
6298 typedef enum HDMI_PACKET_GEN_VERSION {
6299 HDMI_PACKET_GEN_VERSION_OLD              = 0x00000000,
6300 HDMI_PACKET_GEN_VERSION_NEW              = 0x00000001,
6301 } HDMI_PACKET_GEN_VERSION;
6302 
6303 /*
6304  * HDMI_ERROR_ACK enum
6305  */
6306 
6307 typedef enum HDMI_ERROR_ACK {
6308 HDMI_ERROR_ACK_INT                       = 0x00000000,
6309 HDMI_ERROR_NOT_ACK                       = 0x00000001,
6310 } HDMI_ERROR_ACK;
6311 
6312 /*
6313  * HDMI_ERROR_MASK enum
6314  */
6315 
6316 typedef enum HDMI_ERROR_MASK {
6317 HDMI_ERROR_MASK_INT                      = 0x00000000,
6318 HDMI_ERROR_NOT_MASK                      = 0x00000001,
6319 } HDMI_ERROR_MASK;
6320 
6321 /*
6322  * HDMI_DEEP_COLOR_DEPTH enum
6323  */
6324 
6325 typedef enum HDMI_DEEP_COLOR_DEPTH {
6326 HDMI_DEEP_COLOR_DEPTH_24BPP              = 0x00000000,
6327 HDMI_DEEP_COLOR_DEPTH_30BPP              = 0x00000001,
6328 HDMI_DEEP_COLOR_DEPTH_36BPP              = 0x00000002,
6329 HDMI_DEEP_COLOR_DEPTH_48BPP              = 0x00000003,
6330 } HDMI_DEEP_COLOR_DEPTH;
6331 
6332 /*
6333  * HDMI_AUDIO_DELAY_EN enum
6334  */
6335 
6336 typedef enum HDMI_AUDIO_DELAY_EN {
6337 HDMI_AUDIO_DELAY_DISABLE                 = 0x00000000,
6338 HDMI_AUDIO_DELAY_58CLK                   = 0x00000001,
6339 HDMI_AUDIO_DELAY_56CLK                   = 0x00000002,
6340 HDMI_AUDIO_DELAY_RESERVED                = 0x00000003,
6341 } HDMI_AUDIO_DELAY_EN;
6342 
6343 /*
6344  * HDMI_AUDIO_SEND_MAX_PACKETS enum
6345  */
6346 
6347 typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
6348 HDMI_NOT_SEND_MAX_AUDIO_PACKETS          = 0x00000000,
6349 HDMI_SEND_MAX_AUDIO_PACKETS              = 0x00000001,
6350 } HDMI_AUDIO_SEND_MAX_PACKETS;
6351 
6352 /*
6353  * HDMI_ACR_SEND enum
6354  */
6355 
6356 typedef enum HDMI_ACR_SEND {
6357 HDMI_ACR_NOT_SEND                        = 0x00000000,
6358 HDMI_ACR_PKT_SEND                        = 0x00000001,
6359 } HDMI_ACR_SEND;
6360 
6361 /*
6362  * HDMI_ACR_CONT enum
6363  */
6364 
6365 typedef enum HDMI_ACR_CONT {
6366 HDMI_ACR_CONT_DISABLE                    = 0x00000000,
6367 HDMI_ACR_CONT_ENABLE                     = 0x00000001,
6368 } HDMI_ACR_CONT;
6369 
6370 /*
6371  * HDMI_ACR_SELECT enum
6372  */
6373 
6374 typedef enum HDMI_ACR_SELECT {
6375 HDMI_ACR_SELECT_HW                       = 0x00000000,
6376 HDMI_ACR_SELECT_32K                      = 0x00000001,
6377 HDMI_ACR_SELECT_44K                      = 0x00000002,
6378 HDMI_ACR_SELECT_48K                      = 0x00000003,
6379 } HDMI_ACR_SELECT;
6380 
6381 /*
6382  * HDMI_ACR_SOURCE enum
6383  */
6384 
6385 typedef enum HDMI_ACR_SOURCE {
6386 HDMI_ACR_SOURCE_HW                       = 0x00000000,
6387 HDMI_ACR_SOURCE_SW                       = 0x00000001,
6388 } HDMI_ACR_SOURCE;
6389 
6390 /*
6391  * HDMI_ACR_N_MULTIPLE enum
6392  */
6393 
6394 typedef enum HDMI_ACR_N_MULTIPLE {
6395 HDMI_ACR_0_MULTIPLE_RESERVED             = 0x00000000,
6396 HDMI_ACR_1_MULTIPLE                      = 0x00000001,
6397 HDMI_ACR_2_MULTIPLE                      = 0x00000002,
6398 HDMI_ACR_3_MULTIPLE_RESERVED             = 0x00000003,
6399 HDMI_ACR_4_MULTIPLE                      = 0x00000004,
6400 HDMI_ACR_5_MULTIPLE_RESERVED             = 0x00000005,
6401 HDMI_ACR_6_MULTIPLE_RESERVED             = 0x00000006,
6402 HDMI_ACR_7_MULTIPLE_RESERVED             = 0x00000007,
6403 } HDMI_ACR_N_MULTIPLE;
6404 
6405 /*
6406  * HDMI_ACR_AUDIO_PRIORITY enum
6407  */
6408 
6409 typedef enum HDMI_ACR_AUDIO_PRIORITY {
6410 HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE  = 0x00000000,
6411 HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT  = 0x00000001,
6412 } HDMI_ACR_AUDIO_PRIORITY;
6413 
6414 /*
6415  * HDMI_NULL_SEND enum
6416  */
6417 
6418 typedef enum HDMI_NULL_SEND {
6419 HDMI_NULL_NOT_SEND                       = 0x00000000,
6420 HDMI_NULL_PKT_SEND                       = 0x00000001,
6421 } HDMI_NULL_SEND;
6422 
6423 /*
6424  * HDMI_GC_SEND enum
6425  */
6426 
6427 typedef enum HDMI_GC_SEND {
6428 HDMI_GC_NOT_SEND                         = 0x00000000,
6429 HDMI_GC_PKT_SEND                         = 0x00000001,
6430 } HDMI_GC_SEND;
6431 
6432 /*
6433  * HDMI_GC_CONT enum
6434  */
6435 
6436 typedef enum HDMI_GC_CONT {
6437 HDMI_GC_CONT_DISABLE                     = 0x00000000,
6438 HDMI_GC_CONT_ENABLE                      = 0x00000001,
6439 } HDMI_GC_CONT;
6440 
6441 /*
6442  * HDMI_ISRC_SEND enum
6443  */
6444 
6445 typedef enum HDMI_ISRC_SEND {
6446 HDMI_ISRC_NOT_SEND                       = 0x00000000,
6447 HDMI_ISRC_PKT_SEND                       = 0x00000001,
6448 } HDMI_ISRC_SEND;
6449 
6450 /*
6451  * HDMI_ISRC_CONT enum
6452  */
6453 
6454 typedef enum HDMI_ISRC_CONT {
6455 HDMI_ISRC_CONT_DISABLE                   = 0x00000000,
6456 HDMI_ISRC_CONT_ENABLE                    = 0x00000001,
6457 } HDMI_ISRC_CONT;
6458 
6459 /*
6460  * HDMI_AUDIO_INFO_SEND enum
6461  */
6462 
6463 typedef enum HDMI_AUDIO_INFO_SEND {
6464 HDMI_AUDIO_INFO_NOT_SEND                 = 0x00000000,
6465 HDMI_AUDIO_INFO_PKT_SEND                 = 0x00000001,
6466 } HDMI_AUDIO_INFO_SEND;
6467 
6468 /*
6469  * HDMI_AUDIO_INFO_CONT enum
6470  */
6471 
6472 typedef enum HDMI_AUDIO_INFO_CONT {
6473 HDMI_AUDIO_INFO_CONT_DISABLE             = 0x00000000,
6474 HDMI_AUDIO_INFO_CONT_ENABLE              = 0x00000001,
6475 } HDMI_AUDIO_INFO_CONT;
6476 
6477 /*
6478  * HDMI_MPEG_INFO_SEND enum
6479  */
6480 
6481 typedef enum HDMI_MPEG_INFO_SEND {
6482 HDMI_MPEG_INFO_NOT_SEND                  = 0x00000000,
6483 HDMI_MPEG_INFO_PKT_SEND                  = 0x00000001,
6484 } HDMI_MPEG_INFO_SEND;
6485 
6486 /*
6487  * HDMI_MPEG_INFO_CONT enum
6488  */
6489 
6490 typedef enum HDMI_MPEG_INFO_CONT {
6491 HDMI_MPEG_INFO_CONT_DISABLE              = 0x00000000,
6492 HDMI_MPEG_INFO_CONT_ENABLE               = 0x00000001,
6493 } HDMI_MPEG_INFO_CONT;
6494 
6495 /*
6496  * HDMI_GENERIC_SEND enum
6497  */
6498 
6499 typedef enum HDMI_GENERIC_SEND {
6500 HDMI_GENERIC_NOT_SEND                    = 0x00000000,
6501 HDMI_GENERIC_PKT_SEND                    = 0x00000001,
6502 } HDMI_GENERIC_SEND;
6503 
6504 /*
6505  * HDMI_GENERIC_CONT enum
6506  */
6507 
6508 typedef enum HDMI_GENERIC_CONT {
6509 HDMI_GENERIC_CONT_DISABLE                = 0x00000000,
6510 HDMI_GENERIC_CONT_ENABLE                 = 0x00000001,
6511 } HDMI_GENERIC_CONT;
6512 
6513 /*
6514  * HDMI_GC_AVMUTE_CONT enum
6515  */
6516 
6517 typedef enum HDMI_GC_AVMUTE_CONT {
6518 HDMI_GC_AVMUTE_CONT_DISABLE              = 0x00000000,
6519 HDMI_GC_AVMUTE_CONT_ENABLE               = 0x00000001,
6520 } HDMI_GC_AVMUTE_CONT;
6521 
6522 /*
6523  * HDMI_PACKING_PHASE_OVERRIDE enum
6524  */
6525 
6526 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
6527 HDMI_PACKING_PHASE_SET_BY_HW             = 0x00000000,
6528 HDMI_PACKING_PHASE_SET_BY_SW             = 0x00000001,
6529 } HDMI_PACKING_PHASE_OVERRIDE;
6530 
6531 /*
6532  * TMDS_PIXEL_ENCODING enum
6533  */
6534 
6535 typedef enum TMDS_PIXEL_ENCODING {
6536 TMDS_PIXEL_ENCODING_444_OR_420           = 0x00000000,
6537 TMDS_PIXEL_ENCODING_422                  = 0x00000001,
6538 } TMDS_PIXEL_ENCODING;
6539 
6540 /*
6541  * TMDS_COLOR_FORMAT enum
6542  */
6543 
6544 typedef enum TMDS_COLOR_FORMAT {
6545 TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP  = 0x00000000,
6546 TMDS_COLOR_FORMAT_TWIN30BPP_LSB          = 0x00000001,
6547 TMDS_COLOR_FORMAT_DUAL30BPP              = 0x00000002,
6548 TMDS_COLOR_FORMAT_RESERVED               = 0x00000003,
6549 } TMDS_COLOR_FORMAT;
6550 
6551 /*
6552  * TMDS_STEREOSYNC_CTL_SEL_REG enum
6553  */
6554 
6555 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
6556 TMDS_STEREOSYNC_CTL0                     = 0x00000000,
6557 TMDS_STEREOSYNC_CTL1                     = 0x00000001,
6558 TMDS_STEREOSYNC_CTL2                     = 0x00000002,
6559 TMDS_STEREOSYNC_CTL3                     = 0x00000003,
6560 } TMDS_STEREOSYNC_CTL_SEL_REG;
6561 
6562 /*
6563  * TMDS_CTL0_DATA_SEL enum
6564  */
6565 
6566 typedef enum TMDS_CTL0_DATA_SEL {
6567 TMDS_CTL0_DATA_SEL0_RESERVED             = 0x00000000,
6568 TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
6569 TMDS_CTL0_DATA_SEL2_VSYNC                = 0x00000002,
6570 TMDS_CTL0_DATA_SEL3_RESERVED             = 0x00000003,
6571 TMDS_CTL0_DATA_SEL4_HSYNC                = 0x00000004,
6572 TMDS_CTL0_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
6573 TMDS_CTL0_DATA_SEL8_RANDOM_DATA          = 0x00000006,
6574 TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA    = 0x00000007,
6575 } TMDS_CTL0_DATA_SEL;
6576 
6577 /*
6578  * TMDS_CTL0_DATA_INVERT enum
6579  */
6580 
6581 typedef enum TMDS_CTL0_DATA_INVERT {
6582 TMDS_CTL0_DATA_NORMAL                    = 0x00000000,
6583 TMDS_CTL0_DATA_INVERT_EN                 = 0x00000001,
6584 } TMDS_CTL0_DATA_INVERT;
6585 
6586 /*
6587  * TMDS_CTL0_DATA_MODULATION enum
6588  */
6589 
6590 typedef enum TMDS_CTL0_DATA_MODULATION {
6591 TMDS_CTL0_DATA_MODULATION_DISABLE        = 0x00000000,
6592 TMDS_CTL0_DATA_MODULATION_BIT0           = 0x00000001,
6593 TMDS_CTL0_DATA_MODULATION_BIT1           = 0x00000002,
6594 TMDS_CTL0_DATA_MODULATION_BIT2           = 0x00000003,
6595 } TMDS_CTL0_DATA_MODULATION;
6596 
6597 /*
6598  * TMDS_CTL0_PATTERN_OUT_EN enum
6599  */
6600 
6601 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
6602 TMDS_CTL0_PATTERN_OUT_DISABLE            = 0x00000000,
6603 TMDS_CTL0_PATTERN_OUT_ENABLE             = 0x00000001,
6604 } TMDS_CTL0_PATTERN_OUT_EN;
6605 
6606 /*
6607  * TMDS_CTL1_DATA_SEL enum
6608  */
6609 
6610 typedef enum TMDS_CTL1_DATA_SEL {
6611 TMDS_CTL1_DATA_SEL0_RESERVED             = 0x00000000,
6612 TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
6613 TMDS_CTL1_DATA_SEL2_VSYNC                = 0x00000002,
6614 TMDS_CTL1_DATA_SEL3_RESERVED             = 0x00000003,
6615 TMDS_CTL1_DATA_SEL4_HSYNC                = 0x00000004,
6616 TMDS_CTL1_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
6617 TMDS_CTL1_DATA_SEL8_BLANK_TIME           = 0x00000006,
6618 TMDS_CTL1_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
6619 } TMDS_CTL1_DATA_SEL;
6620 
6621 /*
6622  * TMDS_CTL1_DATA_INVERT enum
6623  */
6624 
6625 typedef enum TMDS_CTL1_DATA_INVERT {
6626 TMDS_CTL1_DATA_NORMAL                    = 0x00000000,
6627 TMDS_CTL1_DATA_INVERT_EN                 = 0x00000001,
6628 } TMDS_CTL1_DATA_INVERT;
6629 
6630 /*
6631  * TMDS_CTL1_DATA_MODULATION enum
6632  */
6633 
6634 typedef enum TMDS_CTL1_DATA_MODULATION {
6635 TMDS_CTL1_DATA_MODULATION_DISABLE        = 0x00000000,
6636 TMDS_CTL1_DATA_MODULATION_BIT0           = 0x00000001,
6637 TMDS_CTL1_DATA_MODULATION_BIT1           = 0x00000002,
6638 TMDS_CTL1_DATA_MODULATION_BIT2           = 0x00000003,
6639 } TMDS_CTL1_DATA_MODULATION;
6640 
6641 /*
6642  * TMDS_CTL1_PATTERN_OUT_EN enum
6643  */
6644 
6645 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
6646 TMDS_CTL1_PATTERN_OUT_DISABLE            = 0x00000000,
6647 TMDS_CTL1_PATTERN_OUT_ENABLE             = 0x00000001,
6648 } TMDS_CTL1_PATTERN_OUT_EN;
6649 
6650 /*
6651  * TMDS_CTL2_DATA_SEL enum
6652  */
6653 
6654 typedef enum TMDS_CTL2_DATA_SEL {
6655 TMDS_CTL2_DATA_SEL0_RESERVED             = 0x00000000,
6656 TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
6657 TMDS_CTL2_DATA_SEL2_VSYNC                = 0x00000002,
6658 TMDS_CTL2_DATA_SEL3_RESERVED             = 0x00000003,
6659 TMDS_CTL2_DATA_SEL4_HSYNC                = 0x00000004,
6660 TMDS_CTL2_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
6661 TMDS_CTL2_DATA_SEL8_BLANK_TIME           = 0x00000006,
6662 TMDS_CTL2_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
6663 } TMDS_CTL2_DATA_SEL;
6664 
6665 /*
6666  * TMDS_CTL2_DATA_INVERT enum
6667  */
6668 
6669 typedef enum TMDS_CTL2_DATA_INVERT {
6670 TMDS_CTL2_DATA_NORMAL                    = 0x00000000,
6671 TMDS_CTL2_DATA_INVERT_EN                 = 0x00000001,
6672 } TMDS_CTL2_DATA_INVERT;
6673 
6674 /*
6675  * TMDS_CTL2_DATA_MODULATION enum
6676  */
6677 
6678 typedef enum TMDS_CTL2_DATA_MODULATION {
6679 TMDS_CTL2_DATA_MODULATION_DISABLE        = 0x00000000,
6680 TMDS_CTL2_DATA_MODULATION_BIT0           = 0x00000001,
6681 TMDS_CTL2_DATA_MODULATION_BIT1           = 0x00000002,
6682 TMDS_CTL2_DATA_MODULATION_BIT2           = 0x00000003,
6683 } TMDS_CTL2_DATA_MODULATION;
6684 
6685 /*
6686  * TMDS_CTL2_PATTERN_OUT_EN enum
6687  */
6688 
6689 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
6690 TMDS_CTL2_PATTERN_OUT_DISABLE            = 0x00000000,
6691 TMDS_CTL2_PATTERN_OUT_ENABLE             = 0x00000001,
6692 } TMDS_CTL2_PATTERN_OUT_EN;
6693 
6694 /*
6695  * TMDS_CTL3_DATA_INVERT enum
6696  */
6697 
6698 typedef enum TMDS_CTL3_DATA_INVERT {
6699 TMDS_CTL3_DATA_NORMAL                    = 0x00000000,
6700 TMDS_CTL3_DATA_INVERT_EN                 = 0x00000001,
6701 } TMDS_CTL3_DATA_INVERT;
6702 
6703 /*
6704  * TMDS_CTL3_DATA_MODULATION enum
6705  */
6706 
6707 typedef enum TMDS_CTL3_DATA_MODULATION {
6708 TMDS_CTL3_DATA_MODULATION_DISABLE        = 0x00000000,
6709 TMDS_CTL3_DATA_MODULATION_BIT0           = 0x00000001,
6710 TMDS_CTL3_DATA_MODULATION_BIT1           = 0x00000002,
6711 TMDS_CTL3_DATA_MODULATION_BIT2           = 0x00000003,
6712 } TMDS_CTL3_DATA_MODULATION;
6713 
6714 /*
6715  * TMDS_CTL3_PATTERN_OUT_EN enum
6716  */
6717 
6718 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
6719 TMDS_CTL3_PATTERN_OUT_DISABLE            = 0x00000000,
6720 TMDS_CTL3_PATTERN_OUT_ENABLE             = 0x00000001,
6721 } TMDS_CTL3_PATTERN_OUT_EN;
6722 
6723 /*
6724  * TMDS_CTL3_DATA_SEL enum
6725  */
6726 
6727 typedef enum TMDS_CTL3_DATA_SEL {
6728 TMDS_CTL3_DATA_SEL0_RESERVED             = 0x00000000,
6729 TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
6730 TMDS_CTL3_DATA_SEL2_VSYNC                = 0x00000002,
6731 TMDS_CTL3_DATA_SEL3_RESERVED             = 0x00000003,
6732 TMDS_CTL3_DATA_SEL4_HSYNC                = 0x00000004,
6733 TMDS_CTL3_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
6734 TMDS_CTL3_DATA_SEL8_BLANK_TIME           = 0x00000006,
6735 TMDS_CTL3_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
6736 } TMDS_CTL3_DATA_SEL;
6737 
6738 /*
6739  * DIG_FE_CNTL_SOURCE_SELECT enum
6740  */
6741 
6742 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
6743 DIG_FE_SOURCE_FROM_OTG0                  = 0x00000000,
6744 DIG_FE_SOURCE_FROM_OTG1                  = 0x00000001,
6745 DIG_FE_SOURCE_FROM_OTG2                  = 0x00000002,
6746 DIG_FE_SOURCE_FROM_OTG3                  = 0x00000003,
6747 DIG_FE_SOURCE_FROM_OTG4                  = 0x00000004,
6748 DIG_FE_SOURCE_FROM_OTG5                  = 0x00000005,
6749 DIG_FE_SOURCE_RESERVED                   = 0x00000006,
6750 } DIG_FE_CNTL_SOURCE_SELECT;
6751 
6752 /*
6753  * DIG_FE_CNTL_STEREOSYNC_SELECT enum
6754  */
6755 
6756 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
6757 DIG_FE_STEREOSYNC_FROM_OTG0              = 0x00000000,
6758 DIG_FE_STEREOSYNC_FROM_OTG1              = 0x00000001,
6759 DIG_FE_STEREOSYNC_FROM_OTG2              = 0x00000002,
6760 DIG_FE_STEREOSYNC_FROM_OTG3              = 0x00000003,
6761 DIG_FE_STEREOSYNC_FROM_OTG4              = 0x00000004,
6762 DIG_FE_STEREOSYNC_FROM_OTG5              = 0x00000005,
6763 DIG_FE_STEREOSYNC_RESERVED               = 0x00000006,
6764 } DIG_FE_CNTL_STEREOSYNC_SELECT;
6765 
6766 /*
6767  * DIG_FIFO_READ_CLOCK_SRC enum
6768  */
6769 
6770 typedef enum DIG_FIFO_READ_CLOCK_SRC {
6771 DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG        = 0x00000000,
6772 DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE  = 0x00000001,
6773 } DIG_FIFO_READ_CLOCK_SRC;
6774 
6775 /*
6776  * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
6777  */
6778 
6779 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
6780 DIG_OUTPUT_CRC_ON_LINK0                  = 0x00000000,
6781 DIG_OUTPUT_CRC_ON_LINK1                  = 0x00000001,
6782 } DIG_OUTPUT_CRC_CNTL_LINK_SEL;
6783 
6784 /*
6785  * DIG_OUTPUT_CRC_DATA_SEL enum
6786  */
6787 
6788 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
6789 DIG_OUTPUT_CRC_FOR_FULLFRAME             = 0x00000000,
6790 DIG_OUTPUT_CRC_FOR_ACTIVEONLY            = 0x00000001,
6791 DIG_OUTPUT_CRC_FOR_VBI                   = 0x00000002,
6792 DIG_OUTPUT_CRC_FOR_AUDIO                 = 0x00000003,
6793 } DIG_OUTPUT_CRC_DATA_SEL;
6794 
6795 /*
6796  * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
6797  */
6798 
6799 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
6800 DIG_IN_NORMAL_OPERATION                  = 0x00000000,
6801 DIG_IN_DEBUG_MODE                        = 0x00000001,
6802 } DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
6803 
6804 /*
6805  * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
6806  */
6807 
6808 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
6809 DIG_10BIT_TEST_PATTERN                   = 0x00000000,
6810 DIG_ALTERNATING_TEST_PATTERN             = 0x00000001,
6811 } DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
6812 
6813 /*
6814  * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
6815  */
6816 
6817 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
6818 DIG_TEST_PATTERN_NORMAL                  = 0x00000000,
6819 DIG_TEST_PATTERN_RANDOM                  = 0x00000001,
6820 } DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
6821 
6822 /*
6823  * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
6824  */
6825 
6826 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
6827 DIG_RANDOM_PATTERN_ENABLED               = 0x00000000,
6828 DIG_RANDOM_PATTERN_RESETED               = 0x00000001,
6829 } DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
6830 
6831 /*
6832  * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
6833  */
6834 
6835 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
6836 DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE   = 0x00000000,
6837 DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG  = 0x00000001,
6838 } DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
6839 
6840 /*
6841  * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
6842  */
6843 
6844 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
6845 DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS  = 0x00000000,
6846 DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH  = 0x00000001,
6847 } DIG_RANDOM_PATTERN_SEED_RAN_PAT;
6848 
6849 /*
6850  * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
6851  */
6852 
6853 typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
6854 DIG_FIFO_USE_OVERWRITE_LEVEL             = 0x00000000,
6855 DIG_FIFO_USE_CAL_AVERAGE_LEVEL           = 0x00000001,
6856 } DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
6857 
6858 /*
6859  * DIG_FIFO_ERROR_ACK enum
6860  */
6861 
6862 typedef enum DIG_FIFO_ERROR_ACK {
6863 DIG_FIFO_ERROR_ACK_INT                   = 0x00000000,
6864 DIG_FIFO_ERROR_NOT_ACK                   = 0x00000001,
6865 } DIG_FIFO_ERROR_ACK;
6866 
6867 /*
6868  * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
6869  */
6870 
6871 typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
6872 DIG_FIFO_NOT_FORCE_RECAL_AVERAGE         = 0x00000000,
6873 DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL       = 0x00000001,
6874 } DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
6875 
6876 /*
6877  * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
6878  */
6879 
6880 typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
6881 DIG_FIFO_NOT_FORCE_RECOMP_MINMAX         = 0x00000000,
6882 DIG_FIFO_FORCE_RECOMP_MINMAX             = 0x00000001,
6883 } DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
6884 
6885 /*
6886  * AFMT_INTERRUPT_STATUS_CHG_MASK enum
6887  */
6888 
6889 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
6890 AFMT_INTERRUPT_DISABLE                   = 0x00000000,
6891 AFMT_INTERRUPT_ENABLE                    = 0x00000001,
6892 } AFMT_INTERRUPT_STATUS_CHG_MASK;
6893 
6894 /*
6895  * HDMI_GC_AVMUTE enum
6896  */
6897 
6898 typedef enum HDMI_GC_AVMUTE {
6899 HDMI_GC_AVMUTE_SET                       = 0x00000000,
6900 HDMI_GC_AVMUTE_UNSET                     = 0x00000001,
6901 } HDMI_GC_AVMUTE;
6902 
6903 /*
6904  * HDMI_DEFAULT_PAHSE enum
6905  */
6906 
6907 typedef enum HDMI_DEFAULT_PAHSE {
6908 HDMI_DEFAULT_PHASE_IS_0                  = 0x00000000,
6909 HDMI_DEFAULT_PHASE_IS_1                  = 0x00000001,
6910 } HDMI_DEFAULT_PAHSE;
6911 
6912 /*
6913  * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
6914  */
6915 
6916 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
6917 AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS  = 0x00000000,
6918 AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER       = 0x00000001,
6919 } AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
6920 
6921 /*
6922  * AUDIO_LAYOUT_SELECT enum
6923  */
6924 
6925 typedef enum AUDIO_LAYOUT_SELECT {
6926 AUDIO_LAYOUT_0                           = 0x00000000,
6927 AUDIO_LAYOUT_1                           = 0x00000001,
6928 } AUDIO_LAYOUT_SELECT;
6929 
6930 /*
6931  * AFMT_AUDIO_CRC_CONTROL_CONT enum
6932  */
6933 
6934 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
6935 AFMT_AUDIO_CRC_ONESHOT                   = 0x00000000,
6936 AFMT_AUDIO_CRC_AUTO_RESTART              = 0x00000001,
6937 } AFMT_AUDIO_CRC_CONTROL_CONT;
6938 
6939 /*
6940  * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
6941  */
6942 
6943 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
6944 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT    = 0x00000000,
6945 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT   = 0x00000001,
6946 } AFMT_AUDIO_CRC_CONTROL_SOURCE;
6947 
6948 /*
6949  * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
6950  */
6951 
6952 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
6953 AFMT_AUDIO_CRC_CH0_SIG                   = 0x00000000,
6954 AFMT_AUDIO_CRC_CH1_SIG                   = 0x00000001,
6955 AFMT_AUDIO_CRC_CH2_SIG                   = 0x00000002,
6956 AFMT_AUDIO_CRC_CH3_SIG                   = 0x00000003,
6957 AFMT_AUDIO_CRC_CH4_SIG                   = 0x00000004,
6958 AFMT_AUDIO_CRC_CH5_SIG                   = 0x00000005,
6959 AFMT_AUDIO_CRC_CH6_SIG                   = 0x00000006,
6960 AFMT_AUDIO_CRC_CH7_SIG                   = 0x00000007,
6961 AFMT_AUDIO_CRC_RESERVED_8                = 0x00000008,
6962 AFMT_AUDIO_CRC_RESERVED_9                = 0x00000009,
6963 AFMT_AUDIO_CRC_RESERVED_10               = 0x0000000a,
6964 AFMT_AUDIO_CRC_RESERVED_11               = 0x0000000b,
6965 AFMT_AUDIO_CRC_RESERVED_12               = 0x0000000c,
6966 AFMT_AUDIO_CRC_RESERVED_13               = 0x0000000d,
6967 AFMT_AUDIO_CRC_RESERVED_14               = 0x0000000e,
6968 AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT        = 0x0000000f,
6969 } AFMT_AUDIO_CRC_CONTROL_CH_SEL;
6970 
6971 /*
6972  * AFMT_RAMP_CONTROL0_SIGN enum
6973  */
6974 
6975 typedef enum AFMT_RAMP_CONTROL0_SIGN {
6976 AFMT_RAMP_SIGNED                         = 0x00000000,
6977 AFMT_RAMP_UNSIGNED                       = 0x00000001,
6978 } AFMT_RAMP_CONTROL0_SIGN;
6979 
6980 /*
6981  * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
6982  */
6983 
6984 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
6985 AFMT_AUDIO_PACKET_SENT_DISABLED          = 0x00000000,
6986 AFMT_AUDIO_PACKET_SENT_ENABLED           = 0x00000001,
6987 } AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
6988 
6989 /*
6990  * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
6991  */
6992 
6993 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
6994 AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED  = 0x00000000,
6995 AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED  = 0x00000001,
6996 } AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
6997 
6998 /*
6999  * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
7000  */
7001 
7002 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
7003 AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK  = 0x00000000,
7004 AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS  = 0x00000001,
7005 } AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
7006 
7007 /*
7008  * AFMT_AUDIO_SRC_CONTROL_SELECT enum
7009  */
7010 
7011 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
7012 AFMT_AUDIO_SRC_FROM_AZ_STREAM0           = 0x00000000,
7013 AFMT_AUDIO_SRC_FROM_AZ_STREAM1           = 0x00000001,
7014 AFMT_AUDIO_SRC_FROM_AZ_STREAM2           = 0x00000002,
7015 AFMT_AUDIO_SRC_FROM_AZ_STREAM3           = 0x00000003,
7016 AFMT_AUDIO_SRC_FROM_AZ_STREAM4           = 0x00000004,
7017 AFMT_AUDIO_SRC_FROM_AZ_STREAM5           = 0x00000005,
7018 AFMT_AUDIO_SRC_RESERVED                  = 0x00000006,
7019 } AFMT_AUDIO_SRC_CONTROL_SELECT;
7020 
7021 /*
7022  * DIG_BE_CNTL_MODE enum
7023  */
7024 
7025 typedef enum DIG_BE_CNTL_MODE {
7026 DIG_BE_DP_SST_MODE                       = 0x00000000,
7027 DIG_BE_RESERVED1                         = 0x00000001,
7028 DIG_BE_TMDS_DVI_MODE                     = 0x00000002,
7029 DIG_BE_TMDS_HDMI_MODE                    = 0x00000003,
7030 DIG_BE_RESERVED4                         = 0x00000004,
7031 DIG_BE_DP_MST_MODE                       = 0x00000005,
7032 DIG_BE_RESERVED2                         = 0x00000006,
7033 DIG_BE_RESERVED3                         = 0x00000007,
7034 } DIG_BE_CNTL_MODE;
7035 
7036 /*
7037  * DIG_BE_CNTL_HPD_SELECT enum
7038  */
7039 
7040 typedef enum DIG_BE_CNTL_HPD_SELECT {
7041 DIG_BE_CNTL_HPD1                         = 0x00000000,
7042 DIG_BE_CNTL_HPD2                         = 0x00000001,
7043 DIG_BE_CNTL_HPD3                         = 0x00000002,
7044 DIG_BE_CNTL_HPD4                         = 0x00000003,
7045 DIG_BE_CNTL_HPD5                         = 0x00000004,
7046 DIG_BE_CNTL_HPD6                         = 0x00000005,
7047 DIG_BE_CNTL_NO_HPD                       = 0x00000006,
7048 } DIG_BE_CNTL_HPD_SELECT;
7049 
7050 /*
7051  * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
7052  */
7053 
7054 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
7055 LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS     = 0x00000000,
7056 LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH   = 0x00000001,
7057 } LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
7058 
7059 /*
7060  * TMDS_SYNC_PHASE enum
7061  */
7062 
7063 typedef enum TMDS_SYNC_PHASE {
7064 TMDS_NOT_SYNC_PHASE_ON_FRAME_START       = 0x00000000,
7065 TMDS_SYNC_PHASE_ON_FRAME_START           = 0x00000001,
7066 } TMDS_SYNC_PHASE;
7067 
7068 /*
7069  * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
7070  */
7071 
7072 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
7073 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS  = 0x00000000,
7074 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL  = 0x00000001,
7075 } TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
7076 
7077 /*
7078  * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
7079  */
7080 
7081 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
7082 TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE   = 0x00000000,
7083 TMDS_TRANSMITTER_HPD_MASK_OVERRIDE       = 0x00000001,
7084 } TMDS_TRANSMITTER_ENABLE_HPD_MASK;
7085 
7086 /*
7087  * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
7088  */
7089 
7090 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
7091 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
7092 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE  = 0x00000001,
7093 } TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
7094 
7095 /*
7096  * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
7097  */
7098 
7099 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
7100 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
7101 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE  = 0x00000001,
7102 } TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
7103 
7104 /*
7105  * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
7106  */
7107 
7108 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
7109 TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE  = 0x00000000,
7110 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON  = 0x00000001,
7111 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x00000002,
7112 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE  = 0x00000003,
7113 } TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
7114 
7115 /*
7116  * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
7117  */
7118 
7119 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
7120 TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK   = 0x00000000,
7121 TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK     = 0x00000001,
7122 } TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
7123 
7124 /*
7125  * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
7126  */
7127 
7128 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
7129 TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK   = 0x00000000,
7130 TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK     = 0x00000001,
7131 } TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
7132 
7133 /*
7134  * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
7135  */
7136 
7137 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
7138 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE   = 0x00000000,
7139 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE    = 0x00000001,
7140 } TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
7141 
7142 /*
7143  * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
7144  */
7145 
7146 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
7147 TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD      = 0x00000000,
7148 TMDS_TRANSMITTER_PLL_RST_ON_HPD          = 0x00000001,
7149 } TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
7150 
7151 /*
7152  * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
7153  */
7154 
7155 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
7156 TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK   = 0x00000000,
7157 TMDS_TRANSMITTER_TMCLK_FROM_PADS         = 0x00000001,
7158 } TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
7159 
7160 /*
7161  * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
7162  */
7163 
7164 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
7165 TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK   = 0x00000000,
7166 TMDS_TRANSMITTER_TDCLK_FROM_PADS         = 0x00000001,
7167 } TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
7168 
7169 /*
7170  * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
7171  */
7172 
7173 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
7174 TMDS_TRANSMITTER_PLLSEL_BY_HW            = 0x00000000,
7175 TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW  = 0x00000001,
7176 } TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
7177 
7178 /*
7179  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
7180  */
7181 
7182 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
7183 TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT    = 0x00000000,
7184 TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT  = 0x00000001,
7185 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
7186 
7187 /*
7188  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
7189  */
7190 
7191 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
7192 TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT    = 0x00000000,
7193 TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT  = 0x00000001,
7194 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
7195 
7196 /*
7197  * TMDS_REG_TEST_OUTPUTA_CNTLA enum
7198  */
7199 
7200 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
7201 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0      = 0x00000000,
7202 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1      = 0x00000001,
7203 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2      = 0x00000002,
7204 TMDS_REG_TEST_OUTPUTA_CNTLA_NA           = 0x00000003,
7205 } TMDS_REG_TEST_OUTPUTA_CNTLA;
7206 
7207 /*
7208  * TMDS_REG_TEST_OUTPUTB_CNTLB enum
7209  */
7210 
7211 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
7212 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0      = 0x00000000,
7213 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1      = 0x00000001,
7214 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2      = 0x00000002,
7215 TMDS_REG_TEST_OUTPUTB_CNTLB_NA           = 0x00000003,
7216 } TMDS_REG_TEST_OUTPUTB_CNTLB;
7217 
7218 /*
7219  * AFMT_VBI_GSP_INDEX enum
7220  */
7221 
7222 typedef enum AFMT_VBI_GSP_INDEX {
7223 AFMT_VBI_GSP0_INDEX                      = 0x00000000,
7224 AFMT_VBI_GSP1_INDEX                      = 0x00000001,
7225 AFMT_VBI_GSP2_INDEX                      = 0x00000002,
7226 AFMT_VBI_GSP3_INDEX                      = 0x00000003,
7227 AFMT_VBI_GSP4_INDEX                      = 0x00000004,
7228 AFMT_VBI_GSP5_INDEX                      = 0x00000005,
7229 AFMT_VBI_GSP6_INDEX                      = 0x00000006,
7230 AFMT_VBI_GSP7_INDEX                      = 0x00000007,
7231 AFMT_VBI_GSP8_INDEX                      = 0x00000008,
7232 AFMT_VBI_GSP9_INDEX                      = 0x00000009,
7233 AFMT_VBI_GSP10_INDEX                     = 0x0000000a,
7234 } AFMT_VBI_GSP_INDEX;
7235 
7236 /*
7237  * DIG_DIGITAL_BYPASS_SEL enum
7238  */
7239 
7240 typedef enum DIG_DIGITAL_BYPASS_SEL {
7241 DIG_DIGITAL_BYPASS_SEL_BYPASS            = 0x00000000,
7242 DIG_DIGITAL_BYPASS_SEL_36BPP             = 0x00000001,
7243 DIG_DIGITAL_BYPASS_SEL_48BPP_LSB         = 0x00000002,
7244 DIG_DIGITAL_BYPASS_SEL_48BPP_MSB         = 0x00000003,
7245 DIG_DIGITAL_BYPASS_SEL_10BPP_LSB         = 0x00000004,
7246 DIG_DIGITAL_BYPASS_SEL_12BPC_LSB         = 0x00000005,
7247 DIG_DIGITAL_BYPASS_SEL_ALPHA             = 0x00000006,
7248 } DIG_DIGITAL_BYPASS_SEL;
7249 
7250 /*
7251  * DIG_INPUT_PIXEL_SEL enum
7252  */
7253 
7254 typedef enum DIG_INPUT_PIXEL_SEL {
7255 DIG_ALL_PIXEL                            = 0x00000000,
7256 DIG_EVEN_PIXEL_ONLY                      = 0x00000001,
7257 DIG_ODD_PIXEL_ONLY                       = 0x00000002,
7258 } DIG_INPUT_PIXEL_SEL;
7259 
7260 /*
7261  * DOLBY_VISION_ENABLE enum
7262  */
7263 
7264 typedef enum DOLBY_VISION_ENABLE {
7265 DOLBY_VISION_ENABLED                     = 0x00000000,
7266 DOLBY_VISION_DISABLED                    = 0x00000001,
7267 } DOLBY_VISION_ENABLE;
7268 
7269 /*
7270  * METADATA_HUBP_SEL enum
7271  */
7272 
7273 typedef enum METADATA_HUBP_SEL {
7274 METADATA_HUBP_SEL_0                      = 0x00000000,
7275 METADATA_HUBP_SEL_1                      = 0x00000001,
7276 METADATA_HUBP_SEL_2                      = 0x00000002,
7277 METADATA_HUBP_SEL_3                      = 0x00000003,
7278 METADATA_HUBP_SEL_4                      = 0x00000004,
7279 METADATA_HUBP_SEL_5                      = 0x00000005,
7280 METADATA_HUBP_SEL_RESERVED               = 0x00000006,
7281 } METADATA_HUBP_SEL;
7282 
7283 /*
7284  * METADATA_STREAM_TYPE_SEL enum
7285  */
7286 
7287 typedef enum METADATA_STREAM_TYPE_SEL {
7288 METADATA_STREAM_DP                       = 0x00000000,
7289 METADATA_STREAM_DVE                      = 0x00000001,
7290 } METADATA_STREAM_TYPE_SEL;
7291 
7292 /*
7293  * HDMI_METADATA_ENABLE enum
7294  */
7295 
7296 typedef enum HDMI_METADATA_ENABLE {
7297 HDMI_METADATA_NOT_SEND                   = 0x00000000,
7298 HDMI_METADATA_PKT_SEND                   = 0x00000001,
7299 } HDMI_METADATA_ENABLE;
7300 
7301 /*
7302  * HDMI_PACKET_LINE_REFERENCE enum
7303  */
7304 
7305 typedef enum HDMI_PACKET_LINE_REFERENCE {
7306 HDMI_PKT_LINE_REF_VSYNC                  = 0x00000000,
7307 HDMI_PKT_LINE_REF_OTGSOF                 = 0x00000001,
7308 } HDMI_PACKET_LINE_REFERENCE;
7309 
7310 /*******************************************************
7311  * DP_AUX Enums
7312  *******************************************************/
7313 
7314 /*
7315  * DP_AUX_CONTROL_HPD_SEL enum
7316  */
7317 
7318 typedef enum DP_AUX_CONTROL_HPD_SEL {
7319 DP_AUX_CONTROL_HPD1_SELECTED             = 0x00000000,
7320 DP_AUX_CONTROL_HPD2_SELECTED             = 0x00000001,
7321 DP_AUX_CONTROL_HPD3_SELECTED             = 0x00000002,
7322 DP_AUX_CONTROL_HPD4_SELECTED             = 0x00000003,
7323 DP_AUX_CONTROL_HPD5_SELECTED             = 0x00000004,
7324 DP_AUX_CONTROL_HPD6_SELECTED             = 0x00000005,
7325 DP_AUX_CONTROL_NO_HPD_SELECTED           = 0x00000006,
7326 } DP_AUX_CONTROL_HPD_SEL;
7327 
7328 /*
7329  * DP_AUX_CONTROL_TEST_MODE enum
7330  */
7331 
7332 typedef enum DP_AUX_CONTROL_TEST_MODE {
7333 DP_AUX_CONTROL_TEST_MODE_DISABLE         = 0x00000000,
7334 DP_AUX_CONTROL_TEST_MODE_ENABLE          = 0x00000001,
7335 } DP_AUX_CONTROL_TEST_MODE;
7336 
7337 /*
7338  * DP_AUX_SW_CONTROL_SW_GO enum
7339  */
7340 
7341 typedef enum DP_AUX_SW_CONTROL_SW_GO {
7342 DP_AUX_SW_CONTROL_SW__NOT_GO             = 0x00000000,
7343 DP_AUX_SW_CONTROL_SW__GO                 = 0x00000001,
7344 } DP_AUX_SW_CONTROL_SW_GO;
7345 
7346 /*
7347  * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
7348  */
7349 
7350 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
7351 DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG      = 0x00000000,
7352 DP_AUX_SW_CONTROL_LS_READ__TRIG          = 0x00000001,
7353 } DP_AUX_SW_CONTROL_LS_READ_TRIG;
7354 
7355 /*
7356  * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
7357  */
7358 
7359 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
7360 DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW  = 0x00000000,
7361 DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW  = 0x00000001,
7362 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC  = 0x00000002,
7363 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS  = 0x00000003,
7364 } DP_AUX_ARB_CONTROL_ARB_PRIORITY;
7365 
7366 /*
7367  * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
7368  */
7369 
7370 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
7371 DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ  = 0x00000000,
7372 DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ      = 0x00000001,
7373 } DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
7374 
7375 /*
7376  * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
7377  */
7378 
7379 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
7380 DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
7381 DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG   = 0x00000001,
7382 } DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
7383 
7384 /*
7385  * DP_AUX_INT_ACK enum
7386  */
7387 
7388 typedef enum DP_AUX_INT_ACK {
7389 DP_AUX_INT__NOT_ACK                      = 0x00000000,
7390 DP_AUX_INT__ACK                          = 0x00000001,
7391 } DP_AUX_INT_ACK;
7392 
7393 /*
7394  * DP_AUX_LS_UPDATE_ACK enum
7395  */
7396 
7397 typedef enum DP_AUX_LS_UPDATE_ACK {
7398 DP_AUX_INT_LS_UPDATE_NOT_ACK             = 0x00000000,
7399 DP_AUX_INT_LS_UPDATE_ACK                 = 0x00000001,
7400 } DP_AUX_LS_UPDATE_ACK;
7401 
7402 /*
7403  * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
7404  */
7405 
7406 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
7407 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK  = 0x00000000,
7408 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF  = 0x00000001,
7409 } DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
7410 
7411 /*
7412  * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
7413  */
7414 
7415 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
7416 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
7417 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
7418 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
7419 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
7420 } DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
7421 
7422 /*
7423  * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
7424  */
7425 
7426 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
7427 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
7428 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
7429 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
7430 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
7431 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
7432 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
7433 } DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
7434 
7435 /*
7436  * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
7437  */
7438 
7439 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
7440 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD  = 0x00000000,
7441 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD  = 0x00000001,
7442 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD  = 0x00000002,
7443 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD  = 0x00000003,
7444 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD  = 0x00000004,
7445 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD  = 0x00000005,
7446 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD  = 0x00000006,
7447 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD  = 0x00000007,
7448 } DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
7449 
7450 /*
7451  * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
7452  */
7453 
7454 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
7455 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD  = 0x00000000,
7456 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD  = 0x00000001,
7457 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD  = 0x00000002,
7458 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD  = 0x00000003,
7459 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD  = 0x00000004,
7460 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD  = 0x00000005,
7461 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD  = 0x00000006,
7462 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD  = 0x00000007,
7463 } DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
7464 
7465 /*
7466  * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
7467  */
7468 
7469 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
7470 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
7471 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
7472 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
7473 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
7474 } DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
7475 
7476 /*
7477  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
7478  */
7479 
7480 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
7481 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
7482 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
7483 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
7484 
7485 /*
7486  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
7487  */
7488 
7489 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
7490 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
7491 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
7492 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
7493 
7494 /*
7495  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
7496  */
7497 
7498 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
7499 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
7500 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
7501 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
7502 
7503 /*
7504  * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
7505  */
7506 
7507 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
7508 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
7509 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
7510 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
7511 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
7512 } DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
7513 
7514 /*
7515  * DP_AUX_RX_TIMEOUT_LEN_MUL enum
7516  */
7517 
7518 typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
7519 DP_AUX_RX_TIMEOUT_LEN_NO_MUL             = 0x00000000,
7520 DP_AUX_RX_TIMEOUT_LEN_MUL_2              = 0x00000001,
7521 DP_AUX_RX_TIMEOUT_LEN_MUL_4              = 0x00000002,
7522 DP_AUX_RX_TIMEOUT_LEN_MUL_8              = 0x00000003,
7523 } DP_AUX_RX_TIMEOUT_LEN_MUL;
7524 
7525 /*
7526  * DP_AUX_TX_PRECHARGE_LEN_MUL enum
7527  */
7528 
7529 typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
7530 DP_AUX_TX_PRECHARGE_LEN_NO_MUL           = 0x00000000,
7531 DP_AUX_TX_PRECHARGE_LEN_MUL_2            = 0x00000001,
7532 DP_AUX_TX_PRECHARGE_LEN_MUL_4            = 0x00000002,
7533 DP_AUX_TX_PRECHARGE_LEN_MUL_8            = 0x00000003,
7534 } DP_AUX_TX_PRECHARGE_LEN_MUL;
7535 
7536 /*
7537  * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
7538  */
7539 
7540 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
7541 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2  = 0x00000000,
7542 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4  = 0x00000001,
7543 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8  = 0x00000002,
7544 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16  = 0x00000003,
7545 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32  = 0x00000004,
7546 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64  = 0x00000005,
7547 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128  = 0x00000006,
7548 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256  = 0x00000007,
7549 } DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
7550 
7551 /*
7552  * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
7553  */
7554 
7555 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
7556 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX  = 0x00000000,
7557 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX  = 0x00000001,
7558 } DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
7559 
7560 /*
7561  * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
7562  */
7563 
7564 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
7565 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
7566 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
7567 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
7568 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
7569 } DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
7570 
7571 /*
7572  * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
7573  */
7574 
7575 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
7576 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
7577 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
7578 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
7579 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
7580 } DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
7581 
7582 /*
7583  * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
7584  */
7585 
7586 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
7587 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0  = 0x00000000,
7588 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64  = 0x00000001,
7589 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128  = 0x00000002,
7590 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256  = 0x00000003,
7591 } DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
7592 
7593 /*
7594  * DP_AUX_ERR_OCCURRED_ACK enum
7595  */
7596 
7597 typedef enum DP_AUX_ERR_OCCURRED_ACK {
7598 DP_AUX_ERR_OCCURRED__NOT_ACK             = 0x00000000,
7599 DP_AUX_ERR_OCCURRED__ACK                 = 0x00000001,
7600 } DP_AUX_ERR_OCCURRED_ACK;
7601 
7602 /*
7603  * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
7604  */
7605 
7606 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
7607 DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK    = 0x00000000,
7608 DP_AUX_POTENTIAL_ERR_REACHED__ACK        = 0x00000001,
7609 } DP_AUX_POTENTIAL_ERR_REACHED_ACK;
7610 
7611 /*
7612  * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
7613  */
7614 
7615 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
7616 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
7617 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK    = 0x00000001,
7618 } DP_AUX_DEFINITE_ERR_REACHED_ACK;
7619 
7620 /*
7621  * DP_AUX_RESET enum
7622  */
7623 
7624 typedef enum DP_AUX_RESET {
7625 DP_AUX_RESET_DEASSERTED                  = 0x00000000,
7626 DP_AUX_RESET_ASSERTED                    = 0x00000001,
7627 } DP_AUX_RESET;
7628 
7629 /*
7630  * DP_AUX_RESET_DONE enum
7631  */
7632 
7633 typedef enum DP_AUX_RESET_DONE {
7634 DP_AUX_RESET_SEQUENCE_NOT_DONE           = 0x00000000,
7635 DP_AUX_RESET_SEQUENCE_DONE               = 0x00000001,
7636 } DP_AUX_RESET_DONE;
7637 
7638 /*
7639  * DP_AUX_PHY_WAKE_PRIORITY enum
7640  */
7641 
7642 typedef enum DP_AUX_PHY_WAKE_PRIORITY {
7643 DP_AUX_PHY_WAKE_HIGH_PRIORITY            = 0x00000000,
7644 DP_AUX_PHY_WAKE_LOW_PRIORITY             = 0x00000001,
7645 } DP_AUX_PHY_WAKE_PRIORITY;
7646 
7647 /*******************************************************
7648  * DOUT_I2C Enums
7649  *******************************************************/
7650 
7651 /*
7652  * DOUT_I2C_CONTROL_GO enum
7653  */
7654 
7655 typedef enum DOUT_I2C_CONTROL_GO {
7656 DOUT_I2C_CONTROL_STOP_TRANSFER           = 0x00000000,
7657 DOUT_I2C_CONTROL_START_TRANSFER          = 0x00000001,
7658 } DOUT_I2C_CONTROL_GO;
7659 
7660 /*
7661  * DOUT_I2C_CONTROL_SOFT_RESET enum
7662  */
7663 
7664 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
7665 DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
7666 DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER    = 0x00000001,
7667 } DOUT_I2C_CONTROL_SOFT_RESET;
7668 
7669 /*
7670  * DOUT_I2C_CONTROL_SEND_RESET enum
7671  */
7672 
7673 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
7674 DOUT_I2C_CONTROL__NOT_SEND_RESET         = 0x00000000,
7675 DOUT_I2C_CONTROL__SEND_RESET             = 0x00000001,
7676 } DOUT_I2C_CONTROL_SEND_RESET;
7677 
7678 /*
7679  * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
7680  */
7681 
7682 typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
7683 DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9    = 0x00000000,
7684 DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10   = 0x00000001,
7685 } DOUT_I2C_CONTROL_SEND_RESET_LENGTH;
7686 
7687 /*
7688  * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
7689  */
7690 
7691 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
7692 DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS     = 0x00000000,
7693 DOUT_I2C_CONTROL_RESET_SW_STATUS         = 0x00000001,
7694 } DOUT_I2C_CONTROL_SW_STATUS_RESET;
7695 
7696 /*
7697  * DOUT_I2C_CONTROL_DDC_SELECT enum
7698  */
7699 
7700 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
7701 DOUT_I2C_CONTROL_SELECT_DDC1             = 0x00000000,
7702 DOUT_I2C_CONTROL_SELECT_DDC2             = 0x00000001,
7703 DOUT_I2C_CONTROL_SELECT_DDC3             = 0x00000002,
7704 DOUT_I2C_CONTROL_SELECT_DDC4             = 0x00000003,
7705 DOUT_I2C_CONTROL_SELECT_DDC5             = 0x00000004,
7706 DOUT_I2C_CONTROL_SELECT_DDC6             = 0x00000005,
7707 DOUT_I2C_CONTROL_SELECT_DDCVGA           = 0x00000006,
7708 } DOUT_I2C_CONTROL_DDC_SELECT;
7709 
7710 /*
7711  * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
7712  */
7713 
7714 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
7715 DOUT_I2C_CONTROL_TRANS0                  = 0x00000000,
7716 DOUT_I2C_CONTROL_TRANS0_TRANS1           = 0x00000001,
7717 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2    = 0x00000002,
7718 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3  = 0x00000003,
7719 } DOUT_I2C_CONTROL_TRANSACTION_COUNT;
7720 
7721 /*
7722  * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
7723  */
7724 
7725 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
7726 DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL  = 0x00000000,
7727 DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH    = 0x00000001,
7728 DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
7729 DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
7730 } DOUT_I2C_ARBITRATION_SW_PRIORITY;
7731 
7732 /*
7733  * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
7734  */
7735 
7736 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
7737 DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED    = 0x00000000,
7738 DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED   = 0x00000001,
7739 } DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
7740 
7741 /*
7742  * DOUT_I2C_ARBITRATION_ABORT_XFER enum
7743  */
7744 
7745 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
7746 DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
7747 DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER  = 0x00000001,
7748 } DOUT_I2C_ARBITRATION_ABORT_XFER;
7749 
7750 /*
7751  * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
7752  */
7753 
7754 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
7755 DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
7756 DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ    = 0x00000001,
7757 } DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
7758 
7759 /*
7760  * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
7761  */
7762 
7763 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
7764 DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
7765 DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG  = 0x00000001,
7766 } DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
7767 
7768 /*
7769  * DOUT_I2C_ACK enum
7770  */
7771 
7772 typedef enum DOUT_I2C_ACK {
7773 DOUT_I2C_NO_ACK                          = 0x00000000,
7774 DOUT_I2C_ACK_TO_CLEAN                    = 0x00000001,
7775 } DOUT_I2C_ACK;
7776 
7777 /*
7778  * DOUT_I2C_DDC_SPEED_THRESHOLD enum
7779  */
7780 
7781 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
7782 DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO  = 0x00000000,
7783 DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE  = 0x00000001,
7784 DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE  = 0x00000002,
7785 DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE  = 0x00000003,
7786 } DOUT_I2C_DDC_SPEED_THRESHOLD;
7787 
7788 /*
7789  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
7790  */
7791 
7792 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
7793 DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
7794 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA     = 0x00000001,
7795 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
7796 
7797 /*
7798  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
7799  */
7800 
7801 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
7802 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS  = 0x00000000,
7803 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS  = 0x00000001,
7804 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
7805 
7806 /*
7807  * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
7808  */
7809 
7810 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
7811 DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT   = 0x00000000,
7812 DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT  = 0x00000001,
7813 } DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
7814 
7815 /*
7816  * DOUT_I2C_DDC_EDID_DETECT_STATUS enum
7817  */
7818 
7819 typedef enum DOUT_I2C_DDC_EDID_DETECT_STATUS {
7820 DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED  = 0x00000000,
7821 DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED  = 0x00000001,
7822 } DOUT_I2C_DDC_EDID_DETECT_STATUS;
7823 
7824 /*
7825  * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
7826  */
7827 
7828 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
7829 DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
7830 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL     = 0x00000001,
7831 } DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
7832 
7833 /*
7834  * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
7835  */
7836 
7837 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
7838 DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS  = 0x00000000,
7839 DOUT_I2C_TRANSACTION_STOP_ALL_TRANS      = 0x00000001,
7840 } DOUT_I2C_TRANSACTION_STOP_ON_NACK;
7841 
7842 /*
7843  * DOUT_I2C_DATA_INDEX_WRITE enum
7844  */
7845 
7846 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
7847 DOUT_I2C_DATA__NOT_INDEX_WRITE           = 0x00000000,
7848 DOUT_I2C_DATA__INDEX_WRITE               = 0x00000001,
7849 } DOUT_I2C_DATA_INDEX_WRITE;
7850 
7851 /*
7852  * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
7853  */
7854 
7855 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
7856 DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
7857 DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION  = 0x00000001,
7858 } DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
7859 
7860 /*
7861  * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
7862  */
7863 
7864 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
7865 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL  = 0x00000000,
7866 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE  = 0x00000001,
7867 } DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
7868 
7869 /*******************************************************
7870  * DIO_MISC Enums
7871  *******************************************************/
7872 
7873 /*
7874  * DIOMEM_PWR_FORCE_CTRL enum
7875  */
7876 
7877 typedef enum DIOMEM_PWR_FORCE_CTRL {
7878 DIOMEM_NO_FORCE_REQUEST                  = 0x00000000,
7879 DIOMEM_FORCE_LIGHT_SLEEP_REQUEST         = 0x00000001,
7880 DIOMEM_FORCE_DEEP_SLEEP_REQUEST          = 0x00000002,
7881 DIOMEM_FORCE_SHUT_DOWN_REQUEST           = 0x00000003,
7882 } DIOMEM_PWR_FORCE_CTRL;
7883 
7884 /*
7885  * DIOMEM_PWR_FORCE_CTRL2 enum
7886  */
7887 
7888 typedef enum DIOMEM_PWR_FORCE_CTRL2 {
7889 DIOMEM_NO_FORCE_REQ                      = 0x00000000,
7890 DIOMEM_FORCE_LIGHT_SLEEP_REQ             = 0x00000001,
7891 } DIOMEM_PWR_FORCE_CTRL2;
7892 
7893 /*
7894  * DIOMEM_PWR_DIS_CTRL enum
7895  */
7896 
7897 typedef enum DIOMEM_PWR_DIS_CTRL {
7898 DIOMEM_ENABLE_MEM_PWR_CTRL               = 0x00000000,
7899 DIOMEM_DISABLE_MEM_PWR_CTRL              = 0x00000001,
7900 } DIOMEM_PWR_DIS_CTRL;
7901 
7902 /*
7903  * CLOCK_GATING_EN enum
7904  */
7905 
7906 typedef enum CLOCK_GATING_EN {
7907 CLOCK_GATING_ENABLE                      = 0x00000000,
7908 CLOCK_GATING_DISABLE                     = 0x00000001,
7909 } CLOCK_GATING_EN;
7910 
7911 /*
7912  * DIOMEM_PWR_SEL_CTRL enum
7913  */
7914 
7915 typedef enum DIOMEM_PWR_SEL_CTRL {
7916 DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE          = 0x00000000,
7917 DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE         = 0x00000001,
7918 DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE        = 0x00000002,
7919 } DIOMEM_PWR_SEL_CTRL;
7920 
7921 /*
7922  * DIOMEM_PWR_SEL_CTRL2 enum
7923  */
7924 
7925 typedef enum DIOMEM_PWR_SEL_CTRL2 {
7926 DIOMEM_DYNAMIC_DEEP_SLEEP_EN             = 0x00000000,
7927 DIOMEM_DYNAMIC_LIGHT_SLEEP_EN            = 0x00000001,
7928 } DIOMEM_PWR_SEL_CTRL2;
7929 
7930 /*
7931  * PM_ASSERT_RESET enum
7932  */
7933 
7934 typedef enum PM_ASSERT_RESET {
7935 PM_ASSERT_RESET_0                        = 0x00000000,
7936 PM_ASSERT_RESET_1                        = 0x00000001,
7937 } PM_ASSERT_RESET;
7938 
7939 /*
7940  * DAC_MUX_SELECT enum
7941  */
7942 
7943 typedef enum DAC_MUX_SELECT {
7944 DAC_MUX_SELECT_DACA                      = 0x00000000,
7945 DAC_MUX_SELECT_DACB                      = 0x00000001,
7946 } DAC_MUX_SELECT;
7947 
7948 /*
7949  * TMDS_MUX_SELECT enum
7950  */
7951 
7952 typedef enum TMDS_MUX_SELECT {
7953 TMDS_MUX_SELECT_B                        = 0x00000000,
7954 TMDS_MUX_SELECT_G                        = 0x00000001,
7955 TMDS_MUX_SELECT_R                        = 0x00000002,
7956 TMDS_MUX_SELECT_RESERVED                 = 0x00000003,
7957 } TMDS_MUX_SELECT;
7958 
7959 /*
7960  * SOFT_RESET enum
7961  */
7962 
7963 typedef enum SOFT_RESET {
7964 SOFT_RESET_0                             = 0x00000000,
7965 SOFT_RESET_1                             = 0x00000001,
7966 } SOFT_RESET;
7967 
7968 /*
7969  * GENERIC_STEREOSYNC_SEL enum
7970  */
7971 
7972 typedef enum GENERIC_STEREOSYNC_SEL {
7973 GENERIC_STEREOSYNC_SEL_D1                = 0x00000000,
7974 GENERIC_STEREOSYNC_SEL_D2                = 0x00000001,
7975 GENERIC_STEREOSYNC_SEL_D3                = 0x00000002,
7976 GENERIC_STEREOSYNC_SEL_D4                = 0x00000003,
7977 GENERIC_STEREOSYNC_SEL_D5                = 0x00000004,
7978 GENERIC_STEREOSYNC_SEL_D6                = 0x00000005,
7979 GENERIC_STEREOSYNC_SEL_RESERVED          = 0x00000006,
7980 } GENERIC_STEREOSYNC_SEL;
7981 
7982 /*
7983  * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
7984  */
7985 
7986 typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
7987 DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL       = 0x00000000,
7988 DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE       = 0x00000001,
7989 } DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE;
7990 
7991 /*
7992  * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum
7993  */
7994 
7995 typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE {
7996 DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0  = 0x00000000,
7997 DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1  = 0x00000001,
7998 } DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE;
7999 
8000 /*******************************************************
8001  * DCIO Enums
8002  *******************************************************/
8003 
8004 /*
8005  * DCIO_DC_GENERICA_SEL enum
8006  */
8007 
8008 typedef enum DCIO_DC_GENERICA_SEL {
8009 DCIO_GENERICA_SEL_DACA_STEREOSYNC        = 0x00000000,
8010 DCIO_GENERICA_SEL_STEREOSYNC             = 0x00000001,
8011 DCIO_GENERICA_SEL_DACA_PIXCLK            = 0x00000002,
8012 DCIO_GENERICA_SEL_DACB_PIXCLK            = 0x00000003,
8013 DCIO_GENERICA_SEL_DVOA_CTL3              = 0x00000004,
8014 DCIO_GENERICA_SEL_P1_PLLCLK              = 0x00000005,
8015 DCIO_GENERICA_SEL_P2_PLLCLK              = 0x00000006,
8016 DCIO_GENERICA_SEL_DVOA_STEREOSYNC        = 0x00000007,
8017 DCIO_GENERICA_SEL_DACA_FIELD_NUMBER      = 0x00000008,
8018 DCIO_GENERICA_SEL_DACB_FIELD_NUMBER      = 0x00000009,
8019 DCIO_GENERICA_SEL_GENERICA_DCCG          = 0x0000000a,
8020 DCIO_GENERICA_SEL_SYNCEN                 = 0x0000000b,
8021 DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
8022 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
8023 DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
8024 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
8025 DCIO_GENERICA_SEL_GENERICA_DPRX          = 0x00000010,
8026 DCIO_GENERICA_SEL_GENERICB_DPRX          = 0x00000011,
8027 } DCIO_DC_GENERICA_SEL;
8028 
8029 /*
8030  * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
8031  */
8032 
8033 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
8034 DCIO_UNIPHYA_TEST_REFDIV_CLK             = 0x00000000,
8035 DCIO_UNIPHYB_TEST_REFDIV_CLK             = 0x00000001,
8036 DCIO_UNIPHYC_TEST_REFDIV_CLK             = 0x00000002,
8037 DCIO_UNIPHYD_TEST_REFDIV_CLK             = 0x00000003,
8038 DCIO_UNIPHYE_TEST_REFDIV_CLK             = 0x00000004,
8039 DCIO_UNIPHYF_TEST_REFDIV_CLK             = 0x00000005,
8040 DCIO_UNIPHYG_TEST_REFDIV_CLK             = 0x00000006,
8041 } DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
8042 
8043 /*
8044  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
8045  */
8046 
8047 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
8048 DCIO_UNIPHYA_FBDIV_CLK                   = 0x00000000,
8049 DCIO_UNIPHYB_FBDIV_CLK                   = 0x00000001,
8050 DCIO_UNIPHYC_FBDIV_CLK                   = 0x00000002,
8051 DCIO_UNIPHYD_FBDIV_CLK                   = 0x00000003,
8052 DCIO_UNIPHYE_FBDIV_CLK                   = 0x00000004,
8053 DCIO_UNIPHYF_FBDIV_CLK                   = 0x00000005,
8054 DCIO_UNIPHYG_FBDIV_CLK                   = 0x00000006,
8055 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
8056 
8057 /*
8058  * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
8059  */
8060 
8061 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
8062 DCIO_UNIPHYA_FBDIV_SSC_CLK               = 0x00000000,
8063 DCIO_UNIPHYB_FBDIV_SSC_CLK               = 0x00000001,
8064 DCIO_UNIPHYC_FBDIV_SSC_CLK               = 0x00000002,
8065 DCIO_UNIPHYD_FBDIV_SSC_CLK               = 0x00000003,
8066 DCIO_UNIPHYE_FBDIV_SSC_CLK               = 0x00000004,
8067 DCIO_UNIPHYF_FBDIV_SSC_CLK               = 0x00000005,
8068 DCIO_UNIPHYG_FBDIV_SSC_CLK               = 0x00000006,
8069 } DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
8070 
8071 /*
8072  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
8073  */
8074 
8075 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
8076 DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2         = 0x00000000,
8077 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2         = 0x00000001,
8078 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2         = 0x00000002,
8079 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2         = 0x00000003,
8080 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2         = 0x00000004,
8081 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2         = 0x00000005,
8082 DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2         = 0x00000006,
8083 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
8084 
8085 /*
8086  * DCIO_DC_GENERICB_SEL enum
8087  */
8088 
8089 typedef enum DCIO_DC_GENERICB_SEL {
8090 DCIO_GENERICB_SEL_DACA_STEREOSYNC        = 0x00000000,
8091 DCIO_GENERICB_SEL_STEREOSYNC             = 0x00000001,
8092 DCIO_GENERICB_SEL_DACA_PIXCLK            = 0x00000002,
8093 DCIO_GENERICB_SEL_DACB_PIXCLK            = 0x00000003,
8094 DCIO_GENERICB_SEL_DVOA_CTL3              = 0x00000004,
8095 DCIO_GENERICB_SEL_P1_PLLCLK              = 0x00000005,
8096 DCIO_GENERICB_SEL_P2_PLLCLK              = 0x00000006,
8097 DCIO_GENERICB_SEL_DVOA_STEREOSYNC        = 0x00000007,
8098 DCIO_GENERICB_SEL_DACA_FIELD_NUMBER      = 0x00000008,
8099 DCIO_GENERICB_SEL_DACB_FIELD_NUMBER      = 0x00000009,
8100 DCIO_GENERICB_SEL_GENERICB_DCCG          = 0x0000000a,
8101 DCIO_GENERICB_SEL_SYNCEN                 = 0x0000000b,
8102 DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
8103 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
8104 DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
8105 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
8106 } DCIO_DC_GENERICB_SEL;
8107 
8108 /*
8109  * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
8110  */
8111 
8112 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
8113 DCIO_HSYNCA_OUTPUT_SEL_DISABLE           = 0x00000000,
8114 DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,
8115 DCIO_HSYNCA_OUTPUT_SEL_PPLL2             = 0x00000002,
8116 DCIO_HSYNCA_OUTPUT_SEL_RESERVED          = 0x00000003,
8117 } DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
8118 
8119 /*
8120  * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
8121  */
8122 
8123 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
8124 DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE        = 0x00000000,
8125 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1          = 0x00000001,
8126 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,
8127 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3  = 0x00000003,
8128 } DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
8129 
8130 /*
8131  * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
8132  */
8133 
8134 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
8135 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
8136 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
8137 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
8138 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
8139 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
8140 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
8141 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
8142 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
8143 } DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
8144 
8145 /*
8146  * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
8147  */
8148 
8149 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
8150 DCIO_UNIPHY_CHANNEL_NO_INVERSION         = 0x00000000,
8151 DCIO_UNIPHY_CHANNEL_INVERTED             = 0x00000001,
8152 } DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
8153 
8154 /*
8155  * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
8156  */
8157 
8158 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
8159 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW  = 0x00000000,
8160 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW   = 0x00000001,
8161 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED  = 0x00000002,
8162 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED  = 0x00000003,
8163 } DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
8164 
8165 /*
8166  * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
8167  */
8168 
8169 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
8170 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0      = 0x00000000,
8171 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1      = 0x00000001,
8172 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2      = 0x00000002,
8173 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3      = 0x00000003,
8174 } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
8175 
8176 /*
8177  * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
8178  */
8179 
8180 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
8181 DCIO_VIP_MUX_EN_DVO                      = 0x00000000,
8182 DCIO_VIP_MUX_EN_VIP                      = 0x00000001,
8183 } DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
8184 
8185 /*
8186  * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
8187  */
8188 
8189 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
8190 DCIO_VIP_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
8191 DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
8192 } DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
8193 
8194 /*
8195  * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
8196  */
8197 
8198 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
8199 DCIO_DVO_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
8200 DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
8201 } DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
8202 
8203 /*
8204  * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
8205  */
8206 
8207 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
8208 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE  = 0x00000000,
8209 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE  = 0x00000001,
8210 } DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
8211 
8212 /*
8213  * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
8214  */
8215 
8216 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
8217 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF   = 0x00000000,
8218 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON    = 0x00000001,
8219 } DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
8220 
8221 /*
8222  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
8223  */
8224 
8225 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
8226 DCIO_LVTMA_SYNCEN_POL_NON_INVERT         = 0x00000000,
8227 DCIO_LVTMA_SYNCEN_POL_INVERT             = 0x00000001,
8228 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
8229 
8230 /*
8231  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
8232  */
8233 
8234 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
8235 DCIO_LVTMA_DIGON_OFF                     = 0x00000000,
8236 DCIO_LVTMA_DIGON_ON                      = 0x00000001,
8237 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
8238 
8239 /*
8240  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
8241  */
8242 
8243 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
8244 DCIO_LVTMA_DIGON_POL_NON_INVERT          = 0x00000000,
8245 DCIO_LVTMA_DIGON_POL_INVERT              = 0x00000001,
8246 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
8247 
8248 /*
8249  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
8250  */
8251 
8252 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
8253 DCIO_LVTMA_BLON_OFF                      = 0x00000000,
8254 DCIO_LVTMA_BLON_ON                       = 0x00000001,
8255 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
8256 
8257 /*
8258  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
8259  */
8260 
8261 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
8262 DCIO_LVTMA_BLON_POL_NON_INVERT           = 0x00000000,
8263 DCIO_LVTMA_BLON_POL_INVERT               = 0x00000001,
8264 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
8265 
8266 /*
8267  * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
8268  */
8269 
8270 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
8271 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON      = 0x00000000,
8272 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE  = 0x00000001,
8273 } DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
8274 
8275 /*
8276  * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
8277  */
8278 
8279 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
8280 DCIO_BL_PWM_FRACTIONAL_DISABLE           = 0x00000000,
8281 DCIO_BL_PWM_FRACTIONAL_ENABLE            = 0x00000001,
8282 } DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
8283 
8284 /*
8285  * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
8286  */
8287 
8288 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
8289 DCIO_BL_PWM_DISABLE                      = 0x00000000,
8290 DCIO_BL_PWM_ENABLE                       = 0x00000001,
8291 } DCIO_BL_PWM_CNTL_BL_PWM_EN;
8292 
8293 /*
8294  * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
8295  */
8296 
8297 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
8298 DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE      = 0x00000000,
8299 DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE       = 0x00000001,
8300 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
8301 
8302 /*
8303  * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
8304  */
8305 
8306 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
8307 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL  = 0x00000000,
8308 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM  = 0x00000001,
8309 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
8310 
8311 /*
8312  * DCIO_BL_PWM_GRP1_REG_LOCK enum
8313  */
8314 
8315 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
8316 DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE        = 0x00000000,
8317 DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE         = 0x00000001,
8318 } DCIO_BL_PWM_GRP1_REG_LOCK;
8319 
8320 /*
8321  * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
8322  */
8323 
8324 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
8325 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE  = 0x00000000,
8326 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE  = 0x00000001,
8327 } DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
8328 
8329 /*
8330  * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
8331  */
8332 
8333 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
8334 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1  = 0x00000000,
8335 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2  = 0x00000001,
8336 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3  = 0x00000002,
8337 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4  = 0x00000003,
8338 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5  = 0x00000004,
8339 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6  = 0x00000005,
8340 } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
8341 
8342 /*
8343  * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
8344  */
8345 
8346 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
8347 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM  = 0x00000000,
8348 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM  = 0x00000001,
8349 } DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
8350 
8351 /*
8352  * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
8353  */
8354 
8355 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
8356 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE  = 0x00000000,
8357 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE  = 0x00000001,
8358 } DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
8359 
8360 /*
8361  * DCIO_GSL_SEL enum
8362  */
8363 
8364 typedef enum DCIO_GSL_SEL {
8365 DCIO_GSL_SEL_GROUP_0                     = 0x00000000,
8366 DCIO_GSL_SEL_GROUP_1                     = 0x00000001,
8367 DCIO_GSL_SEL_GROUP_2                     = 0x00000002,
8368 } DCIO_GSL_SEL;
8369 
8370 /*
8371  * DCIO_GENLK_CLK_GSL_MASK enum
8372  */
8373 
8374 typedef enum DCIO_GENLK_CLK_GSL_MASK {
8375 DCIO_GENLK_CLK_GSL_MASK_NO               = 0x00000000,
8376 DCIO_GENLK_CLK_GSL_MASK_TIMING           = 0x00000001,
8377 DCIO_GENLK_CLK_GSL_MASK_STEREO           = 0x00000002,
8378 } DCIO_GENLK_CLK_GSL_MASK;
8379 
8380 /*
8381  * DCIO_GENLK_VSYNC_GSL_MASK enum
8382  */
8383 
8384 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
8385 DCIO_GENLK_VSYNC_GSL_MASK_NO             = 0x00000000,
8386 DCIO_GENLK_VSYNC_GSL_MASK_TIMING         = 0x00000001,
8387 DCIO_GENLK_VSYNC_GSL_MASK_STEREO         = 0x00000002,
8388 } DCIO_GENLK_VSYNC_GSL_MASK;
8389 
8390 /*
8391  * DCIO_SWAPLOCK_A_GSL_MASK enum
8392  */
8393 
8394 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
8395 DCIO_SWAPLOCK_A_GSL_MASK_NO              = 0x00000000,
8396 DCIO_SWAPLOCK_A_GSL_MASK_TIMING          = 0x00000001,
8397 DCIO_SWAPLOCK_A_GSL_MASK_STEREO          = 0x00000002,
8398 } DCIO_SWAPLOCK_A_GSL_MASK;
8399 
8400 /*
8401  * DCIO_SWAPLOCK_B_GSL_MASK enum
8402  */
8403 
8404 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
8405 DCIO_SWAPLOCK_B_GSL_MASK_NO              = 0x00000000,
8406 DCIO_SWAPLOCK_B_GSL_MASK_TIMING          = 0x00000001,
8407 DCIO_SWAPLOCK_B_GSL_MASK_STEREO          = 0x00000002,
8408 } DCIO_SWAPLOCK_B_GSL_MASK;
8409 
8410 /*
8411  * DCIO_DC_GPU_TIMER_START_POSITION enum
8412  */
8413 
8414 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
8415 DCIO_GPU_TIMER_START_0_END_27            = 0x00000000,
8416 DCIO_GPU_TIMER_START_1_END_28            = 0x00000001,
8417 DCIO_GPU_TIMER_START_2_END_29            = 0x00000002,
8418 DCIO_GPU_TIMER_START_3_END_30            = 0x00000003,
8419 DCIO_GPU_TIMER_START_4_END_31            = 0x00000004,
8420 DCIO_GPU_TIMER_START_6_END_33            = 0x00000005,
8421 DCIO_GPU_TIMER_START_8_END_35            = 0x00000006,
8422 DCIO_GPU_TIMER_START_10_END_37           = 0x00000007,
8423 } DCIO_DC_GPU_TIMER_START_POSITION;
8424 
8425 /*
8426  * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
8427  */
8428 
8429 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
8430 DCIO_TEST_CLK_SEL_DISPCLK                = 0x00000000,
8431 DCIO_TEST_CLK_SEL_GATED_DISPCLK          = 0x00000001,
8432 DCIO_TEST_CLK_SEL_SOCCLK                 = 0x00000002,
8433 } DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
8434 
8435 /*
8436  * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
8437  */
8438 
8439 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
8440 DCIO_DISPCLK_R_DCIO_GATE_DISABLE         = 0x00000000,
8441 DCIO_DISPCLK_R_DCIO_GATE_ENABLE          = 0x00000001,
8442 } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
8443 
8444 /*
8445  * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
8446  */
8447 
8448 typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
8449 DCIO_EXT_VSYNC_MUX_SWAPLOCKB             = 0x00000000,
8450 DCIO_EXT_VSYNC_MUX_OTG0                  = 0x00000001,
8451 DCIO_EXT_VSYNC_MUX_OTG1                  = 0x00000002,
8452 DCIO_EXT_VSYNC_MUX_OTG2                  = 0x00000003,
8453 DCIO_EXT_VSYNC_MUX_OTG3                  = 0x00000004,
8454 DCIO_EXT_VSYNC_MUX_OTG4                  = 0x00000005,
8455 DCIO_EXT_VSYNC_MUX_OTG5                  = 0x00000006,
8456 DCIO_EXT_VSYNC_MUX_GENERICB              = 0x00000007,
8457 } DCIO_DIO_OTG_EXT_VSYNC_MUX;
8458 
8459 /*
8460  * DCIO_DIO_EXT_VSYNC_MASK enum
8461  */
8462 
8463 typedef enum DCIO_DIO_EXT_VSYNC_MASK {
8464 DCIO_EXT_VSYNC_MASK_NONE                 = 0x00000000,
8465 DCIO_EXT_VSYNC_MASK_PIPE0                = 0x00000001,
8466 DCIO_EXT_VSYNC_MASK_PIPE1                = 0x00000002,
8467 DCIO_EXT_VSYNC_MASK_PIPE2                = 0x00000003,
8468 DCIO_EXT_VSYNC_MASK_PIPE3                = 0x00000004,
8469 DCIO_EXT_VSYNC_MASK_PIPE4                = 0x00000005,
8470 DCIO_EXT_VSYNC_MASK_PIPE5                = 0x00000006,
8471 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE       = 0x00000007,
8472 } DCIO_DIO_EXT_VSYNC_MASK;
8473 
8474 /*
8475  * DCIO_DSYNC_SOFT_RESET enum
8476  */
8477 
8478 typedef enum DCIO_DSYNC_SOFT_RESET {
8479 DCIO_DSYNC_SOFT_RESET_DEASSERT           = 0x00000000,
8480 DCIO_DSYNC_SOFT_RESET_ASSERT             = 0x00000001,
8481 } DCIO_DSYNC_SOFT_RESET;
8482 
8483 /*
8484  * DCIO_DACA_SOFT_RESET enum
8485  */
8486 
8487 typedef enum DCIO_DACA_SOFT_RESET {
8488 DCIO_DACA_SOFT_RESET_DEASSERT            = 0x00000000,
8489 DCIO_DACA_SOFT_RESET_ASSERT              = 0x00000001,
8490 } DCIO_DACA_SOFT_RESET;
8491 
8492 /*
8493  * DCIO_DCRXPHY_SOFT_RESET enum
8494  */
8495 
8496 typedef enum DCIO_DCRXPHY_SOFT_RESET {
8497 DCIO_DCRXPHY_SOFT_RESET_DEASSERT         = 0x00000000,
8498 DCIO_DCRXPHY_SOFT_RESET_ASSERT           = 0x00000001,
8499 } DCIO_DCRXPHY_SOFT_RESET;
8500 
8501 /*
8502  * DCIO_DPHY_LANE_SEL enum
8503  */
8504 
8505 typedef enum DCIO_DPHY_LANE_SEL {
8506 DCIO_DPHY_LANE_SEL_LANE0                 = 0x00000000,
8507 DCIO_DPHY_LANE_SEL_LANE1                 = 0x00000001,
8508 DCIO_DPHY_LANE_SEL_LANE2                 = 0x00000002,
8509 DCIO_DPHY_LANE_SEL_LANE3                 = 0x00000003,
8510 } DCIO_DPHY_LANE_SEL;
8511 
8512 /*
8513  * DCIO_DPCS_INTERRUPT_TYPE enum
8514  */
8515 
8516 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
8517 DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED     = 0x00000000,
8518 DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED     = 0x00000001,
8519 } DCIO_DPCS_INTERRUPT_TYPE;
8520 
8521 /*
8522  * DCIO_DPCS_INTERRUPT_MASK enum
8523  */
8524 
8525 typedef enum DCIO_DPCS_INTERRUPT_MASK {
8526 DCIO_DPCS_INTERRUPT_DISABLE              = 0x00000000,
8527 DCIO_DPCS_INTERRUPT_ENABLE               = 0x00000001,
8528 } DCIO_DPCS_INTERRUPT_MASK;
8529 
8530 /*
8531  * DCIO_DC_GPU_TIMER_READ_SELECT enum
8532  */
8533 
8534 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
8535 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE  = 0x00000000,
8536 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE  = 0x00000001,
8537 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP  = 0x00000002,
8538 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP  = 0x00000003,
8539 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM  = 0x00000004,
8540 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM  = 0x00000005,
8541 } DCIO_DC_GPU_TIMER_READ_SELECT;
8542 
8543 /*
8544  * DCIO_IMPCAL_STEP_DELAY enum
8545  */
8546 
8547 typedef enum DCIO_IMPCAL_STEP_DELAY {
8548 DCIO_IMPCAL_STEP_DELAY_1us               = 0x00000000,
8549 DCIO_IMPCAL_STEP_DELAY_2us               = 0x00000001,
8550 DCIO_IMPCAL_STEP_DELAY_3us               = 0x00000002,
8551 DCIO_IMPCAL_STEP_DELAY_4us               = 0x00000003,
8552 DCIO_IMPCAL_STEP_DELAY_5us               = 0x00000004,
8553 DCIO_IMPCAL_STEP_DELAY_6us               = 0x00000005,
8554 DCIO_IMPCAL_STEP_DELAY_7us               = 0x00000006,
8555 DCIO_IMPCAL_STEP_DELAY_8us               = 0x00000007,
8556 DCIO_IMPCAL_STEP_DELAY_9us               = 0x00000008,
8557 DCIO_IMPCAL_STEP_DELAY_10us              = 0x00000009,
8558 DCIO_IMPCAL_STEP_DELAY_11us              = 0x0000000a,
8559 DCIO_IMPCAL_STEP_DELAY_12us              = 0x0000000b,
8560 DCIO_IMPCAL_STEP_DELAY_13us              = 0x0000000c,
8561 DCIO_IMPCAL_STEP_DELAY_14us              = 0x0000000d,
8562 DCIO_IMPCAL_STEP_DELAY_15us              = 0x0000000e,
8563 DCIO_IMPCAL_STEP_DELAY_16us              = 0x0000000f,
8564 } DCIO_IMPCAL_STEP_DELAY;
8565 
8566 /*
8567  * DCIO_UNIPHY_IMPCAL_SEL enum
8568  */
8569 
8570 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
8571 DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE       = 0x00000000,
8572 DCIO_UNIPHY_IMPCAL_SEL_BINARY            = 0x00000001,
8573 } DCIO_UNIPHY_IMPCAL_SEL;
8574 
8575 /*******************************************************
8576  * DCIO_CHIP Enums
8577  *******************************************************/
8578 
8579 /*
8580  * DCIOCHIP_HPD_SEL enum
8581  */
8582 
8583 typedef enum DCIOCHIP_HPD_SEL {
8584 DCIOCHIP_HPD_SEL_ASYNC                   = 0x00000000,
8585 DCIOCHIP_HPD_SEL_CLOCKED                 = 0x00000001,
8586 } DCIOCHIP_HPD_SEL;
8587 
8588 /*
8589  * DCIOCHIP_PAD_MODE enum
8590  */
8591 
8592 typedef enum DCIOCHIP_PAD_MODE {
8593 DCIOCHIP_PAD_MODE_DDC                    = 0x00000000,
8594 DCIOCHIP_PAD_MODE_DP                     = 0x00000001,
8595 } DCIOCHIP_PAD_MODE;
8596 
8597 /*
8598  * DCIOCHIP_AUXSLAVE_PAD_MODE enum
8599  */
8600 
8601 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
8602 DCIOCHIP_AUXSLAVE_PAD_MODE_I2C           = 0x00000000,
8603 DCIOCHIP_AUXSLAVE_PAD_MODE_AUX           = 0x00000001,
8604 } DCIOCHIP_AUXSLAVE_PAD_MODE;
8605 
8606 /*
8607  * DCIOCHIP_INVERT enum
8608  */
8609 
8610 typedef enum DCIOCHIP_INVERT {
8611 DCIOCHIP_POL_NON_INVERT                  = 0x00000000,
8612 DCIOCHIP_POL_INVERT                      = 0x00000001,
8613 } DCIOCHIP_INVERT;
8614 
8615 /*
8616  * DCIOCHIP_PD_EN enum
8617  */
8618 
8619 typedef enum DCIOCHIP_PD_EN {
8620 DCIOCHIP_PD_EN_NOTALLOW                  = 0x00000000,
8621 DCIOCHIP_PD_EN_ALLOW                     = 0x00000001,
8622 } DCIOCHIP_PD_EN;
8623 
8624 /*
8625  * DCIOCHIP_GPIO_MASK_EN enum
8626  */
8627 
8628 typedef enum DCIOCHIP_GPIO_MASK_EN {
8629 DCIOCHIP_GPIO_MASK_EN_HARDWARE           = 0x00000000,
8630 DCIOCHIP_GPIO_MASK_EN_SOFTWARE           = 0x00000001,
8631 } DCIOCHIP_GPIO_MASK_EN;
8632 
8633 /*
8634  * DCIOCHIP_MASK enum
8635  */
8636 
8637 typedef enum DCIOCHIP_MASK {
8638 DCIOCHIP_MASK_DISABLE                    = 0x00000000,
8639 DCIOCHIP_MASK_ENABLE                     = 0x00000001,
8640 } DCIOCHIP_MASK;
8641 
8642 /*
8643  * DCIOCHIP_GPIO_I2C_MASK enum
8644  */
8645 
8646 typedef enum DCIOCHIP_GPIO_I2C_MASK {
8647 DCIOCHIP_GPIO_I2C_MASK_DISABLE           = 0x00000000,
8648 DCIOCHIP_GPIO_I2C_MASK_ENABLE            = 0x00000001,
8649 } DCIOCHIP_GPIO_I2C_MASK;
8650 
8651 /*
8652  * DCIOCHIP_GPIO_I2C_DRIVE enum
8653  */
8654 
8655 typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
8656 DCIOCHIP_GPIO_I2C_DRIVE_LOW              = 0x00000000,
8657 DCIOCHIP_GPIO_I2C_DRIVE_HIGH             = 0x00000001,
8658 } DCIOCHIP_GPIO_I2C_DRIVE;
8659 
8660 /*
8661  * DCIOCHIP_GPIO_I2C_EN enum
8662  */
8663 
8664 typedef enum DCIOCHIP_GPIO_I2C_EN {
8665 DCIOCHIP_GPIO_I2C_DISABLE                = 0x00000000,
8666 DCIOCHIP_GPIO_I2C_ENABLE                 = 0x00000001,
8667 } DCIOCHIP_GPIO_I2C_EN;
8668 
8669 /*
8670  * DCIOCHIP_MASK_4BIT enum
8671  */
8672 
8673 typedef enum DCIOCHIP_MASK_4BIT {
8674 DCIOCHIP_MASK_4BIT_DISABLE               = 0x00000000,
8675 DCIOCHIP_MASK_4BIT_ENABLE                = 0x0000000f,
8676 } DCIOCHIP_MASK_4BIT;
8677 
8678 /*
8679  * DCIOCHIP_ENABLE_4BIT enum
8680  */
8681 
8682 typedef enum DCIOCHIP_ENABLE_4BIT {
8683 DCIOCHIP_4BIT_DISABLE                    = 0x00000000,
8684 DCIOCHIP_4BIT_ENABLE                     = 0x0000000f,
8685 } DCIOCHIP_ENABLE_4BIT;
8686 
8687 /*
8688  * DCIOCHIP_MASK_5BIT enum
8689  */
8690 
8691 typedef enum DCIOCHIP_MASK_5BIT {
8692 DCIOCHIP_MASIK_5BIT_DISABLE              = 0x00000000,
8693 DCIOCHIP_MASIK_5BIT_ENABLE               = 0x0000001f,
8694 } DCIOCHIP_MASK_5BIT;
8695 
8696 /*
8697  * DCIOCHIP_ENABLE_5BIT enum
8698  */
8699 
8700 typedef enum DCIOCHIP_ENABLE_5BIT {
8701 DCIOCHIP_5BIT_DISABLE                    = 0x00000000,
8702 DCIOCHIP_5BIT_ENABLE                     = 0x0000001f,
8703 } DCIOCHIP_ENABLE_5BIT;
8704 
8705 /*
8706  * DCIOCHIP_MASK_2BIT enum
8707  */
8708 
8709 typedef enum DCIOCHIP_MASK_2BIT {
8710 DCIOCHIP_MASK_2BIT_DISABLE               = 0x00000000,
8711 DCIOCHIP_MASK_2BIT_ENABLE                = 0x00000003,
8712 } DCIOCHIP_MASK_2BIT;
8713 
8714 /*
8715  * DCIOCHIP_ENABLE_2BIT enum
8716  */
8717 
8718 typedef enum DCIOCHIP_ENABLE_2BIT {
8719 DCIOCHIP_2BIT_DISABLE                    = 0x00000000,
8720 DCIOCHIP_2BIT_ENABLE                     = 0x00000003,
8721 } DCIOCHIP_ENABLE_2BIT;
8722 
8723 /*
8724  * DCIOCHIP_REF_27_SRC_SEL enum
8725  */
8726 
8727 typedef enum DCIOCHIP_REF_27_SRC_SEL {
8728 DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER     = 0x00000000,
8729 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER  = 0x00000001,
8730 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS      = 0x00000002,
8731 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS  = 0x00000003,
8732 } DCIOCHIP_REF_27_SRC_SEL;
8733 
8734 /*
8735  * DCIOCHIP_DVO_VREFPON enum
8736  */
8737 
8738 typedef enum DCIOCHIP_DVO_VREFPON {
8739 DCIOCHIP_DVO_VREFPON_DISABLE             = 0x00000000,
8740 DCIOCHIP_DVO_VREFPON_ENABLE              = 0x00000001,
8741 } DCIOCHIP_DVO_VREFPON;
8742 
8743 /*
8744  * DCIOCHIP_DVO_VREFSEL enum
8745  */
8746 
8747 typedef enum DCIOCHIP_DVO_VREFSEL {
8748 DCIOCHIP_DVO_VREFSEL_ONCHIP              = 0x00000000,
8749 DCIOCHIP_DVO_VREFSEL_EXTERNAL            = 0x00000001,
8750 } DCIOCHIP_DVO_VREFSEL;
8751 
8752 /*
8753  * DCIOCHIP_SPDIF1_IMODE enum
8754  */
8755 
8756 typedef enum DCIOCHIP_SPDIF1_IMODE {
8757 DCIOCHIP_SPDIF1_IMODE_OE_A               = 0x00000000,
8758 DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO          = 0x00000001,
8759 } DCIOCHIP_SPDIF1_IMODE;
8760 
8761 /*
8762  * DCIOCHIP_AUX_FALLSLEWSEL enum
8763  */
8764 
8765 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
8766 DCIOCHIP_AUX_FALLSLEWSEL_LOW             = 0x00000000,
8767 DCIOCHIP_AUX_FALLSLEWSEL_HIGH0           = 0x00000001,
8768 DCIOCHIP_AUX_FALLSLEWSEL_HIGH1           = 0x00000002,
8769 DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH       = 0x00000003,
8770 } DCIOCHIP_AUX_FALLSLEWSEL;
8771 
8772 /*
8773  * DCIOCHIP_I2C_FALLSLEWSEL enum
8774  */
8775 
8776 typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
8777 DCIOCHIP_I2C_FALLSLEWSEL_00              = 0x00000000,
8778 DCIOCHIP_I2C_FALLSLEWSEL_01              = 0x00000001,
8779 DCIOCHIP_I2C_FALLSLEWSEL_10              = 0x00000002,
8780 DCIOCHIP_I2C_FALLSLEWSEL_11              = 0x00000003,
8781 } DCIOCHIP_I2C_FALLSLEWSEL;
8782 
8783 /*
8784  * DCIOCHIP_AUX_SPIKESEL enum
8785  */
8786 
8787 typedef enum DCIOCHIP_AUX_SPIKESEL {
8788 DCIOCHIP_AUX_SPIKESEL_50NS               = 0x00000000,
8789 DCIOCHIP_AUX_SPIKESEL_10NS               = 0x00000001,
8790 } DCIOCHIP_AUX_SPIKESEL;
8791 
8792 /*
8793  * DCIOCHIP_AUX_CSEL0P9 enum
8794  */
8795 
8796 typedef enum DCIOCHIP_AUX_CSEL0P9 {
8797 DCIOCHIP_AUX_CSEL_DEC1P0                 = 0x00000000,
8798 DCIOCHIP_AUX_CSEL_DEC0P9                 = 0x00000001,
8799 } DCIOCHIP_AUX_CSEL0P9;
8800 
8801 /*
8802  * DCIOCHIP_AUX_CSEL1P1 enum
8803  */
8804 
8805 typedef enum DCIOCHIP_AUX_CSEL1P1 {
8806 DCIOCHIP_AUX_CSEL_INC1P0                 = 0x00000000,
8807 DCIOCHIP_AUX_CSEL_INC1P1                 = 0x00000001,
8808 } DCIOCHIP_AUX_CSEL1P1;
8809 
8810 /*
8811  * DCIOCHIP_AUX_RSEL0P9 enum
8812  */
8813 
8814 typedef enum DCIOCHIP_AUX_RSEL0P9 {
8815 DCIOCHIP_AUX_RSEL_DEC1P0                 = 0x00000000,
8816 DCIOCHIP_AUX_RSEL_DEC0P9                 = 0x00000001,
8817 } DCIOCHIP_AUX_RSEL0P9;
8818 
8819 /*
8820  * DCIOCHIP_AUX_RSEL1P1 enum
8821  */
8822 
8823 typedef enum DCIOCHIP_AUX_RSEL1P1 {
8824 DCIOCHIP_AUX_RSEL_INC1P0                 = 0x00000000,
8825 DCIOCHIP_AUX_RSEL_INC1P1                 = 0x00000001,
8826 } DCIOCHIP_AUX_RSEL1P1;
8827 
8828 /*
8829  * DCIOCHIP_AUX_HYS_TUNE enum
8830  */
8831 
8832 typedef enum DCIOCHIP_AUX_HYS_TUNE {
8833 DCIOCHIP_AUX_HYS_TUNE_0                  = 0x00000000,
8834 DCIOCHIP_AUX_HYS_TUNE_1                  = 0x00000001,
8835 DCIOCHIP_AUX_HYS_TUNE_2                  = 0x00000002,
8836 DCIOCHIP_AUX_HYS_TUNE_3                  = 0x00000003,
8837 } DCIOCHIP_AUX_HYS_TUNE;
8838 
8839 /*
8840  * DCIOCHIP_AUX_VOD_TUNE enum
8841  */
8842 
8843 typedef enum DCIOCHIP_AUX_VOD_TUNE {
8844 DCIOCHIP_AUX_VOD_TUNE_0                  = 0x00000000,
8845 DCIOCHIP_AUX_VOD_TUNE_1                  = 0x00000001,
8846 DCIOCHIP_AUX_VOD_TUNE_2                  = 0x00000002,
8847 DCIOCHIP_AUX_VOD_TUNE_3                  = 0x00000003,
8848 } DCIOCHIP_AUX_VOD_TUNE;
8849 
8850 /*
8851  * DCIOCHIP_I2C_VPH_1V2_EN enum
8852  */
8853 
8854 typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
8855 DCIOCHIP_I2C_VPH_1V2_EN_0                = 0x00000000,
8856 DCIOCHIP_I2C_VPH_1V2_EN_1                = 0x00000001,
8857 } DCIOCHIP_I2C_VPH_1V2_EN;
8858 
8859 /*
8860  * DCIOCHIP_I2C_COMPSEL enum
8861  */
8862 
8863 typedef enum DCIOCHIP_I2C_COMPSEL {
8864 DCIOCHIP_I2C_REC_SCHMIT                  = 0x00000000,
8865 DCIOCHIP_I2C_REC_COMPARATOR              = 0x00000001,
8866 } DCIOCHIP_I2C_COMPSEL;
8867 
8868 /*
8869  * DCIOCHIP_AUX_ALL_PWR_OK enum
8870  */
8871 
8872 typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
8873 DCIOCHIP_AUX_ALL_PWR_OK_0                = 0x00000000,
8874 DCIOCHIP_AUX_ALL_PWR_OK_1                = 0x00000001,
8875 } DCIOCHIP_AUX_ALL_PWR_OK;
8876 
8877 /*
8878  * DCIOCHIP_I2C_RECEIVER_SEL enum
8879  */
8880 
8881 typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
8882 DCIOCHIP_I2C_RECEIVER_SEL_0              = 0x00000000,
8883 DCIOCHIP_I2C_RECEIVER_SEL_1              = 0x00000001,
8884 DCIOCHIP_I2C_RECEIVER_SEL_2              = 0x00000002,
8885 DCIOCHIP_I2C_RECEIVER_SEL_3              = 0x00000003,
8886 } DCIOCHIP_I2C_RECEIVER_SEL;
8887 
8888 /*
8889  * DCIOCHIP_AUX_RECEIVER_SEL enum
8890  */
8891 
8892 typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
8893 DCIOCHIP_AUX_RECEIVER_SEL_0              = 0x00000000,
8894 DCIOCHIP_AUX_RECEIVER_SEL_1              = 0x00000001,
8895 DCIOCHIP_AUX_RECEIVER_SEL_2              = 0x00000002,
8896 DCIOCHIP_AUX_RECEIVER_SEL_3              = 0x00000003,
8897 } DCIOCHIP_AUX_RECEIVER_SEL;
8898 
8899 /*******************************************************
8900  * AZCONTROLLER Enums
8901  *******************************************************/
8902 
8903 /*
8904  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
8905  */
8906 
8907 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
8908 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE   = 0x00000000,
8909 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE    = 0x00000001,
8910 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
8911 
8912 /*
8913  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
8914  */
8915 
8916 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
8917 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x00000000,
8918 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED  = 0x00000001,
8919 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
8920 
8921 /*
8922  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
8923  */
8924 
8925 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
8926 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET  = 0x00000000,
8927 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET  = 0x00000001,
8928 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
8929 
8930 /*
8931  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
8932  */
8933 
8934 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
8935 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED  = 0x00000000,
8936 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED  = 0x00000001,
8937 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
8938 
8939 /*
8940  * AZ_GLOBAL_CAPABILITIES enum
8941  */
8942 
8943 typedef enum AZ_GLOBAL_CAPABILITIES {
8944 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED  = 0x00000000,
8945 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED  = 0x00000001,
8946 } AZ_GLOBAL_CAPABILITIES;
8947 
8948 /*
8949  * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
8950  */
8951 
8952 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
8953 ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE   = 0x00000000,
8954 ACCEPT_UNSOLICITED_RESPONSE_ENABLE       = 0x00000001,
8955 } GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
8956 
8957 /*
8958  * GLOBAL_CONTROL_FLUSH_CONTROL enum
8959  */
8960 
8961 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
8962 FLUSH_CONTROL_FLUSH_NOT_STARTED          = 0x00000000,
8963 FLUSH_CONTROL_FLUSH_STARTED              = 0x00000001,
8964 } GLOBAL_CONTROL_FLUSH_CONTROL;
8965 
8966 /*
8967  * GLOBAL_CONTROL_CONTROLLER_RESET enum
8968  */
8969 
8970 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
8971 CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET  = 0x00000000,
8972 CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET  = 0x00000001,
8973 } GLOBAL_CONTROL_CONTROLLER_RESET;
8974 
8975 /*
8976  * AZ_STATE_CHANGE_STATUS enum
8977  */
8978 
8979 typedef enum AZ_STATE_CHANGE_STATUS {
8980 AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT  = 0x00000000,
8981 AZ_STATE_CHANGE_STATUS_CODEC_PRESENT     = 0x00000001,
8982 } AZ_STATE_CHANGE_STATUS;
8983 
8984 /*
8985  * GLOBAL_STATUS_FLUSH_STATUS enum
8986  */
8987 
8988 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
8989 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED  = 0x00000000,
8990 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED   = 0x00000001,
8991 } GLOBAL_STATUS_FLUSH_STATUS;
8992 
8993 /*
8994  * STREAM_0_SYNCHRONIZATION enum
8995  */
8996 
8997 typedef enum STREAM_0_SYNCHRONIZATION {
8998 STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
8999 STREAM_0_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
9000 } STREAM_0_SYNCHRONIZATION;
9001 
9002 /*
9003  * STREAM_1_SYNCHRONIZATION enum
9004  */
9005 
9006 typedef enum STREAM_1_SYNCHRONIZATION {
9007 STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
9008 STREAM_1_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
9009 } STREAM_1_SYNCHRONIZATION;
9010 
9011 /*
9012  * STREAM_2_SYNCHRONIZATION enum
9013  */
9014 
9015 typedef enum STREAM_2_SYNCHRONIZATION {
9016 STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
9017 STREAM_2_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
9018 } STREAM_2_SYNCHRONIZATION;
9019 
9020 /*
9021  * STREAM_3_SYNCHRONIZATION enum
9022  */
9023 
9024 typedef enum STREAM_3_SYNCHRONIZATION {
9025 STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
9026 STREAM_3_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
9027 } STREAM_3_SYNCHRONIZATION;
9028 
9029 /*
9030  * STREAM_4_SYNCHRONIZATION enum
9031  */
9032 
9033 typedef enum STREAM_4_SYNCHRONIZATION {
9034 STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
9035 STREAM_4_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
9036 } STREAM_4_SYNCHRONIZATION;
9037 
9038 /*
9039  * STREAM_5_SYNCHRONIZATION enum
9040  */
9041 
9042 typedef enum STREAM_5_SYNCHRONIZATION {
9043 STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
9044 STREAM_5_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
9045 } STREAM_5_SYNCHRONIZATION;
9046 
9047 /*
9048  * STREAM_6_SYNCHRONIZATION enum
9049  */
9050 
9051 typedef enum STREAM_6_SYNCHRONIZATION {
9052 STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9053 STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9054 } STREAM_6_SYNCHRONIZATION;
9055 
9056 /*
9057  * STREAM_7_SYNCHRONIZATION enum
9058  */
9059 
9060 typedef enum STREAM_7_SYNCHRONIZATION {
9061 STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9062 STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9063 } STREAM_7_SYNCHRONIZATION;
9064 
9065 /*
9066  * STREAM_8_SYNCHRONIZATION enum
9067  */
9068 
9069 typedef enum STREAM_8_SYNCHRONIZATION {
9070 STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9071 STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9072 } STREAM_8_SYNCHRONIZATION;
9073 
9074 /*
9075  * STREAM_9_SYNCHRONIZATION enum
9076  */
9077 
9078 typedef enum STREAM_9_SYNCHRONIZATION {
9079 STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9080 STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9081 } STREAM_9_SYNCHRONIZATION;
9082 
9083 /*
9084  * STREAM_10_SYNCHRONIZATION enum
9085  */
9086 
9087 typedef enum STREAM_10_SYNCHRONIZATION {
9088 STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9089 STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9090 } STREAM_10_SYNCHRONIZATION;
9091 
9092 /*
9093  * STREAM_11_SYNCHRONIZATION enum
9094  */
9095 
9096 typedef enum STREAM_11_SYNCHRONIZATION {
9097 STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9098 STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9099 } STREAM_11_SYNCHRONIZATION;
9100 
9101 /*
9102  * STREAM_12_SYNCHRONIZATION enum
9103  */
9104 
9105 typedef enum STREAM_12_SYNCHRONIZATION {
9106 STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9107 STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9108 } STREAM_12_SYNCHRONIZATION;
9109 
9110 /*
9111  * STREAM_13_SYNCHRONIZATION enum
9112  */
9113 
9114 typedef enum STREAM_13_SYNCHRONIZATION {
9115 STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9116 STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9117 } STREAM_13_SYNCHRONIZATION;
9118 
9119 /*
9120  * STREAM_14_SYNCHRONIZATION enum
9121  */
9122 
9123 typedef enum STREAM_14_SYNCHRONIZATION {
9124 STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9125 STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9126 } STREAM_14_SYNCHRONIZATION;
9127 
9128 /*
9129  * STREAM_15_SYNCHRONIZATION enum
9130  */
9131 
9132 typedef enum STREAM_15_SYNCHRONIZATION {
9133 STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
9134 STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
9135 } STREAM_15_SYNCHRONIZATION;
9136 
9137 /*
9138  * CORB_READ_POINTER_RESET enum
9139  */
9140 
9141 typedef enum CORB_READ_POINTER_RESET {
9142 CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET  = 0x00000000,
9143 CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET  = 0x00000001,
9144 } CORB_READ_POINTER_RESET;
9145 
9146 /*
9147  * AZ_CORB_SIZE enum
9148  */
9149 
9150 typedef enum AZ_CORB_SIZE {
9151 AZ_CORB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
9152 AZ_CORB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
9153 AZ_CORB_SIZE_256ENTRIES                  = 0x00000002,
9154 AZ_CORB_SIZE_RESERVED                    = 0x00000003,
9155 } AZ_CORB_SIZE;
9156 
9157 /*
9158  * AZ_RIRB_WRITE_POINTER_RESET enum
9159  */
9160 
9161 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
9162 AZ_RIRB_WRITE_POINTER_NOT_RESET          = 0x00000000,
9163 AZ_RIRB_WRITE_POINTER_DO_RESET           = 0x00000001,
9164 } AZ_RIRB_WRITE_POINTER_RESET;
9165 
9166 /*
9167  * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
9168  */
9169 
9170 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
9171 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
9172 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
9173 } RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
9174 
9175 /*
9176  * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
9177  */
9178 
9179 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
9180 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
9181 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
9182 } RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
9183 
9184 /*
9185  * AZ_RIRB_SIZE enum
9186  */
9187 
9188 typedef enum AZ_RIRB_SIZE {
9189 AZ_RIRB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
9190 AZ_RIRB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
9191 AZ_RIRB_SIZE_256ENTRIES                  = 0x00000002,
9192 AZ_RIRB_SIZE_UNDEFINED                   = 0x00000003,
9193 } AZ_RIRB_SIZE;
9194 
9195 /*
9196  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
9197  */
9198 
9199 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
9200 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID  = 0x00000000,
9201 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID  = 0x00000001,
9202 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
9203 
9204 /*
9205  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
9206  */
9207 
9208 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
9209 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY  = 0x00000000,
9210 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY  = 0x00000001,
9211 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
9212 
9213 /*
9214  * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
9215  */
9216 
9217 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
9218 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE  = 0x00000000,
9219 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE  = 0x00000001,
9220 } DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
9221 
9222 /*******************************************************
9223  * AZENDPOINT Enums
9224  *******************************************************/
9225 
9226 /*
9227  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
9228  */
9229 
9230 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
9231 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
9232 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
9233 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
9234 
9235 /*
9236  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
9237  */
9238 
9239 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
9240 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
9241 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
9242 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
9243 
9244 /*
9245  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
9246  */
9247 
9248 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
9249 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
9250 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
9251 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
9252 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
9253 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
9254 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
9255 
9256 /*
9257  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
9258  */
9259 
9260 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
9261 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
9262 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
9263 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
9264 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
9265 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
9266 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
9267 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
9268 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
9269 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
9270 
9271 /*
9272  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
9273  */
9274 
9275 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
9276 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
9277 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
9278 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
9279 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
9280 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
9281 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
9282 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
9283 
9284 /*
9285  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
9286  */
9287 
9288 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
9289 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
9290 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
9291 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
9292 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
9293 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
9294 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
9295 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
9296 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
9297 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
9298 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
9299 
9300 /*
9301  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
9302  */
9303 
9304 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
9305 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET  = 0x00000000,
9306 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET  = 0x00000001,
9307 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
9308 
9309 /*
9310  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
9311  */
9312 
9313 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
9314 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET  = 0x00000000,
9315 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET  = 0x00000001,
9316 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
9317 
9318 /*
9319  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
9320  */
9321 
9322 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
9323 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET  = 0x00000000,
9324 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET  = 0x00000001,
9325 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
9326 
9327 /*
9328  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
9329  */
9330 
9331 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
9332 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET  = 0x00000000,
9333 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET  = 0x00000001,
9334 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
9335 
9336 /*
9337  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
9338  */
9339 
9340 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
9341 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET  = 0x00000000,
9342 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET  = 0x00000001,
9343 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
9344 
9345 /*
9346  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
9347  */
9348 
9349 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
9350 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON  = 0x00000000,
9351 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON  = 0x00000001,
9352 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
9353 
9354 /*
9355  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
9356  */
9357 
9358 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
9359 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO  = 0x00000000,
9360 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE  = 0x00000001,
9361 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
9362 
9363 /*
9364  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
9365  */
9366 
9367 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
9368 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
9369 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
9370 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
9371 
9372 /*
9373  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
9374  */
9375 
9376 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
9377 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE  = 0x00000000,
9378 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE  = 0x00000001,
9379 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
9380 
9381 /*
9382  * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
9383  */
9384 
9385 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
9386 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF  = 0x00000000,
9387 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN  = 0x00000001,
9388 } AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
9389 
9390 /*
9391  * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
9392  */
9393 
9394 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
9395 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
9396 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
9397 } AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
9398 
9399 /*
9400  * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
9401  */
9402 
9403 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
9404 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED  = 0x00000000,
9405 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN  = 0x00000001,
9406 } AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
9407 
9408 /*
9409  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
9410  */
9411 
9412 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
9413 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED  = 0x00000000,
9414 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED  = 0x00000001,
9415 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
9416 
9417 /*
9418  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
9419  */
9420 
9421 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
9422 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED  = 0x00000000,
9423 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED  = 0x00000001,
9424 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
9425 
9426 /*
9427  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
9428  */
9429 
9430 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
9431 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED  = 0x00000000,
9432 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED  = 0x00000001,
9433 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
9434 
9435 /*
9436  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
9437  */
9438 
9439 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
9440 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED  = 0x00000000,
9441 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED  = 0x00000001,
9442 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
9443 
9444 /*
9445  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
9446  */
9447 
9448 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
9449 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
9450 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
9451 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
9452 
9453 /*
9454  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
9455  */
9456 
9457 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
9458 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
9459 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
9460 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
9461 
9462 /*
9463  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
9464  */
9465 
9466 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
9467 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
9468 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
9469 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
9470 
9471 /*
9472  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
9473  */
9474 
9475 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
9476 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
9477 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
9478 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
9479 
9480 /*
9481  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
9482  */
9483 
9484 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
9485 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
9486 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
9487 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
9488 
9489 /*
9490  * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
9491  */
9492 
9493 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
9494 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0  = 0x00000000,
9495 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1  = 0x00000001,
9496 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2  = 0x00000002,
9497 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3  = 0x00000003,
9498 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4  = 0x00000004,
9499 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5  = 0x00000005,
9500 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6  = 0x00000006,
9501 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7  = 0x00000007,
9502 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8  = 0x00000008,
9503 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9  = 0x00000009,
9504 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10  = 0x0000000a,
9505 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11  = 0x0000000b,
9506 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12  = 0x0000000c,
9507 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13  = 0x0000000d,
9508 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14  = 0x0000000e,
9509 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15  = 0x0000000f,
9510 } AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE;
9511 
9512 /*******************************************************
9513  * AZF0CONTROLLER Enums
9514  *******************************************************/
9515 
9516 /*
9517  * MEM_PWR_FORCE_CTRL enum
9518  */
9519 
9520 typedef enum MEM_PWR_FORCE_CTRL {
9521 NO_FORCE_REQUEST                         = 0x00000000,
9522 FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
9523 FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
9524 FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
9525 } MEM_PWR_FORCE_CTRL;
9526 
9527 /*
9528  * MEM_PWR_FORCE_CTRL2 enum
9529  */
9530 
9531 typedef enum MEM_PWR_FORCE_CTRL2 {
9532 NO_FORCE_REQ                             = 0x00000000,
9533 FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
9534 } MEM_PWR_FORCE_CTRL2;
9535 
9536 /*
9537  * MEM_PWR_DIS_CTRL enum
9538  */
9539 
9540 typedef enum MEM_PWR_DIS_CTRL {
9541 ENABLE_MEM_PWR_CTRL                      = 0x00000000,
9542 DISABLE_MEM_PWR_CTRL                     = 0x00000001,
9543 } MEM_PWR_DIS_CTRL;
9544 
9545 /*
9546  * MEM_PWR_SEL_CTRL enum
9547  */
9548 
9549 typedef enum MEM_PWR_SEL_CTRL {
9550 DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
9551 DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
9552 DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
9553 } MEM_PWR_SEL_CTRL;
9554 
9555 /*
9556  * MEM_PWR_SEL_CTRL2 enum
9557  */
9558 
9559 typedef enum MEM_PWR_SEL_CTRL2 {
9560 DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
9561 DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
9562 } MEM_PWR_SEL_CTRL2;
9563 
9564 /*
9565  * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
9566  */
9567 
9568 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
9569 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET  = 0x00000000,
9570 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC  = 0x00000001,
9571 } AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
9572 
9573 /*******************************************************
9574  * AZF0ROOT Enums
9575  *******************************************************/
9576 
9577 /*
9578  * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
9579  */
9580 
9581 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
9582 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL  = 0x00000000,
9583 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6  = 0x00000001,
9584 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5  = 0x00000002,
9585 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4  = 0x00000003,
9586 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3  = 0x00000004,
9587 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2  = 0x00000005,
9588 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1  = 0x00000006,
9589 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0  = 0x00000007,
9590 } CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
9591 
9592 /*
9593  * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
9594  */
9595 
9596 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
9597 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL  = 0x00000000,
9598 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6  = 0x00000001,
9599 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5  = 0x00000002,
9600 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4  = 0x00000003,
9601 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3  = 0x00000004,
9602 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2  = 0x00000005,
9603 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1  = 0x00000006,
9604 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0  = 0x00000007,
9605 } CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
9606 
9607 /*******************************************************
9608  * AZINPUTENDPOINT Enums
9609  *******************************************************/
9610 
9611 /*
9612  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
9613  */
9614 
9615 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
9616 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
9617 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
9618 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
9619 
9620 /*
9621  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
9622  */
9623 
9624 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
9625 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
9626 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
9627 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
9628 
9629 /*
9630  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
9631  */
9632 
9633 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
9634 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
9635 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
9636 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
9637 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
9638 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
9639 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
9640 
9641 /*
9642  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
9643  */
9644 
9645 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
9646 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
9647 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
9648 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
9649 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
9650 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
9651 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
9652 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
9653 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
9654 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
9655 
9656 /*
9657  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
9658  */
9659 
9660 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
9661 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
9662 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
9663 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
9664 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
9665 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
9666 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
9667 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
9668 
9669 /*
9670  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
9671  */
9672 
9673 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
9674 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
9675 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
9676 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
9677 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
9678 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
9679 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
9680 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
9681 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
9682 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
9683 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
9684 
9685 /*
9686  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
9687  */
9688 
9689 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
9690 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
9691 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
9692 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
9693 
9694 /*
9695  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
9696  */
9697 
9698 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
9699 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF  = 0x00000000,
9700 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN  = 0x00000001,
9701 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
9702 
9703 /*
9704  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
9705  */
9706 
9707 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
9708 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
9709 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
9710 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
9711 
9712 /*
9713  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
9714  */
9715 
9716 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
9717 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED  = 0x00000000,
9718 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED  = 0x00000001,
9719 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
9720 
9721 /*
9722  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
9723  */
9724 
9725 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
9726 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
9727 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
9728 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
9729 
9730 /*
9731  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
9732  */
9733 
9734 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
9735 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED  = 0x00000000,
9736 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED  = 0x00000001,
9737 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
9738 
9739 /*
9740  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
9741  */
9742 
9743 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
9744 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
9745 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
9746 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
9747 
9748 /*
9749  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
9750  */
9751 
9752 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
9753 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED  = 0x00000000,
9754 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED  = 0x00000001,
9755 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
9756 
9757 /*
9758  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
9759  */
9760 
9761 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
9762 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
9763 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
9764 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
9765 
9766 /*
9767  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
9768  */
9769 
9770 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
9771 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED  = 0x00000000,
9772 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED  = 0x00000001,
9773 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
9774 
9775 /*
9776  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
9777  */
9778 
9779 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
9780 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
9781 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
9782 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
9783 
9784 /*******************************************************
9785  * AZROOT Enums
9786  *******************************************************/
9787 
9788 /*
9789  * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
9790  */
9791 
9792 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
9793 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET  = 0x00000000,
9794 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET  = 0x00000001,
9795 } AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
9796 
9797 /*******************************************************
9798  * AZF0STREAM Enums
9799  *******************************************************/
9800 
9801 /*
9802  * AZ_LATENCY_COUNTER_CONTROL enum
9803  */
9804 
9805 typedef enum AZ_LATENCY_COUNTER_CONTROL {
9806 AZ_LATENCY_COUNTER_NO_RESET              = 0x00000000,
9807 AZ_LATENCY_COUNTER_RESET_DONE            = 0x00000001,
9808 } AZ_LATENCY_COUNTER_CONTROL;
9809 
9810 /*******************************************************
9811  * AZSTREAM Enums
9812  *******************************************************/
9813 
9814 /*
9815  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
9816  */
9817 
9818 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
9819 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET  = 0x00000000,
9820 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET  = 0x00000001,
9821 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
9822 
9823 /*
9824  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
9825  */
9826 
9827 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
9828 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET  = 0x00000000,
9829 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET  = 0x00000001,
9830 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
9831 
9832 /*
9833  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
9834  */
9835 
9836 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
9837 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET  = 0x00000000,
9838 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET  = 0x00000001,
9839 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
9840 
9841 /*
9842  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
9843  */
9844 
9845 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
9846 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY  = 0x00000000,
9847 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY  = 0x00000001,
9848 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
9849 
9850 /*
9851  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
9852  */
9853 
9854 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
9855 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED  = 0x00000000,
9856 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED  = 0x00000001,
9857 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
9858 
9859 /*
9860  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
9861  */
9862 
9863 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
9864 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED  = 0x00000000,
9865 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED  = 0x00000001,
9866 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
9867 
9868 /*
9869  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
9870  */
9871 
9872 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
9873 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED  = 0x00000000,
9874 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED  = 0x00000001,
9875 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
9876 
9877 /*
9878  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
9879  */
9880 
9881 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
9882 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN  = 0x00000000,
9883 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN  = 0x00000001,
9884 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
9885 
9886 /*
9887  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
9888  */
9889 
9890 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
9891 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET  = 0x00000000,
9892 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET  = 0x00000001,
9893 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
9894 
9895 /*
9896  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
9897  */
9898 
9899 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
9900 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
9901 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
9902 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
9903 
9904 /*
9905  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
9906  */
9907 
9908 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
9909 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
9910 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
9911 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
9912 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
9913 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
9914 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
9915 
9916 /*
9917  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
9918  */
9919 
9920 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
9921 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
9922 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
9923 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
9924 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
9925 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
9926 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
9927 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
9928 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
9929 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
9930 
9931 /*
9932  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
9933  */
9934 
9935 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
9936 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
9937 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
9938 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
9939 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
9940 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
9941 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
9942 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
9943 
9944 /*
9945  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
9946  */
9947 
9948 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
9949 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
9950 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
9951 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
9952 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
9953 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
9954 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
9955 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
9956 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
9957 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED  = 0x00000008,
9958 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED  = 0x00000009,
9959 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED  = 0x0000000a,
9960 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED  = 0x0000000b,
9961 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED  = 0x0000000c,
9962 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED  = 0x0000000d,
9963 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED  = 0x0000000e,
9964 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED  = 0x0000000f,
9965 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
9966 
9967 /*******************************************************
9968  * AZF0ENDPOINT Enums
9969  *******************************************************/
9970 
9971 /*
9972  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
9973  */
9974 
9975 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
9976 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
9977 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
9978 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
9979 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
9980 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
9981 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
9982 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
9983 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
9984 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
9985 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
9986 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
9987 
9988 /*
9989  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
9990  */
9991 
9992 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
9993 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
9994 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
9995 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
9996 
9997 /*
9998  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
9999  */
10000 
10001 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10002 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
10003 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
10004 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10005 
10006 /*
10007  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10008  */
10009 
10010 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10011 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
10012 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
10013 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10014 
10015 /*
10016  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10017  */
10018 
10019 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10020 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
10021 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
10022 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10023 
10024 /*
10025  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10026  */
10027 
10028 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10029 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
10030 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
10031 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10032 
10033 /*
10034  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10035  */
10036 
10037 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10038 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
10039 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
10040 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10041 
10042 /*
10043  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10044  */
10045 
10046 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10047 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
10048 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
10049 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10050 
10051 /*
10052  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
10053  */
10054 
10055 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
10056 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
10057 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE  = 0x00000001,
10058 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
10059 
10060 /*
10061  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10062  */
10063 
10064 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10065 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
10066 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
10067 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10068 
10069 /*
10070  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10071  */
10072 
10073 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10074 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
10075 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
10076 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10077 
10078 /*
10079  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10080  */
10081 
10082 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10083 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
10084 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
10085 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10086 
10087 /*
10088  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
10089  */
10090 
10091 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
10092 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
10093 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
10094 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
10095 
10096 /*
10097  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10098  */
10099 
10100 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10101 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
10102 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
10103 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
10104 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
10105 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
10106 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
10107 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
10108 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
10109 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
10110 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
10111 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
10112 
10113 /*
10114  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10115  */
10116 
10117 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10118 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
10119 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
10120 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
10121 
10122 /*
10123  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10124  */
10125 
10126 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10127 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
10128 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
10129 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10130 
10131 /*
10132  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10133  */
10134 
10135 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10136 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
10137 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
10138 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10139 
10140 /*
10141  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10142  */
10143 
10144 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10145 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
10146 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
10147 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10148 
10149 /*
10150  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10151  */
10152 
10153 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10154 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
10155 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
10156 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10157 
10158 /*
10159  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10160  */
10161 
10162 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10163 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
10164 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
10165 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10166 
10167 /*
10168  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10169  */
10170 
10171 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10172 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
10173 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
10174 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10175 
10176 /*
10177  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10178  */
10179 
10180 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10181 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
10182 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
10183 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10184 
10185 /*
10186  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10187  */
10188 
10189 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10190 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
10191 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
10192 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10193 
10194 /*
10195  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10196  */
10197 
10198 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10199 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT  = 0x00000000,
10200 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
10201 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10202 
10203 /*
10204  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
10205  */
10206 
10207 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
10208 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN  = 0x00000000,
10209 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN  = 0x00000001,
10210 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
10211 
10212 /*
10213  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
10214  */
10215 
10216 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
10217 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED  = 0x00000000,
10218 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
10219 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
10220 
10221 /*
10222  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
10223  */
10224 
10225 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
10226 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
10227 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
10228 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
10229 
10230 /*
10231  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
10232  */
10233 
10234 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
10235 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
10236 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
10237 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
10238 
10239 /*
10240  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
10241  */
10242 
10243 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
10244 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
10245 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
10246 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
10247 
10248 /*
10249  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
10250  */
10251 
10252 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
10253 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY  = 0x00000000,
10254 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY  = 0x00000001,
10255 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
10256 
10257 /*
10258  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
10259  */
10260 
10261 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
10262 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
10263 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
10264 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
10265 
10266 /*
10267  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
10268  */
10269 
10270 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
10271 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
10272 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
10273 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
10274 
10275 /*
10276  * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10277  */
10278 
10279 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10280 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
10281 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
10282 } AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10283 
10284 /*
10285  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
10286  */
10287 
10288 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
10289 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY  = 0x00000000,
10290 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY  = 0x00000001,
10291 } AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
10292 
10293 /*******************************************************
10294  * AZF0INPUTENDPOINT Enums
10295  *******************************************************/
10296 
10297 /*
10298  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10299  */
10300 
10301 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10302 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
10303 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
10304 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
10305 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
10306 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
10307 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
10308 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
10309 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
10310 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
10311 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
10312 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
10313 
10314 /*
10315  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10316  */
10317 
10318 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10319 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
10320 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
10321 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
10322 
10323 /*
10324  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10325  */
10326 
10327 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10328 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
10329 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
10330 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10331 
10332 /*
10333  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10334  */
10335 
10336 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10337 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG  = 0x00000000,
10338 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL  = 0x00000001,
10339 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10340 
10341 /*
10342  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10343  */
10344 
10345 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10346 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
10347 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
10348 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10349 
10350 /*
10351  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10352  */
10353 
10354 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10355 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
10356 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
10357 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10358 
10359 /*
10360  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10361  */
10362 
10363 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10364 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES  = 0x00000000,
10365 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
10366 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10367 
10368 /*
10369  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10370  */
10371 
10372 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10373 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING  = 0x00000000,
10374 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
10375 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10376 
10377 /*
10378  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
10379  */
10380 
10381 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
10382 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
10383 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE  = 0x00000001,
10384 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
10385 
10386 /*
10387  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10388  */
10389 
10390 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10391 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
10392 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER  = 0x00000001,
10393 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10394 
10395 /*
10396  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10397  */
10398 
10399 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10400 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
10401 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
10402 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10403 
10404 /*
10405  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10406  */
10407 
10408 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10409 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
10410 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
10411 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10412 
10413 /*
10414  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
10415  */
10416 
10417 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
10418 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
10419 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
10420 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
10421 
10422 /*
10423  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10424  */
10425 
10426 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10427 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
10428 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
10429 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
10430 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
10431 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
10432 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
10433 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
10434 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
10435 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
10436 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
10437 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
10438 
10439 /*
10440  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10441  */
10442 
10443 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10444 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP  = 0x00000000,
10445 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP  = 0x00000001,
10446 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
10447 
10448 /*
10449  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10450  */
10451 
10452 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10453 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
10454 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
10455 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10456 
10457 /*
10458  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10459  */
10460 
10461 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10462 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
10463 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
10464 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10465 
10466 /*
10467  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10468  */
10469 
10470 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10471 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
10472 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
10473 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10474 
10475 /*
10476  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10477  */
10478 
10479 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10480 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
10481 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
10482 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10483 
10484 /*
10485  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10486  */
10487 
10488 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10489 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES  = 0x00000000,
10490 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES  = 0x00000001,
10491 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10492 
10493 /*
10494  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10495  */
10496 
10497 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10498 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
10499 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
10500 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10501 
10502 /*
10503  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10504  */
10505 
10506 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10507 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
10508 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
10509 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10510 
10511 /*
10512  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10513  */
10514 
10515 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10516 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
10517 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
10518 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10519 
10520 /*
10521  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10522  */
10523 
10524 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10525 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
10526 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
10527 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10528 
10529 /*
10530  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
10531  */
10532 
10533 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
10534 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED  = 0x00000000,
10535 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED  = 0x00000001,
10536 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
10537 
10538 /*
10539  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
10540  */
10541 
10542 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
10543 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN  = 0x00000000,
10544 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN  = 0x00000001,
10545 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
10546 
10547 /*
10548  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
10549  */
10550 
10551 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
10552 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED  = 0x00000000,
10553 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED  = 0x00000001,
10554 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
10555 
10556 /*
10557  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
10558  */
10559 
10560 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
10561 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED  = 0x00000000,
10562 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
10563 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
10564 
10565 /*
10566  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
10567  */
10568 
10569 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
10570 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
10571 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
10572 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
10573 
10574 /*
10575  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
10576  */
10577 
10578 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
10579 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
10580 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
10581 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
10582 
10583 /*
10584  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
10585  */
10586 
10587 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
10588 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
10589 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
10590 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
10591 
10592 /*
10593  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
10594  */
10595 
10596 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
10597 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000000,
10598 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000001,
10599 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
10600 
10601 /*
10602  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
10603  */
10604 
10605 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
10606 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
10607 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
10608 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
10609 
10610 /*
10611  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
10612  */
10613 
10614 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
10615 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
10616 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
10617 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
10618 
10619 /*
10620  * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
10621  */
10622 
10623 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
10624 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY  = 0x00000000,
10625 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY  = 0x00000001,
10626 } AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
10627 
10628 /*******************************************************
10629  * DSCC Enums
10630  *******************************************************/
10631 
10632 /*
10633  * DSCC_ICH_RESET_ENUM enum
10634  */
10635 
10636 typedef enum DSCC_ICH_RESET_ENUM {
10637 DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET     = 0x00000001,
10638 DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET     = 0x00000002,
10639 DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET     = 0x00000004,
10640 DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET     = 0x00000008,
10641 } DSCC_ICH_RESET_ENUM;
10642 
10643 /*
10644  * DSCC_DSC_VERSION_MINOR_ENUM enum
10645  */
10646 
10647 typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
10648 DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION  = 0x00000001,
10649 DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION  = 0x00000002,
10650 } DSCC_DSC_VERSION_MINOR_ENUM;
10651 
10652 /*
10653  * DSCC_DSC_VERSION_MAJOR_ENUM enum
10654  */
10655 
10656 typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
10657 DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION  = 0x00000001,
10658 } DSCC_DSC_VERSION_MAJOR_ENUM;
10659 
10660 /*
10661  * DSCC_LINEBUF_DEPTH_ENUM enum
10662  */
10663 
10664 typedef enum DSCC_LINEBUF_DEPTH_ENUM {
10665 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT  = 0x00000008,
10666 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT  = 0x00000009,
10667 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT  = 0x0000000a,
10668 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT  = 0x0000000b,
10669 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT  = 0x0000000c,
10670 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT  = 0x0000000d,
10671 } DSCC_LINEBUF_DEPTH_ENUM;
10672 
10673 /*
10674  * DSCC_BITS_PER_COMPONENT_ENUM enum
10675  */
10676 
10677 typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
10678 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT  = 0x00000008,
10679 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT  = 0x0000000a,
10680 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT  = 0x0000000c,
10681 } DSCC_BITS_PER_COMPONENT_ENUM;
10682 
10683 /*
10684  * DSCC_ENABLE_ENUM enum
10685  */
10686 
10687 typedef enum DSCC_ENABLE_ENUM {
10688 DSCC_ENABLE_ENUM_DISABLED                = 0x00000000,
10689 DSCC_ENABLE_ENUM_ENABLED                 = 0x00000001,
10690 } DSCC_ENABLE_ENUM;
10691 
10692 /*
10693  * DSCC_MEM_PWR_FORCE_ENUM enum
10694  */
10695 
10696 typedef enum DSCC_MEM_PWR_FORCE_ENUM {
10697 DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST  = 0x00000000,
10698 DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST  = 0x00000001,
10699 DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST  = 0x00000002,
10700 DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST  = 0x00000003,
10701 } DSCC_MEM_PWR_FORCE_ENUM;
10702 
10703 /*
10704  * POWER_STATE_ENUM enum
10705  */
10706 
10707 typedef enum POWER_STATE_ENUM {
10708 POWER_STATE_ENUM_ON                      = 0x00000000,
10709 POWER_STATE_ENUM_LS                      = 0x00000001,
10710 POWER_STATE_ENUM_DS                      = 0x00000002,
10711 POWER_STATE_ENUM_SD                      = 0x00000003,
10712 } POWER_STATE_ENUM;
10713 
10714 /*
10715  * DSCC_MEM_PWR_DIS_ENUM enum
10716  */
10717 
10718 typedef enum DSCC_MEM_PWR_DIS_ENUM {
10719 DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN         = 0x00000000,
10720 DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS        = 0x00000001,
10721 } DSCC_MEM_PWR_DIS_ENUM;
10722 
10723 /*******************************************************
10724  * DSCCIF Enums
10725  *******************************************************/
10726 
10727 /*
10728  * DSCCIF_ENABLE_ENUM enum
10729  */
10730 
10731 typedef enum DSCCIF_ENABLE_ENUM {
10732 DSCCIF_ENABLE_ENUM_DISABLED              = 0x00000000,
10733 DSCCIF_ENABLE_ENUM_ENABLED               = 0x00000001,
10734 } DSCCIF_ENABLE_ENUM;
10735 
10736 /*
10737  * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
10738  */
10739 
10740 typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
10741 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB       = 0x00000000,
10742 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444  = 0x00000001,
10743 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422  = 0x00000002,
10744 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422  = 0x00000003,
10745 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420  = 0x00000004,
10746 } DSCCIF_INPUT_PIXEL_FORMAT_ENUM;
10747 
10748 /*
10749  * DSCCIF_BITS_PER_COMPONENT_ENUM enum
10750  */
10751 
10752 typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
10753 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT  = 0x00000008,
10754 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT  = 0x0000000a,
10755 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT  = 0x0000000c,
10756 } DSCCIF_BITS_PER_COMPONENT_ENUM;
10757 
10758 /*******************************************************
10759  * DSC_TOP Enums
10760  *******************************************************/
10761 
10762 /*
10763  * ENABLE_ENUM enum
10764  */
10765 
10766 typedef enum ENABLE_ENUM {
10767 ENABLE_ENUM_DISABLED                     = 0x00000000,
10768 ENABLE_ENUM_ENABLED                      = 0x00000001,
10769 } ENABLE_ENUM;
10770 
10771 /*
10772  * CLOCK_GATING_DISABLE_ENUM enum
10773  */
10774 
10775 typedef enum CLOCK_GATING_DISABLE_ENUM {
10776 CLOCK_GATING_DISABLE_ENUM_ENABLED        = 0x00000000,
10777 CLOCK_GATING_DISABLE_ENUM_DISABLED       = 0x00000001,
10778 } CLOCK_GATING_DISABLE_ENUM;
10779 
10780 /*
10781  * TEST_CLOCK_MUX_SELECT_ENUM enum
10782  */
10783 
10784 typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
10785 TEST_CLOCK_MUX_SELECT_DISPCLK_P          = 0x00000000,
10786 TEST_CLOCK_MUX_SELECT_DISPCLK_G          = 0x00000001,
10787 TEST_CLOCK_MUX_SELECT_DISPCLK_R          = 0x00000002,
10788 TEST_CLOCK_MUX_SELECT_DSCCLK_P           = 0x00000003,
10789 TEST_CLOCK_MUX_SELECT_DSCCLK_G           = 0x00000004,
10790 TEST_CLOCK_MUX_SELECT_DSCCLK_R           = 0x00000005,
10791 } TEST_CLOCK_MUX_SELECT_ENUM;
10792 
10793 /*******************************************************
10794  * CNV Enums
10795  *******************************************************/
10796 
10797 /*
10798  * WB_ENABLE_ENUM enum
10799  */
10800 
10801 typedef enum WB_ENABLE_ENUM {
10802 WB_EN_DISABLE                            = 0x00000000,
10803 WB_EN_ENABLE                             = 0x00000001,
10804 } WB_ENABLE_ENUM;
10805 
10806 /*
10807  * WB_CLK_GATE_DIS_ENUM enum
10808  */
10809 
10810 typedef enum WB_CLK_GATE_DIS_ENUM {
10811 WB_CLK_GATE_ENABLE                       = 0x00000000,
10812 WB_CLK_GATE_DISABLE                      = 0x00000001,
10813 } WB_CLK_GATE_DIS_ENUM;
10814 
10815 /*
10816  * WB_MEM_PWR_DIS_ENUM enum
10817  */
10818 
10819 typedef enum WB_MEM_PWR_DIS_ENUM {
10820 WB_MEM_PWR_ENABLE                        = 0x00000000,
10821 WB_MEM_PWR_DISABLE                       = 0x00000001,
10822 } WB_MEM_PWR_DIS_ENUM;
10823 
10824 /*
10825  * WB_TEST_CLK_SEL_ENUM enum
10826  */
10827 
10828 typedef enum WB_TEST_CLK_SEL_ENUM {
10829 WB_TEST_CLK_SEL_REG                      = 0x00000000,
10830 WB_TEST_CLK_SEL_WB                       = 0x00000001,
10831 WB_TEST_CLK_SEL_WBSCL                    = 0x00000002,
10832 WB_TEST_CLK_SEL_PERM                     = 0x00000003,
10833 } WB_TEST_CLK_SEL_ENUM;
10834 
10835 /*
10836  * WBSCL_LB_MEM_PWR_MODE_SEL_ENUM enum
10837  */
10838 
10839 typedef enum WBSCL_LB_MEM_PWR_MODE_SEL_ENUM {
10840 WBSCL_LB_MEM_PWR_MODE_SEL_SD             = 0x00000000,
10841 WBSCL_LB_MEM_PWR_MODE_SEL_DS             = 0x00000001,
10842 WBSCL_LB_MEM_PWR_MODE_SEL_LS             = 0x00000002,
10843 WBSCL_LB_MEM_PWR_MODE_SEL_ON             = 0x00000003,
10844 } WBSCL_LB_MEM_PWR_MODE_SEL_ENUM;
10845 
10846 /*
10847  * WBSCL_LB_MEM_PWR_FORCE_ENUM enum
10848  */
10849 
10850 typedef enum WBSCL_LB_MEM_PWR_FORCE_ENUM {
10851 WBSCL_LB_MEM_PWR_FORCE_NO                = 0x00000000,
10852 WBSCL_LB_MEM_PWR_FORCE_LS                = 0x00000001,
10853 WBSCL_LB_MEM_PWR_FORCE_DS                = 0x00000002,
10854 WBSCL_LB_MEM_PWR_FORCE_SD                = 0x00000003,
10855 } WBSCL_LB_MEM_PWR_FORCE_ENUM;
10856 
10857 /*
10858  * WBSCL_MEM_PWR_STATE_ENUM enum
10859  */
10860 
10861 typedef enum WBSCL_MEM_PWR_STATE_ENUM {
10862 WBSCL_MEM_PWR_STATE_ON                   = 0x00000000,
10863 WBSCL_MEM_PWR_STATE_LS                   = 0x00000001,
10864 WBSCL_MEM_PWR_STATE_DS                   = 0x00000002,
10865 WBSCL_MEM_PWR_STATE_SD                   = 0x00000003,
10866 } WBSCL_MEM_PWR_STATE_ENUM;
10867 
10868 /*
10869  * WBSCL_LUT_MEM_PWR_STATE_ENUM enum
10870  */
10871 
10872 typedef enum WBSCL_LUT_MEM_PWR_STATE_ENUM {
10873 WBSCL_LUT_MEM_PWR_STATE_ON               = 0x00000000,
10874 WBSCL_LUT_MEM_PWR_STATE_LS               = 0x00000001,
10875 WBSCL_LUT_MEM_PWR_STATE_RESERVED2        = 0x00000002,
10876 WBSCL_LUT_MEM_PWR_STATE_RESERVED3        = 0x00000003,
10877 } WBSCL_LUT_MEM_PWR_STATE_ENUM;
10878 
10879 /*
10880  * WB_RAM_PW_SAVE_MODE_ENUM enum
10881  */
10882 
10883 typedef enum WB_RAM_PW_SAVE_MODE_ENUM {
10884 WB_RAM_PW_SAVE_MODE_LS                   = 0x00000000,
10885 WB_RAM_PW_SAVE_MODE_SD                   = 0x00000001,
10886 } WB_RAM_PW_SAVE_MODE_ENUM;
10887 
10888 /*
10889  * CNV_OUT_BPC_ENUM enum
10890  */
10891 
10892 typedef enum CNV_OUT_BPC_ENUM {
10893 CNV_OUT_BPC_8BPC                         = 0x00000000,
10894 CNV_OUT_BPC_10BPC                        = 0x00000001,
10895 } CNV_OUT_BPC_ENUM;
10896 
10897 /*
10898  * CNV_FRAME_CAPTURE_RATE_ENUM enum
10899  */
10900 
10901 typedef enum CNV_FRAME_CAPTURE_RATE_ENUM {
10902 CNV_FRAME_CAPTURE_RATE_0                 = 0x00000000,
10903 CNV_FRAME_CAPTURE_RATE_1                 = 0x00000001,
10904 CNV_FRAME_CAPTURE_RATE_2                 = 0x00000002,
10905 CNV_FRAME_CAPTURE_RATE_3                 = 0x00000003,
10906 } CNV_FRAME_CAPTURE_RATE_ENUM;
10907 
10908 /*
10909  * CNV_WINDOW_CROP_EN_ENUM enum
10910  */
10911 
10912 typedef enum CNV_WINDOW_CROP_EN_ENUM {
10913 CNV_WINDOW_CROP_DISABLE                  = 0x00000000,
10914 CNV_WINDOW_CROP_ENABLE                   = 0x00000001,
10915 } CNV_WINDOW_CROP_EN_ENUM;
10916 
10917 /*
10918  * CNV_INTERLACED_MODE_ENUM enum
10919  */
10920 
10921 typedef enum CNV_INTERLACED_MODE_ENUM {
10922 CNV_INTERLACED_MODE_PROGRESSIVE          = 0x00000000,
10923 CNV_INTERLACED_MODE_INTERLACED           = 0x00000001,
10924 } CNV_INTERLACED_MODE_ENUM;
10925 
10926 /*
10927  * CNV_EYE_SELECT enum
10928  */
10929 
10930 typedef enum CNV_EYE_SELECT {
10931 STEREO_DISABLED                          = 0x00000000,
10932 LEFT_EYE                                 = 0x00000001,
10933 RIGHT_EYE                                = 0x00000002,
10934 BOTH_EYE                                 = 0x00000003,
10935 } CNV_EYE_SELECT;
10936 
10937 /*
10938  * CNV_STEREO_TYPE_ENUM enum
10939  */
10940 
10941 typedef enum CNV_STEREO_TYPE_ENUM {
10942 CNV_STEREO_TYPE_RESERVED0                = 0x00000000,
10943 CNV_STEREO_TYPE_RESERVED1                = 0x00000001,
10944 CNV_STEREO_TYPE_RESERVED2                = 0x00000002,
10945 CNV_STEREO_TYPE_FRAME_SEQUENTIAL         = 0x00000003,
10946 } CNV_STEREO_TYPE_ENUM;
10947 
10948 /*
10949  * CNV_STEREO_POLARITY_ENUM enum
10950  */
10951 
10952 typedef enum CNV_STEREO_POLARITY_ENUM {
10953 CNV_STEREO_POLARITY_LEFT                 = 0x00000000,
10954 CNV_STEREO_POLARITY_RIGHT                = 0x00000001,
10955 } CNV_STEREO_POLARITY_ENUM;
10956 
10957 /*
10958  * CNV_INTERLACED_FIELD_ORDER_ENUM enum
10959  */
10960 
10961 typedef enum CNV_INTERLACED_FIELD_ORDER_ENUM {
10962 CNV_INTERLACED_FIELD_ORDER_TOP           = 0x00000000,
10963 CNV_INTERLACED_FIELD_ORDER_BOT           = 0x00000001,
10964 } CNV_INTERLACED_FIELD_ORDER_ENUM;
10965 
10966 /*
10967  * CNV_STEREO_SPLIT_ENUM enum
10968  */
10969 
10970 typedef enum CNV_STEREO_SPLIT_ENUM {
10971 CNV_STEREO_SPLIT_DISABLE                 = 0x00000000,
10972 CNV_STEREO_SPLIT_ENABLE                  = 0x00000001,
10973 } CNV_STEREO_SPLIT_ENUM;
10974 
10975 /*
10976  * CNV_NEW_CONTENT_ENUM enum
10977  */
10978 
10979 typedef enum CNV_NEW_CONTENT_ENUM {
10980 CNV_NEW_CONTENT_NEG                      = 0x00000000,
10981 CNV_NEW_CONTENT_POS                      = 0x00000001,
10982 } CNV_NEW_CONTENT_ENUM;
10983 
10984 /*
10985  * CNV_FRAME_CAPTURE_EN_ENUM enum
10986  */
10987 
10988 typedef enum CNV_FRAME_CAPTURE_EN_ENUM {
10989 CNV_FRAME_CAPTURE_DISABLE                = 0x00000000,
10990 CNV_FRAME_CAPTURE_ENABLE                 = 0x00000001,
10991 } CNV_FRAME_CAPTURE_EN_ENUM;
10992 
10993 /*
10994  * CNV_UPDATE_PENDING_ENUM enum
10995  */
10996 
10997 typedef enum CNV_UPDATE_PENDING_ENUM {
10998 CNV_UPDATE_PENDING_NEG                   = 0x00000000,
10999 CNV_UPDATE_PENDING_POS                   = 0x00000001,
11000 } CNV_UPDATE_PENDING_ENUM;
11001 
11002 /*
11003  * CNV_UPDATE_LOCK_ENUM enum
11004  */
11005 
11006 typedef enum CNV_UPDATE_LOCK_ENUM {
11007 CNV_UPDATE_UNLOCK                        = 0x00000000,
11008 CNV_UPDATE_LOCK                          = 0x00000001,
11009 } CNV_UPDATE_LOCK_ENUM;
11010 
11011 /*
11012  * CNV_CSC_BYPASS_ENUM enum
11013  */
11014 
11015 typedef enum CNV_CSC_BYPASS_ENUM {
11016 CNV_CSC_BYPASS_NEG                       = 0x00000000,
11017 CNV_CSC_BYPASS_POS                       = 0x00000001,
11018 } CNV_CSC_BYPASS_ENUM;
11019 
11020 /*
11021  * CNV_TEST_CRC_EN_ENUM enum
11022  */
11023 
11024 typedef enum CNV_TEST_CRC_EN_ENUM {
11025 CNV_TEST_CRC_DISABLE                     = 0x00000000,
11026 CNV_TEST_CRC_ENABLE                      = 0x00000001,
11027 } CNV_TEST_CRC_EN_ENUM;
11028 
11029 /*
11030  * CNV_TEST_CRC_CONT_EN_ENUM enum
11031  */
11032 
11033 typedef enum CNV_TEST_CRC_CONT_EN_ENUM {
11034 CNV_TEST_CRC_CONT_DISABLE                = 0x00000000,
11035 CNV_TEST_CRC_CONT_ENABLE                 = 0x00000001,
11036 } CNV_TEST_CRC_CONT_EN_ENUM;
11037 
11038 /*
11039  * WB_SOFT_RESET_ENUM enum
11040  */
11041 
11042 typedef enum WB_SOFT_RESET_ENUM {
11043 WB_SOFT_RESET_NEG                        = 0x00000000,
11044 WB_SOFT_RESET_POS                        = 0x00000001,
11045 } WB_SOFT_RESET_ENUM;
11046 
11047 /*
11048  * DWB_GMC_WARM_UP_ENABLE_ENUM enum
11049  */
11050 
11051 typedef enum DWB_GMC_WARM_UP_ENABLE_ENUM {
11052 DWB_GMC_WARM_UP_DISABLE                  = 0x00000000,
11053 DWB_GMC_WARM_UP_ENABLE                   = 0x00000001,
11054 } DWB_GMC_WARM_UP_ENABLE_ENUM;
11055 
11056 /*
11057  * DWB_MODE_WARMUP_ENUM enum
11058  */
11059 
11060 typedef enum DWB_MODE_WARMUP_ENUM {
11061 DWB_MODE_WARMUP_420                      = 0x00000000,
11062 DWB_MODE_WARMUP_444                      = 0x00000001,
11063 } DWB_MODE_WARMUP_ENUM;
11064 
11065 /*
11066  * DWB_DATA_DEPTH_WARMUP_ENUM enum
11067  */
11068 
11069 typedef enum DWB_DATA_DEPTH_WARMUP_ENUM {
11070 DWB_DATA_DEPTH_WARMUP_8BPC               = 0x00000000,
11071 DWB_DATA_DEPTH_WARMUP_10BPC              = 0x00000001,
11072 } DWB_DATA_DEPTH_WARMUP_ENUM;
11073 
11074 /*******************************************************
11075  * WBSCL Enums
11076  *******************************************************/
11077 
11078 /*
11079  * WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM enum
11080  */
11081 
11082 typedef enum WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM {
11083 WBSCL_COEF_RAM_TAP_PAIR_IDX0             = 0x00000000,
11084 WBSCL_COEF_RAM_TAP_PAIR_IDX1             = 0x00000001,
11085 WBSCL_COEF_RAM_TAP_PAIR_IDX2             = 0x00000002,
11086 WBSCL_COEF_RAM_TAP_PAIR_IDX3             = 0x00000003,
11087 WBSCL_COEF_RAM_TAP_PAIR_IDX4             = 0x00000004,
11088 WBSCL_COEF_RAM_TAP_PAIR_IDX5             = 0x00000005,
11089 } WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM;
11090 
11091 /*
11092  * WBSCL_COEF_RAM_PHASE_ENUM enum
11093  */
11094 
11095 typedef enum WBSCL_COEF_RAM_PHASE_ENUM {
11096 WBSCL_COEF_RAM_PHASE0                    = 0x00000000,
11097 WBSCL_COEF_RAM_PHASE1                    = 0x00000001,
11098 WBSCL_COEF_RAM_PHASE2                    = 0x00000002,
11099 WBSCL_COEF_RAM_PHASE3                    = 0x00000003,
11100 WBSCL_COEF_RAM_PHASE4                    = 0x00000004,
11101 WBSCL_COEF_RAM_PHASE5                    = 0x00000005,
11102 WBSCL_COEF_RAM_PHASE6                    = 0x00000006,
11103 WBSCL_COEF_RAM_PHASE7                    = 0x00000007,
11104 WBSCL_COEF_RAM_PHASE8                    = 0x00000008,
11105 } WBSCL_COEF_RAM_PHASE_ENUM;
11106 
11107 /*
11108  * WBSCL_COEF_RAM_FILTER_TYPE_ENUM enum
11109  */
11110 
11111 typedef enum WBSCL_COEF_RAM_FILTER_TYPE_ENUM {
11112 WBSCL_COEF_RAM_FILTER_TYPE_VL            = 0x00000000,
11113 WBSCL_COEF_RAM_FILTER_TYPE_VC            = 0x00000001,
11114 WBSCL_COEF_RAM_FILTER_TYPE_HL            = 0x00000002,
11115 WBSCL_COEF_RAM_FILTER_TYPE_HC            = 0x00000003,
11116 } WBSCL_COEF_RAM_FILTER_TYPE_ENUM;
11117 
11118 /*
11119  * WBSCL_COEF_FILTER_TYPE_SEL enum
11120  */
11121 
11122 typedef enum WBSCL_COEF_FILTER_TYPE_SEL {
11123 WBSCL_COEF_LUMA_VERT_FILTER              = 0x00000000,
11124 WBSCL_COEF_CHROMA_VERT_FILTER            = 0x00000001,
11125 WBSCL_COEF_LUMA_HORZ_FILTER              = 0x00000002,
11126 WBSCL_COEF_CHROMA_HORZ_FILTER            = 0x00000003,
11127 } WBSCL_COEF_FILTER_TYPE_SEL;
11128 
11129 /*
11130  * WBSCL_MODE_SEL enum
11131  */
11132 
11133 typedef enum WBSCL_MODE_SEL {
11134 WBSCL_MODE_SCALING_444_BYPASS            = 0x00000000,
11135 WBSCL_MODE_SCALING_444_RGB_ENABLE        = 0x00000001,
11136 WBSCL_MODE_SCALING_444_YCBCR_ENABLE      = 0x00000002,
11137 WBSCL_MODE_SCALING_YCBCR_ENABLE          = 0x00000003,
11138 } WBSCL_MODE_SEL;
11139 
11140 /*
11141  * WBSCL_PIXEL_DEPTH enum
11142  */
11143 
11144 typedef enum WBSCL_PIXEL_DEPTH {
11145 PIXEL_DEPTH_8BPC                         = 0x00000000,
11146 PIXEL_DEPTH_10BPC                        = 0x00000001,
11147 } WBSCL_PIXEL_DEPTH;
11148 
11149 /*
11150  * WBSCL_COEF_RAM_SEL_ENUM enum
11151  */
11152 
11153 typedef enum WBSCL_COEF_RAM_SEL_ENUM {
11154 WBSCL_COEF_RAM_SEL_0                     = 0x00000000,
11155 WBSCL_COEF_RAM_SEL_1                     = 0x00000001,
11156 } WBSCL_COEF_RAM_SEL_ENUM;
11157 
11158 /*
11159  * WBSCL_COEF_RAM_RD_SEL_ENUM enum
11160  */
11161 
11162 typedef enum WBSCL_COEF_RAM_RD_SEL_ENUM {
11163 WBSCL_COEF_RAM_RD_SEL_0                  = 0x00000000,
11164 WBSCL_COEF_RAM_RD_SEL_1                  = 0x00000001,
11165 } WBSCL_COEF_RAM_RD_SEL_ENUM;
11166 
11167 /*
11168  * WBSCL_COEF_RAM_TAP_COEF_EN_ENUM enum
11169  */
11170 
11171 typedef enum WBSCL_COEF_RAM_TAP_COEF_EN_ENUM {
11172 WBSCL_COEF_RAM_TAP_COEF_DISABLE          = 0x00000000,
11173 WBSCL_COEF_RAM_TAP_COEF_ENABLE           = 0x00000001,
11174 } WBSCL_COEF_RAM_TAP_COEF_EN_ENUM;
11175 
11176 /*
11177  * WBSCL_NUM_OF_TAPS_ENUM enum
11178  */
11179 
11180 typedef enum WBSCL_NUM_OF_TAPS_ENUM {
11181 WBSCL_NUM_OF_TAPS0                       = 0x00000000,
11182 WBSCL_NUM_OF_TAPS1                       = 0x00000001,
11183 WBSCL_NUM_OF_TAPS2                       = 0x00000002,
11184 WBSCL_NUM_OF_TAPS3                       = 0x00000003,
11185 WBSCL_NUM_OF_TAPS4                       = 0x00000004,
11186 WBSCL_NUM_OF_TAPS5                       = 0x00000005,
11187 WBSCL_NUM_OF_TAPS6                       = 0x00000006,
11188 WBSCL_NUM_OF_TAPS7                       = 0x00000007,
11189 WBSCL_NUM_OF_TAPS8                       = 0x00000008,
11190 WBSCL_NUM_OF_TAPS9                       = 0x00000009,
11191 WBSCL_NUM_OF_TAPS10                      = 0x0000000a,
11192 WBSCL_NUM_OF_TAPS11                      = 0x0000000b,
11193 } WBSCL_NUM_OF_TAPS_ENUM;
11194 
11195 /*
11196  * WBSCL_STATUS_ACK_ENUM enum
11197  */
11198 
11199 typedef enum WBSCL_STATUS_ACK_ENUM {
11200 WBSCL_STATUS_ACK_NCLR                    = 0x00000000,
11201 WBSCL_STATUS_ACK_CLR                     = 0x00000001,
11202 } WBSCL_STATUS_ACK_ENUM;
11203 
11204 /*
11205  * WBSCL_STATUS_MASK_ENUM enum
11206  */
11207 
11208 typedef enum WBSCL_STATUS_MASK_ENUM {
11209 WBSCL_STATUS_MASK_DISABLE                = 0x00000000,
11210 WBSCL_STATUS_MASK_ENABLE                 = 0x00000001,
11211 } WBSCL_STATUS_MASK_ENUM;
11212 
11213 /*
11214  * WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM enum
11215  */
11216 
11217 typedef enum WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM {
11218 WBSCL_DATA_OVERFLOW_INT_TYPE_REG         = 0x00000000,
11219 WBSCL_DATA_OVERFLOW_INT_TYPE_HW          = 0x00000001,
11220 } WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM;
11221 
11222 /*
11223  * WBSCL_HOST_CONFLICT_INT_TYPE_ENUM enum
11224  */
11225 
11226 typedef enum WBSCL_HOST_CONFLICT_INT_TYPE_ENUM {
11227 WBSCL_HOST_CONFLICT_INT_TYPE_REG         = 0x00000000,
11228 WBSCL_HOST_CONFLICT_INT_TYPE_HW          = 0x00000001,
11229 } WBSCL_HOST_CONFLICT_INT_TYPE_ENUM;
11230 
11231 /*
11232  * WBSCL_TEST_CRC_EN_ENUM enum
11233  */
11234 
11235 typedef enum WBSCL_TEST_CRC_EN_ENUM {
11236 WBSCL_TEST_CRC_DISABLE                   = 0x00000000,
11237 WBSCL_TEST_CRC_ENABLE                    = 0x00000001,
11238 } WBSCL_TEST_CRC_EN_ENUM;
11239 
11240 /*
11241  * WBSCL_TEST_CRC_CONT_EN_ENUM enum
11242  */
11243 
11244 typedef enum WBSCL_TEST_CRC_CONT_EN_ENUM {
11245 WBSCL_TEST_CRC_CONT_DISABLE              = 0x00000000,
11246 WBSCL_TEST_CRC_CONT_ENABLE               = 0x00000001,
11247 } WBSCL_TEST_CRC_CONT_EN_ENUM;
11248 
11249 /*
11250  * WBSCL_TEST_CRC_MASK_ENUM enum
11251  */
11252 
11253 typedef enum WBSCL_TEST_CRC_MASK_ENUM {
11254 WBSCL_TEST_CRC_MASKED                    = 0x00000000,
11255 WBSCL_TEST_CRC_UNMASKED                  = 0x00000001,
11256 } WBSCL_TEST_CRC_MASK_ENUM;
11257 
11258 /*
11259  * WBSCL_BACKPRESSURE_CNT_EN_ENUM enum
11260  */
11261 
11262 typedef enum WBSCL_BACKPRESSURE_CNT_EN_ENUM {
11263 WBSCL_BACKPRESSURE_CNT_DISABLE           = 0x00000000,
11264 WBSCL_BACKPRESSURE_CNT_ENABLE            = 0x00000001,
11265 } WBSCL_BACKPRESSURE_CNT_EN_ENUM;
11266 
11267 /*
11268  * WBSCL_OUTSIDE_PIX_STRATEGY_ENUM enum
11269  */
11270 
11271 typedef enum WBSCL_OUTSIDE_PIX_STRATEGY_ENUM {
11272 WBSCL_OUTSIDE_PIX_STRATEGY_BLACK         = 0x00000000,
11273 WBSCL_OUTSIDE_PIX_STRATEGY_EDGE          = 0x00000001,
11274 } WBSCL_OUTSIDE_PIX_STRATEGY_ENUM;
11275 
11276 /*******************************************************
11277  * DPCSRX Enums
11278  *******************************************************/
11279 
11280 /*
11281  * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
11282  */
11283 
11284 typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
11285 DPCSRX_BPHY_PCS_RX0_CLK                  = 0x00000000,
11286 DPCSRX_BPHY_PCS_RX1_CLK                  = 0x00000001,
11287 DPCSRX_BPHY_PCS_RX2_CLK                  = 0x00000002,
11288 DPCSRX_BPHY_PCS_RX3_CLK                  = 0x00000003,
11289 } DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;
11290 
11291 /*******************************************************
11292  * DPCSTX Enums
11293  *******************************************************/
11294 
11295 /*
11296  * DPCSTX_DVI_LINK_MODE enum
11297  */
11298 
11299 typedef enum DPCSTX_DVI_LINK_MODE {
11300 DPCSTX_DVI_LINK_MODE_NORMAL              = 0x00000000,
11301 DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER    = 0x00000001,
11302 DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER    = 0x00000002,
11303 } DPCSTX_DVI_LINK_MODE;
11304 
11305 /*******************************************************
11306  * RDPCSTX Enums
11307  *******************************************************/
11308 
11309 /*
11310  * RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET enum
11311  */
11312 
11313 typedef enum RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET {
11314 RDPCS_CBUS_SOFT_RESET_DISABLE            = 0x00000000,
11315 RDPCS_CBUS_SOFT_RESET_ENABLE             = 0x00000001,
11316 } RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET;
11317 
11318 /*
11319  * RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET enum
11320  */
11321 
11322 typedef enum RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET {
11323 RDPCS_SRAM_SRAM_RESET_DISABLE            = 0x00000000,
11324 } RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET;
11325 
11326 /*
11327  * RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN enum
11328  */
11329 
11330 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN {
11331 RDPCS_TX_FIFO_LANE_DISABLE               = 0x00000000,
11332 RDPCS_TX_FIFO_LANE_ENABLE                = 0x00000001,
11333 } RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN;
11334 
11335 /*
11336  * RDPCSTX_CNTL_RDPCS_TX_FIFO_EN enum
11337  */
11338 
11339 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_EN {
11340 RDPCS_TX_FIFO_DISABLE                    = 0x00000000,
11341 RDPCS_TX_FIFO_ENABLE                     = 0x00000001,
11342 } RDPCSTX_CNTL_RDPCS_TX_FIFO_EN;
11343 
11344 /*
11345  * RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET enum
11346  */
11347 
11348 typedef enum RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET {
11349 RDPCS_TX_SOFT_RESET_DISABLE              = 0x00000000,
11350 RDPCS_TX_SOFT_RESET_ENABLE               = 0x00000001,
11351 } RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET;
11352 
11353 /*
11354  * RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN enum
11355  */
11356 
11357 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN {
11358 RDPCS_EXT_REFCLK_DISABLE                 = 0x00000000,
11359 RDPCS_EXT_REFCLK_ENABLE                  = 0x00000001,
11360 } RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN;
11361 
11362 /*
11363  * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN enum
11364  */
11365 
11366 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN {
11367 RDPCS_EXT_REFCLK_EN_DISABLE              = 0x00000000,
11368 RDPCS_EXT_REFCLK_EN_ENABLE               = 0x00000001,
11369 } RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN;
11370 
11371 /*
11372  * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS enum
11373  */
11374 
11375 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS {
11376 RDPCS_SYMCLK_DIV2_GATE_ENABLE            = 0x00000000,
11377 RDPCS_SYMCLK_DIV2_GATE_DISABLE           = 0x00000001,
11378 } RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS;
11379 
11380 /*
11381  * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN enum
11382  */
11383 
11384 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN {
11385 RDPCS_SYMCLK_DIV2_DISABLE                = 0x00000000,
11386 RDPCS_SYMCLK_DIV2_ENABLE                 = 0x00000001,
11387 } RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN;
11388 
11389 /*
11390  * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON enum
11391  */
11392 
11393 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON {
11394 RDPCS_SYMCLK_DIV2_CLOCK_OFF              = 0x00000000,
11395 RDPCS_SYMCLK_DIV2_CLOCK_ON               = 0x00000001,
11396 } RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON;
11397 
11398 /*
11399  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
11400  */
11401 
11402 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
11403 RDPCS_SRAMCLK_GATE_ENABLE                = 0x00000000,
11404 RDPCS_SRAMCLK_GATE_DISABLE               = 0x00000001,
11405 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS;
11406 
11407 /*
11408  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
11409  */
11410 
11411 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
11412 RDPCS_SRAMCLK_DISABLE                    = 0x00000000,
11413 RDPCS_SRAMCLK_ENABLE                     = 0x00000001,
11414 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN;
11415 
11416 /*
11417  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS enum
11418  */
11419 
11420 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS {
11421 RDPCS_SRAMCLK_NOT_BYPASS                 = 0x00000000,
11422 RDPCS_SRAMCLK_BYPASS                     = 0x00000001,
11423 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS;
11424 
11425 /*
11426  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
11427  */
11428 
11429 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
11430 RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF           = 0x00000000,
11431 RDPCS_SYMCLK_SRAMCLK_CLOCK_ON            = 0x00000001,
11432 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON;
11433 
11434 /*
11435  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
11436  */
11437 
11438 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
11439 RDPCS_DPALT_DISABLE_TOGGLE_ENABLE        = 0x00000000,
11440 RDPCS_DPALT_DISABLE_TOGGLE_DISABLE       = 0x00000001,
11441 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE;
11442 
11443 /*
11444  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
11445  */
11446 
11447 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
11448 RDPCS_DPALT_4LANE_TOGGLE_2LANE           = 0x00000000,
11449 RDPCS_DPALT_4LANE_TOGGLE_4LANE           = 0x00000001,
11450 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE;
11451 
11452 /*
11453  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
11454  */
11455 
11456 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
11457 RDPCS_REG_FIFO_ERROR_MASK_DISABLE        = 0x00000000,
11458 RDPCS_REG_FIFO_ERROR_MASK_ENABLE         = 0x00000001,
11459 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK;
11460 
11461 /*
11462  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
11463  */
11464 
11465 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
11466 RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE  = 0x00000000,
11467 RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE   = 0x00000001,
11468 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK;
11469 
11470 /*
11471  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
11472  */
11473 
11474 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
11475 RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE    = 0x00000000,
11476 RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE     = 0x00000001,
11477 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK;
11478 
11479 /*
11480  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK enum
11481  */
11482 
11483 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK {
11484 RDPCS_TX_FIFO_ERROR_MASK_DISABLE         = 0x00000000,
11485 RDPCS_TX_FIFO_ERROR_MASK_ENABLE          = 0x00000001,
11486 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK;
11487 
11488 /*
11489  * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
11490  */
11491 
11492 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
11493 RDPCS_MEM_PWR_NO_FORCE                   = 0x00000000,
11494 RDPCS_MEM_PWR_LIGHT_SLEEP                = 0x00000001,
11495 RDPCS_MEM_PWR_DEEP_SLEEP                 = 0x00000002,
11496 RDPCS_MEM_PWR_SHUT_DOWN                  = 0x00000003,
11497 } RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE;
11498 
11499 /*
11500  * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
11501  */
11502 
11503 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
11504 RDPCS_MEM_PWR_PWR_STATE_ON               = 0x00000000,
11505 RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP      = 0x00000001,
11506 RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP       = 0x00000002,
11507 RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN        = 0x00000003,
11508 } RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE;
11509 
11510 /*
11511  * RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF enum
11512  */
11513 
11514 typedef enum RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF {
11515 RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY  = 0x00000000,
11516 RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD   = 0x00000001,
11517 RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3        = 0x00000002,
11518 RDPCS_MEM_POWER_CTRL_POFF_FOR_SD         = 0x00000003,
11519 } RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF;
11520 
11521 /*
11522  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
11523  */
11524 
11525 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
11526 RDPCS_PHY_REF_RANGE_0                    = 0x00000000,
11527 RDPCS_PHY_REF_RANGE_1                    = 0x00000001,
11528 RDPCS_PHY_REF_RANGE_2                    = 0x00000002,
11529 RDPCS_PHY_REF_RANGE_3                    = 0x00000003,
11530 RDPCS_PHY_REF_RANGE_4                    = 0x00000004,
11531 RDPCS_PHY_REF_RANGE_5                    = 0x00000005,
11532 RDPCS_PHY_REF_RANGE_6                    = 0x00000006,
11533 RDPCS_PHY_REF_RANGE_7                    = 0x00000007,
11534 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE;
11535 
11536 /*
11537  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
11538  */
11539 
11540 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
11541 RDPCS_PHY_CR_PARA_SEL_JTAG               = 0x00000000,
11542 RDPCS_PHY_CR_PARA_SEL_CR                 = 0x00000001,
11543 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL;
11544 
11545 /*
11546  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum
11547  */
11548 
11549 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL {
11550 RDPCS_PHY_CR_MUX_SEL_FOR_USB             = 0x00000000,
11551 RDPCS_PHY_CR_MUX_SEL_FOR_DC              = 0x00000001,
11552 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL;
11553 
11554 /*
11555  * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum
11556  */
11557 
11558 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE {
11559 RDPCS_SRAM_INIT_NOT_DONE                 = 0x00000000,
11560 RDPCS_SRAM_INIT_DONE                     = 0x00000001,
11561 } RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE;
11562 
11563 /*
11564  * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum
11565  */
11566 
11567 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE {
11568 RDPCS_SRAM_EXT_LD_NOT_DONE               = 0x00000000,
11569 RDPCS_SRAM_EXT_LD_DONE                   = 0x00000001,
11570 } RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE;
11571 
11572 /*
11573  * RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum
11574  */
11575 
11576 typedef enum RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL {
11577 RDPCS_PHY_DP_TX_TERM_CTRL_54             = 0x00000000,
11578 RDPCS_PHY_DP_TX_TERM_CTRL_52             = 0x00000001,
11579 RDPCS_PHY_DP_TX_TERM_CTRL_50             = 0x00000002,
11580 RDPCS_PHY_DP_TX_TERM_CTRL_48             = 0x00000003,
11581 RDPCS_PHY_DP_TX_TERM_CTRL_46             = 0x00000004,
11582 RDPCS_PHY_DP_TX_TERM_CTRL_44             = 0x00000005,
11583 RDPCS_PHY_DP_TX_TERM_CTRL_42             = 0x00000006,
11584 RDPCS_PHY_DP_TX_TERM_CTRL_40             = 0x00000007,
11585 } RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL;
11586 
11587 /*
11588  * RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum
11589  */
11590 
11591 typedef enum RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE {
11592 RRDPCS_PHY_DP_TX_PSTATE_POWER_UP         = 0x00000000,
11593 RRDPCS_PHY_DP_TX_PSTATE_HOLD             = 0x00000001,
11594 RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF         = 0x00000002,
11595 RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN       = 0x00000003,
11596 } RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE;
11597 
11598 /*
11599  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum
11600  */
11601 
11602 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE {
11603 RDPCS_PHY_DP_TX_RATE                     = 0x00000000,
11604 RDPCS_PHY_DP_TX_RATE_DIV2                = 0x00000001,
11605 RDPCS_PHY_DP_TX_RATE_DIV4                = 0x00000002,
11606 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE;
11607 
11608 /*
11609  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum
11610  */
11611 
11612 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH {
11613 RDPCS_PHY_DP_TX_WIDTH_8                  = 0x00000000,
11614 RDPCS_PHY_DP_TX_WIDTH_10                 = 0x00000001,
11615 RDPCS_PHY_DP_TX_WIDTH_16                 = 0x00000002,
11616 RDPCS_PHY_DP_TX_WIDTH_20                 = 0x00000003,
11617 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH;
11618 
11619 /*
11620  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum
11621  */
11622 
11623 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT {
11624 RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT   = 0x00000000,
11625 RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT      = 0x00000001,
11626 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT;
11627 
11628 /*
11629  * RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum
11630  */
11631 
11632 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV {
11633 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1          = 0x00000000,
11634 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2          = 0x00000001,
11635 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3          = 0x00000002,
11636 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8          = 0x00000003,
11637 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16         = 0x00000004,
11638 } RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;
11639 
11640 /*
11641  * RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum
11642  */
11643 
11644 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV {
11645 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0  = 0x00000000,
11646 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1  = 0x00000001,
11647 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2  = 0x00000002,
11648 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3  = 0x00000003,
11649 } RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV;
11650 
11651 /*
11652  * RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum
11653  */
11654 
11655 typedef enum RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV {
11656 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV            = 0x00000000,
11657 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2           = 0x00000001,
11658 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4           = 0x00000002,
11659 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8           = 0x00000003,
11660 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3           = 0x00000004,
11661 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5           = 0x00000005,
11662 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6           = 0x00000006,
11663 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10          = 0x00000007,
11664 } RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;
11665 
11666 /*
11667  * RDPCS_TEST_CLK_SEL enum
11668  */
11669 
11670 typedef enum RDPCS_TEST_CLK_SEL {
11671 RDPCS_TEST_CLK_SEL_NONE                  = 0x00000000,
11672 RDPCS_TEST_CLK_SEL_CFGCLK                = 0x00000001,
11673 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS     = 0x00000002,
11674 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS     = 0x00000003,
11675 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4  = 0x00000004,
11676 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4  = 0x00000005,
11677 RDPCS_TEST_CLK_SEL_SRAMCLK               = 0x00000006,
11678 RDPCS_TEST_CLK_SEL_EXT_CR_CLK            = 0x00000007,
11679 RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK       = 0x00000008,
11680 RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK       = 0x00000009,
11681 RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK       = 0x0000000a,
11682 RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK       = 0x0000000b,
11683 RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK      = 0x0000000c,
11684 RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK  = 0x0000000d,
11685 RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK       = 0x0000000e,
11686 RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk        = 0x0000000f,
11687 RDPCS_TEST_CLK_SEL_dtb_out0              = 0x00000010,
11688 RDPCS_TEST_CLK_SEL_dtb_out1              = 0x00000011,
11689 } RDPCS_TEST_CLK_SEL;
11690 
11691 /*******************************************************
11692  * CB Enums
11693  *******************************************************/
11694 
11695 /*
11696  * CBMode enum
11697  */
11698 
11699 typedef enum CBMode {
11700 CB_DISABLE                               = 0x00000000,
11701 CB_NORMAL                                = 0x00000001,
11702 CB_ELIMINATE_FAST_CLEAR                  = 0x00000002,
11703 CB_RESOLVE                               = 0x00000003,
11704 CB_DECOMPRESS                            = 0x00000004,
11705 CB_FMASK_DECOMPRESS                      = 0x00000005,
11706 CB_DCC_DECOMPRESS                        = 0x00000006,
11707 CB_RESERVED                              = 0x00000007,
11708 } CBMode;
11709 
11710 /*
11711  * BlendOp enum
11712  */
11713 
11714 typedef enum BlendOp {
11715 BLEND_ZERO                               = 0x00000000,
11716 BLEND_ONE                                = 0x00000001,
11717 BLEND_SRC_COLOR                          = 0x00000002,
11718 BLEND_ONE_MINUS_SRC_COLOR                = 0x00000003,
11719 BLEND_SRC_ALPHA                          = 0x00000004,
11720 BLEND_ONE_MINUS_SRC_ALPHA                = 0x00000005,
11721 BLEND_DST_ALPHA                          = 0x00000006,
11722 BLEND_ONE_MINUS_DST_ALPHA                = 0x00000007,
11723 BLEND_DST_COLOR                          = 0x00000008,
11724 BLEND_ONE_MINUS_DST_COLOR                = 0x00000009,
11725 BLEND_SRC_ALPHA_SATURATE                 = 0x0000000a,
11726 BLEND_BOTH_SRC_ALPHA                     = 0x0000000b,
11727 BLEND_BOTH_INV_SRC_ALPHA                 = 0x0000000c,
11728 BLEND_CONSTANT_COLOR                     = 0x0000000d,
11729 BLEND_ONE_MINUS_CONSTANT_COLOR           = 0x0000000e,
11730 BLEND_SRC1_COLOR                         = 0x0000000f,
11731 BLEND_INV_SRC1_COLOR                     = 0x00000010,
11732 BLEND_SRC1_ALPHA                         = 0x00000011,
11733 BLEND_INV_SRC1_ALPHA                     = 0x00000012,
11734 BLEND_CONSTANT_ALPHA                     = 0x00000013,
11735 BLEND_ONE_MINUS_CONSTANT_ALPHA           = 0x00000014,
11736 } BlendOp;
11737 
11738 /*
11739  * CombFunc enum
11740  */
11741 
11742 typedef enum CombFunc {
11743 COMB_DST_PLUS_SRC                        = 0x00000000,
11744 COMB_SRC_MINUS_DST                       = 0x00000001,
11745 COMB_MIN_DST_SRC                         = 0x00000002,
11746 COMB_MAX_DST_SRC                         = 0x00000003,
11747 COMB_DST_MINUS_SRC                       = 0x00000004,
11748 } CombFunc;
11749 
11750 /*
11751  * BlendOpt enum
11752  */
11753 
11754 typedef enum BlendOpt {
11755 FORCE_OPT_AUTO                           = 0x00000000,
11756 FORCE_OPT_DISABLE                        = 0x00000001,
11757 FORCE_OPT_ENABLE_IF_SRC_A_0              = 0x00000002,
11758 FORCE_OPT_ENABLE_IF_SRC_RGB_0            = 0x00000003,
11759 FORCE_OPT_ENABLE_IF_SRC_ARGB_0           = 0x00000004,
11760 FORCE_OPT_ENABLE_IF_SRC_A_1              = 0x00000005,
11761 FORCE_OPT_ENABLE_IF_SRC_RGB_1            = 0x00000006,
11762 FORCE_OPT_ENABLE_IF_SRC_ARGB_1           = 0x00000007,
11763 } BlendOpt;
11764 
11765 /*
11766  * CmaskCode enum
11767  */
11768 
11769 typedef enum CmaskCode {
11770 CMASK_CLR00_F0                           = 0x00000000,
11771 CMASK_CLR00_F1                           = 0x00000001,
11772 CMASK_CLR00_F2                           = 0x00000002,
11773 CMASK_CLR00_FX                           = 0x00000003,
11774 CMASK_CLR01_F0                           = 0x00000004,
11775 CMASK_CLR01_F1                           = 0x00000005,
11776 CMASK_CLR01_F2                           = 0x00000006,
11777 CMASK_CLR01_FX                           = 0x00000007,
11778 CMASK_CLR10_F0                           = 0x00000008,
11779 CMASK_CLR10_F1                           = 0x00000009,
11780 CMASK_CLR10_F2                           = 0x0000000a,
11781 CMASK_CLR10_FX                           = 0x0000000b,
11782 CMASK_CLR11_F0                           = 0x0000000c,
11783 CMASK_CLR11_F1                           = 0x0000000d,
11784 CMASK_CLR11_F2                           = 0x0000000e,
11785 CMASK_CLR11_FX                           = 0x0000000f,
11786 } CmaskCode;
11787 
11788 /*
11789  * MemArbMode enum
11790  */
11791 
11792 typedef enum MemArbMode {
11793 MEM_ARB_MODE_FIXED                       = 0x00000000,
11794 MEM_ARB_MODE_AGE                         = 0x00000001,
11795 MEM_ARB_MODE_WEIGHT                      = 0x00000002,
11796 MEM_ARB_MODE_BOTH                        = 0x00000003,
11797 } MemArbMode;
11798 
11799 /*
11800  * CBPerfOpFilterSel enum
11801  */
11802 
11803 typedef enum CBPerfOpFilterSel {
11804 CB_PERF_OP_FILTER_SEL_WRITE_ONLY         = 0x00000000,
11805 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION  = 0x00000001,
11806 CB_PERF_OP_FILTER_SEL_RESOLVE            = 0x00000002,
11807 CB_PERF_OP_FILTER_SEL_DECOMPRESS         = 0x00000003,
11808 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS   = 0x00000004,
11809 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR  = 0x00000005,
11810 } CBPerfOpFilterSel;
11811 
11812 /*
11813  * CBPerfClearFilterSel enum
11814  */
11815 
11816 typedef enum CBPerfClearFilterSel {
11817 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR        = 0x00000000,
11818 CB_PERF_CLEAR_FILTER_SEL_CLEAR           = 0x00000001,
11819 } CBPerfClearFilterSel;
11820 
11821 /*
11822  * CBPerfSel enum
11823  */
11824 
11825 typedef enum CBPerfSel {
11826 CB_PERF_SEL_NONE                         = 0x00000000,
11827 CB_PERF_SEL_BUSY                         = 0x00000001,
11828 CB_PERF_SEL_CORE_SCLK_VLD                = 0x00000002,
11829 CB_PERF_SEL_REG_SCLK0_VLD                = 0x00000003,
11830 CB_PERF_SEL_REG_SCLK1_VLD                = 0x00000004,
11831 CB_PERF_SEL_DRAWN_QUAD                   = 0x00000005,
11832 CB_PERF_SEL_DRAWN_PIXEL                  = 0x00000006,
11833 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT          = 0x00000007,
11834 CB_PERF_SEL_DRAWN_TILE                   = 0x00000008,
11835 CB_PERF_SEL_DB_CB_TILE_VALID_READY       = 0x00000009,
11836 CB_PERF_SEL_DB_CB_TILE_VALID_READYB      = 0x0000000a,
11837 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY      = 0x0000000b,
11838 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB     = 0x0000000c,
11839 CB_PERF_SEL_CM_FC_TILE_VALID_READY       = 0x0000000d,
11840 CB_PERF_SEL_CM_FC_TILE_VALID_READYB      = 0x0000000e,
11841 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY      = 0x0000000f,
11842 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB     = 0x00000010,
11843 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY  = 0x00000011,
11844 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB  = 0x00000012,
11845 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY      = 0x00000013,
11846 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB     = 0x00000014,
11847 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY     = 0x00000015,
11848 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB    = 0x00000016,
11849 CB_PERF_SEL_LQUAD_NO_TILE                = 0x00000017,
11850 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R  = 0x00000018,
11851 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR  = 0x00000019,
11852 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR  = 0x0000001a,
11853 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR  = 0x0000001b,
11854 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR  = 0x0000001c,
11855 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR  = 0x0000001d,
11856 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR  = 0x0000001e,
11857 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT  = 0x0000001f,
11858 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID  = 0x00000020,
11859 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK  = 0x00000021,
11860 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK  = 0x00000022,
11861 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL  = 0x00000023,
11862 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY    = 0x00000024,
11863 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB   = 0x00000025,
11864 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY   = 0x00000026,
11865 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB  = 0x00000027,
11866 CB_PERF_SEL_FOP_IN_VALID_READY           = 0x00000028,
11867 CB_PERF_SEL_FOP_IN_VALID_READYB          = 0x00000029,
11868 CB_PERF_SEL_FOP_IN_VALIDB_READY          = 0x0000002a,
11869 CB_PERF_SEL_FOP_IN_VALIDB_READYB         = 0x0000002b,
11870 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY   = 0x0000002c,
11871 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB  = 0x0000002d,
11872 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY  = 0x0000002e,
11873 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB  = 0x0000002f,
11874 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY    = 0x00000030,
11875 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB   = 0x00000031,
11876 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY   = 0x00000032,
11877 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB  = 0x00000033,
11878 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY    = 0x00000034,
11879 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB   = 0x00000035,
11880 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY   = 0x00000036,
11881 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB  = 0x00000037,
11882 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY  = 0x00000038,
11883 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB  = 0x00000039,
11884 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY  = 0x0000003a,
11885 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB  = 0x0000003b,
11886 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY  = 0x0000003c,
11887 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB  = 0x0000003d,
11888 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY  = 0x0000003e,
11889 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB  = 0x0000003f,
11890 CB_PERF_SEL_CC_BC_CS_FRAG_VALID          = 0x00000040,
11891 CB_PERF_SEL_CM_CACHE_HIT                 = 0x00000041,
11892 CB_PERF_SEL_CM_CACHE_TAG_MISS            = 0x00000042,
11893 CB_PERF_SEL_CM_CACHE_SECTOR_MISS         = 0x00000043,
11894 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL    = 0x00000044,
11895 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000045,
11896 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000046,
11897 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000047,
11898 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL   = 0x00000048,
11899 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL  = 0x00000049,
11900 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL    = 0x0000004a,
11901 CB_PERF_SEL_CM_CACHE_STALL               = 0x0000004b,
11902 CB_PERF_SEL_CM_CACHE_FLUSH               = 0x0000004c,
11903 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED        = 0x0000004d,
11904 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED     = 0x0000004e,
11905 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000004f,
11906 CB_PERF_SEL_FC_CACHE_HIT                 = 0x00000050,
11907 CB_PERF_SEL_FC_CACHE_TAG_MISS            = 0x00000051,
11908 CB_PERF_SEL_FC_CACHE_SECTOR_MISS         = 0x00000052,
11909 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL    = 0x00000053,
11910 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000054,
11911 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000055,
11912 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000056,
11913 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL   = 0x00000057,
11914 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL  = 0x00000058,
11915 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL    = 0x00000059,
11916 CB_PERF_SEL_FC_CACHE_STALL               = 0x0000005a,
11917 CB_PERF_SEL_FC_CACHE_FLUSH               = 0x0000005b,
11918 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED        = 0x0000005c,
11919 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED     = 0x0000005d,
11920 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000005e,
11921 CB_PERF_SEL_CC_CACHE_HIT                 = 0x0000005f,
11922 CB_PERF_SEL_CC_CACHE_TAG_MISS            = 0x00000060,
11923 CB_PERF_SEL_CC_CACHE_SECTOR_MISS         = 0x00000061,
11924 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL    = 0x00000062,
11925 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000063,
11926 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000064,
11927 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000065,
11928 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL   = 0x00000066,
11929 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL  = 0x00000067,
11930 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL    = 0x00000068,
11931 CB_PERF_SEL_CC_CACHE_STALL               = 0x00000069,
11932 CB_PERF_SEL_CC_CACHE_FLUSH               = 0x0000006a,
11933 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED        = 0x0000006b,
11934 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED     = 0x0000006c,
11935 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000006d,
11936 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION  = 0x0000006e,
11937 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY     = 0x0000006f,
11938 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB    = 0x00000070,
11939 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY    = 0x00000071,
11940 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB   = 0x00000072,
11941 CB_PERF_SEL_CM_MC_WRITE_REQUEST          = 0x00000073,
11942 CB_PERF_SEL_FC_MC_WRITE_REQUEST          = 0x00000074,
11943 CB_PERF_SEL_CC_MC_WRITE_REQUEST          = 0x00000075,
11944 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000076,
11945 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000077,
11946 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000078,
11947 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY     = 0x00000079,
11948 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB    = 0x0000007a,
11949 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY    = 0x0000007b,
11950 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB   = 0x0000007c,
11951 CB_PERF_SEL_CM_MC_READ_REQUEST           = 0x0000007d,
11952 CB_PERF_SEL_FC_MC_READ_REQUEST           = 0x0000007e,
11953 CB_PERF_SEL_CC_MC_READ_REQUEST           = 0x0000007f,
11954 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000080,
11955 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000081,
11956 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000082,
11957 CB_PERF_SEL_CM_TQ_FULL                   = 0x00000083,
11958 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL  = 0x00000084,
11959 CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL     = 0x00000085,
11960 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL      = 0x00000086,
11961 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL      = 0x00000087,
11962 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL  = 0x00000088,
11963 CB_PERF_SEL_FC_TILE_STUTTER_STALL        = 0x00000089,
11964 CB_PERF_SEL_FC_QUAD_STUTTER_STALL        = 0x0000008a,
11965 CB_PERF_SEL_FC_KEYID_STUTTER_STALL       = 0x0000008b,
11966 CB_PERF_SEL_FOP_FMASK_RAW_STALL          = 0x0000008c,
11967 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL       = 0x0000008d,
11968 CB_PERF_SEL_CC_SF_FULL                   = 0x0000008e,
11969 CB_PERF_SEL_CC_RB_FULL                   = 0x0000008f,
11970 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL  = 0x00000090,
11971 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL  = 0x00000091,
11972 CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL    = 0x00000092,
11973 CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL     = 0x00000093,
11974 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL     = 0x00000094,
11975 CB_PERF_SEL_EVENT                        = 0x00000095,
11976 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS         = 0x00000096,
11977 CB_PERF_SEL_EVENT_CONTEXT_DONE           = 0x00000097,
11978 CB_PERF_SEL_EVENT_CACHE_FLUSH            = 0x00000098,
11979 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT  = 0x00000099,
11980 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT  = 0x0000009a,
11981 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS  = 0x0000009b,
11982 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META  = 0x0000009c,
11983 CB_PERF_SEL_CC_SURFACE_SYNC              = 0x0000009d,
11984 CB_PERF_SEL_CMASK_READ_DATA_0xC          = 0x0000009e,
11985 CB_PERF_SEL_CMASK_READ_DATA_0xD          = 0x0000009f,
11986 CB_PERF_SEL_CMASK_READ_DATA_0xE          = 0x000000a0,
11987 CB_PERF_SEL_CMASK_READ_DATA_0xF          = 0x000000a1,
11988 CB_PERF_SEL_CMASK_WRITE_DATA_0xC         = 0x000000a2,
11989 CB_PERF_SEL_CMASK_WRITE_DATA_0xD         = 0x000000a3,
11990 CB_PERF_SEL_CMASK_WRITE_DATA_0xE         = 0x000000a4,
11991 CB_PERF_SEL_CMASK_WRITE_DATA_0xF         = 0x000000a5,
11992 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT      = 0x000000a6,
11993 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT  = 0x000000a7,
11994 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT  = 0x000000a8,
11995 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE  = 0x000000a9,
11996 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE  = 0x000000aa,
11997 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE  = 0x000000ab,
11998 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE  = 0x000000ac,
11999 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE  = 0x000000ad,
12000 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE  = 0x000000ae,
12001 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE  = 0x000000af,
12002 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE  = 0x000000b0,
12003 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE  = 0x000000b1,
12004 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE  = 0x000000b2,
12005 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE  = 0x000000b3,
12006 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE  = 0x000000b4,
12007 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE  = 0x000000b5,
12008 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE  = 0x000000b6,
12009 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE  = 0x000000b7,
12010 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE  = 0x000000b8,
12011 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT        = 0x000000b9,
12012 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS       = 0x000000ba,
12013 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS       = 0x000000bb,
12014 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS       = 0x000000bc,
12015 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS       = 0x000000bd,
12016 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS       = 0x000000be,
12017 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS       = 0x000000bf,
12018 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT      = 0x000000c0,
12019 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS     = 0x000000c1,
12020 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS     = 0x000000c2,
12021 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS     = 0x000000c3,
12022 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS     = 0x000000c4,
12023 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS     = 0x000000c5,
12024 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS     = 0x000000c6,
12025 CB_PERF_SEL_QUAD_READS_FRAGMENT_0        = 0x000000c7,
12026 CB_PERF_SEL_QUAD_READS_FRAGMENT_1        = 0x000000c8,
12027 CB_PERF_SEL_QUAD_READS_FRAGMENT_2        = 0x000000c9,
12028 CB_PERF_SEL_QUAD_READS_FRAGMENT_3        = 0x000000ca,
12029 CB_PERF_SEL_QUAD_READS_FRAGMENT_4        = 0x000000cb,
12030 CB_PERF_SEL_QUAD_READS_FRAGMENT_5        = 0x000000cc,
12031 CB_PERF_SEL_QUAD_READS_FRAGMENT_6        = 0x000000cd,
12032 CB_PERF_SEL_QUAD_READS_FRAGMENT_7        = 0x000000ce,
12033 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0       = 0x000000cf,
12034 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1       = 0x000000d0,
12035 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2       = 0x000000d1,
12036 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3       = 0x000000d2,
12037 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4       = 0x000000d3,
12038 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5       = 0x000000d4,
12039 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6       = 0x000000d5,
12040 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7       = 0x000000d6,
12041 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST  = 0x000000d7,
12042 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS  = 0x000000d8,
12043 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS  = 0x000000d9,
12044 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED  = 0x000000da,
12045 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED  = 0x000000db,
12046 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED  = 0x000000dc,
12047 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST  = 0x000000dd,
12048 CB_PERF_SEL_DRAWN_BUSY                   = 0x000000de,
12049 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY      = 0x000000df,
12050 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY       = 0x000000e0,
12051 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY       = 0x000000e1,
12052 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY       = 0x000000e2,
12053 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED  = 0x000000e3,
12054 CB_PERF_SEL_FC_SEQUENCER_CLEAR           = 0x000000e4,
12055 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR  = 0x000000e5,
12056 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS  = 0x000000e6,
12057 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE  = 0x000000e7,
12058 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC  = 0x000000e8,
12059 CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL     = 0x000000e9,
12060 CB_PERF_SEL_FC_DOC_IS_STALLED            = 0x000000ea,
12061 CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED     = 0x000000eb,
12062 CB_PERF_SEL_FC_DOC_MRTS_COMBINED         = 0x000000ec,
12063 CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS        = 0x000000ed,
12064 CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT         = 0x000000ee,
12065 CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS        = 0x000000ef,
12066 CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT         = 0x000000f0,
12067 CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL  = 0x000000f1,
12068 CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR    = 0x000000f2,
12069 CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS   = 0x000000f3,
12070 CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS   = 0x000000f4,
12071 CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS   = 0x000000f5,
12072 CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS  = 0x000000f6,
12073 CB_PERF_SEL_FC_DCC_CACHE_HIT             = 0x000000f7,
12074 CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS        = 0x000000f8,
12075 CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS     = 0x000000f9,
12076 CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL  = 0x000000fa,
12077 CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x000000fb,
12078 CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x000000fc,
12079 CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x000000fd,
12080 CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL  = 0x000000fe,
12081 CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL  = 0x000000ff,
12082 CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL  = 0x00000100,
12083 CB_PERF_SEL_FC_DCC_CACHE_STALL           = 0x00000101,
12084 CB_PERF_SEL_FC_DCC_CACHE_FLUSH           = 0x00000102,
12085 CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED    = 0x00000103,
12086 CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED  = 0x00000104,
12087 CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x00000105,
12088 CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT     = 0x00000106,
12089 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST      = 0x00000107,
12090 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000108,
12091 CB_PERF_SEL_FC_MC_DCC_READ_REQUEST       = 0x00000109,
12092 CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT  = 0x0000010a,
12093 CB_PERF_SEL_CC_DCC_RDREQ_STALL           = 0x0000010b,
12094 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN    = 0x0000010c,
12095 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT   = 0x0000010d,
12096 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN      = 0x0000010e,
12097 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT     = 0x0000010f,
12098 CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR      = 0x00000110,
12099 CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1  = 0x00000111,
12100 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2  = 0x00000112,
12101 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000113,
12102 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1  = 0x00000114,
12103 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1  = 0x00000115,
12104 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2  = 0x00000116,
12105 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1  = 0x00000117,
12106 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000118,
12107 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000119,
12108 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1  = 0x0000011a,
12109 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2  = 0x0000011b,
12110 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2  = 0x0000011c,
12111 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2  = 0x0000011d,
12112 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x0000011e,
12113 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1  = 0x0000011f,
12114 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1  = 0x00000120,
12115 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2  = 0x00000121,
12116 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3  = 0x00000122,
12117 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4  = 0x00000123,
12118 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1  = 0x00000124,
12119 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2  = 0x00000125,
12120 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3  = 0x00000126,
12121 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4  = 0x00000127,
12122 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1  = 0x00000128,
12123 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2  = 0x00000129,
12124 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3  = 0x0000012a,
12125 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4  = 0x0000012b,
12126 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1  = 0x0000012c,
12127 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2  = 0x0000012d,
12128 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3  = 0x0000012e,
12129 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1  = 0x0000012f,
12130 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2  = 0x00000130,
12131 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3  = 0x00000131,
12132 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4  = 0x00000132,
12133 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1  = 0x00000133,
12134 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2  = 0x00000134,
12135 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3  = 0x00000135,
12136 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4  = 0x00000136,
12137 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1  = 0x00000137,
12138 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2  = 0x00000138,
12139 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3  = 0x00000139,
12140 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4  = 0x0000013a,
12141 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1  = 0x0000013b,
12142 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2  = 0x0000013c,
12143 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3  = 0x0000013d,
12144 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1  = 0x0000013e,
12145 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1  = 0x0000013f,
12146 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1  = 0x00000140,
12147 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1  = 0x00000141,
12148 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1  = 0x00000142,
12149 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1  = 0x00000143,
12150 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1  = 0x00000144,
12151 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1  = 0x00000145,
12152 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2  = 0x00000146,
12153 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2  = 0x00000147,
12154 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2  = 0x00000148,
12155 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2  = 0x00000149,
12156 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2  = 0x0000014a,
12157 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2  = 0x0000014b,
12158 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2  = 0x0000014c,
12159 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1  = 0x0000014d,
12160 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1  = 0x0000014e,
12161 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1  = 0x0000014f,
12162 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1  = 0x00000150,
12163 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2  = 0x00000151,
12164 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2  = 0x00000152,
12165 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2  = 0x00000153,
12166 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000154,
12167 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000155,
12168 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000156,
12169 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000157,
12170 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000158,
12171 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000159,
12172 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1  = 0x0000015a,
12173 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1  = 0x0000015b,
12174 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1  = 0x0000015c,
12175 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2  = 0x0000015d,
12176 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3  = 0x0000015e,
12177 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4  = 0x0000015f,
12178 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5  = 0x00000160,
12179 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6  = 0x00000161,
12180 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0  = 0x00000162,
12181 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1  = 0x00000163,
12182 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1  = 0x00000164,
12183 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2  = 0x00000165,
12184 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3  = 0x00000166,
12185 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4  = 0x00000167,
12186 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5  = 0x00000168,
12187 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0  = 0x00000169,
12188 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1  = 0x0000016a,
12189 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1  = 0x0000016b,
12190 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1  = 0x0000016c,
12191 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1  = 0x0000016d,
12192 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1  = 0x0000016e,
12193 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1  = 0x0000016f,
12194 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1  = 0x00000170,
12195 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1  = 0x00000171,
12196 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1  = 0x00000172,
12197 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2  = 0x00000173,
12198 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2  = 0x00000174,
12199 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2  = 0x00000175,
12200 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2  = 0x00000176,
12201 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2  = 0x00000177,
12202 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2  = 0x00000178,
12203 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2  = 0x00000179,
12204 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1  = 0x0000017a,
12205 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2  = 0x0000017b,
12206 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3  = 0x0000017c,
12207 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4  = 0x0000017d,
12208 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5  = 0x0000017e,
12209 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6  = 0x0000017f,
12210 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7  = 0x00000180,
12211 CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED  = 0x00000181,
12212 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1   = 0x00000182,
12213 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1   = 0x00000183,
12214 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2   = 0x00000184,
12215 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3   = 0x00000185,
12216 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1   = 0x00000186,
12217 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2   = 0x00000187,
12218 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3   = 0x00000188,
12219 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4   = 0x00000189,
12220 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5   = 0x0000018a,
12221 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1   = 0x0000018b,
12222 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2   = 0x0000018c,
12223 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3   = 0x0000018d,
12224 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4   = 0x0000018e,
12225 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5   = 0x0000018f,
12226 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6   = 0x00000190,
12227 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7   = 0x00000191,
12228 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH     = 0x00000192,
12229 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT     = 0x00000193,
12230 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT    = 0x00000194,
12231 CB_PERF_SEL_RBP_SPLIT_MICROTILE          = 0x00000195,
12232 CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK     = 0x00000196,
12233 CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK  = 0x00000197,
12234 CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING  = 0x00000198,
12235 CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS  = 0x00000199,
12236 CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD  = 0x0000019a,
12237 CB_PERF_SEL_NACK_CM_READ                 = 0x0000019b,
12238 CB_PERF_SEL_NACK_CM_WRITE                = 0x0000019c,
12239 CB_PERF_SEL_NACK_FC_READ                 = 0x0000019d,
12240 CB_PERF_SEL_NACK_FC_WRITE                = 0x0000019e,
12241 CB_PERF_SEL_NACK_DC_READ                 = 0x0000019f,
12242 CB_PERF_SEL_NACK_DC_WRITE                = 0x000001a0,
12243 CB_PERF_SEL_NACK_CC_READ                 = 0x000001a1,
12244 CB_PERF_SEL_NACK_CC_WRITE                = 0x000001a2,
12245 CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN     = 0x000001a3,
12246 CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN     = 0x000001a4,
12247 CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN     = 0x000001a5,
12248 CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN     = 0x000001a6,
12249 CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT  = 0x000001a7,
12250 CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT  = 0x000001a8,
12251 CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT  = 0x000001a9,
12252 CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT  = 0x000001aa,
12253 CB_PERF_SEL_CM_MC_WRITE_ACK64B           = 0x000001ab,
12254 CB_PERF_SEL_FC_MC_WRITE_ACK64B           = 0x000001ac,
12255 CB_PERF_SEL_DC_MC_WRITE_ACK64B           = 0x000001ad,
12256 CB_PERF_SEL_CC_MC_WRITE_ACK64B           = 0x000001ae,
12257 CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS      = 0x000001af,
12258 CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS  = 0x000001b0,
12259 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA  = 0x000001b1,
12260 CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT      = 0x000001b2,
12261 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX  = 0x000001b3,
12262 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX  = 0x000001b4,
12263 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX  = 0x000001b5,
12264 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX  = 0x000001b6,
12265 CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED  = 0x000001b7,
12266 CB_PERF_SEL_DB_CB_CONTEXT_DONE           = 0x000001b8,
12267 CB_PERF_SEL_DB_CB_EOP_DONE               = 0x000001b9,
12268 CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL  = 0x000001ba,
12269 CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD        = 0x000001bb,
12270 } CBPerfSel;
12271 
12272 /*
12273  * CmaskAddr enum
12274  */
12275 
12276 typedef enum CmaskAddr {
12277 CMASK_ADDR_TILED                         = 0x00000000,
12278 CMASK_ADDR_LINEAR                        = 0x00000001,
12279 CMASK_ADDR_COMPATIBLE                    = 0x00000002,
12280 } CmaskAddr;
12281 
12282 /*
12283  * SourceFormat enum
12284  */
12285 
12286 typedef enum SourceFormat {
12287 EXPORT_4C_32BPC                          = 0x00000000,
12288 EXPORT_4C_16BPC                          = 0x00000001,
12289 EXPORT_2C_32BPC_GR                       = 0x00000002,
12290 EXPORT_2C_32BPC_AR                       = 0x00000003,
12291 } SourceFormat;
12292 
12293 /*******************************************************
12294  * TC Enums
12295  *******************************************************/
12296 
12297 /*
12298  * TC_OP_MASKS enum
12299  */
12300 
12301 typedef enum TC_OP_MASKS {
12302 TC_OP_MASK_FLUSH_DENROM                  = 0x00000008,
12303 TC_OP_MASK_64                            = 0x00000020,
12304 TC_OP_MASK_NO_RTN                        = 0x00000040,
12305 } TC_OP_MASKS;
12306 
12307 /*
12308  * TC_OP enum
12309  */
12310 
12311 typedef enum TC_OP {
12312 TC_OP_READ                               = 0x00000000,
12313 TC_OP_ATOMIC_FCMPSWAP_RTN_32             = 0x00000001,
12314 TC_OP_ATOMIC_FMIN_RTN_32                 = 0x00000002,
12315 TC_OP_ATOMIC_FMAX_RTN_32                 = 0x00000003,
12316 TC_OP_RESERVED_FOP_RTN_32_0              = 0x00000004,
12317 TC_OP_RESERVED_FOP_RTN_32_1              = 0x00000005,
12318 TC_OP_RESERVED_FOP_RTN_32_2              = 0x00000006,
12319 TC_OP_ATOMIC_SWAP_RTN_32                 = 0x00000007,
12320 TC_OP_ATOMIC_CMPSWAP_RTN_32              = 0x00000008,
12321 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32  = 0x00000009,
12322 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32    = 0x0000000a,
12323 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32    = 0x0000000b,
12324 TC_OP_PROBE_FILTER                       = 0x0000000c,
12325 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1  = 0x0000000d,
12326 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2  = 0x0000000e,
12327 TC_OP_ATOMIC_ADD_RTN_32                  = 0x0000000f,
12328 TC_OP_ATOMIC_SUB_RTN_32                  = 0x00000010,
12329 TC_OP_ATOMIC_SMIN_RTN_32                 = 0x00000011,
12330 TC_OP_ATOMIC_UMIN_RTN_32                 = 0x00000012,
12331 TC_OP_ATOMIC_SMAX_RTN_32                 = 0x00000013,
12332 TC_OP_ATOMIC_UMAX_RTN_32                 = 0x00000014,
12333 TC_OP_ATOMIC_AND_RTN_32                  = 0x00000015,
12334 TC_OP_ATOMIC_OR_RTN_32                   = 0x00000016,
12335 TC_OP_ATOMIC_XOR_RTN_32                  = 0x00000017,
12336 TC_OP_ATOMIC_INC_RTN_32                  = 0x00000018,
12337 TC_OP_ATOMIC_DEC_RTN_32                  = 0x00000019,
12338 TC_OP_WBINVL1_VOL                        = 0x0000001a,
12339 TC_OP_WBINVL1_SD                         = 0x0000001b,
12340 TC_OP_RESERVED_NON_FLOAT_RTN_32_0        = 0x0000001c,
12341 TC_OP_RESERVED_NON_FLOAT_RTN_32_1        = 0x0000001d,
12342 TC_OP_RESERVED_NON_FLOAT_RTN_32_2        = 0x0000001e,
12343 TC_OP_RESERVED_NON_FLOAT_RTN_32_3        = 0x0000001f,
12344 TC_OP_WRITE                              = 0x00000020,
12345 TC_OP_ATOMIC_FCMPSWAP_RTN_64             = 0x00000021,
12346 TC_OP_ATOMIC_FMIN_RTN_64                 = 0x00000022,
12347 TC_OP_ATOMIC_FMAX_RTN_64                 = 0x00000023,
12348 TC_OP_RESERVED_FOP_RTN_64_0              = 0x00000024,
12349 TC_OP_RESERVED_FOP_RTN_64_1              = 0x00000025,
12350 TC_OP_RESERVED_FOP_RTN_64_2              = 0x00000026,
12351 TC_OP_ATOMIC_SWAP_RTN_64                 = 0x00000027,
12352 TC_OP_ATOMIC_CMPSWAP_RTN_64              = 0x00000028,
12353 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64  = 0x00000029,
12354 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64    = 0x0000002a,
12355 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64    = 0x0000002b,
12356 TC_OP_WBINVL2_SD                         = 0x0000002c,
12357 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0  = 0x0000002d,
12358 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1  = 0x0000002e,
12359 TC_OP_ATOMIC_ADD_RTN_64                  = 0x0000002f,
12360 TC_OP_ATOMIC_SUB_RTN_64                  = 0x00000030,
12361 TC_OP_ATOMIC_SMIN_RTN_64                 = 0x00000031,
12362 TC_OP_ATOMIC_UMIN_RTN_64                 = 0x00000032,
12363 TC_OP_ATOMIC_SMAX_RTN_64                 = 0x00000033,
12364 TC_OP_ATOMIC_UMAX_RTN_64                 = 0x00000034,
12365 TC_OP_ATOMIC_AND_RTN_64                  = 0x00000035,
12366 TC_OP_ATOMIC_OR_RTN_64                   = 0x00000036,
12367 TC_OP_ATOMIC_XOR_RTN_64                  = 0x00000037,
12368 TC_OP_ATOMIC_INC_RTN_64                  = 0x00000038,
12369 TC_OP_ATOMIC_DEC_RTN_64                  = 0x00000039,
12370 TC_OP_WBL2_NC                            = 0x0000003a,
12371 TC_OP_WBL2_WC                            = 0x0000003b,
12372 TC_OP_RESERVED_NON_FLOAT_RTN_64_1        = 0x0000003c,
12373 TC_OP_RESERVED_NON_FLOAT_RTN_64_2        = 0x0000003d,
12374 TC_OP_RESERVED_NON_FLOAT_RTN_64_3        = 0x0000003e,
12375 TC_OP_RESERVED_NON_FLOAT_RTN_64_4        = 0x0000003f,
12376 TC_OP_WBINVL1                            = 0x00000040,
12377 TC_OP_ATOMIC_FCMPSWAP_32                 = 0x00000041,
12378 TC_OP_ATOMIC_FMIN_32                     = 0x00000042,
12379 TC_OP_ATOMIC_FMAX_32                     = 0x00000043,
12380 TC_OP_RESERVED_FOP_32_0                  = 0x00000044,
12381 TC_OP_RESERVED_FOP_32_1                  = 0x00000045,
12382 TC_OP_RESERVED_FOP_32_2                  = 0x00000046,
12383 TC_OP_ATOMIC_SWAP_32                     = 0x00000047,
12384 TC_OP_ATOMIC_CMPSWAP_32                  = 0x00000048,
12385 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32    = 0x00000049,
12386 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32        = 0x0000004a,
12387 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32        = 0x0000004b,
12388 TC_OP_INV_METADATA                       = 0x0000004c,
12389 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1     = 0x0000004d,
12390 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2     = 0x0000004e,
12391 TC_OP_ATOMIC_ADD_32                      = 0x0000004f,
12392 TC_OP_ATOMIC_SUB_32                      = 0x00000050,
12393 TC_OP_ATOMIC_SMIN_32                     = 0x00000051,
12394 TC_OP_ATOMIC_UMIN_32                     = 0x00000052,
12395 TC_OP_ATOMIC_SMAX_32                     = 0x00000053,
12396 TC_OP_ATOMIC_UMAX_32                     = 0x00000054,
12397 TC_OP_ATOMIC_AND_32                      = 0x00000055,
12398 TC_OP_ATOMIC_OR_32                       = 0x00000056,
12399 TC_OP_ATOMIC_XOR_32                      = 0x00000057,
12400 TC_OP_ATOMIC_INC_32                      = 0x00000058,
12401 TC_OP_ATOMIC_DEC_32                      = 0x00000059,
12402 TC_OP_INVL2_NC                           = 0x0000005a,
12403 TC_OP_NOP_RTN0                           = 0x0000005b,
12404 TC_OP_RESERVED_NON_FLOAT_32_1            = 0x0000005c,
12405 TC_OP_RESERVED_NON_FLOAT_32_2            = 0x0000005d,
12406 TC_OP_RESERVED_NON_FLOAT_32_3            = 0x0000005e,
12407 TC_OP_RESERVED_NON_FLOAT_32_4            = 0x0000005f,
12408 TC_OP_WBINVL2                            = 0x00000060,
12409 TC_OP_ATOMIC_FCMPSWAP_64                 = 0x00000061,
12410 TC_OP_ATOMIC_FMIN_64                     = 0x00000062,
12411 TC_OP_ATOMIC_FMAX_64                     = 0x00000063,
12412 TC_OP_RESERVED_FOP_64_0                  = 0x00000064,
12413 TC_OP_RESERVED_FOP_64_1                  = 0x00000065,
12414 TC_OP_RESERVED_FOP_64_2                  = 0x00000066,
12415 TC_OP_ATOMIC_SWAP_64                     = 0x00000067,
12416 TC_OP_ATOMIC_CMPSWAP_64                  = 0x00000068,
12417 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64    = 0x00000069,
12418 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64        = 0x0000006a,
12419 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64        = 0x0000006b,
12420 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0     = 0x0000006c,
12421 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1     = 0x0000006d,
12422 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2     = 0x0000006e,
12423 TC_OP_ATOMIC_ADD_64                      = 0x0000006f,
12424 TC_OP_ATOMIC_SUB_64                      = 0x00000070,
12425 TC_OP_ATOMIC_SMIN_64                     = 0x00000071,
12426 TC_OP_ATOMIC_UMIN_64                     = 0x00000072,
12427 TC_OP_ATOMIC_SMAX_64                     = 0x00000073,
12428 TC_OP_ATOMIC_UMAX_64                     = 0x00000074,
12429 TC_OP_ATOMIC_AND_64                      = 0x00000075,
12430 TC_OP_ATOMIC_OR_64                       = 0x00000076,
12431 TC_OP_ATOMIC_XOR_64                      = 0x00000077,
12432 TC_OP_ATOMIC_INC_64                      = 0x00000078,
12433 TC_OP_ATOMIC_DEC_64                      = 0x00000079,
12434 TC_OP_WBINVL2_NC                         = 0x0000007a,
12435 TC_OP_NOP_ACK                            = 0x0000007b,
12436 TC_OP_RESERVED_NON_FLOAT_64_1            = 0x0000007c,
12437 TC_OP_RESERVED_NON_FLOAT_64_2            = 0x0000007d,
12438 TC_OP_RESERVED_NON_FLOAT_64_3            = 0x0000007e,
12439 TC_OP_RESERVED_NON_FLOAT_64_4            = 0x0000007f,
12440 } TC_OP;
12441 
12442 /*
12443  * TC_NACKS enum
12444  */
12445 
12446 typedef enum TC_NACKS {
12447 TC_NACK_NO_FAULT                         = 0x00000000,
12448 TC_NACK_PAGE_FAULT                       = 0x00000001,
12449 TC_NACK_PROTECTION_FAULT                 = 0x00000002,
12450 TC_NACK_DATA_ERROR                       = 0x00000003,
12451 } TC_NACKS;
12452 
12453 /*
12454  * TC_EA_CID enum
12455  */
12456 
12457 typedef enum TC_EA_CID {
12458 TC_EA_CID_RT                             = 0x00000000,
12459 TC_EA_CID_FMASK                          = 0x00000001,
12460 TC_EA_CID_DCC                            = 0x00000002,
12461 TC_EA_CID_TCPMETA                        = 0x00000003,
12462 TC_EA_CID_Z                              = 0x00000004,
12463 TC_EA_CID_STENCIL                        = 0x00000005,
12464 TC_EA_CID_HTILE                          = 0x00000006,
12465 TC_EA_CID_MISC                           = 0x00000007,
12466 TC_EA_CID_TCP                            = 0x00000008,
12467 TC_EA_CID_SQC                            = 0x00000009,
12468 TC_EA_CID_CPF                            = 0x0000000a,
12469 TC_EA_CID_CPG                            = 0x0000000b,
12470 TC_EA_CID_IA                             = 0x0000000c,
12471 TC_EA_CID_WD                             = 0x0000000d,
12472 TC_EA_CID_PA                             = 0x0000000e,
12473 TC_EA_CID_UTCL2_TPI                      = 0x0000000f,
12474 } TC_EA_CID;
12475 
12476 /*******************************************************
12477  * GL2 Enums
12478  *******************************************************/
12479 
12480 /*
12481  * GL2_OP_MASKS enum
12482  */
12483 
12484 typedef enum GL2_OP_MASKS {
12485 GL2_OP_MASK_FLUSH_DENROM                 = 0x00000008,
12486 GL2_OP_MASK_64                           = 0x00000020,
12487 GL2_OP_MASK_NO_RTN                       = 0x00000040,
12488 } GL2_OP_MASKS;
12489 
12490 /*
12491  * GL2_OP enum
12492  */
12493 
12494 typedef enum GL2_OP {
12495 GL2_OP_READ                              = 0x00000000,
12496 GL2_OP_ATOMIC_FCMPSWAP_RTN_32            = 0x00000001,
12497 GL2_OP_ATOMIC_FMIN_RTN_32                = 0x00000002,
12498 GL2_OP_ATOMIC_FMAX_RTN_32                = 0x00000003,
12499 GL2_OP_ATOMIC_SWAP_RTN_32                = 0x00000007,
12500 GL2_OP_ATOMIC_CMPSWAP_RTN_32             = 0x00000008,
12501 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32  = 0x00000009,
12502 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32   = 0x0000000a,
12503 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32   = 0x0000000b,
12504 GL2_OP_PROBE_FILTER                      = 0x0000000c,
12505 GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1  = 0x0000000d,
12506 GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2  = 0x0000000e,
12507 GL2_OP_ATOMIC_ADD_RTN_32                 = 0x0000000f,
12508 GL2_OP_ATOMIC_SUB_RTN_32                 = 0x00000010,
12509 GL2_OP_ATOMIC_SMIN_RTN_32                = 0x00000011,
12510 GL2_OP_ATOMIC_UMIN_RTN_32                = 0x00000012,
12511 GL2_OP_ATOMIC_SMAX_RTN_32                = 0x00000013,
12512 GL2_OP_ATOMIC_UMAX_RTN_32                = 0x00000014,
12513 GL2_OP_ATOMIC_AND_RTN_32                 = 0x00000015,
12514 GL2_OP_ATOMIC_OR_RTN_32                  = 0x00000016,
12515 GL2_OP_ATOMIC_XOR_RTN_32                 = 0x00000017,
12516 GL2_OP_ATOMIC_INC_RTN_32                 = 0x00000018,
12517 GL2_OP_ATOMIC_DEC_RTN_32                 = 0x00000019,
12518 GL2_OP_WRITE                             = 0x00000020,
12519 GL2_OP_ATOMIC_FCMPSWAP_RTN_64            = 0x00000021,
12520 GL2_OP_ATOMIC_FMIN_RTN_64                = 0x00000022,
12521 GL2_OP_ATOMIC_FMAX_RTN_64                = 0x00000023,
12522 GL2_OP_ATOMIC_SWAP_RTN_64                = 0x00000027,
12523 GL2_OP_ATOMIC_CMPSWAP_RTN_64             = 0x00000028,
12524 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64  = 0x00000029,
12525 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64   = 0x0000002a,
12526 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64   = 0x0000002b,
12527 GL2_OP_ATOMIC_ADD_RTN_64                 = 0x0000002f,
12528 GL2_OP_ATOMIC_SUB_RTN_64                 = 0x00000030,
12529 GL2_OP_ATOMIC_SMIN_RTN_64                = 0x00000031,
12530 GL2_OP_ATOMIC_UMIN_RTN_64                = 0x00000032,
12531 GL2_OP_ATOMIC_SMAX_RTN_64                = 0x00000033,
12532 GL2_OP_ATOMIC_UMAX_RTN_64                = 0x00000034,
12533 GL2_OP_ATOMIC_AND_RTN_64                 = 0x00000035,
12534 GL2_OP_ATOMIC_OR_RTN_64                  = 0x00000036,
12535 GL2_OP_ATOMIC_XOR_RTN_64                 = 0x00000037,
12536 GL2_OP_ATOMIC_INC_RTN_64                 = 0x00000038,
12537 GL2_OP_ATOMIC_DEC_RTN_64                 = 0x00000039,
12538 GL2_OP_GL1_INV                           = 0x00000040,
12539 GL2_OP_ATOMIC_FCMPSWAP_32                = 0x00000041,
12540 GL2_OP_ATOMIC_FMIN_32                    = 0x00000042,
12541 GL2_OP_ATOMIC_FMAX_32                    = 0x00000043,
12542 GL2_OP_ATOMIC_SWAP_32                    = 0x00000047,
12543 GL2_OP_ATOMIC_CMPSWAP_32                 = 0x00000048,
12544 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32   = 0x00000049,
12545 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32       = 0x0000004a,
12546 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32       = 0x0000004b,
12547 GL2_OP_ATOMIC_ADD_32                     = 0x0000004f,
12548 GL2_OP_ATOMIC_SUB_32                     = 0x00000050,
12549 GL2_OP_ATOMIC_SMIN_32                    = 0x00000051,
12550 GL2_OP_ATOMIC_UMIN_32                    = 0x00000052,
12551 GL2_OP_ATOMIC_SMAX_32                    = 0x00000053,
12552 GL2_OP_ATOMIC_UMAX_32                    = 0x00000054,
12553 GL2_OP_ATOMIC_AND_32                     = 0x00000055,
12554 GL2_OP_ATOMIC_OR_32                      = 0x00000056,
12555 GL2_OP_ATOMIC_XOR_32                     = 0x00000057,
12556 GL2_OP_ATOMIC_INC_32                     = 0x00000058,
12557 GL2_OP_ATOMIC_DEC_32                     = 0x00000059,
12558 GL2_OP_NOP_RTN0                          = 0x0000005b,
12559 GL2_OP_ATOMIC_FCMPSWAP_64                = 0x00000061,
12560 GL2_OP_ATOMIC_FMIN_64                    = 0x00000062,
12561 GL2_OP_ATOMIC_FMAX_64                    = 0x00000063,
12562 GL2_OP_ATOMIC_SWAP_64                    = 0x00000067,
12563 GL2_OP_ATOMIC_CMPSWAP_64                 = 0x00000068,
12564 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64   = 0x00000069,
12565 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64       = 0x0000006a,
12566 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64       = 0x0000006b,
12567 GL2_OP_ATOMIC_ADD_64                     = 0x0000006f,
12568 GL2_OP_ATOMIC_SUB_64                     = 0x00000070,
12569 GL2_OP_ATOMIC_SMIN_64                    = 0x00000071,
12570 GL2_OP_ATOMIC_UMIN_64                    = 0x00000072,
12571 GL2_OP_ATOMIC_SMAX_64                    = 0x00000073,
12572 GL2_OP_ATOMIC_UMAX_64                    = 0x00000074,
12573 GL2_OP_ATOMIC_AND_64                     = 0x00000075,
12574 GL2_OP_ATOMIC_OR_64                      = 0x00000076,
12575 GL2_OP_ATOMIC_XOR_64                     = 0x00000077,
12576 GL2_OP_ATOMIC_INC_64                     = 0x00000078,
12577 GL2_OP_ATOMIC_DEC_64                     = 0x00000079,
12578 GL2_OP_NOP_ACK                           = 0x0000007b,
12579 } GL2_OP;
12580 
12581 /*
12582  * GL2_NACKS enum
12583  */
12584 
12585 typedef enum GL2_NACKS {
12586 GL2_NACK_NO_FAULT                        = 0x00000000,
12587 GL2_NACK_PAGE_FAULT                      = 0x00000001,
12588 GL2_NACK_PROTECTION_FAULT                = 0x00000002,
12589 GL2_NACK_DATA_ERROR                      = 0x00000003,
12590 } GL2_NACKS;
12591 
12592 /*
12593  * GL2_EA_CID enum
12594  */
12595 
12596 typedef enum GL2_EA_CID {
12597 GL2_EA_CID_CLIENT                        = 0x00000000,
12598 GL2_EA_CID_SDMA                          = 0x00000001,
12599 GL2_EA_CID_RLC                           = 0x00000002,
12600 GL2_EA_CID_CP                            = 0x00000004,
12601 GL2_EA_CID_CPDMA                         = 0x00000005,
12602 GL2_EA_CID_UTCL2                         = 0x00000006,
12603 GL2_EA_CID_RT                            = 0x00000007,
12604 GL2_EA_CID_FMASK                         = 0x00000008,
12605 GL2_EA_CID_DCC                           = 0x00000009,
12606 GL2_EA_CID_Z_STENCIL                     = 0x0000000a,
12607 GL2_EA_CID_ZPCPSD                        = 0x0000000b,
12608 GL2_EA_CID_HTILE                         = 0x0000000c,
12609 GL2_EA_CID_TCPMETA                       = 0x0000000f,
12610 } GL2_EA_CID;
12611 
12612 /*******************************************************
12613  * SPI Enums
12614  *******************************************************/
12615 
12616 /*
12617  * SPI_SAMPLE_CNTL enum
12618  */
12619 
12620 typedef enum SPI_SAMPLE_CNTL {
12621 CENTROIDS_ONLY                           = 0x00000000,
12622 CENTERS_ONLY                             = 0x00000001,
12623 CENTROIDS_AND_CENTERS                    = 0x00000002,
12624 UNDEF                                    = 0x00000003,
12625 } SPI_SAMPLE_CNTL;
12626 
12627 /*
12628  * SPI_FOG_MODE enum
12629  */
12630 
12631 typedef enum SPI_FOG_MODE {
12632 SPI_FOG_NONE                             = 0x00000000,
12633 SPI_FOG_EXP                              = 0x00000001,
12634 SPI_FOG_EXP2                             = 0x00000002,
12635 SPI_FOG_LINEAR                           = 0x00000003,
12636 } SPI_FOG_MODE;
12637 
12638 /*
12639  * SPI_PNT_SPRITE_OVERRIDE enum
12640  */
12641 
12642 typedef enum SPI_PNT_SPRITE_OVERRIDE {
12643 SPI_PNT_SPRITE_SEL_0                     = 0x00000000,
12644 SPI_PNT_SPRITE_SEL_1                     = 0x00000001,
12645 SPI_PNT_SPRITE_SEL_S                     = 0x00000002,
12646 SPI_PNT_SPRITE_SEL_T                     = 0x00000003,
12647 SPI_PNT_SPRITE_SEL_NONE                  = 0x00000004,
12648 } SPI_PNT_SPRITE_OVERRIDE;
12649 
12650 /*
12651  * SPI_PERFCNT_SEL enum
12652  */
12653 
12654 typedef enum SPI_PERFCNT_SEL {
12655 SPI_PERF_VS_WINDOW_VALID                 = 0x00000000,
12656 SPI_PERF_VS_BUSY                         = 0x00000001,
12657 SPI_PERF_VS_FIRST_WAVE                   = 0x00000002,
12658 SPI_PERF_VS_LAST_WAVE                    = 0x00000003,
12659 SPI_PERF_VS_LSHS_DEALLOC                 = 0x00000004,
12660 SPI_PERF_VS_PC_STALL                     = 0x00000005,
12661 SPI_PERF_VS_POS0_STALL                   = 0x00000006,
12662 SPI_PERF_VS_POS1_STALL                   = 0x00000007,
12663 SPI_PERF_VS_CRAWLER_STALL                = 0x00000008,
12664 SPI_PERF_VS_EVENT_WAVE                   = 0x00000009,
12665 SPI_PERF_VS_WAVE                         = 0x0000000a,
12666 SPI_PERF_VS_PERS_UPD_FULL0               = 0x0000000b,
12667 SPI_PERF_VS_PERS_UPD_FULL1               = 0x0000000c,
12668 SPI_PERF_VS_LATE_ALLOC_FULL              = 0x0000000d,
12669 SPI_PERF_VS_FIRST_SUBGRP                 = 0x0000000e,
12670 SPI_PERF_VS_LAST_SUBGRP                  = 0x0000000f,
12671 SPI_PERF_VS_ALLOC_CNT                    = 0x00000010,
12672 SPI_PERF_VS_PC_ALLOC_CNT                 = 0x00000011,
12673 SPI_PERF_VS_LATE_ALLOC_ACCUM             = 0x00000012,
12674 SPI_PERF_GS_WINDOW_VALID                 = 0x00000013,
12675 SPI_PERF_GS_BUSY                         = 0x00000014,
12676 SPI_PERF_GS_CRAWLER_STALL                = 0x00000015,
12677 SPI_PERF_GS_EVENT_WAVE                   = 0x00000016,
12678 SPI_PERF_GS_WAVE                         = 0x00000017,
12679 SPI_PERF_GS_PERS_UPD_FULL0               = 0x00000018,
12680 SPI_PERF_GS_PERS_UPD_FULL1               = 0x00000019,
12681 SPI_PERF_GS_FIRST_SUBGRP                 = 0x0000001a,
12682 SPI_PERF_GS_LAST_SUBGRP                  = 0x0000001b,
12683 SPI_PERF_GS_HS_DEALLOC                   = 0x0000001c,
12684 SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT      = 0x0000001d,
12685 SPI_PERF_GS_GRP_FIFO_FULL                = 0x0000001e,
12686 SPI_PERF_HS_WINDOW_VALID                 = 0x0000001f,
12687 SPI_PERF_HS_BUSY                         = 0x00000020,
12688 SPI_PERF_HS_CRAWLER_STALL                = 0x00000021,
12689 SPI_PERF_HS_FIRST_WAVE                   = 0x00000022,
12690 SPI_PERF_HS_LAST_WAVE                    = 0x00000023,
12691 SPI_PERF_HS_OFFCHIP_LDS_STALL            = 0x00000024,
12692 SPI_PERF_HS_EVENT_WAVE                   = 0x00000025,
12693 SPI_PERF_HS_WAVE                         = 0x00000026,
12694 SPI_PERF_HS_PERS_UPD_FULL0               = 0x00000027,
12695 SPI_PERF_HS_PERS_UPD_FULL1               = 0x00000028,
12696 SPI_PERF_CSG_WINDOW_VALID                = 0x00000029,
12697 SPI_PERF_CSG_BUSY                        = 0x0000002a,
12698 SPI_PERF_CSG_NUM_THREADGROUPS            = 0x0000002b,
12699 SPI_PERF_CSG_CRAWLER_STALL               = 0x0000002c,
12700 SPI_PERF_CSG_EVENT_WAVE                  = 0x0000002d,
12701 SPI_PERF_CSG_WAVE                        = 0x0000002e,
12702 SPI_PERF_CSN_WINDOW_VALID                = 0x0000002f,
12703 SPI_PERF_CSN_BUSY                        = 0x00000030,
12704 SPI_PERF_CSN_NUM_THREADGROUPS            = 0x00000031,
12705 SPI_PERF_CSN_CRAWLER_STALL               = 0x00000032,
12706 SPI_PERF_CSN_EVENT_WAVE                  = 0x00000033,
12707 SPI_PERF_CSN_WAVE                        = 0x00000034,
12708 SPI_PERF_PS0_WINDOW_VALID                = 0x00000035,
12709 SPI_PERF_PS1_WINDOW_VALID                = 0x00000036,
12710 SPI_PERF_PS2_WINDOW_VALID                = 0x00000037,
12711 SPI_PERF_PS3_WINDOW_VALID                = 0x00000038,
12712 SPI_PERF_PS0_BUSY                        = 0x00000039,
12713 SPI_PERF_PS1_BUSY                        = 0x0000003a,
12714 SPI_PERF_PS2_BUSY                        = 0x0000003b,
12715 SPI_PERF_PS3_BUSY                        = 0x0000003c,
12716 SPI_PERF_PS0_ACTIVE                      = 0x0000003d,
12717 SPI_PERF_PS1_ACTIVE                      = 0x0000003e,
12718 SPI_PERF_PS2_ACTIVE                      = 0x0000003f,
12719 SPI_PERF_PS3_ACTIVE                      = 0x00000040,
12720 SPI_PERF_PS0_DEALLOC_BIN0                = 0x00000041,
12721 SPI_PERF_PS1_DEALLOC_BIN0                = 0x00000042,
12722 SPI_PERF_PS2_DEALLOC_BIN0                = 0x00000043,
12723 SPI_PERF_PS3_DEALLOC_BIN0                = 0x00000044,
12724 SPI_PERF_PS0_FPOS_BIN1_STALL             = 0x00000045,
12725 SPI_PERF_PS1_FPOS_BIN1_STALL             = 0x00000046,
12726 SPI_PERF_PS2_FPOS_BIN1_STALL             = 0x00000047,
12727 SPI_PERF_PS3_FPOS_BIN1_STALL             = 0x00000048,
12728 SPI_PERF_PS0_EVENT_WAVE                  = 0x00000049,
12729 SPI_PERF_PS1_EVENT_WAVE                  = 0x0000004a,
12730 SPI_PERF_PS2_EVENT_WAVE                  = 0x0000004b,
12731 SPI_PERF_PS3_EVENT_WAVE                  = 0x0000004c,
12732 SPI_PERF_PS0_WAVE                        = 0x0000004d,
12733 SPI_PERF_PS1_WAVE                        = 0x0000004e,
12734 SPI_PERF_PS2_WAVE                        = 0x0000004f,
12735 SPI_PERF_PS3_WAVE                        = 0x00000050,
12736 SPI_PERF_PS0_OPT_WAVE                    = 0x00000051,
12737 SPI_PERF_PS1_OPT_WAVE                    = 0x00000052,
12738 SPI_PERF_PS2_OPT_WAVE                    = 0x00000053,
12739 SPI_PERF_PS3_OPT_WAVE                    = 0x00000054,
12740 SPI_PERF_PS0_PASS_BIN0                   = 0x00000055,
12741 SPI_PERF_PS1_PASS_BIN0                   = 0x00000056,
12742 SPI_PERF_PS2_PASS_BIN0                   = 0x00000057,
12743 SPI_PERF_PS3_PASS_BIN0                   = 0x00000058,
12744 SPI_PERF_PS0_PASS_BIN1                   = 0x00000059,
12745 SPI_PERF_PS1_PASS_BIN1                   = 0x0000005a,
12746 SPI_PERF_PS2_PASS_BIN1                   = 0x0000005b,
12747 SPI_PERF_PS3_PASS_BIN1                   = 0x0000005c,
12748 SPI_PERF_PS0_FPOS_BIN2                   = 0x0000005d,
12749 SPI_PERF_PS1_FPOS_BIN2                   = 0x0000005e,
12750 SPI_PERF_PS2_FPOS_BIN2                   = 0x0000005f,
12751 SPI_PERF_PS3_FPOS_BIN2                   = 0x00000060,
12752 SPI_PERF_PS0_PRIM_BIN0                   = 0x00000061,
12753 SPI_PERF_PS1_PRIM_BIN0                   = 0x00000062,
12754 SPI_PERF_PS2_PRIM_BIN0                   = 0x00000063,
12755 SPI_PERF_PS3_PRIM_BIN0                   = 0x00000064,
12756 SPI_PERF_PS0_PRIM_BIN1                   = 0x00000065,
12757 SPI_PERF_PS1_PRIM_BIN1                   = 0x00000066,
12758 SPI_PERF_PS2_PRIM_BIN1                   = 0x00000067,
12759 SPI_PERF_PS3_PRIM_BIN1                   = 0x00000068,
12760 SPI_PERF_PS0_CNF_BIN2                    = 0x00000069,
12761 SPI_PERF_PS1_CNF_BIN2                    = 0x0000006a,
12762 SPI_PERF_PS2_CNF_BIN2                    = 0x0000006b,
12763 SPI_PERF_PS3_CNF_BIN2                    = 0x0000006c,
12764 SPI_PERF_PS0_CNF_BIN3                    = 0x0000006d,
12765 SPI_PERF_PS1_CNF_BIN3                    = 0x0000006e,
12766 SPI_PERF_PS2_CNF_BIN3                    = 0x0000006f,
12767 SPI_PERF_PS3_CNF_BIN3                    = 0x00000070,
12768 SPI_PERF_PS0_CRAWLER_STALL               = 0x00000071,
12769 SPI_PERF_PS1_CRAWLER_STALL               = 0x00000072,
12770 SPI_PERF_PS2_CRAWLER_STALL               = 0x00000073,
12771 SPI_PERF_PS3_CRAWLER_STALL               = 0x00000074,
12772 SPI_PERF_PS0_LDS_RES_FULL                = 0x00000075,
12773 SPI_PERF_PS1_LDS_RES_FULL                = 0x00000076,
12774 SPI_PERF_PS2_LDS_RES_FULL                = 0x00000077,
12775 SPI_PERF_PS3_LDS_RES_FULL                = 0x00000078,
12776 SPI_PERF_PS_PERS_UPD_FULL0               = 0x00000079,
12777 SPI_PERF_PS_PERS_UPD_FULL1               = 0x0000007a,
12778 SPI_PERF_PS0_POPS_WAVE_SENT              = 0x0000007b,
12779 SPI_PERF_PS1_POPS_WAVE_SENT              = 0x0000007c,
12780 SPI_PERF_PS2_POPS_WAVE_SENT              = 0x0000007d,
12781 SPI_PERF_PS3_POPS_WAVE_SENT              = 0x0000007e,
12782 SPI_PERF_PS0_POPS_WAVE_EXIT              = 0x0000007f,
12783 SPI_PERF_PS1_POPS_WAVE_EXIT              = 0x00000080,
12784 SPI_PERF_PS2_POPS_WAVE_EXIT              = 0x00000081,
12785 SPI_PERF_PS3_POPS_WAVE_EXIT              = 0x00000082,
12786 SPI_PERF_LDS0_PC_VALID                   = 0x00000083,
12787 SPI_PERF_LDS1_PC_VALID                   = 0x00000084,
12788 SPI_PERF_RA_PIPE_REQ_BIN2                = 0x00000085,
12789 SPI_PERF_RA_TASK_REQ_BIN3                = 0x00000086,
12790 SPI_PERF_RA_WR_CTL_FULL                  = 0x00000087,
12791 SPI_PERF_RA_REQ_NO_ALLOC                 = 0x00000088,
12792 SPI_PERF_RA_REQ_NO_ALLOC_PS              = 0x00000089,
12793 SPI_PERF_RA_REQ_NO_ALLOC_VS              = 0x0000008a,
12794 SPI_PERF_RA_REQ_NO_ALLOC_GS              = 0x0000008b,
12795 SPI_PERF_RA_REQ_NO_ALLOC_HS              = 0x0000008c,
12796 SPI_PERF_RA_REQ_NO_ALLOC_CSG             = 0x0000008d,
12797 SPI_PERF_RA_REQ_NO_ALLOC_CSN             = 0x0000008e,
12798 SPI_PERF_RA_RES_STALL_PS                 = 0x0000008f,
12799 SPI_PERF_RA_RES_STALL_VS                 = 0x00000090,
12800 SPI_PERF_RA_RES_STALL_GS                 = 0x00000091,
12801 SPI_PERF_RA_RES_STALL_HS                 = 0x00000092,
12802 SPI_PERF_RA_RES_STALL_CSG                = 0x00000093,
12803 SPI_PERF_RA_RES_STALL_CSN                = 0x00000094,
12804 SPI_PERF_RA_TMP_STALL_PS                 = 0x00000095,
12805 SPI_PERF_RA_TMP_STALL_VS                 = 0x00000096,
12806 SPI_PERF_RA_TMP_STALL_GS                 = 0x00000097,
12807 SPI_PERF_RA_TMP_STALL_HS                 = 0x00000098,
12808 SPI_PERF_RA_TMP_STALL_CSG                = 0x00000099,
12809 SPI_PERF_RA_TMP_STALL_CSN                = 0x0000009a,
12810 SPI_PERF_RA_WAVE_SIMD_FULL_PS            = 0x0000009b,
12811 SPI_PERF_RA_WAVE_SIMD_FULL_VS            = 0x0000009c,
12812 SPI_PERF_RA_WAVE_SIMD_FULL_GS            = 0x0000009d,
12813 SPI_PERF_RA_WAVE_SIMD_FULL_HS            = 0x0000009e,
12814 SPI_PERF_RA_WAVE_SIMD_FULL_CSG           = 0x0000009f,
12815 SPI_PERF_RA_WAVE_SIMD_FULL_CSN           = 0x000000a0,
12816 SPI_PERF_RA_VGPR_SIMD_FULL_PS            = 0x000000a1,
12817 SPI_PERF_RA_VGPR_SIMD_FULL_VS            = 0x000000a2,
12818 SPI_PERF_RA_VGPR_SIMD_FULL_GS            = 0x000000a3,
12819 SPI_PERF_RA_VGPR_SIMD_FULL_HS            = 0x000000a4,
12820 SPI_PERF_RA_VGPR_SIMD_FULL_CSG           = 0x000000a5,
12821 SPI_PERF_RA_VGPR_SIMD_FULL_CSN           = 0x000000a6,
12822 SPI_PERF_RA_SGPR_SIMD_FULL_PS            = 0x000000a7,
12823 SPI_PERF_RA_SGPR_SIMD_FULL_VS            = 0x000000a8,
12824 SPI_PERF_RA_SGPR_SIMD_FULL_GS            = 0x000000a9,
12825 SPI_PERF_RA_SGPR_SIMD_FULL_HS            = 0x000000aa,
12826 SPI_PERF_RA_SGPR_SIMD_FULL_CSG           = 0x000000ab,
12827 SPI_PERF_RA_SGPR_SIMD_FULL_CSN           = 0x000000ac,
12828 SPI_PERF_RA_LDS_CU_FULL_PS               = 0x000000ad,
12829 SPI_PERF_RA_LDS_CU_FULL_LS               = 0x000000ae,
12830 SPI_PERF_RA_LDS_CU_FULL_ES               = 0x000000af,
12831 SPI_PERF_RA_LDS_CU_FULL_CSG              = 0x000000b0,
12832 SPI_PERF_RA_LDS_CU_FULL_CSN              = 0x000000b1,
12833 SPI_PERF_RA_BAR_CU_FULL_HS               = 0x000000b2,
12834 SPI_PERF_RA_BAR_CU_FULL_CSG              = 0x000000b3,
12835 SPI_PERF_RA_BAR_CU_FULL_CSN              = 0x000000b4,
12836 SPI_PERF_RA_BULKY_CU_FULL_CSG            = 0x000000b5,
12837 SPI_PERF_RA_BULKY_CU_FULL_CSN            = 0x000000b6,
12838 SPI_PERF_RA_TGLIM_CU_FULL_CSG            = 0x000000b7,
12839 SPI_PERF_RA_TGLIM_CU_FULL_CSN            = 0x000000b8,
12840 SPI_PERF_RA_WVLIM_STALL_PS               = 0x000000b9,
12841 SPI_PERF_RA_WVLIM_STALL_VS               = 0x000000ba,
12842 SPI_PERF_RA_WVLIM_STALL_GS               = 0x000000bb,
12843 SPI_PERF_RA_WVLIM_STALL_HS               = 0x000000bc,
12844 SPI_PERF_RA_WVLIM_STALL_CSG              = 0x000000bd,
12845 SPI_PERF_RA_WVLIM_STALL_CSN              = 0x000000be,
12846 SPI_PERF_RA_VS_LOCK                      = 0x000000bf,
12847 SPI_PERF_RA_GS_LOCK                      = 0x000000c0,
12848 SPI_PERF_RA_HS_LOCK                      = 0x000000c1,
12849 SPI_PERF_RA_CSG_LOCK                     = 0x000000c2,
12850 SPI_PERF_RA_CSN_LOCK                     = 0x000000c3,
12851 SPI_PERF_RA_RSV_UPD                      = 0x000000c4,
12852 SPI_PERF_EXP_ARB_COL_CNT                 = 0x000000c5,
12853 SPI_PERF_EXP_ARB_PAR_CNT                 = 0x000000c6,
12854 SPI_PERF_EXP_ARB_POS_CNT                 = 0x000000c7,
12855 SPI_PERF_EXP_ARB_GDS_CNT                 = 0x000000c8,
12856 SPI_PERF_NUM_PS_COL_R0_EXPORTS           = 0x000000c9,
12857 SPI_PERF_NUM_PS_COL_R1_EXPORTS           = 0x000000ca,
12858 SPI_PERF_NUM_VS_POS_R0_EXPORTS           = 0x000000cb,
12859 SPI_PERF_NUM_VS_POS_R1_EXPORTS           = 0x000000cc,
12860 SPI_PERF_NUM_VS_PARAM_R0_EXPORTS         = 0x000000cd,
12861 SPI_PERF_NUM_VS_PARAM_R1_EXPORTS         = 0x000000ce,
12862 SPI_PERF_NUM_VS_GDS_R0_EXPORTS           = 0x000000cf,
12863 SPI_PERF_NUM_VS_GDS_R1_EXPORTS           = 0x000000d0,
12864 SPI_PERF_NUM_EXPGRANT_EXPORTS            = 0x000000d1,
12865 SPI_PERF_CLKGATE_BUSY_STALL              = 0x000000d2,
12866 SPI_PERF_CLKGATE_ACTIVE_STALL            = 0x000000d3,
12867 SPI_PERF_CLKGATE_ALL_CLOCKS_ON           = 0x000000d4,
12868 SPI_PERF_CLKGATE_CGTT_DYN_ON             = 0x000000d5,
12869 SPI_PERF_CLKGATE_CGTT_REG_ON             = 0x000000d6,
12870 SPI_PERF_PIX_ALLOC_PEND_CNT              = 0x000000d7,
12871 SPI_PERF_PIX_ALLOC_SCB0_STALL            = 0x000000d8,
12872 SPI_PERF_PIX_ALLOC_SCB1_STALL            = 0x000000d9,
12873 SPI_PERF_PIX_ALLOC_SCB2_STALL            = 0x000000da,
12874 SPI_PERF_PIX_ALLOC_SCB3_STALL            = 0x000000db,
12875 SPI_PERF_PIX_ALLOC_DB0_STALL             = 0x000000dc,
12876 SPI_PERF_PIX_ALLOC_DB1_STALL             = 0x000000dd,
12877 SPI_PERF_PIX_ALLOC_DB2_STALL             = 0x000000de,
12878 SPI_PERF_PIX_ALLOC_DB3_STALL             = 0x000000df,
12879 SPI_PERF_PIX_ALLOC_DB4_STALL             = 0x000000e0,
12880 SPI_PERF_PIX_ALLOC_DB5_STALL             = 0x000000e1,
12881 SPI_PERF_PIX_ALLOC_DB6_STALL             = 0x000000e2,
12882 SPI_PERF_PIX_ALLOC_DB7_STALL             = 0x000000e3,
12883 SPI_PERF_PC_ALLOC_ACCUM                  = 0x000000e4,
12884 SPI_PERF_GS_NGG_SE_HAS_BATON             = 0x000000e5,
12885 SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON   = 0x000000e6,
12886 SPI_PERF_GS_NGG_SE_FORWARDED_BATON       = 0x000000e7,
12887 SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT         = 0x000000e8,
12888 SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT  = 0x000000e9,
12889 SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT  = 0x000000ea,
12890 SPI_PERF_GS_NGG_PC_FULL                  = 0x000000eb,
12891 SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC         = 0x000000ec,
12892 SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY      = 0x000000ed,
12893 SPI_PERF_GSC_VTX_BUSY                    = 0x000000ee,
12894 SPI_PERF_GSC_VTX_INPUT_STARVED           = 0x000000ef,
12895 SPI_PERF_GSC_VTX_VSR_STALL               = 0x000000f0,
12896 SPI_PERF_GSC_VTX_VSR_FULL                = 0x000000f1,
12897 SPI_PERF_GSC_VTX_CAC_BUSY                = 0x000000f2,
12898 SPI_PERF_ESC_VTX_BUSY                    = 0x000000f3,
12899 SPI_PERF_ESC_VTX_INPUT_STARVED           = 0x000000f4,
12900 SPI_PERF_ESC_VTX_VSR_STALL               = 0x000000f5,
12901 SPI_PERF_ESC_VTX_VSR_FULL                = 0x000000f6,
12902 SPI_PERF_ESC_VTX_CAC_BUSY                = 0x000000f7,
12903 SPI_PERF_SWC_PS_WR                       = 0x000000f8,
12904 SPI_PERF_SWC_VS_WR                       = 0x000000f9,
12905 SPI_PERF_SWC_GS_WR                       = 0x000000fa,
12906 SPI_PERF_SWC_HS_WR                       = 0x000000fb,
12907 SPI_PERF_SWC_CSG_WR                      = 0x000000fc,
12908 SPI_PERF_SWC_CSC_WR                      = 0x000000fd,
12909 SPI_PERF_VWC_PS_WR                       = 0x000000fe,
12910 SPI_PERF_VWC_VS_WR                       = 0x000000ff,
12911 SPI_PERF_VWC_GS_WR                       = 0x00000100,
12912 SPI_PERF_VWC_HS_WR                       = 0x00000101,
12913 SPI_PERF_VWC_CSG_WR                      = 0x00000102,
12914 SPI_PERF_VWC_CSC_WR                      = 0x00000103,
12915 SPI_PERF_ES_WINDOW_VALID                 = 0x00000104,
12916 SPI_PERF_ES_BUSY                         = 0x00000105,
12917 SPI_PERF_ES_CRAWLER_STALL                = 0x00000106,
12918 SPI_PERF_ES_FIRST_WAVE                   = 0x00000107,
12919 SPI_PERF_ES_LAST_WAVE                    = 0x00000108,
12920 SPI_PERF_ES_LSHS_DEALLOC                 = 0x00000109,
12921 SPI_PERF_ES_EVENT_WAVE                   = 0x0000010a,
12922 SPI_PERF_ES_WAVE                         = 0x0000010b,
12923 SPI_PERF_ES_PERS_UPD_FULL0               = 0x0000010c,
12924 SPI_PERF_ES_PERS_UPD_FULL1               = 0x0000010d,
12925 SPI_PERF_ES_FIRST_SUBGRP                 = 0x0000010e,
12926 SPI_PERF_ES_LAST_SUBGRP                  = 0x0000010f,
12927 SPI_PERF_LS_WINDOW_VALID                 = 0x00000110,
12928 SPI_PERF_LS_BUSY                         = 0x00000111,
12929 SPI_PERF_LS_CRAWLER_STALL                = 0x00000112,
12930 SPI_PERF_LS_FIRST_WAVE                   = 0x00000113,
12931 SPI_PERF_LS_LAST_WAVE                    = 0x00000114,
12932 SPI_PERF_LS_OFFCHIP_LDS_STALL            = 0x00000115,
12933 SPI_PERF_LS_EVENT_WAVE                   = 0x00000116,
12934 SPI_PERF_LS_WAVE                         = 0x00000117,
12935 SPI_PERF_LS_PERS_UPD_FULL0               = 0x00000118,
12936 SPI_PERF_LS_PERS_UPD_FULL1               = 0x00000119,
12937 } SPI_PERFCNT_SEL;
12938 
12939 /*
12940  * SPI_SHADER_FORMAT enum
12941  */
12942 
12943 typedef enum SPI_SHADER_FORMAT {
12944 SPI_SHADER_NONE                          = 0x00000000,
12945 SPI_SHADER_1COMP                         = 0x00000001,
12946 SPI_SHADER_2COMP                         = 0x00000002,
12947 SPI_SHADER_4COMPRESS                     = 0x00000003,
12948 SPI_SHADER_4COMP                         = 0x00000004,
12949 } SPI_SHADER_FORMAT;
12950 
12951 /*
12952  * SPI_SHADER_EX_FORMAT enum
12953  */
12954 
12955 typedef enum SPI_SHADER_EX_FORMAT {
12956 SPI_SHADER_ZERO                          = 0x00000000,
12957 SPI_SHADER_32_R                          = 0x00000001,
12958 SPI_SHADER_32_GR                         = 0x00000002,
12959 SPI_SHADER_32_AR                         = 0x00000003,
12960 SPI_SHADER_FP16_ABGR                     = 0x00000004,
12961 SPI_SHADER_UNORM16_ABGR                  = 0x00000005,
12962 SPI_SHADER_SNORM16_ABGR                  = 0x00000006,
12963 SPI_SHADER_UINT16_ABGR                   = 0x00000007,
12964 SPI_SHADER_SINT16_ABGR                   = 0x00000008,
12965 SPI_SHADER_32_ABGR                       = 0x00000009,
12966 } SPI_SHADER_EX_FORMAT;
12967 
12968 /*
12969  * CLKGATE_SM_MODE enum
12970  */
12971 
12972 typedef enum CLKGATE_SM_MODE {
12973 ON_SEQ                                   = 0x00000000,
12974 OFF_SEQ                                  = 0x00000001,
12975 PROG_SEQ                                 = 0x00000002,
12976 READ_SEQ                                 = 0x00000003,
12977 SM_MODE_RESERVED                         = 0x00000004,
12978 } CLKGATE_SM_MODE;
12979 
12980 /*
12981  * CLKGATE_BASE_MODE enum
12982  */
12983 
12984 typedef enum CLKGATE_BASE_MODE {
12985 MULT_8                                   = 0x00000000,
12986 MULT_16                                  = 0x00000001,
12987 } CLKGATE_BASE_MODE;
12988 
12989 /*
12990  * SPI_LB_WAVES_SELECT enum
12991  */
12992 
12993 typedef enum SPI_LB_WAVES_SELECT {
12994 HS_GS                                    = 0x00000000,
12995 VS_PS                                    = 0x00000001,
12996 CS_NA                                    = 0x00000002,
12997 SPI_LB_WAVES_RSVD                        = 0x00000003,
12998 } SPI_LB_WAVES_SELECT;
12999 
13000 /*******************************************************
13001  * SQ Enums
13002  *******************************************************/
13003 
13004 /*
13005  * SQ_TEX_CLAMP enum
13006  */
13007 
13008 typedef enum SQ_TEX_CLAMP {
13009 SQ_TEX_WRAP                              = 0x00000000,
13010 SQ_TEX_MIRROR                            = 0x00000001,
13011 SQ_TEX_CLAMP_LAST_TEXEL                  = 0x00000002,
13012 SQ_TEX_MIRROR_ONCE_LAST_TEXEL            = 0x00000003,
13013 SQ_TEX_CLAMP_HALF_BORDER                 = 0x00000004,
13014 SQ_TEX_MIRROR_ONCE_HALF_BORDER           = 0x00000005,
13015 SQ_TEX_CLAMP_BORDER                      = 0x00000006,
13016 SQ_TEX_MIRROR_ONCE_BORDER                = 0x00000007,
13017 } SQ_TEX_CLAMP;
13018 
13019 /*
13020  * SQ_TEX_XY_FILTER enum
13021  */
13022 
13023 typedef enum SQ_TEX_XY_FILTER {
13024 SQ_TEX_XY_FILTER_POINT                   = 0x00000000,
13025 SQ_TEX_XY_FILTER_BILINEAR                = 0x00000001,
13026 SQ_TEX_XY_FILTER_ANISO_POINT             = 0x00000002,
13027 SQ_TEX_XY_FILTER_ANISO_BILINEAR          = 0x00000003,
13028 } SQ_TEX_XY_FILTER;
13029 
13030 /*
13031  * SQ_TEX_Z_FILTER enum
13032  */
13033 
13034 typedef enum SQ_TEX_Z_FILTER {
13035 SQ_TEX_Z_FILTER_NONE                     = 0x00000000,
13036 SQ_TEX_Z_FILTER_POINT                    = 0x00000001,
13037 SQ_TEX_Z_FILTER_LINEAR                   = 0x00000002,
13038 } SQ_TEX_Z_FILTER;
13039 
13040 /*
13041  * SQ_TEX_MIP_FILTER enum
13042  */
13043 
13044 typedef enum SQ_TEX_MIP_FILTER {
13045 SQ_TEX_MIP_FILTER_NONE                   = 0x00000000,
13046 SQ_TEX_MIP_FILTER_POINT                  = 0x00000001,
13047 SQ_TEX_MIP_FILTER_LINEAR                 = 0x00000002,
13048 SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ        = 0x00000003,
13049 } SQ_TEX_MIP_FILTER;
13050 
13051 /*
13052  * SQ_TEX_ANISO_RATIO enum
13053  */
13054 
13055 typedef enum SQ_TEX_ANISO_RATIO {
13056 SQ_TEX_ANISO_RATIO_1                     = 0x00000000,
13057 SQ_TEX_ANISO_RATIO_2                     = 0x00000001,
13058 SQ_TEX_ANISO_RATIO_4                     = 0x00000002,
13059 SQ_TEX_ANISO_RATIO_8                     = 0x00000003,
13060 SQ_TEX_ANISO_RATIO_16                    = 0x00000004,
13061 } SQ_TEX_ANISO_RATIO;
13062 
13063 /*
13064  * SQ_TEX_DEPTH_COMPARE enum
13065  */
13066 
13067 typedef enum SQ_TEX_DEPTH_COMPARE {
13068 SQ_TEX_DEPTH_COMPARE_NEVER               = 0x00000000,
13069 SQ_TEX_DEPTH_COMPARE_LESS                = 0x00000001,
13070 SQ_TEX_DEPTH_COMPARE_EQUAL               = 0x00000002,
13071 SQ_TEX_DEPTH_COMPARE_LESSEQUAL           = 0x00000003,
13072 SQ_TEX_DEPTH_COMPARE_GREATER             = 0x00000004,
13073 SQ_TEX_DEPTH_COMPARE_NOTEQUAL            = 0x00000005,
13074 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL        = 0x00000006,
13075 SQ_TEX_DEPTH_COMPARE_ALWAYS              = 0x00000007,
13076 } SQ_TEX_DEPTH_COMPARE;
13077 
13078 /*
13079  * SQ_TEX_BORDER_COLOR enum
13080  */
13081 
13082 typedef enum SQ_TEX_BORDER_COLOR {
13083 SQ_TEX_BORDER_COLOR_TRANS_BLACK          = 0x00000000,
13084 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK         = 0x00000001,
13085 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE         = 0x00000002,
13086 SQ_TEX_BORDER_COLOR_REGISTER             = 0x00000003,
13087 } SQ_TEX_BORDER_COLOR;
13088 
13089 /*
13090  * SQ_RSRC_BUF_TYPE enum
13091  */
13092 
13093 typedef enum SQ_RSRC_BUF_TYPE {
13094 SQ_RSRC_BUF                              = 0x00000000,
13095 SQ_RSRC_BUF_RSVD_1                       = 0x00000001,
13096 SQ_RSRC_BUF_RSVD_2                       = 0x00000002,
13097 SQ_RSRC_BUF_RSVD_3                       = 0x00000003,
13098 } SQ_RSRC_BUF_TYPE;
13099 
13100 /*
13101  * SQ_RSRC_IMG_TYPE enum
13102  */
13103 
13104 typedef enum SQ_RSRC_IMG_TYPE {
13105 SQ_RSRC_IMG_RSVD_0                       = 0x00000000,
13106 SQ_RSRC_IMG_RSVD_1                       = 0x00000001,
13107 SQ_RSRC_IMG_RSVD_2                       = 0x00000002,
13108 SQ_RSRC_IMG_RSVD_3                       = 0x00000003,
13109 SQ_RSRC_IMG_RSVD_4                       = 0x00000004,
13110 SQ_RSRC_IMG_RSVD_5                       = 0x00000005,
13111 SQ_RSRC_IMG_RSVD_6                       = 0x00000006,
13112 SQ_RSRC_IMG_RSVD_7                       = 0x00000007,
13113 SQ_RSRC_IMG_1D                           = 0x00000008,
13114 SQ_RSRC_IMG_2D                           = 0x00000009,
13115 SQ_RSRC_IMG_3D                           = 0x0000000a,
13116 SQ_RSRC_IMG_CUBE                         = 0x0000000b,
13117 SQ_RSRC_IMG_1D_ARRAY                     = 0x0000000c,
13118 SQ_RSRC_IMG_2D_ARRAY                     = 0x0000000d,
13119 SQ_RSRC_IMG_2D_MSAA                      = 0x0000000e,
13120 SQ_RSRC_IMG_2D_MSAA_ARRAY                = 0x0000000f,
13121 } SQ_RSRC_IMG_TYPE;
13122 
13123 /*
13124  * SQ_RSRC_FLAT_TYPE enum
13125  */
13126 
13127 typedef enum SQ_RSRC_FLAT_TYPE {
13128 SQ_RSRC_FLAT_RSVD_0                      = 0x00000000,
13129 SQ_RSRC_FLAT                             = 0x00000001,
13130 SQ_RSRC_FLAT_RSVD_2                      = 0x00000002,
13131 SQ_RSRC_FLAT_RSVD_3                      = 0x00000003,
13132 } SQ_RSRC_FLAT_TYPE;
13133 
13134 /*
13135  * SQ_IMG_FILTER_TYPE enum
13136  */
13137 
13138 typedef enum SQ_IMG_FILTER_TYPE {
13139 SQ_IMG_FILTER_MODE_BLEND                 = 0x00000000,
13140 SQ_IMG_FILTER_MODE_MIN                   = 0x00000001,
13141 SQ_IMG_FILTER_MODE_MAX                   = 0x00000002,
13142 } SQ_IMG_FILTER_TYPE;
13143 
13144 /*
13145  * SQ_SEL_XYZW01 enum
13146  */
13147 
13148 typedef enum SQ_SEL_XYZW01 {
13149 SQ_SEL_0                                 = 0x00000000,
13150 SQ_SEL_1                                 = 0x00000001,
13151 SQ_SEL_N_BC_1                            = 0x00000002,
13152 SQ_SEL_RESERVED_1                        = 0x00000003,
13153 SQ_SEL_X                                 = 0x00000004,
13154 SQ_SEL_Y                                 = 0x00000005,
13155 SQ_SEL_Z                                 = 0x00000006,
13156 SQ_SEL_W                                 = 0x00000007,
13157 } SQ_SEL_XYZW01;
13158 
13159 /*
13160  * SQ_OOB_SELECT enum
13161  */
13162 
13163 typedef enum SQ_OOB_SELECT {
13164 SQ_OOB_INDEX_AND_OFFSET                  = 0x00000000,
13165 SQ_OOB_INDEX_ONLY                        = 0x00000001,
13166 SQ_OOB_NUM_RECORDS_0                     = 0x00000002,
13167 SQ_OOB_COMPLETE                          = 0x00000003,
13168 } SQ_OOB_SELECT;
13169 
13170 /*
13171  * SQ_WAVE_TYPE enum
13172  */
13173 
13174 typedef enum SQ_WAVE_TYPE {
13175 SQ_WAVE_TYPE_PS                          = 0x00000000,
13176 SQ_WAVE_TYPE_VS                          = 0x00000001,
13177 SQ_WAVE_TYPE_GS                          = 0x00000002,
13178 SQ_WAVE_TYPE_ES                          = 0x00000003,
13179 SQ_WAVE_TYPE_HS                          = 0x00000004,
13180 SQ_WAVE_TYPE_LS                          = 0x00000005,
13181 SQ_WAVE_TYPE_CS                          = 0x00000006,
13182 SQ_WAVE_TYPE_PS1                         = 0x00000007,
13183 SQ_WAVE_TYPE_PS2                         = 0x00000008,
13184 SQ_WAVE_TYPE_PS3                         = 0x00000009,
13185 } SQ_WAVE_TYPE;
13186 
13187 /*
13188  * SQ_PERF_SEL enum
13189  */
13190 
13191 typedef enum SQ_PERF_SEL {
13192 SQ_PERF_SEL_NONE                         = 0x00000000,
13193 SQ_PERF_SEL_ACCUM_PREV                   = 0x00000001,
13194 SQ_PERF_SEL_CYCLES                       = 0x00000002,
13195 SQ_PERF_SEL_BUSY_CYCLES                  = 0x00000003,
13196 SQ_PERF_SEL_WAVES                        = 0x00000004,
13197 SQ_PERF_SEL_WAVES_32                     = 0x00000005,
13198 SQ_PERF_SEL_WAVES_64                     = 0x00000006,
13199 SQ_PERF_SEL_LEVEL_WAVES                  = 0x00000007,
13200 SQ_PERF_SEL_ITEMS                        = 0x00000008,
13201 SQ_PERF_SEL_WAVE32_ITEMS                 = 0x00000009,
13202 SQ_PERF_SEL_WAVE64_ITEMS                 = 0x0000000a,
13203 SQ_PERF_SEL_QUADS                        = 0x0000000b,
13204 SQ_PERF_SEL_EVENTS                       = 0x0000000c,
13205 SQ_PERF_SEL_WAVES_EQ_64                  = 0x0000000d,
13206 SQ_PERF_SEL_WAVES_LT_64                  = 0x0000000e,
13207 SQ_PERF_SEL_WAVES_LT_48                  = 0x0000000f,
13208 SQ_PERF_SEL_WAVES_LT_32                  = 0x00000010,
13209 SQ_PERF_SEL_WAVES_LT_16                  = 0x00000011,
13210 SQ_PERF_SEL_WAVES_RESTORED               = 0x00000012,
13211 SQ_PERF_SEL_WAVES_SAVED                  = 0x00000013,
13212 SQ_PERF_SEL_MSG                          = 0x00000014,
13213 SQ_PERF_SEL_MSG_GSCNT                    = 0x00000015,
13214 SQ_PERF_SEL_MSG_INTERRUPT                = 0x00000016,
13215 SQ_PERF_SEL_Reserved_1                   = 0x00000017,
13216 SQ_PERF_SEL_Reserved_2                   = 0x00000018,
13217 SQ_PERF_SEL_Reserved_3                   = 0x00000019,
13218 SQ_PERF_SEL_WAVE_CYCLES                  = 0x0000001a,
13219 SQ_PERF_SEL_WAVE_READY                   = 0x0000001b,
13220 SQ_PERF_SEL_WAIT_INST_ANY                = 0x0000001c,
13221 SQ_PERF_SEL_WAIT_INST_VALU               = 0x0000001d,
13222 SQ_PERF_SEL_WAIT_INST_SCA                = 0x0000001e,
13223 SQ_PERF_SEL_WAIT_INST_LDS                = 0x0000001f,
13224 SQ_PERF_SEL_WAIT_INST_TEX                = 0x00000020,
13225 SQ_PERF_SEL_WAIT_INST_FLAT               = 0x00000021,
13226 SQ_PERF_SEL_WAIT_INST_VMEM               = 0x00000022,
13227 SQ_PERF_SEL_WAIT_INST_EXP_GDS            = 0x00000023,
13228 SQ_PERF_SEL_WAIT_INST_BR_MSG             = 0x00000024,
13229 SQ_PERF_SEL_WAIT_ANY                     = 0x00000025,
13230 SQ_PERF_SEL_WAIT_CNT_ANY                 = 0x00000026,
13231 SQ_PERF_SEL_WAIT_CNT_VMVS                = 0x00000027,
13232 SQ_PERF_SEL_WAIT_CNT_LGKM                = 0x00000028,
13233 SQ_PERF_SEL_WAIT_CNT_EXP                 = 0x00000029,
13234 SQ_PERF_SEL_WAIT_TTRACE                  = 0x0000002a,
13235 SQ_PERF_SEL_WAIT_IFETCH                  = 0x0000002b,
13236 SQ_PERF_SEL_WAIT_BARRIER                 = 0x0000002c,
13237 SQ_PERF_SEL_WAIT_EXP_ALLOC               = 0x0000002d,
13238 SQ_PERF_SEL_WAIT_SLEEP                   = 0x0000002e,
13239 SQ_PERF_SEL_WAIT_SLEEP_XNACK             = 0x0000002f,
13240 SQ_PERF_SEL_WAIT_OTHER                   = 0x00000030,
13241 SQ_PERF_SEL_INSTS_ALL                    = 0x00000031,
13242 SQ_PERF_SEL_INSTS_BRANCH                 = 0x00000032,
13243 SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN      = 0x00000033,
13244 SQ_PERF_SEL_INSTS_CBRANCH_TAKEN          = 0x00000034,
13245 SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS   = 0x00000035,
13246 SQ_PERF_SEL_INSTS_EXP_GDS                = 0x00000036,
13247 SQ_PERF_SEL_INSTS_GDS                    = 0x00000037,
13248 SQ_PERF_SEL_INSTS_EXP                    = 0x00000038,
13249 SQ_PERF_SEL_INSTS_FLAT                   = 0x00000039,
13250 SQ_PERF_SEL_Reserved_4                   = 0x0000003a,
13251 SQ_PERF_SEL_INSTS_LDS                    = 0x0000003b,
13252 SQ_PERF_SEL_INSTS_SALU                   = 0x0000003c,
13253 SQ_PERF_SEL_INSTS_SMEM                   = 0x0000003d,
13254 SQ_PERF_SEL_INSTS_SMEM_NORM              = 0x0000003e,
13255 SQ_PERF_SEL_INSTS_SENDMSG                = 0x0000003f,
13256 SQ_PERF_SEL_INSTS_VALU                   = 0x00000040,
13257 SQ_PERF_SEL_Reserved_17                  = 0x00000041,
13258 SQ_PERF_SEL_INSTS_VALU_TRANS32           = 0x00000042,
13259 SQ_PERF_SEL_INSTS_VALU_NO_COEXEC         = 0x00000043,
13260 SQ_PERF_SEL_INSTS_TEX                    = 0x00000044,
13261 SQ_PERF_SEL_INSTS_TEX_LOAD               = 0x00000045,
13262 SQ_PERF_SEL_INSTS_TEX_STORE              = 0x00000046,
13263 SQ_PERF_SEL_INSTS_WAVE32                 = 0x00000047,
13264 SQ_PERF_SEL_INSTS_WAVE32_FLAT            = 0x00000048,
13265 SQ_PERF_SEL_Reserved_5                   = 0x00000049,
13266 SQ_PERF_SEL_INSTS_WAVE32_LDS             = 0x0000004a,
13267 SQ_PERF_SEL_INSTS_WAVE32_VALU            = 0x0000004b,
13268 SQ_PERF_SEL_Reserved_16                  = 0x0000004c,
13269 SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32    = 0x0000004d,
13270 SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC  = 0x0000004e,
13271 SQ_PERF_SEL_INSTS_WAVE32_TEX             = 0x0000004f,
13272 SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD        = 0x00000050,
13273 SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE       = 0x00000051,
13274 SQ_PERF_SEL_ITEM_CYCLES_VALU             = 0x00000052,
13275 SQ_PERF_SEL_VALU_READWRITELANE_CYCLES    = 0x00000053,
13276 SQ_PERF_SEL_WAVE32_INSTS                 = 0x00000054,
13277 SQ_PERF_SEL_WAVE64_INSTS                 = 0x00000055,
13278 SQ_PERF_SEL_Reserved_18                  = 0x00000056,
13279 SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED      = 0x00000057,
13280 SQ_PERF_SEL_WAVE64_HALF_SKIP             = 0x00000058,
13281 SQ_PERF_SEL_INSTS_TEX_REPLAY             = 0x00000059,
13282 SQ_PERF_SEL_INSTS_SMEM_REPLAY            = 0x0000005a,
13283 SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY       = 0x0000005b,
13284 SQ_PERF_SEL_INSTS_FLAT_REPLAY            = 0x0000005c,
13285 SQ_PERF_SEL_XNACK_ALL                    = 0x0000005d,
13286 SQ_PERF_SEL_XNACK_FIRST                  = 0x0000005e,
13287 SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD     = 0x0000005f,
13288 SQ_PERF_SEL_INSTS_VALU_VINTRP_OP         = 0x00000060,
13289 SQ_PERF_SEL_INST_LEVEL_EXP               = 0x00000061,
13290 SQ_PERF_SEL_INST_LEVEL_GDS               = 0x00000062,
13291 SQ_PERF_SEL_INST_LEVEL_LDS               = 0x00000063,
13292 SQ_PERF_SEL_INST_LEVEL_SMEM              = 0x00000064,
13293 SQ_PERF_SEL_INST_LEVEL_TEX_LOAD          = 0x00000065,
13294 SQ_PERF_SEL_INST_LEVEL_TEX_STORE         = 0x00000066,
13295 SQ_PERF_SEL_IFETCH_REQS                  = 0x00000067,
13296 SQ_PERF_SEL_IFETCH_LEVEL                 = 0x00000068,
13297 SQ_PERF_SEL_IFETCH_XNACK                 = 0x00000069,
13298 SQ_PERF_SEL_Reserved_6                   = 0x0000006a,
13299 SQ_PERF_SEL_Reserved_7                   = 0x0000006b,
13300 SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL  = 0x0000006c,
13301 SQ_PERF_SEL_VALU_SGATHER_STALL           = 0x0000006d,
13302 SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL   = 0x0000006e,
13303 SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL  = 0x0000006f,
13304 SQ_PERF_SEL_VALU_SGATHER_FULL_STALL      = 0x00000070,
13305 SQ_PERF_SEL_SALU_SGATHER_STALL           = 0x00000071,
13306 SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL  = 0x00000072,
13307 SQ_PERF_SEL_SALU_GATHER_FULL_STALL       = 0x00000073,
13308 SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL  = 0x00000074,
13309 SQ_PERF_SEL_INST_CYCLES_VALU             = 0x00000075,
13310 SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32     = 0x00000076,
13311 SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC   = 0x00000077,
13312 SQ_PERF_SEL_INST_CYCLES_VMEM             = 0x00000078,
13313 SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD        = 0x00000079,
13314 SQ_PERF_SEL_INST_CYCLES_VMEM_STORE       = 0x0000007a,
13315 SQ_PERF_SEL_INST_CYCLES_LDS              = 0x0000007b,
13316 SQ_PERF_SEL_INST_CYCLES_TEX              = 0x0000007c,
13317 SQ_PERF_SEL_INST_CYCLES_FLAT             = 0x0000007d,
13318 SQ_PERF_SEL_INST_CYCLES_EXP_GDS          = 0x0000007e,
13319 SQ_PERF_SEL_VMEM_ARB_FIFO_FULL           = 0x0000007f,
13320 SQ_PERF_SEL_MSG_FIFO_FULL_STALL          = 0x00000080,
13321 SQ_PERF_SEL_EXP_REQ_FIFO_FULL            = 0x00000081,
13322 SQ_PERF_SEL_Reserved_8                   = 0x00000082,
13323 SQ_PERF_SEL_Reserved_9                   = 0x00000083,
13324 SQ_PERF_SEL_Reserved_10                  = 0x00000084,
13325 SQ_PERF_SEL_Reserved_11                  = 0x00000085,
13326 SQ_PERF_SEL_Reserved_12                  = 0x00000086,
13327 SQ_PERF_SEL_Reserved_13                  = 0x00000087,
13328 SQ_PERF_SEL_Reserved_14                  = 0x00000088,
13329 SQ_PERF_SEL_VMEM_BUS_ACTIVE              = 0x00000089,
13330 SQ_PERF_SEL_VMEM_BUS_STALL               = 0x0000008a,
13331 SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL  = 0x0000008b,
13332 SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL  = 0x0000008c,
13333 SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL  = 0x0000008d,
13334 SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL  = 0x0000008e,
13335 SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY    = 0x0000008f,
13336 SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY   = 0x00000090,
13337 SQ_PERF_SEL_Reserved_15                  = 0x00000091,
13338 SQ_PERF_SEL_SALU_PIPE_STALL              = 0x00000092,
13339 SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES    = 0x00000093,
13340 SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL     = 0x00000094,
13341 SQ_PERF_SEL_MSG_BUS_BUSY                 = 0x00000095,
13342 SQ_PERF_SEL_EXP_REQ_BUS_STALL            = 0x00000096,
13343 SQ_PERF_SEL_EXP_REQ0_BUS_BUSY            = 0x00000097,
13344 SQ_PERF_SEL_EXP_REQ1_BUS_BUSY            = 0x00000098,
13345 SQ_PERF_SEL_EXP_BUS0_BUSY                = 0x00000099,
13346 SQ_PERF_SEL_EXP_BUS1_BUSY                = 0x0000009a,
13347 SQ_PERF_SEL_INST_CACHE_REQS              = 0x0000009b,
13348 SQ_PERF_SEL_INST_CACHE_REQ_STALL         = 0x0000009c,
13349 SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU  = 0x0000009d,
13350 SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU  = 0x0000009e,
13351 SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM  = 0x0000009f,
13352 SQ_PERF_SEL_USER0                        = 0x000000a0,
13353 SQ_PERF_SEL_USER1                        = 0x000000a1,
13354 SQ_PERF_SEL_USER2                        = 0x000000a2,
13355 SQ_PERF_SEL_USER3                        = 0x000000a3,
13356 SQ_PERF_SEL_USER4                        = 0x000000a4,
13357 SQ_PERF_SEL_USER5                        = 0x000000a5,
13358 SQ_PERF_SEL_USER6                        = 0x000000a6,
13359 SQ_PERF_SEL_USER7                        = 0x000000a7,
13360 SQ_PERF_SEL_USER8                        = 0x000000a8,
13361 SQ_PERF_SEL_USER9                        = 0x000000a9,
13362 SQ_PERF_SEL_USER10                       = 0x000000aa,
13363 SQ_PERF_SEL_USER11                       = 0x000000ab,
13364 SQ_PERF_SEL_USER12                       = 0x000000ac,
13365 SQ_PERF_SEL_USER13                       = 0x000000ad,
13366 SQ_PERF_SEL_USER14                       = 0x000000ae,
13367 SQ_PERF_SEL_USER15                       = 0x000000af,
13368 SQ_PERF_SEL_USER_LEVEL0                  = 0x000000b0,
13369 SQ_PERF_SEL_USER_LEVEL1                  = 0x000000b1,
13370 SQ_PERF_SEL_USER_LEVEL2                  = 0x000000b2,
13371 SQ_PERF_SEL_USER_LEVEL3                  = 0x000000b3,
13372 SQ_PERF_SEL_USER_LEVEL4                  = 0x000000b4,
13373 SQ_PERF_SEL_USER_LEVEL5                  = 0x000000b5,
13374 SQ_PERF_SEL_USER_LEVEL6                  = 0x000000b6,
13375 SQ_PERF_SEL_USER_LEVEL7                  = 0x000000b7,
13376 SQ_PERF_SEL_USER_LEVEL8                  = 0x000000b8,
13377 SQ_PERF_SEL_USER_LEVEL9                  = 0x000000b9,
13378 SQ_PERF_SEL_USER_LEVEL10                 = 0x000000ba,
13379 SQ_PERF_SEL_USER_LEVEL11                 = 0x000000bb,
13380 SQ_PERF_SEL_USER_LEVEL12                 = 0x000000bc,
13381 SQ_PERF_SEL_USER_LEVEL13                 = 0x000000bd,
13382 SQ_PERF_SEL_USER_LEVEL14                 = 0x000000be,
13383 SQ_PERF_SEL_USER_LEVEL15                 = 0x000000bf,
13384 SQ_PERF_SEL_VALU_RETURN_SDST             = 0x000000c0,
13385 SQ_PERF_SEL_VMEM_SECOND_TRY_USED         = 0x000000c1,
13386 SQ_PERF_SEL_VMEM_SECOND_TRY_STALL        = 0x000000c2,
13387 SQ_PERF_SEL_DUMMY_END                    = 0x000000c3,
13388 SQ_PERF_SEL_DUMMY_LAST                   = 0x000000ff,
13389 SQG_PERF_SEL_UTCL0_TRANSLATION_MISS      = 0x00000100,
13390 SQG_PERF_SEL_UTCL0_PERMISSION_MISS       = 0x00000101,
13391 SQG_PERF_SEL_UTCL0_TRANSLATION_HIT       = 0x00000102,
13392 SQG_PERF_SEL_UTCL0_REQUEST               = 0x00000103,
13393 SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL   = 0x00000104,
13394 SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX    = 0x00000105,
13395 SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT    = 0x00000106,
13396 SQG_PERF_SEL_UTCL0_LFIFO_FULL            = 0x00000107,
13397 SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES   = 0x00000108,
13398 SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS  = 0x00000109,
13399 SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL         = 0x0000010a,
13400 SQG_PERF_SEL_UTCL0_UTCL1_REQ             = 0x0000010b,
13401 SQG_PERF_SEL_TLB_SHOOTDOWN               = 0x0000010c,
13402 SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES        = 0x0000010d,
13403 SQG_PERF_SEL_TTRACE_REQS                 = 0x0000010e,
13404 SQG_PERF_SEL_TTRACE_INFLIGHT_REQS        = 0x0000010f,
13405 SQG_PERF_SEL_TTRACE_STALL                = 0x00000110,
13406 SQG_PERF_SEL_TTRACE_LOST_PACKETS         = 0x00000111,
13407 SQG_PERF_SEL_DUMMY_LAST                  = 0x00000112,
13408 SQC_PERF_SEL_POWER_VALU                  = 0x00000113,
13409 SQC_PERF_SEL_POWER_VALU0                 = 0x00000114,
13410 SQC_PERF_SEL_POWER_VALU1                 = 0x00000115,
13411 SQC_PERF_SEL_POWER_VALU2                 = 0x00000116,
13412 SQC_PERF_SEL_POWER_GPR_RD                = 0x00000117,
13413 SQC_PERF_SEL_POWER_GPR_WR                = 0x00000118,
13414 SQC_PERF_SEL_POWER_LDS_BUSY              = 0x00000119,
13415 SQC_PERF_SEL_POWER_ALU_BUSY              = 0x0000011a,
13416 SQC_PERF_SEL_POWER_TEX_BUSY              = 0x0000011b,
13417 SQC_PERF_SEL_PT_POWER_STALL              = 0x0000011c,
13418 SQC_PERF_SEL_LDS_BANK_CONFLICT           = 0x0000011d,
13419 SQC_PERF_SEL_LDS_ADDR_CONFLICT           = 0x0000011e,
13420 SQC_PERF_SEL_LDS_UNALIGNED_STALL         = 0x0000011f,
13421 SQC_PERF_SEL_LDS_MEM_VIOLATIONS          = 0x00000120,
13422 SQC_PERF_SEL_LDS_ATOMIC_RETURN           = 0x00000121,
13423 SQC_PERF_SEL_LDS_IDX_ACTIVE              = 0x00000122,
13424 SQC_PERF_SEL_LDS_DATA_FIFO_FULL          = 0x00000123,
13425 SQC_PERF_SEL_LDS_CMD_FIFO_FULL           = 0x00000124,
13426 SQC_PERF_SEL_LDS_ADDR_STALL              = 0x00000125,
13427 SQC_PERF_SEL_LDS_ADDR_ACTIVE             = 0x00000126,
13428 SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL  = 0x00000127,
13429 SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD   = 0x00000128,
13430 SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD  = 0x00000129,
13431 SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL    = 0x0000012a,
13432 SQC_PERF_SEL_LDS_FP_ADD_CYCLES           = 0x0000012b,
13433 SQC_PERF_SEL_ICACHE_BUSY_CYCLES          = 0x0000012c,
13434 SQC_PERF_SEL_ICACHE_REQ                  = 0x0000012d,
13435 SQC_PERF_SEL_ICACHE_HITS                 = 0x0000012e,
13436 SQC_PERF_SEL_ICACHE_MISSES               = 0x0000012f,
13437 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE     = 0x00000130,
13438 SQC_PERF_SEL_ICACHE_INVAL_INST           = 0x00000131,
13439 SQC_PERF_SEL_ICACHE_INVAL_ASYNC          = 0x00000132,
13440 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL       = 0x00000133,
13441 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL       = 0x00000134,
13442 SQC_PERF_SEL_TC_INFLIGHT_LEVEL           = 0x00000135,
13443 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL    = 0x00000136,
13444 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL    = 0x00000137,
13445 SQC_PERF_SEL_ICACHE_INPUT_VALID_READY    = 0x00000138,
13446 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB   = 0x00000139,
13447 SQC_PERF_SEL_ICACHE_INPUT_VALIDB         = 0x0000013a,
13448 SQC_PERF_SEL_DCACHE_INPUT_VALID_READY    = 0x0000013b,
13449 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB   = 0x0000013c,
13450 SQC_PERF_SEL_DCACHE_INPUT_VALIDB         = 0x0000013d,
13451 SQC_PERF_SEL_TC_REQ                      = 0x0000013e,
13452 SQC_PERF_SEL_TC_INST_REQ                 = 0x0000013f,
13453 SQC_PERF_SEL_TC_DATA_READ_REQ            = 0x00000140,
13454 SQC_PERF_SEL_TC_DATA_WRITE_REQ           = 0x00000141,
13455 SQC_PERF_SEL_TC_DATA_ATOMIC_REQ          = 0x00000142,
13456 SQC_PERF_SEL_TC_STALL                    = 0x00000143,
13457 SQC_PERF_SEL_TC_STARVE                   = 0x00000144,
13458 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT  = 0x00000145,
13459 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB  = 0x00000146,
13460 SQC_PERF_SEL_ICACHE_CACHE_STALLED        = 0x00000147,
13461 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO  = 0x00000148,
13462 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX  = 0x00000149,
13463 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT   = 0x0000014a,
13464 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO  = 0x0000014b,
13465 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0x0000014c,
13466 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF  = 0x0000014d,
13467 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT  = 0x0000014e,
13468 SQC_PERF_SEL_DCACHE_BUSY_CYCLES          = 0x0000014f,
13469 SQC_PERF_SEL_DCACHE_REQ                  = 0x00000150,
13470 SQC_PERF_SEL_DCACHE_HITS                 = 0x00000151,
13471 SQC_PERF_SEL_DCACHE_MISSES               = 0x00000152,
13472 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE     = 0x00000153,
13473 SQC_PERF_SEL_DCACHE_INVAL_INST           = 0x00000154,
13474 SQC_PERF_SEL_DCACHE_INVAL_ASYNC          = 0x00000155,
13475 SQC_PERF_SEL_DCACHE_HIT_LRU_READ         = 0x00000156,
13476 SQC_PERF_SEL_DCACHE_WC_LRU_WRITE         = 0x00000157,
13477 SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE       = 0x00000158,
13478 SQC_PERF_SEL_DCACHE_ATOMIC               = 0x00000159,
13479 SQC_PERF_SEL_DCACHE_WB_INST              = 0x0000015a,
13480 SQC_PERF_SEL_DCACHE_WB_ASYNC             = 0x0000015b,
13481 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT  = 0x0000015c,
13482 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB  = 0x0000015d,
13483 SQC_PERF_SEL_DCACHE_CACHE_STALLED        = 0x0000015e,
13484 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO  = 0x0000015f,
13485 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX  = 0x00000160,
13486 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT   = 0x00000161,
13487 SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT    = 0x00000162,
13488 SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED  = 0x00000163,
13489 SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE  = 0x00000164,
13490 SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT  = 0x00000165,
13491 SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH  = 0x00000166,
13492 SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE  = 0x00000167,
13493 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO  = 0x00000168,
13494 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0x00000169,
13495 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF  = 0x0000016a,
13496 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT  = 0x0000016b,
13497 SQC_PERF_SEL_DCACHE_REQ_READ_1           = 0x0000016c,
13498 SQC_PERF_SEL_DCACHE_REQ_READ_2           = 0x0000016d,
13499 SQC_PERF_SEL_DCACHE_REQ_READ_4           = 0x0000016e,
13500 SQC_PERF_SEL_DCACHE_REQ_READ_8           = 0x0000016f,
13501 SQC_PERF_SEL_DCACHE_REQ_READ_16          = 0x00000170,
13502 SQC_PERF_SEL_DCACHE_REQ_TIME             = 0x00000171,
13503 SQC_PERF_SEL_DCACHE_REQ_WRITE_1          = 0x00000172,
13504 SQC_PERF_SEL_DCACHE_REQ_WRITE_2          = 0x00000173,
13505 SQC_PERF_SEL_DCACHE_REQ_WRITE_4          = 0x00000174,
13506 SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE        = 0x00000175,
13507 SQC_PERF_SEL_SQ_DCACHE_REQS              = 0x00000176,
13508 SQC_PERF_SEL_DCACHE_FLAT_REQ             = 0x00000177,
13509 SQC_PERF_SEL_DCACHE_NONFLAT_REQ          = 0x00000178,
13510 SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS  = 0x00000179,
13511 SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS  = 0x0000017a,
13512 SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT  = 0x0000017b,
13513 SQC_PERF_SEL_ICACHE_UTCL0_REQUEST        = 0x0000017c,
13514 SQC_PERF_SEL_ICACHE_UTCL0_XNACK          = 0x0000017d,
13515 SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX  = 0x0000017e,
13516 SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT  = 0x0000017f,
13517 SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL     = 0x00000180,
13518 SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES  = 0x00000181,
13519 SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS  = 0x00000182,
13520 SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT  = 0x00000183,
13521 SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL  = 0x00000184,
13522 SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS  = 0x00000185,
13523 SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS  = 0x00000186,
13524 SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT  = 0x00000187,
13525 SQC_PERF_SEL_DCACHE_UTCL0_REQUEST        = 0x00000188,
13526 SQC_PERF_SEL_DCACHE_UTCL0_XNACK          = 0x00000189,
13527 SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX  = 0x0000018a,
13528 SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT  = 0x0000018b,
13529 SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL     = 0x0000018c,
13530 SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES  = 0x0000018d,
13531 SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS  = 0x0000018e,
13532 SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT  = 0x0000018f,
13533 SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL  = 0x00000190,
13534 SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS  = 0x00000191,
13535 SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL  = 0x00000192,
13536 SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL  = 0x00000193,
13537 SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ        = 0x00000194,
13538 SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL  = 0x00000195,
13539 SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ        = 0x00000196,
13540 SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL  = 0x00000197,
13541 SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ        = 0x00000198,
13542 SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL  = 0x00000199,
13543 SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ        = 0x0000019a,
13544 SQC_PERF_SEL_ICACHE_GCR                  = 0x0000019b,
13545 SQC_PERF_SEL_ICACHE_GCR_HITS             = 0x0000019c,
13546 SQC_PERF_SEL_DCACHE_GCR                  = 0x0000019d,
13547 SQC_PERF_SEL_DCACHE_GCR_HITS             = 0x0000019e,
13548 SQC_PERF_SEL_ICACHE_GCR_INVALIDATE       = 0x0000019f,
13549 SQC_PERF_SEL_DCACHE_GCR_INVALIDATE       = 0x000001a0,
13550 SQC_PERF_SEL_DCACHE_GCR_WRITEBACK        = 0x000001a1,
13551 SQC_PERF_SEL_DUMMY_LAST                  = 0x000001a2,
13552 SP_PERF_SEL_DUMMY_BEGIN                  = 0x000001c0,
13553 SP_PERF_SEL_DUMMY_LAST                   = 0x000001ff,
13554 } SQ_PERF_SEL;
13555 
13556 /*
13557  * SQ_CAC_POWER_SEL enum
13558  */
13559 
13560 typedef enum SQ_CAC_POWER_SEL {
13561 SQ_CAC_POWER_VALU                        = 0x00000000,
13562 SQ_CAC_POWER_VALU0                       = 0x00000001,
13563 SQ_CAC_POWER_VALU1                       = 0x00000002,
13564 SQ_CAC_POWER_VALU2                       = 0x00000003,
13565 SQ_CAC_POWER_GPR_RD                      = 0x00000004,
13566 SQ_CAC_POWER_GPR_WR                      = 0x00000005,
13567 SQ_CAC_POWER_LDS_BUSY                    = 0x00000006,
13568 SQ_CAC_POWER_ALU_BUSY                    = 0x00000007,
13569 SQ_CAC_POWER_TEX_BUSY                    = 0x00000008,
13570 } SQ_CAC_POWER_SEL;
13571 
13572 /*
13573  * SQ_IND_CMD_CMD enum
13574  */
13575 
13576 typedef enum SQ_IND_CMD_CMD {
13577 SQ_IND_CMD_CMD_NULL                      = 0x00000000,
13578 SQ_IND_CMD_CMD_SETHALT                   = 0x00000001,
13579 SQ_IND_CMD_CMD_SAVECTX                   = 0x00000002,
13580 SQ_IND_CMD_CMD_KILL                      = 0x00000003,
13581 SQ_IND_CMD_CMD_DEBUG                     = 0x00000004,
13582 SQ_IND_CMD_CMD_TRAP                      = 0x00000005,
13583 SQ_IND_CMD_CMD_SET_SPI_PRIO              = 0x00000006,
13584 SQ_IND_CMD_CMD_SETFATALHALT              = 0x00000007,
13585 SQ_IND_CMD_CMD_SINGLE_STEP               = 0x00000008,
13586 } SQ_IND_CMD_CMD;
13587 
13588 /*
13589  * SQ_IND_CMD_MODE enum
13590  */
13591 
13592 typedef enum SQ_IND_CMD_MODE {
13593 SQ_IND_CMD_MODE_SINGLE                   = 0x00000000,
13594 SQ_IND_CMD_MODE_BROADCAST                = 0x00000001,
13595 SQ_IND_CMD_MODE_BROADCAST_QUEUE          = 0x00000002,
13596 SQ_IND_CMD_MODE_BROADCAST_PIPE           = 0x00000003,
13597 SQ_IND_CMD_MODE_BROADCAST_ME             = 0x00000004,
13598 } SQ_IND_CMD_MODE;
13599 
13600 /*
13601  * SQ_EDC_INFO_SOURCE enum
13602  */
13603 
13604 typedef enum SQ_EDC_INFO_SOURCE {
13605 SQ_EDC_INFO_SOURCE_INVALID               = 0x00000000,
13606 SQ_EDC_INFO_SOURCE_INST                  = 0x00000001,
13607 SQ_EDC_INFO_SOURCE_SGPR                  = 0x00000002,
13608 SQ_EDC_INFO_SOURCE_VGPR                  = 0x00000003,
13609 SQ_EDC_INFO_SOURCE_LDS                   = 0x00000004,
13610 SQ_EDC_INFO_SOURCE_GDS                   = 0x00000005,
13611 SQ_EDC_INFO_SOURCE_TA                    = 0x00000006,
13612 } SQ_EDC_INFO_SOURCE;
13613 
13614 /*
13615  * SQ_ROUND_MODE enum
13616  */
13617 
13618 typedef enum SQ_ROUND_MODE {
13619 SQ_ROUND_NEAREST_EVEN                    = 0x00000000,
13620 SQ_ROUND_PLUS_INFINITY                   = 0x00000001,
13621 SQ_ROUND_MINUS_INFINITY                  = 0x00000002,
13622 SQ_ROUND_TO_ZERO                         = 0x00000003,
13623 } SQ_ROUND_MODE;
13624 
13625 /*
13626  * SQ_INTERRUPT_WORD_ENCODING enum
13627  */
13628 
13629 typedef enum SQ_INTERRUPT_WORD_ENCODING {
13630 SQ_INTERRUPT_WORD_ENCODING_AUTO          = 0x00000000,
13631 SQ_INTERRUPT_WORD_ENCODING_INST          = 0x00000001,
13632 SQ_INTERRUPT_WORD_ENCODING_ERROR         = 0x00000002,
13633 } SQ_INTERRUPT_WORD_ENCODING;
13634 
13635 /*
13636  * SQ_IBUF_ST enum
13637  */
13638 
13639 typedef enum SQ_IBUF_ST {
13640 SQ_IBUF_IB_IDLE                          = 0x00000000,
13641 SQ_IBUF_IB_INI_WAIT_GNT                  = 0x00000001,
13642 SQ_IBUF_IB_INI_WAIT_DRET                 = 0x00000002,
13643 SQ_IBUF_IB_LE_4DW                        = 0x00000003,
13644 SQ_IBUF_IB_WAIT_DRET                     = 0x00000004,
13645 SQ_IBUF_IB_EMPTY_WAIT_DRET               = 0x00000005,
13646 SQ_IBUF_IB_DRET                          = 0x00000006,
13647 SQ_IBUF_IB_EMPTY_WAIT_GNT                = 0x00000007,
13648 } SQ_IBUF_ST;
13649 
13650 /*
13651  * SQ_INST_STR_ST enum
13652  */
13653 
13654 typedef enum SQ_INST_STR_ST {
13655 SQ_INST_STR_IB_WAVE_NORML                = 0x00000000,
13656 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV    = 0x00000001,
13657 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV     = 0x00000002,
13658 SQ_INST_STR_IB_WAVE_INST_SKIP_AV         = 0x00000003,
13659 SQ_INST_STR_IB_WAVE_SETVSKIP_ST0         = 0x00000004,
13660 SQ_INST_STR_IB_WAVE_SETVSKIP_ST1         = 0x00000005,
13661 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT       = 0x00000006,
13662 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT  = 0x00000007,
13663 } SQ_INST_STR_ST;
13664 
13665 /*
13666  * SQ_WAVE_IB_ECC_ST enum
13667  */
13668 
13669 typedef enum SQ_WAVE_IB_ECC_ST {
13670 SQ_WAVE_IB_ECC_CLEAN                     = 0x00000000,
13671 SQ_WAVE_IB_ECC_ERR_CONTINUE              = 0x00000001,
13672 SQ_WAVE_IB_ECC_ERR_HALT                  = 0x00000002,
13673 SQ_WAVE_IB_ECC_WITH_ERR_MSG              = 0x00000003,
13674 } SQ_WAVE_IB_ECC_ST;
13675 
13676 /*
13677  * SH_MEM_ADDRESS_MODE enum
13678  */
13679 
13680 typedef enum SH_MEM_ADDRESS_MODE {
13681 SH_MEM_ADDRESS_MODE_64                   = 0x00000000,
13682 SH_MEM_ADDRESS_MODE_32                   = 0x00000001,
13683 } SH_MEM_ADDRESS_MODE;
13684 
13685 /*
13686  * SH_MEM_RETRY_MODE enum
13687  */
13688 
13689 typedef enum SH_MEM_RETRY_MODE {
13690 SH_MEM_RETRY_MODE_ALL                    = 0x00000000,
13691 SH_MEM_RETRY_MODE_WRITEATOMIC            = 0x00000001,
13692 SH_MEM_RETRY_MODE_NONE                   = 0x00000002,
13693 } SH_MEM_RETRY_MODE;
13694 
13695 /*
13696  * SH_MEM_ALIGNMENT_MODE enum
13697  */
13698 
13699 typedef enum SH_MEM_ALIGNMENT_MODE {
13700 SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,
13701 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT       = 0x00000001,
13702 SH_MEM_ALIGNMENT_MODE_STRICT             = 0x00000002,
13703 SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000003,
13704 } SH_MEM_ALIGNMENT_MODE;
13705 
13706 /*
13707  * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum
13708  */
13709 
13710 typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT {
13711 SQ_TT_TOKEN_MASK_SQDEC_SHIFT             = 0x00000000,
13712 SQ_TT_TOKEN_MASK_SHDEC_SHIFT             = 0x00000001,
13713 SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT           = 0x00000002,
13714 SQ_TT_TOKEN_MASK_COMP_SHIFT              = 0x00000003,
13715 SQ_TT_TOKEN_MASK_CONTEXT_SHIFT           = 0x00000004,
13716 SQ_TT_TOKEN_MASK_CONFIG_SHIFT            = 0x00000005,
13717 SQ_TT_TOKEN_MASK_OTHER_SHIFT             = 0x00000006,
13718 SQ_TT_TOKEN_MASK_READS_SHIFT             = 0x00000007,
13719 } SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT;
13720 
13721 /*
13722  * SQ_TT_TOKEN_MASK_REG_INCLUDE enum
13723  */
13724 
13725 typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE {
13726 SQ_TT_TOKEN_MASK_SQDEC_BIT               = 0x00000001,
13727 SQ_TT_TOKEN_MASK_SHDEC_BIT               = 0x00000002,
13728 SQ_TT_TOKEN_MASK_GFXUDEC_BIT             = 0x00000004,
13729 SQ_TT_TOKEN_MASK_COMP_BIT                = 0x00000008,
13730 SQ_TT_TOKEN_MASK_CONTEXT_BIT             = 0x00000010,
13731 SQ_TT_TOKEN_MASK_CONFIG_BIT              = 0x00000020,
13732 SQ_TT_TOKEN_MASK_OTHER_BIT               = 0x00000040,
13733 SQ_TT_TOKEN_MASK_READS_BIT               = 0x00000080,
13734 } SQ_TT_TOKEN_MASK_REG_INCLUDE;
13735 
13736 /*
13737  * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum
13738  */
13739 
13740 typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT {
13741 SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT       = 0x00000000,
13742 SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT        = 0x00000001,
13743 SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT       = 0x00000002,
13744 SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT        = 0x00000003,
13745 SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT         = 0x00000004,
13746 SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT      = 0x00000005,
13747 SQ_TT_TOKEN_EXCLUDE_REG_SHIFT            = 0x00000006,
13748 SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT          = 0x00000007,
13749 SQ_TT_TOKEN_EXCLUDE_INST_SHIFT           = 0x00000008,
13750 SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT        = 0x00000009,
13751 SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT      = 0x0000000a,
13752 SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT           = 0x0000000b,
13753 } SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT;
13754 
13755 /*
13756  * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum
13757  */
13758 
13759 typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE {
13760 SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD       = 0x00000000,
13761 SQ_TT_INST_EXCLUDE_EXPGNT234             = 0x00000001,
13762 } SQ_TT_TOKEN_MASK_INST_EXCLUDE;
13763 
13764 /*
13765  * SQ_TT_MODE enum
13766  */
13767 
13768 typedef enum SQ_TT_MODE {
13769 SQ_TT_MODE_OFF                           = 0x00000000,
13770 SQ_TT_MODE_ON                            = 0x00000001,
13771 SQ_TT_MODE_GLOBAL                        = 0x00000002,
13772 SQ_TT_MODE_DETAIL                        = 0x00000003,
13773 } SQ_TT_MODE;
13774 
13775 /*
13776  * SQ_TT_WTYPE_INCLUDE_SHIFT enum
13777  */
13778 
13779 typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT {
13780 SQ_TT_WTYPE_INCLUDE_PS_SHIFT             = 0x00000000,
13781 SQ_TT_WTYPE_INCLUDE_VS_SHIFT             = 0x00000001,
13782 SQ_TT_WTYPE_INCLUDE_GS_SHIFT             = 0x00000002,
13783 SQ_TT_WTYPE_INCLUDE_ES_SHIFT             = 0x00000003,
13784 SQ_TT_WTYPE_INCLUDE_HS_SHIFT             = 0x00000004,
13785 SQ_TT_WTYPE_INCLUDE_LS_SHIFT             = 0x00000005,
13786 SQ_TT_WTYPE_INCLUDE_CS_SHIFT             = 0x00000006,
13787 } SQ_TT_WTYPE_INCLUDE_SHIFT;
13788 
13789 /*
13790  * SQ_TT_WTYPE_INCLUDE enum
13791  */
13792 
13793 typedef enum SQ_TT_WTYPE_INCLUDE {
13794 SQ_TT_WTYPE_INCLUDE_PS_BIT               = 0x00000001,
13795 SQ_TT_WTYPE_INCLUDE_VS_BIT               = 0x00000002,
13796 SQ_TT_WTYPE_INCLUDE_GS_BIT               = 0x00000004,
13797 SQ_TT_WTYPE_INCLUDE_ES_BIT               = 0x00000008,
13798 SQ_TT_WTYPE_INCLUDE_HS_BIT               = 0x00000010,
13799 SQ_TT_WTYPE_INCLUDE_LS_BIT               = 0x00000020,
13800 SQ_TT_WTYPE_INCLUDE_CS_BIT               = 0x00000040,
13801 } SQ_TT_WTYPE_INCLUDE;
13802 
13803 /*
13804  * SQ_TT_UTIL_TIMER enum
13805  */
13806 
13807 typedef enum SQ_TT_UTIL_TIMER {
13808 SQ_TT_UTIL_TIMER_100_CLK                 = 0x00000000,
13809 SQ_TT_UTIL_TIMER_250_CLK                 = 0x00000001,
13810 } SQ_TT_UTIL_TIMER;
13811 
13812 /*
13813  * SQ_TT_WAVESTART_MODE enum
13814  */
13815 
13816 typedef enum SQ_TT_WAVESTART_MODE {
13817 SQ_TT_WAVESTART_MODE_SHORT               = 0x00000000,
13818 SQ_TT_WAVESTART_MODE_ALLOC               = 0x00000001,
13819 SQ_TT_WAVESTART_MODE_PBB_ID              = 0x00000002,
13820 } SQ_TT_WAVESTART_MODE;
13821 
13822 /*
13823  * SQ_TT_RT_FREQ enum
13824  */
13825 
13826 typedef enum SQ_TT_RT_FREQ {
13827 SQ_TT_RT_FREQ_NEVER                      = 0x00000000,
13828 SQ_TT_RT_FREQ_1024_CLK                   = 0x00000001,
13829 SQ_TT_RT_FREQ_4096_CLK                   = 0x00000002,
13830 } SQ_TT_RT_FREQ;
13831 
13832 /*
13833  * SQ_WATCH_MODES enum
13834  */
13835 
13836 typedef enum SQ_WATCH_MODES {
13837 SQ_WATCH_MODE_READ                       = 0x00000000,
13838 SQ_WATCH_MODE_NONREAD                    = 0x00000001,
13839 SQ_WATCH_MODE_ATOMIC                     = 0x00000002,
13840 SQ_WATCH_MODE_ALL                        = 0x00000003,
13841 } SQ_WATCH_MODES;
13842 
13843 /*
13844  * SQ_WAVE_SCHED_MODES enum
13845  */
13846 
13847 typedef enum SQ_WAVE_SCHED_MODES {
13848 SQ_WAVE_SCHED_MODE_NORMAL                = 0x00000000,
13849 SQ_WAVE_SCHED_MODE_EXPERT                = 0x00000001,
13850 SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST       = 0x00000002,
13851 } SQ_WAVE_SCHED_MODES;
13852 
13853 /*
13854  * SQ_WAVE_TYPE value
13855  */
13856 
13857 #define SQ_WAVE_TYPE_PS0               0x00000000
13858 
13859 /*
13860  * SQIND_PARTITIONS value
13861  */
13862 
13863 #define SQIND_GLOBAL_REGS_OFFSET       0x00000000
13864 #define SQIND_GLOBAL_REGS_SIZE         0x00000008
13865 #define SQIND_LOCAL_REGS_OFFSET        0x00000008
13866 #define SQIND_LOCAL_REGS_SIZE          0x00000008
13867 #define SQIND_WAVE_HWREGS_OFFSET       0x00000100
13868 #define SQIND_WAVE_HWREGS_SIZE         0x00000100
13869 #define SQIND_WAVE_SGPRS_OFFSET        0x00000200
13870 #define SQIND_WAVE_SGPRS_SIZE          0x00000200
13871 #define SQIND_WAVE_VGPRS_OFFSET        0x00000400
13872 #define SQIND_WAVE_VGPRS_SIZE          0x00000400
13873 
13874 /*
13875  * SQ_GFXDEC value
13876  */
13877 
13878 #define SQ_GFXDEC_BEGIN                0x0000a000
13879 #define SQ_GFXDEC_END                  0x0000c000
13880 #define SQ_GFXDEC_STATE_ID_SHIFT       0x0000000a
13881 
13882 /*
13883  * SQDEC value
13884  */
13885 
13886 #define SQDEC_BEGIN                    0x00002300
13887 #define SQDEC_END                      0x000023ff
13888 
13889 /*
13890  * SQPERFSDEC value
13891  */
13892 
13893 #define SQPERFSDEC_BEGIN               0x0000d9c0
13894 #define SQPERFSDEC_END                 0x0000da40
13895 
13896 /*
13897  * SQPERFDDEC value
13898  */
13899 
13900 #define SQPERFDDEC_BEGIN               0x0000d1c0
13901 #define SQPERFDDEC_END                 0x0000d240
13902 
13903 /*
13904  * SQGFXUDEC value
13905  */
13906 
13907 #define SQGFXUDEC_BEGIN                0x0000c330
13908 #define SQGFXUDEC_END                  0x0000c380
13909 
13910 /*
13911  * SQPWRDEC value
13912  */
13913 
13914 #define SQPWRDEC_BEGIN                 0x0000f08c
13915 #define SQPWRDEC_END                   0x0000f094
13916 
13917 /*
13918  * SQ_DISPATCHER value
13919  */
13920 
13921 #define SQ_DISPATCHER_GFX_MIN          0x00000010
13922 #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
13923 
13924 /*
13925  * SQ_MAX value
13926  */
13927 
13928 #define SQ_MAX_PGM_SGPRS               0x00000068
13929 #define SQ_MAX_PGM_VGPRS               0x00000100
13930 
13931 /*
13932  * SQ_EXCP_BITS value
13933  */
13934 
13935 #define SQ_EX_MODE_EXCP_VALU_BASE      0x00000000
13936 #define SQ_EX_MODE_EXCP_VALU_SIZE      0x00000007
13937 #define SQ_EX_MODE_EXCP_INVALID        0x00000000
13938 #define SQ_EX_MODE_EXCP_INPUT_DENORM   0x00000001
13939 #define SQ_EX_MODE_EXCP_DIV0           0x00000002
13940 #define SQ_EX_MODE_EXCP_OVERFLOW       0x00000003
13941 #define SQ_EX_MODE_EXCP_UNDERFLOW      0x00000004
13942 #define SQ_EX_MODE_EXCP_INEXACT        0x00000005
13943 #define SQ_EX_MODE_EXCP_INT_DIV0       0x00000006
13944 #define SQ_EX_MODE_EXCP_ADDR_WATCH0    0x00000007
13945 #define SQ_EX_MODE_EXCP_MEM_VIOL       0x00000008
13946 
13947 /*
13948  * SQ_EXCP_HI_BITS value
13949  */
13950 
13951 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
13952 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
13953 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
13954 
13955 /*
13956  * HW_INSERTED_INST_ID value
13957  */
13958 
13959 #define INST_ID_PRIV_START             0x80000000
13960 #define INST_ID_ECC_INTERRUPT_MSG      0xfffffff0
13961 #define INST_ID_TTRACE_NEW_PC_MSG      0xfffffff1
13962 #define INST_ID_HW_TRAP                0xfffffff2
13963 #define INST_ID_KILL_SEQ               0xfffffff3
13964 #define INST_ID_SPI_WREXEC             0xfffffff4
13965 #define INST_ID_HOST_REG_TRAP_MSG      0xfffffffe
13966 
13967 /*
13968  * SIMM16_WAITCNT_PARTITIONS value
13969  */
13970 
13971 #define SIMM16_WAITCNT_VM_CNT_START    0x00000000
13972 #define SIMM16_WAITCNT_VM_CNT_SIZE     0x00000004
13973 #define SIMM16_WAITCNT_EXP_CNT_START   0x00000004
13974 #define SIMM16_WAITCNT_EXP_CNT_SIZE    0x00000003
13975 #define SIMM16_WAITCNT_LGKM_CNT_START  0x00000008
13976 #define SIMM16_WAITCNT_LGKM_CNT_SIZE   0x00000004
13977 #define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e
13978 #define SIMM16_WAITCNT_VM_CNT_HI_SIZE  0x00000002
13979 #define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000
13980 #define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001
13981 #define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001
13982 #define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001
13983 #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002
13984 #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003
13985 #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000008
13986 #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001
13987 #define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000009
13988 #define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003
13989 #define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000c
13990 #define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000004
13991 
13992 /*
13993  * SQ_EDC_FUE_CNTL_BITS value
13994  */
13995 
13996 #define SQ_EDC_FUE_CNTL_SIMD0          0x00000000
13997 #define SQ_EDC_FUE_CNTL_SIMD1          0x00000001
13998 #define SQ_EDC_FUE_CNTL_SIMD2          0x00000002
13999 #define SQ_EDC_FUE_CNTL_SIMD3          0x00000003
14000 #define SQ_EDC_FUE_CNTL_SQ             0x00000004
14001 #define SQ_EDC_FUE_CNTL_LDS            0x00000005
14002 #define SQ_EDC_FUE_CNTL_TD             0x00000006
14003 #define SQ_EDC_FUE_CNTL_TA             0x00000007
14004 #define SQ_EDC_FUE_CNTL_TCP            0x00000008
14005 
14006 /*******************************************************
14007  * COMP Enums
14008  *******************************************************/
14009 
14010 /*
14011  * CSDATA_TYPE enum
14012  */
14013 
14014 typedef enum CSDATA_TYPE {
14015 CSDATA_TYPE_TG                           = 0x00000000,
14016 CSDATA_TYPE_STATE                        = 0x00000001,
14017 CSDATA_TYPE_EVENT                        = 0x00000002,
14018 CSDATA_TYPE_PRIVATE                      = 0x00000003,
14019 } CSDATA_TYPE;
14020 
14021 /*
14022  * CSCNTL_TYPE enum
14023  */
14024 
14025 typedef enum CSCNTL_TYPE {
14026 CSCNTL_TYPE_TG                           = 0x00000000,
14027 CSCNTL_TYPE_STATE                        = 0x00000001,
14028 CSCNTL_TYPE_EVENT                        = 0x00000002,
14029 CSCNTL_TYPE_PRIVATE                      = 0x00000003,
14030 } CSCNTL_TYPE;
14031 
14032 /*
14033  * CSDATA_TYPE_WIDTH value
14034  */
14035 
14036 #define CSDATA_TYPE_WIDTH              0x00000002
14037 
14038 /*
14039  * CSDATA_ADDR_WIDTH value
14040  */
14041 
14042 #define CSDATA_ADDR_WIDTH              0x00000007
14043 
14044 /*
14045  * CSDATA_DATA_WIDTH value
14046  */
14047 
14048 #define CSDATA_DATA_WIDTH              0x00000020
14049 
14050 /*
14051  * CSCNTL_TYPE_WIDTH value
14052  */
14053 
14054 #define CSCNTL_TYPE_WIDTH              0x00000002
14055 
14056 /*
14057  * CSCNTL_ADDR_WIDTH value
14058  */
14059 
14060 #define CSCNTL_ADDR_WIDTH              0x00000007
14061 
14062 /*
14063  * CSCNTL_DATA_WIDTH value
14064  */
14065 
14066 #define CSCNTL_DATA_WIDTH              0x00000020
14067 
14068 /*******************************************************
14069  * GE Enums
14070  *******************************************************/
14071 
14072 /*
14073  * VGT_OUT_PRIM_TYPE enum
14074  */
14075 
14076 typedef enum VGT_OUT_PRIM_TYPE {
14077 VGT_OUT_POINT                            = 0x00000000,
14078 VGT_OUT_LINE                             = 0x00000001,
14079 VGT_OUT_TRI                              = 0x00000002,
14080 VGT_OUT_RECT_V0                          = 0x00000003,
14081 VGT_OUT_RECT_V1                          = 0x00000004,
14082 VGT_OUT_RECT_V2                          = 0x00000005,
14083 VGT_OUT_RECT_V3                          = 0x00000006,
14084 VGT_OUT_2D_RECT                          = 0x00000007,
14085 VGT_TE_QUAD                              = 0x00000008,
14086 VGT_TE_PRIM_INDEX_LINE                   = 0x00000009,
14087 VGT_TE_PRIM_INDEX_TRI                    = 0x0000000a,
14088 VGT_TE_PRIM_INDEX_QUAD                   = 0x0000000b,
14089 VGT_OUT_LINE_ADJ                         = 0x0000000c,
14090 VGT_OUT_TRI_ADJ                          = 0x0000000d,
14091 VGT_OUT_PATCH                            = 0x0000000e,
14092 } VGT_OUT_PRIM_TYPE;
14093 
14094 /*
14095  * VGT_DI_PRIM_TYPE enum
14096  */
14097 
14098 typedef enum VGT_DI_PRIM_TYPE {
14099 DI_PT_NONE                               = 0x00000000,
14100 DI_PT_POINTLIST                          = 0x00000001,
14101 DI_PT_LINELIST                           = 0x00000002,
14102 DI_PT_LINESTRIP                          = 0x00000003,
14103 DI_PT_TRILIST                            = 0x00000004,
14104 DI_PT_TRIFAN                             = 0x00000005,
14105 DI_PT_TRISTRIP                           = 0x00000006,
14106 DI_PT_2D_RECTANGLE                       = 0x00000007,
14107 DI_PT_UNUSED_1                           = 0x00000008,
14108 DI_PT_PATCH                              = 0x00000009,
14109 DI_PT_LINELIST_ADJ                       = 0x0000000a,
14110 DI_PT_LINESTRIP_ADJ                      = 0x0000000b,
14111 DI_PT_TRILIST_ADJ                        = 0x0000000c,
14112 DI_PT_TRISTRIP_ADJ                       = 0x0000000d,
14113 DI_PT_UNUSED_3                           = 0x0000000e,
14114 DI_PT_UNUSED_4                           = 0x0000000f,
14115 DI_PT_TRI_WITH_WFLAGS                    = 0x00000010,
14116 DI_PT_RECTLIST                           = 0x00000011,
14117 DI_PT_LINELOOP                           = 0x00000012,
14118 DI_PT_QUADLIST                           = 0x00000013,
14119 DI_PT_QUADSTRIP                          = 0x00000014,
14120 DI_PT_POLYGON                            = 0x00000015,
14121 } VGT_DI_PRIM_TYPE;
14122 
14123 /*
14124  * VGT_DI_SOURCE_SELECT enum
14125  */
14126 
14127 typedef enum VGT_DI_SOURCE_SELECT {
14128 DI_SRC_SEL_DMA                           = 0x00000000,
14129 DI_SRC_SEL_IMMEDIATE                     = 0x00000001,
14130 DI_SRC_SEL_AUTO_INDEX                    = 0x00000002,
14131 DI_SRC_SEL_RESERVED                      = 0x00000003,
14132 } VGT_DI_SOURCE_SELECT;
14133 
14134 /*
14135  * VGT_DI_MAJOR_MODE_SELECT enum
14136  */
14137 
14138 typedef enum VGT_DI_MAJOR_MODE_SELECT {
14139 DI_MAJOR_MODE_0                          = 0x00000000,
14140 DI_MAJOR_MODE_1                          = 0x00000001,
14141 } VGT_DI_MAJOR_MODE_SELECT;
14142 
14143 /*
14144  * VGT_DI_INDEX_SIZE enum
14145  */
14146 
14147 typedef enum VGT_DI_INDEX_SIZE {
14148 DI_INDEX_SIZE_16_BIT                     = 0x00000000,
14149 DI_INDEX_SIZE_32_BIT                     = 0x00000001,
14150 DI_INDEX_SIZE_8_BIT                      = 0x00000002,
14151 } VGT_DI_INDEX_SIZE;
14152 
14153 /*
14154  * VGT_EVENT_TYPE enum
14155  */
14156 
14157 typedef enum VGT_EVENT_TYPE {
14158 Reserved_0x00                            = 0x00000000,
14159 SAMPLE_STREAMOUTSTATS1                   = 0x00000001,
14160 SAMPLE_STREAMOUTSTATS2                   = 0x00000002,
14161 SAMPLE_STREAMOUTSTATS3                   = 0x00000003,
14162 CACHE_FLUSH_TS                           = 0x00000004,
14163 CONTEXT_DONE                             = 0x00000005,
14164 CACHE_FLUSH                              = 0x00000006,
14165 CS_PARTIAL_FLUSH                         = 0x00000007,
14166 VGT_STREAMOUT_SYNC                       = 0x00000008,
14167 SET_FE_ID                                = 0x00000009,
14168 VGT_STREAMOUT_RESET                      = 0x0000000a,
14169 END_OF_PIPE_INCR_DE                      = 0x0000000b,
14170 END_OF_PIPE_IB_END                       = 0x0000000c,
14171 RST_PIX_CNT                              = 0x0000000d,
14172 BREAK_BATCH                              = 0x0000000e,
14173 VS_PARTIAL_FLUSH                         = 0x0000000f,
14174 PS_PARTIAL_FLUSH                         = 0x00000010,
14175 FLUSH_HS_OUTPUT                          = 0x00000011,
14176 FLUSH_DFSM                               = 0x00000012,
14177 RESET_TO_LOWEST_VGT                      = 0x00000013,
14178 CACHE_FLUSH_AND_INV_TS_EVENT             = 0x00000014,
14179 ZPASS_DONE                               = 0x00000015,
14180 CACHE_FLUSH_AND_INV_EVENT                = 0x00000016,
14181 PERFCOUNTER_START                        = 0x00000017,
14182 PERFCOUNTER_STOP                         = 0x00000018,
14183 PIPELINESTAT_START                       = 0x00000019,
14184 PIPELINESTAT_STOP                        = 0x0000001a,
14185 PERFCOUNTER_SAMPLE                       = 0x0000001b,
14186 FLUSH_ES_OUTPUT                          = 0x0000001c,
14187 BIN_CONF_OVERRIDE_CHECK                  = 0x0000001d,
14188 SAMPLE_PIPELINESTAT                      = 0x0000001e,
14189 SO_VGTSTREAMOUT_FLUSH                    = 0x0000001f,
14190 SAMPLE_STREAMOUTSTATS                    = 0x00000020,
14191 RESET_VTX_CNT                            = 0x00000021,
14192 BLOCK_CONTEXT_DONE                       = 0x00000022,
14193 CS_CONTEXT_DONE                          = 0x00000023,
14194 VGT_FLUSH                                = 0x00000024,
14195 TGID_ROLLOVER                            = 0x00000025,
14196 SQ_NON_EVENT                             = 0x00000026,
14197 SC_SEND_DB_VPZ                           = 0x00000027,
14198 BOTTOM_OF_PIPE_TS                        = 0x00000028,
14199 FLUSH_SX_TS                              = 0x00000029,
14200 DB_CACHE_FLUSH_AND_INV                   = 0x0000002a,
14201 FLUSH_AND_INV_DB_DATA_TS                 = 0x0000002b,
14202 FLUSH_AND_INV_DB_META                    = 0x0000002c,
14203 FLUSH_AND_INV_CB_DATA_TS                 = 0x0000002d,
14204 FLUSH_AND_INV_CB_META                    = 0x0000002e,
14205 CS_DONE                                  = 0x0000002f,
14206 PS_DONE                                  = 0x00000030,
14207 FLUSH_AND_INV_CB_PIXEL_DATA              = 0x00000031,
14208 SX_CB_RAT_ACK_REQUEST                    = 0x00000032,
14209 THREAD_TRACE_START                       = 0x00000033,
14210 THREAD_TRACE_STOP                        = 0x00000034,
14211 THREAD_TRACE_MARKER                      = 0x00000035,
14212 THREAD_TRACE_DRAW                        = 0x00000036,
14213 THREAD_TRACE_FINISH                      = 0x00000037,
14214 PIXEL_PIPE_STAT_CONTROL                  = 0x00000038,
14215 PIXEL_PIPE_STAT_DUMP                     = 0x00000039,
14216 PIXEL_PIPE_STAT_RESET                    = 0x0000003a,
14217 CONTEXT_SUSPEND                          = 0x0000003b,
14218 OFFCHIP_HS_DEALLOC                       = 0x0000003c,
14219 ENABLE_NGG_PIPELINE                      = 0x0000003d,
14220 ENABLE_LEGACY_PIPELINE                   = 0x0000003e,
14221 DRAW_DONE                                = 0x0000003f,
14222 } VGT_EVENT_TYPE;
14223 
14224 /*
14225  * VGT_DMA_SWAP_MODE enum
14226  */
14227 
14228 typedef enum VGT_DMA_SWAP_MODE {
14229 VGT_DMA_SWAP_NONE                        = 0x00000000,
14230 VGT_DMA_SWAP_16_BIT                      = 0x00000001,
14231 VGT_DMA_SWAP_32_BIT                      = 0x00000002,
14232 VGT_DMA_SWAP_WORD                        = 0x00000003,
14233 } VGT_DMA_SWAP_MODE;
14234 
14235 /*
14236  * VGT_INDEX_TYPE_MODE enum
14237  */
14238 
14239 typedef enum VGT_INDEX_TYPE_MODE {
14240 VGT_INDEX_16                             = 0x00000000,
14241 VGT_INDEX_32                             = 0x00000001,
14242 VGT_INDEX_8                              = 0x00000002,
14243 } VGT_INDEX_TYPE_MODE;
14244 
14245 /*
14246  * VGT_DMA_BUF_TYPE enum
14247  */
14248 
14249 typedef enum VGT_DMA_BUF_TYPE {
14250 VGT_DMA_BUF_MEM                          = 0x00000000,
14251 VGT_DMA_BUF_RING                         = 0x00000001,
14252 VGT_DMA_BUF_SETUP                        = 0x00000002,
14253 VGT_DMA_PTR_UPDATE                       = 0x00000003,
14254 } VGT_DMA_BUF_TYPE;
14255 
14256 /*
14257  * VGT_OUTPATH_SELECT enum
14258  */
14259 
14260 typedef enum VGT_OUTPATH_SELECT {
14261 VGT_OUTPATH_VTX_REUSE                    = 0x00000000,
14262 VGT_OUTPATH_GS_BLOCK                     = 0x00000001,
14263 VGT_OUTPATH_HS_BLOCK                     = 0x00000002,
14264 VGT_OUTPATH_PRIM_GEN                     = 0x00000003,
14265 VGT_OUTPATH_TE_PRIM_GEN                  = 0x00000004,
14266 VGT_OUTPATH_TE_GS_BLOCK                  = 0x00000005,
14267 VGT_OUTPATH_TE_OUTPUT                    = 0x00000006,
14268 } VGT_OUTPATH_SELECT;
14269 
14270 /*
14271  * VGT_GRP_PRIM_TYPE enum
14272  */
14273 
14274 typedef enum VGT_GRP_PRIM_TYPE {
14275 VGT_GRP_3D_POINT                         = 0x00000000,
14276 VGT_GRP_3D_LINE                          = 0x00000001,
14277 VGT_GRP_3D_TRI                           = 0x00000002,
14278 VGT_GRP_3D_RECT                          = 0x00000003,
14279 VGT_GRP_3D_QUAD                          = 0x00000004,
14280 VGT_GRP_2D_COPY_RECT_V0                  = 0x00000005,
14281 VGT_GRP_2D_COPY_RECT_V1                  = 0x00000006,
14282 VGT_GRP_2D_COPY_RECT_V2                  = 0x00000007,
14283 VGT_GRP_2D_COPY_RECT_V3                  = 0x00000008,
14284 VGT_GRP_2D_FILL_RECT                     = 0x00000009,
14285 VGT_GRP_2D_LINE                          = 0x0000000a,
14286 VGT_GRP_2D_TRI                           = 0x0000000b,
14287 VGT_GRP_PRIM_INDEX_LINE                  = 0x0000000c,
14288 VGT_GRP_PRIM_INDEX_TRI                   = 0x0000000d,
14289 VGT_GRP_PRIM_INDEX_QUAD                  = 0x0000000e,
14290 VGT_GRP_3D_LINE_ADJ                      = 0x0000000f,
14291 VGT_GRP_3D_TRI_ADJ                       = 0x00000010,
14292 VGT_GRP_3D_PATCH                         = 0x00000011,
14293 VGT_GRP_2D_RECT                          = 0x00000012,
14294 } VGT_GRP_PRIM_TYPE;
14295 
14296 /*
14297  * VGT_GRP_PRIM_ORDER enum
14298  */
14299 
14300 typedef enum VGT_GRP_PRIM_ORDER {
14301 VGT_GRP_LIST                             = 0x00000000,
14302 VGT_GRP_STRIP                            = 0x00000001,
14303 VGT_GRP_FAN                              = 0x00000002,
14304 VGT_GRP_LOOP                             = 0x00000003,
14305 VGT_GRP_POLYGON                          = 0x00000004,
14306 } VGT_GRP_PRIM_ORDER;
14307 
14308 /*
14309  * VGT_GROUP_CONV_SEL enum
14310  */
14311 
14312 typedef enum VGT_GROUP_CONV_SEL {
14313 VGT_GRP_INDEX_16                         = 0x00000000,
14314 VGT_GRP_INDEX_32                         = 0x00000001,
14315 VGT_GRP_UINT_16                          = 0x00000002,
14316 VGT_GRP_UINT_32                          = 0x00000003,
14317 VGT_GRP_SINT_16                          = 0x00000004,
14318 VGT_GRP_SINT_32                          = 0x00000005,
14319 VGT_GRP_FLOAT_32                         = 0x00000006,
14320 VGT_GRP_AUTO_PRIM                        = 0x00000007,
14321 VGT_GRP_FIX_1_23_TO_FLOAT                = 0x00000008,
14322 } VGT_GROUP_CONV_SEL;
14323 
14324 /*
14325  * VGT_GS_MODE_TYPE enum
14326  */
14327 
14328 typedef enum VGT_GS_MODE_TYPE {
14329 GS_OFF                                   = 0x00000000,
14330 GS_SCENARIO_A                            = 0x00000001,
14331 GS_SCENARIO_B                            = 0x00000002,
14332 GS_SCENARIO_G                            = 0x00000003,
14333 GS_SCENARIO_C                            = 0x00000004,
14334 SPRITE_EN                                = 0x00000005,
14335 } VGT_GS_MODE_TYPE;
14336 
14337 /*
14338  * VGT_GS_CUT_MODE enum
14339  */
14340 
14341 typedef enum VGT_GS_CUT_MODE {
14342 GS_CUT_1024                              = 0x00000000,
14343 GS_CUT_512                               = 0x00000001,
14344 GS_CUT_256                               = 0x00000002,
14345 GS_CUT_128                               = 0x00000003,
14346 } VGT_GS_CUT_MODE;
14347 
14348 /*
14349  * VGT_GS_OUTPRIM_TYPE enum
14350  */
14351 
14352 typedef enum VGT_GS_OUTPRIM_TYPE {
14353 POINTLIST                                = 0x00000000,
14354 LINESTRIP                                = 0x00000001,
14355 TRISTRIP                                 = 0x00000002,
14356 RECTLIST                                 = 0x00000003,
14357 } VGT_GS_OUTPRIM_TYPE;
14358 
14359 /*
14360  * VGT_CACHE_INVALID_MODE enum
14361  */
14362 
14363 typedef enum VGT_CACHE_INVALID_MODE {
14364 VC_ONLY                                  = 0x00000000,
14365 TC_ONLY                                  = 0x00000001,
14366 VC_AND_TC                                = 0x00000002,
14367 } VGT_CACHE_INVALID_MODE;
14368 
14369 /*
14370  * VGT_TESS_TYPE enum
14371  */
14372 
14373 typedef enum VGT_TESS_TYPE {
14374 TESS_ISOLINE                             = 0x00000000,
14375 TESS_TRIANGLE                            = 0x00000001,
14376 TESS_QUAD                                = 0x00000002,
14377 } VGT_TESS_TYPE;
14378 
14379 /*
14380  * VGT_TESS_PARTITION enum
14381  */
14382 
14383 typedef enum VGT_TESS_PARTITION {
14384 PART_INTEGER                             = 0x00000000,
14385 PART_POW2                                = 0x00000001,
14386 PART_FRAC_ODD                            = 0x00000002,
14387 PART_FRAC_EVEN                           = 0x00000003,
14388 } VGT_TESS_PARTITION;
14389 
14390 /*
14391  * VGT_TESS_TOPOLOGY enum
14392  */
14393 
14394 typedef enum VGT_TESS_TOPOLOGY {
14395 OUTPUT_POINT                             = 0x00000000,
14396 OUTPUT_LINE                              = 0x00000001,
14397 OUTPUT_TRIANGLE_CW                       = 0x00000002,
14398 OUTPUT_TRIANGLE_CCW                      = 0x00000003,
14399 } VGT_TESS_TOPOLOGY;
14400 
14401 /*
14402  * VGT_RDREQ_POLICY enum
14403  */
14404 
14405 typedef enum VGT_RDREQ_POLICY {
14406 VGT_POLICY_LRU                           = 0x00000000,
14407 VGT_POLICY_STREAM                        = 0x00000001,
14408 VGT_POLICY_BYPASS                        = 0x00000002,
14409 } VGT_RDREQ_POLICY;
14410 
14411 /*
14412  * VGT_DIST_MODE enum
14413  */
14414 
14415 typedef enum VGT_DIST_MODE {
14416 NO_DIST                                  = 0x00000000,
14417 PATCHES                                  = 0x00000001,
14418 DONUTS                                   = 0x00000002,
14419 TRAPEZOIDS                               = 0x00000003,
14420 } VGT_DIST_MODE;
14421 
14422 /*
14423  * VGT_DETECT_ONE enum
14424  */
14425 
14426 typedef enum VGT_DETECT_ONE {
14427 PRE_CLAMP_TF1                            = 0x00000000,
14428 POST_CLAMP_TF1                           = 0x00000001,
14429 DISABLE_TF1                              = 0x00000002,
14430 } VGT_DETECT_ONE;
14431 
14432 /*
14433  * VGT_DETECT_ZERO enum
14434  */
14435 
14436 typedef enum VGT_DETECT_ZERO {
14437 PRE_CLAMP_TF0                            = 0x00000000,
14438 POST_CLAMP_TF0                           = 0x00000001,
14439 DISABLE_TF0                              = 0x00000002,
14440 } VGT_DETECT_ZERO;
14441 
14442 /*
14443  * VGT_STAGES_LS_EN enum
14444  */
14445 
14446 typedef enum VGT_STAGES_LS_EN {
14447 LS_STAGE_OFF                             = 0x00000000,
14448 LS_STAGE_ON                              = 0x00000001,
14449 CS_STAGE_ON                              = 0x00000002,
14450 RESERVED_LS                              = 0x00000003,
14451 } VGT_STAGES_LS_EN;
14452 
14453 /*
14454  * VGT_STAGES_HS_EN enum
14455  */
14456 
14457 typedef enum VGT_STAGES_HS_EN {
14458 HS_STAGE_OFF                             = 0x00000000,
14459 HS_STAGE_ON                              = 0x00000001,
14460 } VGT_STAGES_HS_EN;
14461 
14462 /*
14463  * VGT_STAGES_ES_EN enum
14464  */
14465 
14466 typedef enum VGT_STAGES_ES_EN {
14467 ES_STAGE_OFF                             = 0x00000000,
14468 ES_STAGE_DS                              = 0x00000001,
14469 ES_STAGE_REAL                            = 0x00000002,
14470 RESERVED_ES                              = 0x00000003,
14471 } VGT_STAGES_ES_EN;
14472 
14473 /*
14474  * VGT_STAGES_GS_EN enum
14475  */
14476 
14477 typedef enum VGT_STAGES_GS_EN {
14478 GS_STAGE_OFF                             = 0x00000000,
14479 GS_STAGE_ON                              = 0x00000001,
14480 } VGT_STAGES_GS_EN;
14481 
14482 /*
14483  * VGT_STAGES_VS_EN enum
14484  */
14485 
14486 typedef enum VGT_STAGES_VS_EN {
14487 VS_STAGE_REAL                            = 0x00000000,
14488 VS_STAGE_DS                              = 0x00000001,
14489 VS_STAGE_COPY_SHADER                     = 0x00000002,
14490 RESERVED_VS                              = 0x00000003,
14491 } VGT_STAGES_VS_EN;
14492 
14493 /*
14494  * GE_PERFCOUNT_SELECT enum
14495  */
14496 
14497 typedef enum GE_PERFCOUNT_SELECT {
14498 ge_assembler_busy                        = 0x00000000,
14499 ge_assembler_stalled                     = 0x00000001,
14500 ge_cm_reading_stalled                    = 0x00000002,
14501 ge_cm_stalled_by_gog                     = 0x00000003,
14502 ge_cm_stalled_by_gsfetch_done            = 0x00000004,
14503 ge_dma_busy                              = 0x00000005,
14504 ge_dma_lat_bin_0                         = 0x00000006,
14505 ge_dma_lat_bin_1                         = 0x00000007,
14506 ge_dma_lat_bin_2                         = 0x00000008,
14507 ge_dma_lat_bin_3                         = 0x00000009,
14508 ge_dma_lat_bin_4                         = 0x0000000a,
14509 ge_dma_lat_bin_5                         = 0x0000000b,
14510 ge_dma_lat_bin_6                         = 0x0000000c,
14511 ge_dma_lat_bin_7                         = 0x0000000d,
14512 ge_dma_return                            = 0x0000000e,
14513 ge_dma_utcl1_consecutive_retry_event     = 0x0000000f,
14514 ge_dma_utcl1_request_event               = 0x00000010,
14515 ge_dma_utcl1_retry_event                 = 0x00000011,
14516 ge_dma_utcl1_stall_event                 = 0x00000012,
14517 ge_dma_utcl1_stall_utcl2_event           = 0x00000013,
14518 ge_dma_utcl1_translation_hit_event       = 0x00000014,
14519 ge_dma_utcl1_translation_miss_event      = 0x00000015,
14520 ge_dma_utcl2_stall_on_trans              = 0x00000016,
14521 ge_dma_utcl2_trans_ack                   = 0x00000017,
14522 ge_dma_utcl2_trans_xnack                 = 0x00000018,
14523 ge_ds_cache_hits                         = 0x00000019,
14524 ge_ds_prims                              = 0x0000001a,
14525 ge_es_done                               = 0x0000001b,
14526 ge_es_done_latency                       = 0x0000001c,
14527 ge_es_flush                              = 0x0000001d,
14528 ge_es_ring_high_water_mark               = 0x0000001e,
14529 ge_es_thread_groups                      = 0x0000001f,
14530 ge_esthread_stalled_es_rb_full           = 0x00000020,
14531 ge_esthread_stalled_spi_bp               = 0x00000021,
14532 ge_esvert_stalled_es_tbl                 = 0x00000022,
14533 ge_esvert_stalled_gs_event               = 0x00000023,
14534 ge_esvert_stalled_gs_tbl                 = 0x00000024,
14535 ge_esvert_stalled_gsprim                 = 0x00000025,
14536 ge_gea_dma_starved                       = 0x00000026,
14537 ge_gog_busy                              = 0x00000027,
14538 ge_gog_out_indx_stalled                  = 0x00000028,
14539 ge_gog_out_prim_stalled                  = 0x00000029,
14540 ge_gog_vs_tbl_stalled                    = 0x0000002a,
14541 ge_gs_cache_hits                         = 0x0000002b,
14542 ge_gs_counters_avail_stalled             = 0x0000002c,
14543 ge_gs_done                               = 0x0000002d,
14544 ge_gs_done_latency                       = 0x0000002e,
14545 ge_gs_event_stall                        = 0x0000002f,
14546 ge_gs_issue_rtr_stalled                  = 0x00000030,
14547 ge_gs_rb_space_avail_stalled             = 0x00000031,
14548 ge_gs_ring_high_water_mark               = 0x00000032,
14549 ge_gsprim_stalled_es_tbl                 = 0x00000033,
14550 ge_gsprim_stalled_esvert                 = 0x00000034,
14551 ge_gsprim_stalled_gs_event               = 0x00000035,
14552 ge_gsprim_stalled_gs_tbl                 = 0x00000036,
14553 ge_gsthread_stalled                      = 0x00000037,
14554 ge_hs_done                               = 0x00000038,
14555 ge_hs_done_latency                       = 0x00000039,
14556 ge_hs_done_se0                           = 0x0000003a,
14557 ge_hs_done_se1                           = 0x0000003b,
14558 ge_hs_done_se2_reserved                  = 0x0000003c,
14559 ge_hs_done_se3_reserved                  = 0x0000003d,
14560 ge_hs_tfm_stall                          = 0x0000003e,
14561 ge_hs_tgs_active_high_water_mark         = 0x0000003f,
14562 ge_hs_thread_groups                      = 0x00000040,
14563 ge_inside_tf_bin_0                       = 0x00000041,
14564 ge_inside_tf_bin_1                       = 0x00000042,
14565 ge_inside_tf_bin_2                       = 0x00000043,
14566 ge_inside_tf_bin_3                       = 0x00000044,
14567 ge_inside_tf_bin_4                       = 0x00000045,
14568 ge_inside_tf_bin_5                       = 0x00000046,
14569 ge_inside_tf_bin_6                       = 0x00000047,
14570 ge_inside_tf_bin_7                       = 0x00000048,
14571 ge_inside_tf_bin_8                       = 0x00000049,
14572 ge_ls_done                               = 0x0000004a,
14573 ge_ls_done_latency                       = 0x0000004b,
14574 ge_null_patch                            = 0x0000004c,
14575 ge_pa_clipp_eop                          = 0x0000004d,
14576 ge_pa_clipp_is_event                     = 0x0000004e,
14577 ge_pa_clipp_new_vtx_vect                 = 0x0000004f,
14578 ge_pa_clipp_null_prim                    = 0x00000050,
14579 ge_pa_clipp_send                         = 0x00000051,
14580 ge_pa_clipp_send_not_event               = 0x00000052,
14581 ge_pa_clipp_stalled                      = 0x00000053,
14582 ge_pa_clipp_starved_busy                 = 0x00000054,
14583 ge_pa_clipp_starved_idle                 = 0x00000055,
14584 ge_pa_clipp_valid_prim                   = 0x00000056,
14585 ge_pa_clips_send                         = 0x00000057,
14586 ge_pa_clips_stalled                      = 0x00000058,
14587 ge_pa_clipv_send                         = 0x00000059,
14588 ge_pa_clipv_stalled                      = 0x0000005a,
14589 ge_rbiu_di_fifo_stalled                  = 0x0000005b,
14590 ge_rbiu_di_fifo_starved                  = 0x0000005c,
14591 ge_rbiu_dr_fifo_stalled                  = 0x0000005d,
14592 ge_rbiu_dr_fifo_starved                  = 0x0000005e,
14593 ge_reused_es_indices                     = 0x0000005f,
14594 ge_reused_vs_indices                     = 0x00000060,
14595 ge_sclk_core_vld                         = 0x00000061,
14596 ge_sclk_gs_vld                           = 0x00000062,
14597 ge_sclk_input_vld                        = 0x00000063,
14598 ge_sclk_leg_gs_arb_vld                   = 0x00000064,
14599 ge_sclk_ngg_vld                          = 0x00000065,
14600 ge_sclk_reg_vld                          = 0x00000066,
14601 ge_sclk_te11_vld                         = 0x00000067,
14602 ge_sclk_vr_vld                           = 0x00000068,
14603 ge_sclk_wd_te11_vld                      = 0x00000069,
14604 ge_spi_esvert_eov                        = 0x0000006a,
14605 ge_spi_esvert_stalled                    = 0x0000006b,
14606 ge_spi_esvert_starved_busy               = 0x0000006c,
14607 ge_spi_esvert_valid                      = 0x0000006d,
14608 ge_spi_eswave_is_event                   = 0x0000006e,
14609 ge_spi_eswave_send                       = 0x0000006f,
14610 ge_spi_gsprim_cont                       = 0x00000070,
14611 ge_spi_gsprim_eov                        = 0x00000071,
14612 ge_spi_gsprim_stalled                    = 0x00000072,
14613 ge_spi_gsprim_starved_busy               = 0x00000073,
14614 ge_spi_gsprim_starved_idle               = 0x00000074,
14615 ge_spi_gsprim_valid                      = 0x00000075,
14616 ge_spi_gssubgrp_is_event                 = 0x00000076,
14617 ge_spi_gssubgrp_send                     = 0x00000077,
14618 ge_spi_gswave_is_event                   = 0x00000078,
14619 ge_spi_gswave_send                       = 0x00000079,
14620 ge_spi_hsvert_eov                        = 0x0000007a,
14621 ge_spi_hsvert_stalled                    = 0x0000007b,
14622 ge_spi_hsvert_starved_busy               = 0x0000007c,
14623 ge_spi_hsvert_valid                      = 0x0000007d,
14624 ge_spi_hswave_is_event                   = 0x0000007e,
14625 ge_spi_hswave_send                       = 0x0000007f,
14626 ge_spi_lsvert_eov                        = 0x00000080,
14627 ge_spi_lsvert_stalled                    = 0x00000081,
14628 ge_spi_lsvert_starved_busy               = 0x00000082,
14629 ge_spi_lsvert_starved_idle               = 0x00000083,
14630 ge_spi_lsvert_valid                      = 0x00000084,
14631 ge_spi_lswave_is_event                   = 0x00000085,
14632 ge_spi_lswave_send                       = 0x00000086,
14633 ge_spi_vsvert_eov                        = 0x00000087,
14634 ge_spi_vsvert_send                       = 0x00000088,
14635 ge_spi_vsvert_stalled                    = 0x00000089,
14636 ge_spi_vsvert_starved_busy               = 0x0000008a,
14637 ge_spi_vsvert_starved_idle               = 0x0000008b,
14638 ge_spi_vswave_is_event                   = 0x0000008c,
14639 ge_spi_vswave_send                       = 0x0000008d,
14640 ge_starved_on_hs_done                    = 0x0000008e,
14641 ge_stat_busy                             = 0x0000008f,
14642 ge_stat_combined_busy                    = 0x00000090,
14643 ge_stat_no_dma_busy                      = 0x00000091,
14644 ge_strmout_stalled                       = 0x00000092,
14645 ge_te11_busy                             = 0x00000093,
14646 ge_te11_starved                          = 0x00000094,
14647 ge_tfreq_lat_bin_0                       = 0x00000095,
14648 ge_tfreq_lat_bin_1                       = 0x00000096,
14649 ge_tfreq_lat_bin_2                       = 0x00000097,
14650 ge_tfreq_lat_bin_3                       = 0x00000098,
14651 ge_tfreq_lat_bin_4                       = 0x00000099,
14652 ge_tfreq_lat_bin_5                       = 0x0000009a,
14653 ge_tfreq_lat_bin_6                       = 0x0000009b,
14654 ge_tfreq_lat_bin_7                       = 0x0000009c,
14655 ge_tfreq_utcl1_consecutive_retry_event   = 0x0000009d,
14656 ge_tfreq_utcl1_request_event             = 0x0000009e,
14657 ge_tfreq_utcl1_retry_event               = 0x0000009f,
14658 ge_tfreq_utcl1_stall_event               = 0x000000a0,
14659 ge_tfreq_utcl1_stall_utcl2_event         = 0x000000a1,
14660 ge_tfreq_utcl1_translation_hit_event     = 0x000000a2,
14661 ge_tfreq_utcl1_translation_miss_event    = 0x000000a3,
14662 ge_tfreq_utcl2_stall_on_trans            = 0x000000a4,
14663 ge_tfreq_utcl2_trans_ack                 = 0x000000a5,
14664 ge_tfreq_utcl2_trans_xnack               = 0x000000a6,
14665 ge_vs_cache_hits                         = 0x000000a7,
14666 ge_vs_done                               = 0x000000a8,
14667 ge_vs_pc_stall                           = 0x000000a9,
14668 ge_vs_table_high_water_mark              = 0x000000aa,
14669 ge_vs_thread_groups                      = 0x000000ab,
14670 ge_vsvert_api_send                       = 0x000000ac,
14671 ge_vsvert_ds_send                        = 0x000000ad,
14672 ge_wait_for_es_done_stalled              = 0x000000ae,
14673 ge_waveid_stalled                        = 0x000000af,
14674 } GE_PERFCOUNT_SELECT;
14675 
14676 /*
14677  * WD_IA_DRAW_TYPE enum
14678  */
14679 
14680 typedef enum WD_IA_DRAW_TYPE {
14681 WD_IA_DRAW_TYPE_DI_MM0                   = 0x00000000,
14682 WD_IA_DRAW_TYPE_REG_XFER                 = 0x00000001,
14683 WD_IA_DRAW_TYPE_EVENT_INIT               = 0x00000002,
14684 WD_IA_DRAW_TYPE_EVENT_ADDR               = 0x00000003,
14685 WD_IA_DRAW_TYPE_MIN_INDX                 = 0x00000004,
14686 WD_IA_DRAW_TYPE_MAX_INDX                 = 0x00000005,
14687 WD_IA_DRAW_TYPE_INDX_OFF                 = 0x00000006,
14688 WD_IA_DRAW_TYPE_IMM_DATA                 = 0x00000007,
14689 } WD_IA_DRAW_TYPE;
14690 
14691 /*
14692  * WD_IA_DRAW_REG_XFER enum
14693  */
14694 
14695 typedef enum WD_IA_DRAW_REG_XFER {
14696 WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM   = 0x00000000,
14697 WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
14698 WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000002,
14699 WD_IA_DRAW_REG_XFER_GE_CNTL              = 0x00000003,
14700 } WD_IA_DRAW_REG_XFER;
14701 
14702 /*
14703  * WD_IA_DRAW_SOURCE enum
14704  */
14705 
14706 typedef enum WD_IA_DRAW_SOURCE {
14707 WD_IA_DRAW_SOURCE_DMA                    = 0x00000000,
14708 WD_IA_DRAW_SOURCE_IMMD                   = 0x00000001,
14709 WD_IA_DRAW_SOURCE_AUTO                   = 0x00000002,
14710 WD_IA_DRAW_SOURCE_OPAQ                   = 0x00000003,
14711 } WD_IA_DRAW_SOURCE;
14712 
14713 /*
14714  * GS_THREADID_SIZE value
14715  */
14716 
14717 #define GSTHREADID_SIZE                0x00000002
14718 
14719 /*******************************************************
14720  * GB Enums
14721  *******************************************************/
14722 
14723 /*
14724  * GB_EDC_DED_MODE enum
14725  */
14726 
14727 typedef enum GB_EDC_DED_MODE {
14728 GB_EDC_DED_MODE_LOG                      = 0x00000000,
14729 GB_EDC_DED_MODE_HALT                     = 0x00000001,
14730 GB_EDC_DED_MODE_INT_HALT                 = 0x00000002,
14731 } GB_EDC_DED_MODE;
14732 
14733 /*******************************************************
14734  * GLX Enums
14735  *******************************************************/
14736 
14737 /*
14738  * CHA_PERF_SEL enum
14739  */
14740 
14741 typedef enum CHA_PERF_SEL {
14742 CHA_PERF_SEL_BUSY                        = 0x00000000,
14743 CHA_PERF_SEL_STALL_CHC0                  = 0x00000001,
14744 CHA_PERF_SEL_STALL_CHC1                  = 0x00000002,
14745 CHA_PERF_SEL_STALL_CHC2                  = 0x00000003,
14746 CHA_PERF_SEL_STALL_CHC3                  = 0x00000004,
14747 CHA_PERF_SEL_STALL_CHC4                  = 0x00000005,
14748 CHA_PERF_SEL_REQUEST_CHC0                = 0x00000006,
14749 CHA_PERF_SEL_REQUEST_CHC1                = 0x00000007,
14750 CHA_PERF_SEL_REQUEST_CHC2                = 0x00000008,
14751 CHA_PERF_SEL_REQUEST_CHC3                = 0x00000009,
14752 CHA_PERF_SEL_REQUEST_CHC4                = 0x0000000a,
14753 CHA_PERF_SEL_REQUEST_CHC5                = 0x0000000b,
14754 CHA_PERF_SEL_MEM_32B_WDS_CHC0            = 0x0000000c,
14755 CHA_PERF_SEL_MEM_32B_WDS_CHC1            = 0x0000000d,
14756 CHA_PERF_SEL_MEM_32B_WDS_CHC2            = 0x0000000e,
14757 CHA_PERF_SEL_MEM_32B_WDS_CHC3            = 0x0000000f,
14758 CHA_PERF_SEL_MEM_32B_WDS_CHC4            = 0x00000010,
14759 CHA_PERF_SEL_IO_32B_WDS_CHC0             = 0x00000011,
14760 CHA_PERF_SEL_IO_32B_WDS_CHC1             = 0x00000012,
14761 CHA_PERF_SEL_IO_32B_WDS_CHC2             = 0x00000013,
14762 CHA_PERF_SEL_IO_32B_WDS_CHC3             = 0x00000014,
14763 CHA_PERF_SEL_IO_32B_WDS_CHC4             = 0x00000015,
14764 CHA_PERF_SEL_MEM_BURST_COUNT_CHC0        = 0x00000016,
14765 CHA_PERF_SEL_MEM_BURST_COUNT_CHC1        = 0x00000017,
14766 CHA_PERF_SEL_MEM_BURST_COUNT_CHC2        = 0x00000018,
14767 CHA_PERF_SEL_MEM_BURST_COUNT_CHC3        = 0x00000019,
14768 CHA_PERF_SEL_MEM_BURST_COUNT_CHC4        = 0x0000001a,
14769 CHA_PERF_SEL_IO_BURST_COUNT_CHC0         = 0x0000001b,
14770 CHA_PERF_SEL_IO_BURST_COUNT_CHC1         = 0x0000001c,
14771 CHA_PERF_SEL_IO_BURST_COUNT_CHC2         = 0x0000001d,
14772 CHA_PERF_SEL_IO_BURST_COUNT_CHC3         = 0x0000001e,
14773 CHA_PERF_SEL_IO_BURST_COUNT_CHC4         = 0x0000001f,
14774 CHA_PERF_SEL_ARB_REQUESTS                = 0x00000020,
14775 CHA_PERF_SEL_REQ_INFLIGHT_LEVEL          = 0x00000021,
14776 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0     = 0x00000022,
14777 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1     = 0x00000023,
14778 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2     = 0x00000024,
14779 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3     = 0x00000025,
14780 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4     = 0x00000026,
14781 CHA_PERF_SEL_CYCLE                       = 0x00000027,
14782 } CHA_PERF_SEL;
14783 
14784 /*
14785  * CHC_PERF_SEL enum
14786  */
14787 
14788 typedef enum CHC_PERF_SEL {
14789 CHC_PERF_SEL_GATE_EN1                    = 0x00000000,
14790 CHC_PERF_SEL_GATE_EN2                    = 0x00000001,
14791 CHC_PERF_SEL_CORE_REG_SCLK_VLD           = 0x00000002,
14792 CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES   = 0x00000003,
14793 CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES   = 0x00000004,
14794 CHC_PERF_SEL_CYCLE                       = 0x00000005,
14795 CHC_PERF_SEL_REQ                         = 0x00000006,
14796 } CHC_PERF_SEL;
14797 
14798 /*
14799  * CHCG_PERF_SEL enum
14800  */
14801 
14802 typedef enum CHCG_PERF_SEL {
14803 CHCG_PERF_SEL_GATE_EN1                   = 0x00000000,
14804 CHCG_PERF_SEL_GATE_EN2                   = 0x00000001,
14805 CHCG_PERF_SEL_CORE_REG_SCLK_VLD          = 0x00000002,
14806 CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES  = 0x00000003,
14807 CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES  = 0x00000004,
14808 CHCG_PERF_SEL_CYCLE                      = 0x00000005,
14809 CHCG_PERF_SEL_REQ                        = 0x00000006,
14810 } CHCG_PERF_SEL;
14811 
14812 /*
14813  * GL1A_PERF_SEL enum
14814  */
14815 
14816 typedef enum GL1A_PERF_SEL {
14817 GL1A_PERF_SEL_BUSY                       = 0x00000000,
14818 GL1A_PERF_SEL_STALL_GL1C0                = 0x00000001,
14819 GL1A_PERF_SEL_STALL_GL1C1                = 0x00000002,
14820 GL1A_PERF_SEL_STALL_GL1C2                = 0x00000003,
14821 GL1A_PERF_SEL_STALL_GL1C3                = 0x00000004,
14822 GL1A_PERF_SEL_STALL_GL1C4                = 0x00000005,
14823 GL1A_PERF_SEL_REQUEST_GL1C0              = 0x00000006,
14824 GL1A_PERF_SEL_REQUEST_GL1C1              = 0x00000007,
14825 GL1A_PERF_SEL_REQUEST_GL1C2              = 0x00000008,
14826 GL1A_PERF_SEL_REQUEST_GL1C3              = 0x00000009,
14827 GL1A_PERF_SEL_REQUEST_GL1C4              = 0x0000000a,
14828 GL1A_PERF_SEL_MEM_32B_WDS_GL1C0          = 0x0000000b,
14829 GL1A_PERF_SEL_MEM_32B_WDS_GL1C1          = 0x0000000c,
14830 GL1A_PERF_SEL_MEM_32B_WDS_GL1C2          = 0x0000000d,
14831 GL1A_PERF_SEL_MEM_32B_WDS_GL1C3          = 0x0000000e,
14832 GL1A_PERF_SEL_MEM_32B_WDS_GL1C4          = 0x0000000f,
14833 GL1A_PERF_SEL_IO_32B_WDS_GL1C0           = 0x00000010,
14834 GL1A_PERF_SEL_IO_32B_WDS_GL1C1           = 0x00000011,
14835 GL1A_PERF_SEL_IO_32B_WDS_GL1C2           = 0x00000012,
14836 GL1A_PERF_SEL_IO_32B_WDS_GL1C3           = 0x00000013,
14837 GL1A_PERF_SEL_IO_32B_WDS_GL1C4           = 0x00000014,
14838 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0      = 0x00000015,
14839 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1      = 0x00000016,
14840 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2      = 0x00000017,
14841 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3      = 0x00000018,
14842 GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4      = 0x00000019,
14843 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0       = 0x0000001a,
14844 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1       = 0x0000001b,
14845 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2       = 0x0000001c,
14846 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3       = 0x0000001d,
14847 GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4       = 0x0000001e,
14848 GL1A_PERF_SEL_ARB_REQUESTS               = 0x0000001f,
14849 GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL         = 0x00000020,
14850 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0   = 0x00000021,
14851 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1   = 0x00000022,
14852 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2   = 0x00000023,
14853 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3   = 0x00000024,
14854 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4   = 0x00000025,
14855 GL1A_PERF_SEL_CYCLE                      = 0x00000026,
14856 } GL1A_PERF_SEL;
14857 
14858 /*
14859  * GL1C_PERF_SEL enum
14860  */
14861 
14862 typedef enum GL1C_PERF_SEL {
14863 GL1C_PERF_SEL_GATE_EN1                   = 0x00000000,
14864 GL1C_PERF_SEL_GATE_EN2                   = 0x00000001,
14865 GL1C_PERF_SEL_CORE_REG_SCLK_VLD          = 0x00000002,
14866 GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES  = 0x00000003,
14867 GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES  = 0x00000004,
14868 GL1C_PERF_SEL_CYCLE                      = 0x00000005,
14869 GL1C_PERF_SEL_REQ                        = 0x00000006,
14870 } GL1C_PERF_SEL;
14871 
14872 /*
14873  * GL1CG_PERF_SEL enum
14874  */
14875 
14876 typedef enum GL1CG_PERF_SEL {
14877 GL1CG_PERF_SEL_GATE_EN1                  = 0x00000000,
14878 GL1CG_PERF_SEL_GATE_EN2                  = 0x00000001,
14879 GL1CG_PERF_SEL_CORE_REG_SCLK_VLD         = 0x00000002,
14880 GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES  = 0x00000003,
14881 GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES  = 0x00000004,
14882 GL1CG_PERF_SEL_CYCLE                     = 0x00000005,
14883 GL1CG_PERF_SEL_REQ                       = 0x00000006,
14884 } GL1CG_PERF_SEL;
14885 
14886 /*******************************************************
14887  * TP Enums
14888  *******************************************************/
14889 
14890 /*
14891  * TA_TC_REQ_MODES enum
14892  */
14893 
14894 typedef enum TA_TC_REQ_MODES {
14895 TA_TC_REQ_MODE_BORDER                    = 0x00000000,
14896 TA_TC_REQ_MODE_TEX2                      = 0x00000001,
14897 TA_TC_REQ_MODE_TEX1                      = 0x00000002,
14898 TA_TC_REQ_MODE_TEX0                      = 0x00000003,
14899 TA_TC_REQ_MODE_NORMAL                    = 0x00000004,
14900 TA_TC_REQ_MODE_DWORD                     = 0x00000005,
14901 TA_TC_REQ_MODE_BYTE                      = 0x00000006,
14902 TA_TC_REQ_MODE_BYTE_NV                   = 0x00000007,
14903 } TA_TC_REQ_MODES;
14904 
14905 /*
14906  * TA_TC_ADDR_MODES enum
14907  */
14908 
14909 typedef enum TA_TC_ADDR_MODES {
14910 TA_TC_ADDR_MODE_DEFAULT                  = 0x00000000,
14911 TA_TC_ADDR_MODE_COMP0                    = 0x00000001,
14912 TA_TC_ADDR_MODE_COMP1                    = 0x00000002,
14913 TA_TC_ADDR_MODE_COMP2                    = 0x00000003,
14914 TA_TC_ADDR_MODE_COMP3                    = 0x00000004,
14915 TA_TC_ADDR_MODE_UNALIGNED                = 0x00000005,
14916 TA_TC_ADDR_MODE_BORDER_COLOR             = 0x00000006,
14917 } TA_TC_ADDR_MODES;
14918 
14919 /*
14920  * TA_PERFCOUNT_SEL enum
14921  */
14922 
14923 typedef enum TA_PERFCOUNT_SEL {
14924 TA_PERF_SEL_NULL                         = 0x00000000,
14925 TA_PERF_SEL_sh_fifo_busy                 = 0x00000001,
14926 TA_PERF_SEL_sh_fifo_cmd_busy             = 0x00000002,
14927 TA_PERF_SEL_sh_fifo_addr_busy            = 0x00000003,
14928 TA_PERF_SEL_sh_fifo_data_busy            = 0x00000004,
14929 TA_PERF_SEL_sh_fifo_data_sfifo_busy      = 0x00000005,
14930 TA_PERF_SEL_sh_fifo_data_tfifo_busy      = 0x00000006,
14931 TA_PERF_SEL_gradient_busy                = 0x00000007,
14932 TA_PERF_SEL_gradient_fifo_busy           = 0x00000008,
14933 TA_PERF_SEL_lod_busy                     = 0x00000009,
14934 TA_PERF_SEL_lod_fifo_busy                = 0x0000000a,
14935 TA_PERF_SEL_addresser_busy               = 0x0000000b,
14936 TA_PERF_SEL_addresser_fifo_busy          = 0x0000000c,
14937 TA_PERF_SEL_aligner_busy                 = 0x0000000d,
14938 TA_PERF_SEL_write_path_busy              = 0x0000000e,
14939 TA_PERF_SEL_ta_busy                      = 0x0000000f,
14940 TA_PERF_SEL_sq_ta_cmd_cycles             = 0x00000010,
14941 TA_PERF_SEL_sp_ta_addr_cycles            = 0x00000011,
14942 TA_PERF_SEL_sp_ta_data_cycles            = 0x00000012,
14943 TA_PERF_SEL_ta_fa_data_state_cycles      = 0x00000013,
14944 TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles  = 0x00000014,
14945 TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles  = 0x00000015,
14946 TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles  = 0x00000016,
14947 TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles  = 0x00000017,
14948 TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles  = 0x00000018,
14949 TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles  = 0x00000019,
14950 TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles  = 0x0000001a,
14951 TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles  = 0x0000001b,
14952 TA_PERF_SEL_ta_sh_fifo_starved           = 0x0000001c,
14953 TA_PERF_SEL_RESERVED_29                  = 0x0000001d,
14954 TA_PERF_SEL_sh_fifo_addr_cycles          = 0x0000001e,
14955 TA_PERF_SEL_sh_fifo_data_cycles          = 0x0000001f,
14956 TA_PERF_SEL_total_wavefronts             = 0x00000020,
14957 TA_PERF_SEL_gradient_cycles              = 0x00000021,
14958 TA_PERF_SEL_walker_cycles                = 0x00000022,
14959 TA_PERF_SEL_aligner_cycles               = 0x00000023,
14960 TA_PERF_SEL_image_wavefronts             = 0x00000024,
14961 TA_PERF_SEL_image_read_wavefronts        = 0x00000025,
14962 TA_PERF_SEL_image_write_wavefronts       = 0x00000026,
14963 TA_PERF_SEL_image_atomic_wavefronts      = 0x00000027,
14964 TA_PERF_SEL_image_total_cycles           = 0x00000028,
14965 TA_PERF_SEL_RESERVED_41                  = 0x00000029,
14966 TA_PERF_SEL_RESERVED_42                  = 0x0000002a,
14967 TA_PERF_SEL_RESERVED_43                  = 0x0000002b,
14968 TA_PERF_SEL_buffer_wavefronts            = 0x0000002c,
14969 TA_PERF_SEL_buffer_read_wavefronts       = 0x0000002d,
14970 TA_PERF_SEL_buffer_write_wavefronts      = 0x0000002e,
14971 TA_PERF_SEL_buffer_atomic_wavefronts     = 0x0000002f,
14972 TA_PERF_SEL_buffer_coalescable_wavefronts  = 0x00000030,
14973 TA_PERF_SEL_buffer_total_cycles          = 0x00000031,
14974 TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles  = 0x00000032,
14975 TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles  = 0x00000033,
14976 TA_PERF_SEL_buffer_coalesced_read_cycles  = 0x00000034,
14977 TA_PERF_SEL_buffer_coalesced_write_cycles  = 0x00000035,
14978 TA_PERF_SEL_addr_stalled_by_tc_cycles    = 0x00000036,
14979 TA_PERF_SEL_addr_stalled_by_td_cycles    = 0x00000037,
14980 TA_PERF_SEL_data_stalled_by_tc_cycles    = 0x00000038,
14981 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles  = 0x00000039,
14982 TA_PERF_SEL_addresser_stalled_cycles     = 0x0000003a,
14983 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles  = 0x0000003b,
14984 TA_PERF_SEL_aniso_stalled_cycles         = 0x0000003c,
14985 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles  = 0x0000003d,
14986 TA_PERF_SEL_deriv_stalled_cycles         = 0x0000003e,
14987 TA_PERF_SEL_aniso_gt1_cycle_quads        = 0x0000003f,
14988 TA_PERF_SEL_color_1_cycle_pixels         = 0x00000040,
14989 TA_PERF_SEL_color_2_cycle_pixels         = 0x00000041,
14990 TA_PERF_SEL_color_3_cycle_pixels         = 0x00000042,
14991 TA_PERF_SEL_color_4_cycle_pixels         = 0x00000043,
14992 TA_PERF_SEL_mip_1_cycle_pixels           = 0x00000044,
14993 TA_PERF_SEL_mip_2_cycle_pixels           = 0x00000045,
14994 TA_PERF_SEL_vol_1_cycle_pixels           = 0x00000046,
14995 TA_PERF_SEL_vol_2_cycle_pixels           = 0x00000047,
14996 TA_PERF_SEL_bilin_point_1_cycle_pixels   = 0x00000048,
14997 TA_PERF_SEL_mipmap_lod_0_samples         = 0x00000049,
14998 TA_PERF_SEL_mipmap_lod_1_samples         = 0x0000004a,
14999 TA_PERF_SEL_mipmap_lod_2_samples         = 0x0000004b,
15000 TA_PERF_SEL_mipmap_lod_3_samples         = 0x0000004c,
15001 TA_PERF_SEL_mipmap_lod_4_samples         = 0x0000004d,
15002 TA_PERF_SEL_mipmap_lod_5_samples         = 0x0000004e,
15003 TA_PERF_SEL_mipmap_lod_6_samples         = 0x0000004f,
15004 TA_PERF_SEL_mipmap_lod_7_samples         = 0x00000050,
15005 TA_PERF_SEL_mipmap_lod_8_samples         = 0x00000051,
15006 TA_PERF_SEL_mipmap_lod_9_samples         = 0x00000052,
15007 TA_PERF_SEL_mipmap_lod_10_samples        = 0x00000053,
15008 TA_PERF_SEL_mipmap_lod_11_samples        = 0x00000054,
15009 TA_PERF_SEL_mipmap_lod_12_samples        = 0x00000055,
15010 TA_PERF_SEL_mipmap_lod_13_samples        = 0x00000056,
15011 TA_PERF_SEL_mipmap_lod_14_samples        = 0x00000057,
15012 TA_PERF_SEL_mipmap_invalid_samples       = 0x00000058,
15013 TA_PERF_SEL_aniso_1_cycle_quads          = 0x00000059,
15014 TA_PERF_SEL_aniso_2_cycle_quads          = 0x0000005a,
15015 TA_PERF_SEL_aniso_4_cycle_quads          = 0x0000005b,
15016 TA_PERF_SEL_aniso_6_cycle_quads          = 0x0000005c,
15017 TA_PERF_SEL_aniso_8_cycle_quads          = 0x0000005d,
15018 TA_PERF_SEL_aniso_10_cycle_quads         = 0x0000005e,
15019 TA_PERF_SEL_aniso_12_cycle_quads         = 0x0000005f,
15020 TA_PERF_SEL_aniso_14_cycle_quads         = 0x00000060,
15021 TA_PERF_SEL_aniso_16_cycle_quads         = 0x00000061,
15022 TA_PERF_SEL_write_path_input_cycles      = 0x00000062,
15023 TA_PERF_SEL_write_path_output_cycles     = 0x00000063,
15024 TA_PERF_SEL_flat_wavefronts              = 0x00000064,
15025 TA_PERF_SEL_flat_read_wavefronts         = 0x00000065,
15026 TA_PERF_SEL_flat_write_wavefronts        = 0x00000066,
15027 TA_PERF_SEL_flat_atomic_wavefronts       = 0x00000067,
15028 TA_PERF_SEL_flat_coalesceable_wavefronts  = 0x00000068,
15029 TA_PERF_SEL_reg_sclk_vld                 = 0x00000069,
15030 TA_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x0000006a,
15031 TA_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x0000006b,
15032 TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en  = 0x0000006c,
15033 TA_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x0000006d,
15034 TA_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x0000006e,
15035 TA_PERF_SEL_xnack_on_phase0              = 0x0000006f,
15036 TA_PERF_SEL_xnack_on_phase1              = 0x00000070,
15037 TA_PERF_SEL_xnack_on_phase2              = 0x00000071,
15038 TA_PERF_SEL_xnack_on_phase3              = 0x00000072,
15039 TA_PERF_SEL_first_xnack_on_phase0        = 0x00000073,
15040 TA_PERF_SEL_first_xnack_on_phase1        = 0x00000074,
15041 TA_PERF_SEL_first_xnack_on_phase2        = 0x00000075,
15042 TA_PERF_SEL_first_xnack_on_phase3        = 0x00000076,
15043 } TA_PERFCOUNT_SEL;
15044 
15045 /*
15046  * TD_PERFCOUNT_SEL enum
15047  */
15048 
15049 typedef enum TD_PERFCOUNT_SEL {
15050 TD_PERF_SEL_none                         = 0x00000000,
15051 TD_PERF_SEL_td_busy                      = 0x00000001,
15052 TD_PERF_SEL_input_busy                   = 0x00000002,
15053 TD_PERF_SEL_sampler_lerp_busy            = 0x00000003,
15054 TD_PERF_SEL_sampler_out_busy             = 0x00000004,
15055 TD_PERF_SEL_nofilter_busy                = 0x00000005,
15056 TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off  = 0x00000006,
15057 TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off  = 0x00000007,
15058 TD_PERF_SEL_RESERVED_8                   = 0x00000008,
15059 TD_PERF_SEL_core_state_rams_read         = 0x00000009,
15060 TD_PERF_SEL_weight_data_rams_read        = 0x0000000a,
15061 TD_PERF_SEL_reference_data_rams_read     = 0x0000000b,
15062 TD_PERF_SEL_tc_td_data_fifo_full         = 0x0000000c,
15063 TD_PERF_SEL_tc_td_ram_fifo_full          = 0x0000000d,
15064 TD_PERF_SEL_input_state_fifo_full        = 0x0000000e,
15065 TD_PERF_SEL_ta_data_stall                = 0x0000000f,
15066 TD_PERF_SEL_tc_data_stall                = 0x00000010,
15067 TD_PERF_SEL_tc_ram_stall                 = 0x00000011,
15068 TD_PERF_SEL_lds_stall                    = 0x00000012,
15069 TD_PERF_SEL_sampler_pkr_full             = 0x00000013,
15070 TD_PERF_SEL_nofilter_pkr_full            = 0x00000014,
15071 TD_PERF_SEL_RESERVED_21                  = 0x00000015,
15072 TD_PERF_SEL_gather4_wavefront            = 0x00000016,
15073 TD_PERF_SEL_gather4h_wavefront           = 0x00000017,
15074 TD_PERF_SEL_gather4h_packed_wavefront    = 0x00000018,
15075 TD_PERF_SEL_gather8h_packed_wavefront    = 0x00000019,
15076 TD_PERF_SEL_sample_c_wavefront           = 0x0000001a,
15077 TD_PERF_SEL_load_wavefront               = 0x0000001b,
15078 TD_PERF_SEL_store_wavefront              = 0x0000001c,
15079 TD_PERF_SEL_ldfptr_wavefront             = 0x0000001d,
15080 TD_PERF_SEL_write_ack_wavefront          = 0x0000001e,
15081 TD_PERF_SEL_d16_en_wavefront             = 0x0000001f,
15082 TD_PERF_SEL_bypassLerp_wavefront         = 0x00000020,
15083 TD_PERF_SEL_min_max_filter_wavefront     = 0x00000021,
15084 TD_PERF_SEL_one_comp_wavefront           = 0x00000022,
15085 TD_PERF_SEL_two_comp_wavefront           = 0x00000023,
15086 TD_PERF_SEL_three_comp_wavefront         = 0x00000024,
15087 TD_PERF_SEL_four_comp_wavefront          = 0x00000025,
15088 TD_PERF_SEL_user_defined_border          = 0x00000026,
15089 TD_PERF_SEL_white_border                 = 0x00000027,
15090 TD_PERF_SEL_opaque_black_border          = 0x00000028,
15091 TD_PERF_SEL_lod_warn_from_ta             = 0x00000029,
15092 TD_PERF_SEL_wavefront_dest_is_lds        = 0x0000002a,
15093 TD_PERF_SEL_td_cycling_of_nofilter_instr  = 0x0000002b,
15094 TD_PERF_SEL_tc_cycling_of_nofilter_instr  = 0x0000002c,
15095 TD_PERF_SEL_out_of_order_instr           = 0x0000002d,
15096 TD_PERF_SEL_total_num_instr              = 0x0000002e,
15097 TD_PERF_SEL_mixmode_instruction          = 0x0000002f,
15098 TD_PERF_SEL_mixmode_resource             = 0x00000030,
15099 TD_PERF_SEL_status_packet                = 0x00000031,
15100 TD_PERF_SEL_address_cmd_poison           = 0x00000032,
15101 TD_PERF_SEL_data_poison                  = 0x00000033,
15102 TD_PERF_SEL_done_scoreboard_not_empty    = 0x00000034,
15103 TD_PERF_SEL_done_scoreboard_is_full      = 0x00000035,
15104 TD_PERF_SEL_done_scoreboard_bp_due_to_ooo  = 0x00000036,
15105 TD_PERF_SEL_done_scoreboard_bp_due_to_lds  = 0x00000037,
15106 TD_PERF_SEL_nofilter_formatters_turned_off  = 0x00000038,
15107 TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt  = 0x00000039,
15108 TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt  = 0x0000003a,
15109 } TD_PERFCOUNT_SEL;
15110 
15111 /*
15112  * TCP_PERFCOUNT_SELECT enum
15113  */
15114 
15115 typedef enum TCP_PERFCOUNT_SELECT {
15116 TCP_PERF_SEL_GATE_EN1                    = 0x00000000,
15117 TCP_PERF_SEL_GATE_EN2                    = 0x00000001,
15118 TCP_PERF_SEL_CORE_REG_SCLK_VLD           = 0x00000002,
15119 TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES   = 0x00000003,
15120 TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES   = 0x00000004,
15121 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES    = 0x00000005,
15122 TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES    = 0x00000006,
15123 TCP_PERF_SEL_TD_TCP_STALL_CYCLES         = 0x00000007,
15124 TCP_PERF_SEL_TCR_TCP_STALL_CYCLES        = 0x00000008,
15125 TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES       = 0x00000009,
15126 TCP_PERF_SEL_LOD_STALL_CYCLES            = 0x0000000a,
15127 TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES  = 0x0000000b,
15128 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES  = 0x0000000c,
15129 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES  = 0x0000000d,
15130 TCP_PERF_SEL_ALLOC_STALL_CYCLES          = 0x0000000e,
15131 TCP_PERF_SEL_UNORDERED_MTYPE_STALL       = 0x0000000f,
15132 TCP_PERF_SEL_LFIFO_STALL_CYCLES          = 0x00000010,
15133 TCP_PERF_SEL_RFIFO_STALL_CYCLES          = 0x00000011,
15134 TCP_PERF_SEL_TCR_RDRET_STALL             = 0x00000012,
15135 TCP_PERF_SEL_WRITE_CONFLICT_STALL        = 0x00000013,
15136 TCP_PERF_SEL_HOLE_READ_STALL             = 0x00000014,
15137 TCP_PERF_SEL_READCONFLICT_STALL_CYCLES   = 0x00000015,
15138 TCP_PERF_SEL_PENDING_STALL_CYCLES        = 0x00000016,
15139 TCP_PERF_SEL_READFIFO_STALL_CYCLES       = 0x00000017,
15140 TCP_PERF_SEL_POWER_STALL                 = 0x00000018,
15141 TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL   = 0x00000019,
15142 TCP_PERF_SEL_TC_TA_XNACK_STALL           = 0x0000001a,
15143 TCP_PERF_SEL_TA_TCP_STATE_READ           = 0x0000001b,
15144 TCP_PERF_SEL_TOTAL_ACCESSES              = 0x0000001c,
15145 TCP_PERF_SEL_TOTAL_READ                  = 0x0000001d,
15146 TCP_PERF_SEL_TOTAL_NON_READ              = 0x0000001e,
15147 TCP_PERF_SEL_TOTAL_WRITE                 = 0x0000001f,
15148 TCP_PERF_SEL_TOTAL_HIT_LRU_READ          = 0x00000020,
15149 TCP_PERF_SEL_TOTAL_MISS_LRU_READ         = 0x00000021,
15150 TCP_PERF_SEL_TOTAL_MISS_EVICT_READ       = 0x00000022,
15151 TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE        = 0x00000023,
15152 TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE      = 0x00000024,
15153 TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET       = 0x00000025,
15154 TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET    = 0x00000026,
15155 TCP_PERF_SEL_TOTAL_WBINVL1               = 0x00000027,
15156 TCP_PERF_SEL_CP_TCP_INVALIDATE           = 0x00000028,
15157 TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES  = 0x00000029,
15158 TCP_PERF_SEL_SHOOTDOWN                   = 0x0000002a,
15159 TCP_PERF_SEL_UTCL0_REQUEST               = 0x0000002b,
15160 TCP_PERF_SEL_UTCL0_TRANSLATION_MISS      = 0x0000002c,
15161 TCP_PERF_SEL_UTCL0_TRANSLATION_HIT       = 0x0000002d,
15162 TCP_PERF_SEL_UTCL0_PERMISSION_MISS       = 0x0000002e,
15163 TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX    = 0x0000002f,
15164 TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT    = 0x00000030,
15165 TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS      = 0x00000031,
15166 TCP_PERF_SEL_UTCL0_LFIFO_FULL            = 0x00000032,
15167 TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES   = 0x00000033,
15168 TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x00000034,
15169 TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT       = 0x00000035,
15170 TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT        = 0x00000036,
15171 TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL   = 0x00000037,
15172 TCP_PERF_SEL_TOTAL_CACHE_ACCESSES        = 0x00000038,
15173 TCP_PERF_SEL_TAGRAM0_REQ                 = 0x00000039,
15174 TCP_PERF_SEL_TAGRAM1_REQ                 = 0x0000003a,
15175 TCP_PERF_SEL_TAGRAM2_REQ                 = 0x0000003b,
15176 TCP_PERF_SEL_TAGRAM3_REQ                 = 0x0000003c,
15177 TCP_PERF_SEL_TCP_LATENCY                 = 0x0000003d,
15178 TCP_PERF_SEL_TCC_READ_REQ_LATENCY        = 0x0000003e,
15179 TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY       = 0x0000003f,
15180 TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY  = 0x00000040,
15181 TCP_PERF_SEL_TCC_READ_REQ                = 0x00000041,
15182 TCP_PERF_SEL_TCC_WRITE_REQ               = 0x00000042,
15183 TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ     = 0x00000043,
15184 TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ  = 0x00000044,
15185 TCP_PERF_SEL_TCC_LRU_REQ                 = 0x00000045,
15186 TCP_PERF_SEL_TCC_STREAM_REQ              = 0x00000046,
15187 TCP_PERF_SEL_TCC_NC_READ_REQ             = 0x00000047,
15188 TCP_PERF_SEL_TCC_NC_WRITE_REQ            = 0x00000048,
15189 TCP_PERF_SEL_TCC_NC_ATOMIC_REQ           = 0x00000049,
15190 TCP_PERF_SEL_TCC_UC_READ_REQ             = 0x0000004a,
15191 TCP_PERF_SEL_TCC_UC_WRITE_REQ            = 0x0000004b,
15192 TCP_PERF_SEL_TCC_UC_ATOMIC_REQ           = 0x0000004c,
15193 TCP_PERF_SEL_TCC_CC_READ_REQ             = 0x0000004d,
15194 TCP_PERF_SEL_TCC_CC_WRITE_REQ            = 0x0000004e,
15195 TCP_PERF_SEL_TCC_CC_ATOMIC_REQ           = 0x0000004f,
15196 TCP_PERF_SEL_TCC_DCC_REQ                 = 0x00000050,
15197 TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET     = 0x00000051,
15198 TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET  = 0x00000052,
15199 TCP_PERF_SEL_GL1_REQ_READ                = 0x00000053,
15200 TCP_PERF_SEL_GL1_REQ_READ_LATENCY        = 0x00000054,
15201 TCP_PERF_SEL_GL1_REQ_WRITE               = 0x00000055,
15202 TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY       = 0x00000056,
15203 TCP_PERF_SEL_REQ_MISS_TAGRAM0            = 0x00000057,
15204 TCP_PERF_SEL_REQ_MISS_TAGRAM1            = 0x00000058,
15205 TCP_PERF_SEL_REQ_MISS_TAGRAM2            = 0x00000059,
15206 TCP_PERF_SEL_REQ_MISS_TAGRAM3            = 0x0000005a,
15207 TCP_PERF_SEL_TA_REQ                      = 0x0000005b,
15208 TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET      = 0x0000005c,
15209 TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET   = 0x0000005d,
15210 TCP_PERF_SEL_TA_REQ_READ                 = 0x0000005e,
15211 TCP_PERF_SEL_TA_REQ_WRITE                = 0x0000005f,
15212 TCP_PERF_SEL_TA_REQ_STATE_READ           = 0x00000060,
15213 } TCP_PERFCOUNT_SELECT;
15214 
15215 /*
15216  * TCP_CACHE_POLICIES enum
15217  */
15218 
15219 typedef enum TCP_CACHE_POLICIES {
15220 TCP_CACHE_POLICY_MISS_LRU                = 0x00000000,
15221 TCP_CACHE_POLICY_MISS_EVICT              = 0x00000001,
15222 TCP_CACHE_POLICY_HIT_LRU                 = 0x00000002,
15223 TCP_CACHE_POLICY_HIT_EVICT               = 0x00000003,
15224 } TCP_CACHE_POLICIES;
15225 
15226 /*
15227  * TCP_CACHE_STORE_POLICIES enum
15228  */
15229 
15230 typedef enum TCP_CACHE_STORE_POLICIES {
15231 TCP_CACHE_STORE_POLICY_WT_LRU            = 0x00000000,
15232 TCP_CACHE_STORE_POLICY_WT_EVICT          = 0x00000001,
15233 } TCP_CACHE_STORE_POLICIES;
15234 
15235 /*
15236  * TCP_WATCH_MODES enum
15237  */
15238 
15239 typedef enum TCP_WATCH_MODES {
15240 TCP_WATCH_MODE_READ                      = 0x00000000,
15241 TCP_WATCH_MODE_NONREAD                   = 0x00000001,
15242 TCP_WATCH_MODE_ATOMIC                    = 0x00000002,
15243 TCP_WATCH_MODE_ALL                       = 0x00000003,
15244 } TCP_WATCH_MODES;
15245 
15246 /*
15247  * TCP_DSM_DATA_SEL enum
15248  */
15249 
15250 typedef enum TCP_DSM_DATA_SEL {
15251 TCP_DSM_DISABLE                          = 0x00000000,
15252 TCP_DSM_SEL0                             = 0x00000001,
15253 TCP_DSM_SEL1                             = 0x00000002,
15254 TCP_DSM_SEL_BOTH                         = 0x00000003,
15255 } TCP_DSM_DATA_SEL;
15256 
15257 /*
15258  * TCP_DSM_SINGLE_WRITE enum
15259  */
15260 
15261 typedef enum TCP_DSM_SINGLE_WRITE {
15262 TCP_DSM_SINGLE_WRITE_DIS                 = 0x00000000,
15263 TCP_DSM_SINGLE_WRITE_EN                  = 0x00000001,
15264 } TCP_DSM_SINGLE_WRITE;
15265 
15266 /*
15267  * TCP_DSM_INJECT_SEL enum
15268  */
15269 
15270 typedef enum TCP_DSM_INJECT_SEL {
15271 TCP_DSM_INJECT_SEL0                      = 0x00000000,
15272 TCP_DSM_INJECT_SEL1                      = 0x00000001,
15273 TCP_DSM_INJECT_SEL2                      = 0x00000002,
15274 TCP_DSM_INJECT_SEL3                      = 0x00000003,
15275 } TCP_DSM_INJECT_SEL;
15276 
15277 /*
15278  * TCP_OPCODE_TYPE enum
15279  */
15280 
15281 typedef enum TCP_OPCODE_TYPE {
15282 TCP_OPCODE_READ                          = 0x00000000,
15283 TCP_OPCODE_WRITE                         = 0x00000001,
15284 TCP_OPCODE_ATOMIC                        = 0x00000002,
15285 TCP_OPCODE_WBINVL1                       = 0x00000003,
15286 TCP_OPCODE_ATOMIC_CMPSWAP                = 0x00000004,
15287 TCP_OPCODE_GATHERH                       = 0x00000005,
15288 } TCP_OPCODE_TYPE;
15289 
15290 /*******************************************************
15291  * GL2C Enums
15292  *******************************************************/
15293 
15294 /*
15295  * GL2C_PERF_SEL enum
15296  */
15297 
15298 typedef enum GL2C_PERF_SEL {
15299 GL2C_PERF_SEL_NONE                       = 0x00000000,
15300 GL2C_PERF_SEL_CYCLE                      = 0x00000001,
15301 GL2C_PERF_SEL_BUSY                       = 0x00000002,
15302 GL2C_PERF_SEL_REQ                        = 0x00000003,
15303 GL2C_PERF_SEL_VOL_REQ                    = 0x00000004,
15304 GL2C_PERF_SEL_HIGH_PRIORITY_REQ          = 0x00000005,
15305 GL2C_PERF_SEL_READ                       = 0x00000006,
15306 GL2C_PERF_SEL_WRITE                      = 0x00000007,
15307 GL2C_PERF_SEL_ATOMIC                     = 0x00000008,
15308 GL2C_PERF_SEL_NOP_ACK                    = 0x00000009,
15309 GL2C_PERF_SEL_NOP_RTN0                   = 0x0000000a,
15310 GL2C_PERF_SEL_PROBE                      = 0x0000000b,
15311 GL2C_PERF_SEL_PROBE_ALL                  = 0x0000000c,
15312 GL2C_PERF_SEL_INTERNAL_PROBE             = 0x0000000d,
15313 GL2C_PERF_SEL_COMPRESSED_READ_REQ        = 0x0000000e,
15314 GL2C_PERF_SEL_METADATA_READ_REQ          = 0x0000000f,
15315 GL2C_PERF_SEL_CLIENT0_REQ                = 0x00000010,
15316 GL2C_PERF_SEL_CLIENT1_REQ                = 0x00000011,
15317 GL2C_PERF_SEL_CLIENT2_REQ                = 0x00000012,
15318 GL2C_PERF_SEL_CLIENT3_REQ                = 0x00000013,
15319 GL2C_PERF_SEL_CLIENT4_REQ                = 0x00000014,
15320 GL2C_PERF_SEL_CLIENT5_REQ                = 0x00000015,
15321 GL2C_PERF_SEL_CLIENT6_REQ                = 0x00000016,
15322 GL2C_PERF_SEL_CLIENT7_REQ                = 0x00000017,
15323 GL2C_PERF_SEL_C_RW_S_REQ                 = 0x00000018,
15324 GL2C_PERF_SEL_C_RW_US_REQ                = 0x00000019,
15325 GL2C_PERF_SEL_C_RO_S_REQ                 = 0x0000001a,
15326 GL2C_PERF_SEL_C_RO_US_REQ                = 0x0000001b,
15327 GL2C_PERF_SEL_UC_REQ                     = 0x0000001c,
15328 GL2C_PERF_SEL_LRU_REQ                    = 0x0000001d,
15329 GL2C_PERF_SEL_STREAM_REQ                 = 0x0000001e,
15330 GL2C_PERF_SEL_BYPASS_REQ                 = 0x0000001f,
15331 GL2C_PERF_SEL_NOA_REQ                    = 0x00000020,
15332 GL2C_PERF_SEL_SHARED_REQ                 = 0x00000021,
15333 GL2C_PERF_SEL_HIT                        = 0x00000022,
15334 GL2C_PERF_SEL_MISS                       = 0x00000023,
15335 GL2C_PERF_SEL_FULL_HIT                   = 0x00000024,
15336 GL2C_PERF_SEL_PARTIAL_32B_HIT            = 0x00000025,
15337 GL2C_PERF_SEL_PARTIAL_64B_HIT            = 0x00000026,
15338 GL2C_PERF_SEL_PARTIAL_96B_HIT            = 0x00000027,
15339 GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT       = 0x00000028,
15340 GL2C_PERF_SEL_FULLY_WRITTEN_HIT          = 0x00000029,
15341 GL2C_PERF_SEL_UNCACHED_WRITE             = 0x0000002a,
15342 GL2C_PERF_SEL_WRITEBACK                  = 0x0000002b,
15343 GL2C_PERF_SEL_NORMAL_WRITEBACK           = 0x0000002c,
15344 GL2C_PERF_SEL_EVICT                      = 0x0000002d,
15345 GL2C_PERF_SEL_NORMAL_EVICT               = 0x0000002e,
15346 GL2C_PERF_SEL_PROBE_EVICT                = 0x0000002f,
15347 GL2C_PERF_SEL_REQ_TO_MISS_QUEUE          = 0x00000030,
15348 GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO   = 0x00000031,
15349 GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP      = 0x00000032,
15350 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0   = 0x00000033,
15351 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1   = 0x00000034,
15352 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2   = 0x00000035,
15353 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3   = 0x00000036,
15354 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4   = 0x00000037,
15355 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5   = 0x00000038,
15356 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6   = 0x00000039,
15357 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7   = 0x0000003a,
15358 GL2C_PERF_SEL_READ_32_REQ                = 0x0000003b,
15359 GL2C_PERF_SEL_READ_64_REQ                = 0x0000003c,
15360 GL2C_PERF_SEL_READ_128_REQ               = 0x0000003d,
15361 GL2C_PERF_SEL_WRITE_32_REQ               = 0x0000003e,
15362 GL2C_PERF_SEL_WRITE_64_REQ               = 0x0000003f,
15363 GL2C_PERF_SEL_COMPRESSED_READ_0_REQ      = 0x00000040,
15364 GL2C_PERF_SEL_COMPRESSED_READ_32_REQ     = 0x00000041,
15365 GL2C_PERF_SEL_COMPRESSED_READ_64_REQ     = 0x00000042,
15366 GL2C_PERF_SEL_COMPRESSED_READ_96_REQ     = 0x00000043,
15367 GL2C_PERF_SEL_COMPRESSED_READ_128_REQ    = 0x00000044,
15368 GL2C_PERF_SEL_MC_WRREQ                   = 0x00000045,
15369 GL2C_PERF_SEL_EA_WRREQ_64B               = 0x00000046,
15370 GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND     = 0x00000047,
15371 GL2C_PERF_SEL_EA_WR_UNCACHED_32B         = 0x00000048,
15372 GL2C_PERF_SEL_MC_WRREQ_STALL             = 0x00000049,
15373 GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL   = 0x0000004a,
15374 GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL  = 0x0000004b,
15375 GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL  = 0x0000004c,
15376 GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL   = 0x0000004d,
15377 GL2C_PERF_SEL_MC_WRREQ_LEVEL             = 0x0000004e,
15378 GL2C_PERF_SEL_EA_ATOMIC                  = 0x0000004f,
15379 GL2C_PERF_SEL_EA_ATOMIC_LEVEL            = 0x00000050,
15380 GL2C_PERF_SEL_MC_RDREQ                   = 0x00000051,
15381 GL2C_PERF_SEL_EA_RDREQ_SPLIT             = 0x00000052,
15382 GL2C_PERF_SEL_EA_RDREQ_32B               = 0x00000053,
15383 GL2C_PERF_SEL_EA_RDREQ_64B               = 0x00000054,
15384 GL2C_PERF_SEL_EA_RDREQ_96B               = 0x00000055,
15385 GL2C_PERF_SEL_EA_RDREQ_128B              = 0x00000056,
15386 GL2C_PERF_SEL_EA_RD_UNCACHED_32B         = 0x00000057,
15387 GL2C_PERF_SEL_EA_RD_MDC_32B              = 0x00000058,
15388 GL2C_PERF_SEL_EA_RD_COMPRESSED_32B       = 0x00000059,
15389 GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL   = 0x0000005a,
15390 GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL  = 0x0000005b,
15391 GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL  = 0x0000005c,
15392 GL2C_PERF_SEL_MC_RDREQ_LEVEL             = 0x0000005d,
15393 GL2C_PERF_SEL_EA_RDREQ_DRAM              = 0x0000005e,
15394 GL2C_PERF_SEL_EA_WRREQ_DRAM              = 0x0000005f,
15395 GL2C_PERF_SEL_EA_RDREQ_DRAM_32B          = 0x00000060,
15396 GL2C_PERF_SEL_EA_WRREQ_DRAM_32B          = 0x00000061,
15397 GL2C_PERF_SEL_ONION_READ                 = 0x00000062,
15398 GL2C_PERF_SEL_ONION_WRITE                = 0x00000063,
15399 GL2C_PERF_SEL_IO_READ                    = 0x00000064,
15400 GL2C_PERF_SEL_IO_WRITE                   = 0x00000065,
15401 GL2C_PERF_SEL_GARLIC_READ                = 0x00000066,
15402 GL2C_PERF_SEL_GARLIC_WRITE               = 0x00000067,
15403 GL2C_PERF_SEL_LATENCY_FIFO_FULL          = 0x00000068,
15404 GL2C_PERF_SEL_SRC_FIFO_FULL              = 0x00000069,
15405 GL2C_PERF_SEL_TAG_STALL                  = 0x0000006a,
15406 GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL  = 0x0000006b,
15407 GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x0000006c,
15408 GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL  = 0x0000006d,
15409 GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL  = 0x0000006e,
15410 GL2C_PERF_SEL_TAG_PROBE_STALL            = 0x0000006f,
15411 GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL     = 0x00000070,
15412 GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL  = 0x00000071,
15413 GL2C_PERF_SEL_TAG_READ_DST_STALL         = 0x00000072,
15414 GL2C_PERF_SEL_READ_RETURN_TIMEOUT        = 0x00000073,
15415 GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT     = 0x00000074,
15416 GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE    = 0x00000075,
15417 GL2C_PERF_SEL_BUBBLE                     = 0x00000076,
15418 GL2C_PERF_SEL_IB_REQ                     = 0x00000077,
15419 GL2C_PERF_SEL_IB_STALL                   = 0x00000078,
15420 GL2C_PERF_SEL_IB_TAG_STALL               = 0x00000079,
15421 GL2C_PERF_SEL_IB_CM_STALL                = 0x0000007a,
15422 GL2C_PERF_SEL_RETURN_ACK                 = 0x0000007b,
15423 GL2C_PERF_SEL_RETURN_DATA                = 0x0000007c,
15424 GL2C_PERF_SEL_EA_RDRET_NACK              = 0x0000007d,
15425 GL2C_PERF_SEL_EA_WRRET_NACK              = 0x0000007e,
15426 GL2C_PERF_SEL_GL2A_LEVEL                 = 0x0000007f,
15427 GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION  = 0x00000080,
15428 GL2C_PERF_SEL_PROBE_FILTER_DISABLED      = 0x00000081,
15429 GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START  = 0x00000082,
15430 GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START  = 0x00000083,
15431 GL2C_PERF_SEL_GCR_INV                    = 0x00000084,
15432 GL2C_PERF_SEL_GCR_WB                     = 0x00000085,
15433 GL2C_PERF_SEL_GCR_DISCARD                = 0x00000086,
15434 GL2C_PERF_SEL_GCR_RANGE                  = 0x00000087,
15435 GL2C_PERF_SEL_GCR_ALL                    = 0x00000088,
15436 GL2C_PERF_SEL_GCR_VOL                    = 0x00000089,
15437 GL2C_PERF_SEL_GCR_UNSHARED               = 0x0000008a,
15438 GL2C_PERF_SEL_GCR_MDC_INV                = 0x0000008b,
15439 GL2C_PERF_SEL_GCR_GL2_INV_ALL            = 0x0000008c,
15440 GL2C_PERF_SEL_GCR_GL2_WB_ALL             = 0x0000008d,
15441 GL2C_PERF_SEL_GCR_MDC_INV_ALL            = 0x0000008e,
15442 GL2C_PERF_SEL_GCR_GL2_INV_RANGE          = 0x0000008f,
15443 GL2C_PERF_SEL_GCR_GL2_WB_RANGE           = 0x00000090,
15444 GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE       = 0x00000091,
15445 GL2C_PERF_SEL_GCR_MDC_INV_RANGE          = 0x00000092,
15446 GL2C_PERF_SEL_ALL_GCR_INV_EVICT          = 0x00000093,
15447 GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT      = 0x00000094,
15448 GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE    = 0x00000095,
15449 GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE  = 0x00000096,
15450 GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK       = 0x00000097,
15451 GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE        = 0x00000098,
15452 GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT        = 0x00000099,
15453 GL2C_PERF_SEL_GCR_INVL2_VOL_START        = 0x0000009a,
15454 GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE         = 0x0000009b,
15455 GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT         = 0x0000009c,
15456 GL2C_PERF_SEL_GCR_WBL2_VOL_START         = 0x0000009d,
15457 GL2C_PERF_SEL_GCR_WBINVL2_CYCLE          = 0x0000009e,
15458 GL2C_PERF_SEL_GCR_WBINVL2_EVICT          = 0x0000009f,
15459 GL2C_PERF_SEL_GCR_WBINVL2_START          = 0x000000a0,
15460 GL2C_PERF_SEL_MDC_INV_METADATA           = 0x000000a1,
15461 GL2C_PERF_SEL_MDC_REQ                    = 0x000000a2,
15462 GL2C_PERF_SEL_MDC_LEVEL                  = 0x000000a3,
15463 GL2C_PERF_SEL_MDC_TAG_HIT                = 0x000000a4,
15464 GL2C_PERF_SEL_MDC_SECTOR_HIT             = 0x000000a5,
15465 GL2C_PERF_SEL_MDC_SECTOR_MISS            = 0x000000a6,
15466 GL2C_PERF_SEL_MDC_TAG_STALL              = 0x000000a7,
15467 GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL  = 0x000000a8,
15468 GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL  = 0x000000a9,
15469 GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL  = 0x000000aa,
15470 GL2C_PERF_SEL_CM_CHANNEL0_REQ            = 0x000000ab,
15471 GL2C_PERF_SEL_CM_CHANNEL1_REQ            = 0x000000ac,
15472 GL2C_PERF_SEL_CM_CHANNEL2_REQ            = 0x000000ad,
15473 GL2C_PERF_SEL_CM_CHANNEL3_REQ            = 0x000000ae,
15474 GL2C_PERF_SEL_CM_CHANNEL4_REQ            = 0x000000af,
15475 GL2C_PERF_SEL_CM_CHANNEL5_REQ            = 0x000000b0,
15476 GL2C_PERF_SEL_CM_CHANNEL6_REQ            = 0x000000b1,
15477 GL2C_PERF_SEL_CM_CHANNEL7_REQ            = 0x000000b2,
15478 GL2C_PERF_SEL_CM_CHANNEL8_REQ            = 0x000000b3,
15479 GL2C_PERF_SEL_CM_CHANNEL9_REQ            = 0x000000b4,
15480 GL2C_PERF_SEL_CM_CHANNEL10_REQ           = 0x000000b5,
15481 GL2C_PERF_SEL_CM_CHANNEL11_REQ           = 0x000000b6,
15482 GL2C_PERF_SEL_CM_CHANNEL12_REQ           = 0x000000b7,
15483 GL2C_PERF_SEL_CM_CHANNEL13_REQ           = 0x000000b8,
15484 GL2C_PERF_SEL_CM_CHANNEL14_REQ           = 0x000000b9,
15485 GL2C_PERF_SEL_CM_CHANNEL15_REQ           = 0x000000ba,
15486 GL2C_PERF_SEL_CM_CHANNEL16_REQ           = 0x000000bb,
15487 GL2C_PERF_SEL_CM_CHANNEL17_REQ           = 0x000000bc,
15488 GL2C_PERF_SEL_CM_CHANNEL18_REQ           = 0x000000bd,
15489 GL2C_PERF_SEL_CM_CHANNEL19_REQ           = 0x000000be,
15490 GL2C_PERF_SEL_CM_CHANNEL20_REQ           = 0x000000bf,
15491 GL2C_PERF_SEL_CM_CHANNEL21_REQ           = 0x000000c0,
15492 GL2C_PERF_SEL_CM_CHANNEL22_REQ           = 0x000000c1,
15493 GL2C_PERF_SEL_CM_CHANNEL23_REQ           = 0x000000c2,
15494 GL2C_PERF_SEL_CM_CHANNEL24_REQ           = 0x000000c3,
15495 GL2C_PERF_SEL_CM_CHANNEL25_REQ           = 0x000000c4,
15496 GL2C_PERF_SEL_CM_CHANNEL26_REQ           = 0x000000c5,
15497 GL2C_PERF_SEL_CM_CHANNEL27_REQ           = 0x000000c6,
15498 GL2C_PERF_SEL_CM_CHANNEL28_REQ           = 0x000000c7,
15499 GL2C_PERF_SEL_CM_CHANNEL29_REQ           = 0x000000c8,
15500 GL2C_PERF_SEL_CM_CHANNEL30_REQ           = 0x000000c9,
15501 GL2C_PERF_SEL_CM_CHANNEL31_REQ           = 0x000000ca,
15502 GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ   = 0x000000cb,
15503 GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ  = 0x000000cc,
15504 GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ  = 0x000000cd,
15505 GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ    = 0x000000ce,
15506 GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ  = 0x000000cf,
15507 GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ  = 0x000000d0,
15508 GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ  = 0x000000d1,
15509 GL2C_PERF_SEL_CM_COMP_READ_REQ           = 0x000000d2,
15510 GL2C_PERF_SEL_CM_READ_BACK_REQ           = 0x000000d3,
15511 GL2C_PERF_SEL_CM_METADATA_WR_REQ         = 0x000000d4,
15512 GL2C_PERF_SEL_CM_WR_ACK_REQ              = 0x000000d5,
15513 GL2C_PERF_SEL_CM_NO_ACK_REQ              = 0x000000d6,
15514 GL2C_PERF_SEL_CM_NOOP_REQ                = 0x000000d7,
15515 GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ       = 0x000000d8,
15516 GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ      = 0x000000d9,
15517 GL2C_PERF_SEL_CM_COMP_STENCIL_REQ        = 0x000000da,
15518 GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ        = 0x000000db,
15519 GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ        = 0x000000dc,
15520 GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ        = 0x000000dd,
15521 GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ        = 0x000000de,
15522 GL2C_PERF_SEL_CM_FULL_WRITE_REQ          = 0x000000df,
15523 GL2C_PERF_SEL_CM_RVF_FULL                = 0x000000e0,
15524 GL2C_PERF_SEL_CM_SDR_FULL                = 0x000000e1,
15525 GL2C_PERF_SEL_CM_MERGE_BUF_FULL          = 0x000000e2,
15526 GL2C_PERF_SEL_CM_DCC_STALL               = 0x000000e3,
15527 } GL2C_PERF_SEL;
15528 
15529 /*
15530  * GL2A_PERF_SEL enum
15531  */
15532 
15533 typedef enum GL2A_PERF_SEL {
15534 GL2A_PERF_SEL_NONE                       = 0x00000000,
15535 GL2A_PERF_SEL_CYCLE                      = 0x00000001,
15536 GL2A_PERF_SEL_BUSY                       = 0x00000002,
15537 GL2A_PERF_SEL_REQ_GL2C0                  = 0x00000003,
15538 GL2A_PERF_SEL_REQ_GL2C1                  = 0x00000004,
15539 GL2A_PERF_SEL_REQ_GL2C2                  = 0x00000005,
15540 GL2A_PERF_SEL_REQ_GL2C3                  = 0x00000006,
15541 GL2A_PERF_SEL_REQ_GL2C4                  = 0x00000007,
15542 GL2A_PERF_SEL_REQ_GL2C5                  = 0x00000008,
15543 GL2A_PERF_SEL_REQ_GL2C6                  = 0x00000009,
15544 GL2A_PERF_SEL_REQ_GL2C7                  = 0x0000000a,
15545 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0          = 0x0000000b,
15546 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1          = 0x0000000c,
15547 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2          = 0x0000000d,
15548 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3          = 0x0000000e,
15549 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4          = 0x0000000f,
15550 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5          = 0x00000010,
15551 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6          = 0x00000011,
15552 GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7          = 0x00000012,
15553 GL2A_PERF_SEL_REQ_BURST_GL2C0            = 0x00000013,
15554 GL2A_PERF_SEL_REQ_BURST_GL2C1            = 0x00000014,
15555 GL2A_PERF_SEL_REQ_BURST_GL2C2            = 0x00000015,
15556 GL2A_PERF_SEL_REQ_BURST_GL2C3            = 0x00000016,
15557 GL2A_PERF_SEL_REQ_BURST_GL2C4            = 0x00000017,
15558 GL2A_PERF_SEL_REQ_BURST_GL2C5            = 0x00000018,
15559 GL2A_PERF_SEL_REQ_BURST_GL2C6            = 0x00000019,
15560 GL2A_PERF_SEL_REQ_BURST_GL2C7            = 0x0000001a,
15561 GL2A_PERF_SEL_REQ_STALL_GL2C0            = 0x0000001b,
15562 GL2A_PERF_SEL_REQ_STALL_GL2C1            = 0x0000001c,
15563 GL2A_PERF_SEL_REQ_STALL_GL2C2            = 0x0000001d,
15564 GL2A_PERF_SEL_REQ_STALL_GL2C3            = 0x0000001e,
15565 GL2A_PERF_SEL_REQ_STALL_GL2C4            = 0x0000001f,
15566 GL2A_PERF_SEL_REQ_STALL_GL2C5            = 0x00000020,
15567 GL2A_PERF_SEL_REQ_STALL_GL2C6            = 0x00000021,
15568 GL2A_PERF_SEL_REQ_STALL_GL2C7            = 0x00000022,
15569 GL2A_PERF_SEL_RTN_STALL_GL2C0            = 0x00000023,
15570 GL2A_PERF_SEL_RTN_STALL_GL2C1            = 0x00000024,
15571 GL2A_PERF_SEL_RTN_STALL_GL2C2            = 0x00000025,
15572 GL2A_PERF_SEL_RTN_STALL_GL2C3            = 0x00000026,
15573 GL2A_PERF_SEL_RTN_STALL_GL2C4            = 0x00000027,
15574 GL2A_PERF_SEL_RTN_STALL_GL2C5            = 0x00000028,
15575 GL2A_PERF_SEL_RTN_STALL_GL2C6            = 0x00000029,
15576 GL2A_PERF_SEL_RTN_STALL_GL2C7            = 0x0000002a,
15577 GL2A_PERF_SEL_RTN_CLIENT0                = 0x0000002b,
15578 GL2A_PERF_SEL_RTN_CLIENT1                = 0x0000002c,
15579 GL2A_PERF_SEL_RTN_CLIENT2                = 0x0000002d,
15580 GL2A_PERF_SEL_RTN_CLIENT3                = 0x0000002e,
15581 GL2A_PERF_SEL_RTN_CLIENT4                = 0x0000002f,
15582 GL2A_PERF_SEL_RTN_CLIENT5                = 0x00000030,
15583 GL2A_PERF_SEL_RTN_CLIENT6                = 0x00000031,
15584 GL2A_PERF_SEL_RTN_CLIENT7                = 0x00000032,
15585 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0  = 0x00000033,
15586 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1  = 0x00000034,
15587 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2  = 0x00000035,
15588 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3  = 0x00000036,
15589 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4  = 0x00000037,
15590 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5  = 0x00000038,
15591 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6  = 0x00000039,
15592 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7  = 0x0000003a,
15593 } GL2A_PERF_SEL;
15594 
15595 /*******************************************************
15596  * GRBM Enums
15597  *******************************************************/
15598 
15599 /*
15600  * GRBM_PERF_SEL enum
15601  */
15602 
15603 typedef enum GRBM_PERF_SEL {
15604 GRBM_PERF_SEL_COUNT                      = 0x00000000,
15605 GRBM_PERF_SEL_USER_DEFINED               = 0x00000001,
15606 GRBM_PERF_SEL_GUI_ACTIVE                 = 0x00000002,
15607 GRBM_PERF_SEL_CP_BUSY                    = 0x00000003,
15608 GRBM_PERF_SEL_CP_COHER_BUSY              = 0x00000004,
15609 GRBM_PERF_SEL_CP_DMA_BUSY                = 0x00000005,
15610 GRBM_PERF_SEL_CB_BUSY                    = 0x00000006,
15611 GRBM_PERF_SEL_DB_BUSY                    = 0x00000007,
15612 GRBM_PERF_SEL_PA_BUSY                    = 0x00000008,
15613 GRBM_PERF_SEL_SC_BUSY                    = 0x00000009,
15614 GRBM_PERF_SEL_RESERVED_6                 = 0x0000000a,
15615 GRBM_PERF_SEL_SPI_BUSY                   = 0x0000000b,
15616 GRBM_PERF_SEL_SX_BUSY                    = 0x0000000c,
15617 GRBM_PERF_SEL_TA_BUSY                    = 0x0000000d,
15618 GRBM_PERF_SEL_CB_CLEAN                   = 0x0000000e,
15619 GRBM_PERF_SEL_DB_CLEAN                   = 0x0000000f,
15620 GRBM_PERF_SEL_RESERVED_5                 = 0x00000010,
15621 GRBM_PERF_SEL_RESERVED_9                 = 0x00000011,
15622 GRBM_PERF_SEL_RESERVED_4                 = 0x00000012,
15623 GRBM_PERF_SEL_RESERVED_3                 = 0x00000013,
15624 GRBM_PERF_SEL_RESERVED_2                 = 0x00000014,
15625 GRBM_PERF_SEL_RESERVED_1                 = 0x00000015,
15626 GRBM_PERF_SEL_RESERVED_0                 = 0x00000016,
15627 GRBM_PERF_SEL_RESERVED_8                 = 0x00000017,
15628 GRBM_PERF_SEL_RESERVED_7                 = 0x00000018,
15629 GRBM_PERF_SEL_GDS_BUSY                   = 0x00000019,
15630 GRBM_PERF_SEL_BCI_BUSY                   = 0x0000001a,
15631 GRBM_PERF_SEL_RLC_BUSY                   = 0x0000001b,
15632 GRBM_PERF_SEL_TCP_BUSY                   = 0x0000001c,
15633 GRBM_PERF_SEL_CPG_BUSY                   = 0x0000001d,
15634 GRBM_PERF_SEL_CPC_BUSY                   = 0x0000001e,
15635 GRBM_PERF_SEL_CPF_BUSY                   = 0x0000001f,
15636 GRBM_PERF_SEL_GE_BUSY                    = 0x00000020,
15637 GRBM_PERF_SEL_GE_NO_DMA_BUSY             = 0x00000021,
15638 GRBM_PERF_SEL_UTCL2_BUSY                 = 0x00000022,
15639 GRBM_PERF_SEL_EA_BUSY                    = 0x00000023,
15640 GRBM_PERF_SEL_RMI_BUSY                   = 0x00000024,
15641 GRBM_PERF_SEL_CPAXI_BUSY                 = 0x00000025,
15642 GRBM_PERF_SEL_UTCL1_BUSY                 = 0x00000027,
15643 GRBM_PERF_SEL_GL2CC_BUSY                 = 0x00000028,
15644 GRBM_PERF_SEL_SDMA_BUSY                  = 0x00000029,
15645 GRBM_PERF_SEL_CH_BUSY                    = 0x0000002a,
15646 GRBM_PERF_SEL_PH_BUSY                    = 0x0000002b,
15647 GRBM_PERF_SEL_PMM_BUSY                   = 0x0000002c,
15648 GRBM_PERF_SEL_GUS_BUSY                   = 0x0000002d,
15649 GRBM_PERF_SEL_GL1CC_BUSY                 = 0x0000002e,
15650 } GRBM_PERF_SEL;
15651 
15652 /*
15653  * GRBM_SE0_PERF_SEL enum
15654  */
15655 
15656 typedef enum GRBM_SE0_PERF_SEL {
15657 GRBM_SE0_PERF_SEL_COUNT                  = 0x00000000,
15658 GRBM_SE0_PERF_SEL_USER_DEFINED           = 0x00000001,
15659 GRBM_SE0_PERF_SEL_CB_BUSY                = 0x00000002,
15660 GRBM_SE0_PERF_SEL_DB_BUSY                = 0x00000003,
15661 GRBM_SE0_PERF_SEL_SC_BUSY                = 0x00000004,
15662 GRBM_SE0_PERF_SEL_RESERVED_1             = 0x00000005,
15663 GRBM_SE0_PERF_SEL_SPI_BUSY               = 0x00000006,
15664 GRBM_SE0_PERF_SEL_SX_BUSY                = 0x00000007,
15665 GRBM_SE0_PERF_SEL_TA_BUSY                = 0x00000008,
15666 GRBM_SE0_PERF_SEL_CB_CLEAN               = 0x00000009,
15667 GRBM_SE0_PERF_SEL_DB_CLEAN               = 0x0000000a,
15668 GRBM_SE0_PERF_SEL_RESERVED_0             = 0x0000000b,
15669 GRBM_SE0_PERF_SEL_PA_BUSY                = 0x0000000c,
15670 GRBM_SE0_PERF_SEL_RESERVED_2             = 0x0000000d,
15671 GRBM_SE0_PERF_SEL_BCI_BUSY               = 0x0000000e,
15672 GRBM_SE0_PERF_SEL_RMI_BUSY               = 0x0000000f,
15673 GRBM_SE0_PERF_SEL_UTCL1_BUSY             = 0x00000010,
15674 GRBM_SE0_PERF_SEL_TCP_BUSY               = 0x00000011,
15675 GRBM_SE0_PERF_SEL_GL1CC_BUSY             = 0x00000012,
15676 } GRBM_SE0_PERF_SEL;
15677 
15678 /*
15679  * GRBM_SE1_PERF_SEL enum
15680  */
15681 
15682 typedef enum GRBM_SE1_PERF_SEL {
15683 GRBM_SE1_PERF_SEL_COUNT                  = 0x00000000,
15684 GRBM_SE1_PERF_SEL_USER_DEFINED           = 0x00000001,
15685 GRBM_SE1_PERF_SEL_CB_BUSY                = 0x00000002,
15686 GRBM_SE1_PERF_SEL_DB_BUSY                = 0x00000003,
15687 GRBM_SE1_PERF_SEL_SC_BUSY                = 0x00000004,
15688 GRBM_SE1_PERF_SEL_RESERVED_1             = 0x00000005,
15689 GRBM_SE1_PERF_SEL_SPI_BUSY               = 0x00000006,
15690 GRBM_SE1_PERF_SEL_SX_BUSY                = 0x00000007,
15691 GRBM_SE1_PERF_SEL_TA_BUSY                = 0x00000008,
15692 GRBM_SE1_PERF_SEL_CB_CLEAN               = 0x00000009,
15693 GRBM_SE1_PERF_SEL_DB_CLEAN               = 0x0000000a,
15694 GRBM_SE1_PERF_SEL_RESERVED_0             = 0x0000000b,
15695 GRBM_SE1_PERF_SEL_PA_BUSY                = 0x0000000c,
15696 GRBM_SE1_PERF_SEL_RESERVED_2             = 0x0000000d,
15697 GRBM_SE1_PERF_SEL_BCI_BUSY               = 0x0000000e,
15698 GRBM_SE1_PERF_SEL_RMI_BUSY               = 0x0000000f,
15699 GRBM_SE1_PERF_SEL_UTCL1_BUSY             = 0x00000010,
15700 GRBM_SE1_PERF_SEL_TCP_BUSY               = 0x00000011,
15701 GRBM_SE1_PERF_SEL_GL1CC_BUSY             = 0x00000012,
15702 } GRBM_SE1_PERF_SEL;
15703 
15704 /*
15705  * GRBM_SE2_PERF_SEL enum
15706  */
15707 
15708 typedef enum GRBM_SE2_PERF_SEL {
15709 GRBM_SE2_PERF_SEL_COUNT                  = 0x00000000,
15710 GRBM_SE2_PERF_SEL_USER_DEFINED           = 0x00000001,
15711 GRBM_SE2_PERF_SEL_CB_BUSY                = 0x00000002,
15712 GRBM_SE2_PERF_SEL_DB_BUSY                = 0x00000003,
15713 GRBM_SE2_PERF_SEL_SC_BUSY                = 0x00000004,
15714 GRBM_SE2_PERF_SEL_RESERVED_1             = 0x00000005,
15715 GRBM_SE2_PERF_SEL_SPI_BUSY               = 0x00000006,
15716 GRBM_SE2_PERF_SEL_SX_BUSY                = 0x00000007,
15717 GRBM_SE2_PERF_SEL_TA_BUSY                = 0x00000008,
15718 GRBM_SE2_PERF_SEL_CB_CLEAN               = 0x00000009,
15719 GRBM_SE2_PERF_SEL_DB_CLEAN               = 0x0000000a,
15720 GRBM_SE2_PERF_SEL_RESERVED_0             = 0x0000000b,
15721 GRBM_SE2_PERF_SEL_PA_BUSY                = 0x0000000c,
15722 GRBM_SE2_PERF_SEL_RESERVED_2             = 0x0000000d,
15723 GRBM_SE2_PERF_SEL_BCI_BUSY               = 0x0000000e,
15724 GRBM_SE2_PERF_SEL_RMI_BUSY               = 0x0000000f,
15725 GRBM_SE2_PERF_SEL_UTCL1_BUSY             = 0x00000010,
15726 GRBM_SE2_PERF_SEL_TCP_BUSY               = 0x00000011,
15727 GRBM_SE2_PERF_SEL_GL1CC_BUSY             = 0x00000012,
15728 } GRBM_SE2_PERF_SEL;
15729 
15730 /*
15731  * GRBM_SE3_PERF_SEL enum
15732  */
15733 
15734 typedef enum GRBM_SE3_PERF_SEL {
15735 GRBM_SE3_PERF_SEL_COUNT                  = 0x00000000,
15736 GRBM_SE3_PERF_SEL_USER_DEFINED           = 0x00000001,
15737 GRBM_SE3_PERF_SEL_CB_BUSY                = 0x00000002,
15738 GRBM_SE3_PERF_SEL_DB_BUSY                = 0x00000003,
15739 GRBM_SE3_PERF_SEL_SC_BUSY                = 0x00000004,
15740 GRBM_SE3_PERF_SEL_RESERVED_1             = 0x00000005,
15741 GRBM_SE3_PERF_SEL_SPI_BUSY               = 0x00000006,
15742 GRBM_SE3_PERF_SEL_SX_BUSY                = 0x00000007,
15743 GRBM_SE3_PERF_SEL_TA_BUSY                = 0x00000008,
15744 GRBM_SE3_PERF_SEL_CB_CLEAN               = 0x00000009,
15745 GRBM_SE3_PERF_SEL_DB_CLEAN               = 0x0000000a,
15746 GRBM_SE3_PERF_SEL_RESERVED_0             = 0x0000000b,
15747 GRBM_SE3_PERF_SEL_PA_BUSY                = 0x0000000c,
15748 GRBM_SE3_PERF_SEL_RESERVED_2             = 0x0000000d,
15749 GRBM_SE3_PERF_SEL_BCI_BUSY               = 0x0000000e,
15750 GRBM_SE3_PERF_SEL_RMI_BUSY               = 0x0000000f,
15751 GRBM_SE3_PERF_SEL_UTCL1_BUSY             = 0x00000010,
15752 GRBM_SE3_PERF_SEL_TCP_BUSY               = 0x00000011,
15753 GRBM_SE3_PERF_SEL_GL1CC_BUSY             = 0x00000012,
15754 } GRBM_SE3_PERF_SEL;
15755 
15756 /*******************************************************
15757  * CP Enums
15758  *******************************************************/
15759 
15760 /*
15761  * CP_RING_ID enum
15762  */
15763 
15764 typedef enum CP_RING_ID {
15765 RINGID0                                  = 0x00000000,
15766 RINGID1                                  = 0x00000001,
15767 RINGID2                                  = 0x00000002,
15768 RINGID3                                  = 0x00000003,
15769 } CP_RING_ID;
15770 
15771 /*
15772  * CP_PIPE_ID enum
15773  */
15774 
15775 typedef enum CP_PIPE_ID {
15776 PIPE_ID0                                 = 0x00000000,
15777 PIPE_ID1                                 = 0x00000001,
15778 PIPE_ID2                                 = 0x00000002,
15779 PIPE_ID3                                 = 0x00000003,
15780 } CP_PIPE_ID;
15781 
15782 /*
15783  * CP_ME_ID enum
15784  */
15785 
15786 typedef enum CP_ME_ID {
15787 ME_ID0                                   = 0x00000000,
15788 ME_ID1                                   = 0x00000001,
15789 ME_ID2                                   = 0x00000002,
15790 ME_ID3                                   = 0x00000003,
15791 } CP_ME_ID;
15792 
15793 /*
15794  * SPM_PERFMON_STATE enum
15795  */
15796 
15797 typedef enum SPM_PERFMON_STATE {
15798 STRM_PERFMON_STATE_DISABLE_AND_RESET     = 0x00000000,
15799 STRM_PERFMON_STATE_START_COUNTING        = 0x00000001,
15800 STRM_PERFMON_STATE_STOP_COUNTING         = 0x00000002,
15801 STRM_PERFMON_STATE_RESERVED_3            = 0x00000003,
15802 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM  = 0x00000004,
15803 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
15804 } SPM_PERFMON_STATE;
15805 
15806 /*
15807  * CP_PERFMON_STATE enum
15808  */
15809 
15810 typedef enum CP_PERFMON_STATE {
15811 CP_PERFMON_STATE_DISABLE_AND_RESET       = 0x00000000,
15812 CP_PERFMON_STATE_START_COUNTING          = 0x00000001,
15813 CP_PERFMON_STATE_STOP_COUNTING           = 0x00000002,
15814 CP_PERFMON_STATE_RESERVED_3              = 0x00000003,
15815 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM  = 0x00000004,
15816 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
15817 } CP_PERFMON_STATE;
15818 
15819 /*
15820  * CP_PERFMON_ENABLE_MODE enum
15821  */
15822 
15823 typedef enum CP_PERFMON_ENABLE_MODE {
15824 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT      = 0x00000000,
15825 CP_PERFMON_ENABLE_MODE_RESERVED_1        = 0x00000001,
15826 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE  = 0x00000002,
15827 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE  = 0x00000003,
15828 } CP_PERFMON_ENABLE_MODE;
15829 
15830 /*
15831  * CPG_PERFCOUNT_SEL enum
15832  */
15833 
15834 typedef enum CPG_PERFCOUNT_SEL {
15835 CPG_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
15836 CPG_PERF_SEL_RBIU_FIFO_FULL              = 0x00000001,
15837 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR     = 0x00000002,
15838 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL  = 0x00000003,
15839 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT         = 0x00000004,
15840 CPG_PERF_SEL_ME_PARSER_BUSY              = 0x00000005,
15841 CPG_PERF_SEL_COUNT_TYPE0_PACKETS         = 0x00000006,
15842 CPG_PERF_SEL_COUNT_TYPE3_PACKETS         = 0x00000007,
15843 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x00000008,
15844 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS      = 0x00000009,
15845 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS  = 0x0000000a,
15846 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS  = 0x0000000b,
15847 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ     = 0x0000000c,
15848 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ    = 0x0000000d,
15849 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX  = 0x0000000e,
15850 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS  = 0x0000000f,
15851 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE  = 0x00000010,
15852 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM  = 0x00000011,
15853 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY    = 0x00000012,
15854 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY    = 0x00000013,
15855 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY   = 0x00000014,
15856 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ  = 0x00000015,
15857 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP  = 0x00000016,
15858 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ  = 0x00000017,
15859 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX  = 0x00000018,
15860 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU  = 0x00000019,
15861 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS  = 0x0000001a,
15862 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH  = 0x0000001b,
15863 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER       = 0x0000001c,
15864 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER     = 0x0000001d,
15865 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS  = 0x0000001e,
15866 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY  = 0x0000001f,
15867 CPG_PERF_SEL_DYNAMIC_CLK_VALID           = 0x00000020,
15868 CPG_PERF_SEL_REGISTER_CLK_VALID          = 0x00000021,
15869 CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT      = 0x00000022,
15870 CPG_PERF_SEL_GUS_READ_REQUEST_SENT       = 0x00000023,
15871 CPG_PERF_SEL_CE_STALL_RAM_DUMP           = 0x00000024,
15872 CPG_PERF_SEL_CE_STALL_RAM_WRITE          = 0x00000025,
15873 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO        = 0x00000026,
15874 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO     = 0x00000027,
15875 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU   = 0x00000028,
15876 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ   = 0x00000029,
15877 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG  = 0x0000002a,
15878 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER      = 0x0000002b,
15879 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x0000002c,
15880 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS     = 0x0000002d,
15881 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x0000002e,
15882 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x0000002f,
15883 CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000030,
15884 CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT     = 0x00000031,
15885 CPG_PERF_SEL_TCIU_READ_REQUEST_SENT      = 0x00000032,
15886 CPG_PERF_SEL_CPG_STAT_BUSY               = 0x00000033,
15887 CPG_PERF_SEL_CPG_STAT_IDLE               = 0x00000034,
15888 CPG_PERF_SEL_CPG_STAT_STALL              = 0x00000035,
15889 CPG_PERF_SEL_CPG_TCIU_BUSY               = 0x00000036,
15890 CPG_PERF_SEL_CPG_TCIU_IDLE               = 0x00000037,
15891 CPF_PERF_SEL_CPG_TCIU_STALL              = 0x00000038,
15892 CPG_PERF_SEL_CPG_UTCL2IU_BUSY            = 0x00000039,
15893 CPG_PERF_SEL_CPG_UTCL2IU_IDLE            = 0x0000003a,
15894 CPG_PERF_SEL_CPG_UTCL2IU_STALL           = 0x0000003b,
15895 CPG_PERF_SEL_CPG_GCRIU_BUSY              = 0x0000003c,
15896 CPG_PERF_SEL_CPG_GCRIU_IDLE              = 0x0000003d,
15897 CPG_PERF_SEL_CPG_GCRIU_STALL             = 0x0000003e,
15898 CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE    = 0x0000003f,
15899 CPG_PERF_SEL_ALL_GFX_PIPES_BUSY          = 0x00000040,
15900 CPG_PERF_SEL_CPG_UTCL2IU_XACK            = 0x00000041,
15901 CPG_PERF_SEL_CPG_UTCL2IU_XNACK           = 0x00000042,
15902 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY  = 0x00000043,
15903 CPG_PERF_SEL_PFP_INSTR_CACHE_HIT         = 0x00000044,
15904 CPG_PERF_SEL_PFP_INSTR_CACHE_MISS        = 0x00000045,
15905 CPG_PERF_SEL_CE_INSTR_CACHE_HIT          = 0x00000046,
15906 CPG_PERF_SEL_CE_INSTR_CACHE_MISS         = 0x00000047,
15907 CPG_PERF_SEL_ME_INSTR_CACHE_HIT          = 0x00000048,
15908 CPG_PERF_SEL_ME_INSTR_CACHE_MISS         = 0x00000049,
15909 CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1   = 0x0000004a,
15910 CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1  = 0x0000004b,
15911 CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2   = 0x0000004c,
15912 CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2  = 0x0000004d,
15913 } CPG_PERFCOUNT_SEL;
15914 
15915 /*
15916  * CPF_PERFCOUNT_SEL enum
15917  */
15918 
15919 typedef enum CPF_PERFCOUNT_SEL {
15920 CPF_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
15921 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE  = 0x00000001,
15922 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE  = 0x00000002,
15923 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS  = 0x00000003,
15924 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING  = 0x00000004,
15925 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1   = 0x00000005,
15926 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2   = 0x00000006,
15927 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE  = 0x00000007,
15928 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS  = 0x00000008,
15929 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR         = 0x00000009,
15930 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR      = 0x0000000a,
15931 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x0000000b,
15932 CPF_PERF_SEL_GRBM_DWORDS_SENT            = 0x0000000c,
15933 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID         = 0x0000000d,
15934 CPF_PERF_SEL_REGISTER_CLOCK_VALID        = 0x0000000e,
15935 CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND      = 0x0000000f,
15936 CPF_PERF_SEL_GUS_READ_REQUEST_SEND       = 0x00000010,
15937 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000011,
15938 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000012,
15939 CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION  = 0x00000013,
15940 CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION  = 0x00000014,
15941 CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000015,
15942 CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT     = 0x00000016,
15943 CPF_PERF_SEL_TCIU_READ_REQUEST_SENT      = 0x00000017,
15944 CPF_PERF_SEL_CPF_STAT_BUSY               = 0x00000018,
15945 CPF_PERF_SEL_CPF_STAT_IDLE               = 0x00000019,
15946 CPF_PERF_SEL_CPF_STAT_STALL              = 0x0000001a,
15947 CPF_PERF_SEL_CPF_TCIU_BUSY               = 0x0000001b,
15948 CPF_PERF_SEL_CPF_TCIU_IDLE               = 0x0000001c,
15949 CPF_PERF_SEL_CPF_TCIU_STALL              = 0x0000001d,
15950 CPF_PERF_SEL_CPF_UTCL2IU_BUSY            = 0x0000001e,
15951 CPF_PERF_SEL_CPF_UTCL2IU_IDLE            = 0x0000001f,
15952 CPF_PERF_SEL_CPF_UTCL2IU_STALL           = 0x00000020,
15953 CPF_PERF_SEL_CPF_GCRIU_BUSY              = 0x00000021,
15954 CPF_PERF_SEL_CPF_GCRIU_IDLE              = 0x00000022,
15955 CPF_PERF_SEL_CPF_GCRIU_STALL             = 0x00000023,
15956 CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE    = 0x00000024,
15957 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB    = 0x00000025,
15958 CPF_PERF_SEL_CPF_UTCL2IU_XACK            = 0x00000026,
15959 CPF_PERF_SEL_CPF_UTCL2IU_XNACK           = 0x00000027,
15960 } CPF_PERFCOUNT_SEL;
15961 
15962 /*
15963  * CPC_PERFCOUNT_SEL enum
15964  */
15965 
15966 typedef enum CPC_PERFCOUNT_SEL {
15967 CPC_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
15968 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000001,
15969 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION   = 0x00000002,
15970 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE     = 0x00000003,
15971 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE     = 0x00000004,
15972 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x00000005,
15973 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY  = 0x00000006,
15974 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF  = 0x00000007,
15975 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ  = 0x00000008,
15976 CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ  = 0x00000009,
15977 CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE  = 0x0000000a,
15978 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ  = 0x0000000b,
15979 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF  = 0x0000000c,
15980 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE  = 0x0000000d,
15981 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY  = 0x0000000e,
15982 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF  = 0x0000000f,
15983 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ  = 0x00000010,
15984 CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ  = 0x00000011,
15985 CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE  = 0x00000012,
15986 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ  = 0x00000013,
15987 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF  = 0x00000014,
15988 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE  = 0x00000015,
15989 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000016,
15990 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000017,
15991 CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000018,
15992 CPC_PERF_SEL_CPC_STAT_BUSY               = 0x00000019,
15993 CPC_PERF_SEL_CPC_STAT_IDLE               = 0x0000001a,
15994 CPC_PERF_SEL_CPC_STAT_STALL              = 0x0000001b,
15995 CPC_PERF_SEL_CPC_TCIU_BUSY               = 0x0000001c,
15996 CPC_PERF_SEL_CPC_TCIU_IDLE               = 0x0000001d,
15997 CPC_PERF_SEL_CPC_UTCL2IU_BUSY            = 0x0000001e,
15998 CPC_PERF_SEL_CPC_UTCL2IU_IDLE            = 0x0000001f,
15999 CPC_PERF_SEL_CPC_UTCL2IU_STALL           = 0x00000020,
16000 CPC_PERF_SEL_ME1_DC0_SPI_BUSY            = 0x00000021,
16001 CPC_PERF_SEL_ME2_DC1_SPI_BUSY            = 0x00000022,
16002 CPC_PERF_SEL_CPC_GCRIU_BUSY              = 0x00000023,
16003 CPC_PERF_SEL_CPC_GCRIU_IDLE              = 0x00000024,
16004 CPC_PERF_SEL_CPC_GCRIU_STALL             = 0x00000025,
16005 CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE    = 0x00000026,
16006 CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ  = 0x00000027,
16007 CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ  = 0x00000028,
16008 CPC_PERF_SEL_CPC_UTCL2IU_XACK            = 0x00000029,
16009 CPC_PERF_SEL_CPC_UTCL2IU_XNACK           = 0x0000002a,
16010 CPC_PERF_SEL_MEC_INSTR_CACHE_HIT         = 0x0000002b,
16011 CPC_PERF_SEL_MEC_INSTR_CACHE_MISS        = 0x0000002c,
16012 } CPC_PERFCOUNT_SEL;
16013 
16014 /*
16015  * CP_ALPHA_TAG_RAM_SEL enum
16016  */
16017 
16018 typedef enum CP_ALPHA_TAG_RAM_SEL {
16019 CPG_TAG_RAM                              = 0x00000000,
16020 CPC_TAG_RAM                              = 0x00000001,
16021 CPF_TAG_RAM                              = 0x00000002,
16022 RSV_TAG_RAM                              = 0x00000003,
16023 } CP_ALPHA_TAG_RAM_SEL;
16024 
16025 /*
16026  * CPF_PERFCOUNTWINDOW_SEL enum
16027  */
16028 
16029 typedef enum CPF_PERFCOUNTWINDOW_SEL {
16030 CPF_PERFWINDOW_SEL_CSF                   = 0x00000000,
16031 CPF_PERFWINDOW_SEL_HQD1                  = 0x00000001,
16032 CPF_PERFWINDOW_SEL_HQD2                  = 0x00000002,
16033 CPF_PERFWINDOW_SEL_RDMA                  = 0x00000003,
16034 CPF_PERFWINDOW_SEL_RWPP                  = 0x00000004,
16035 } CPF_PERFCOUNTWINDOW_SEL;
16036 
16037 /*
16038  * CPG_PERFCOUNTWINDOW_SEL enum
16039  */
16040 
16041 typedef enum CPG_PERFCOUNTWINDOW_SEL {
16042 CPG_PERFWINDOW_SEL_PFP                   = 0x00000000,
16043 CPG_PERFWINDOW_SEL_ME                    = 0x00000001,
16044 CPG_PERFWINDOW_SEL_CE                    = 0x00000002,
16045 CPG_PERFWINDOW_SEL_MES                   = 0x00000003,
16046 CPG_PERFWINDOW_SEL_MEC1                  = 0x00000004,
16047 CPG_PERFWINDOW_SEL_MEC2                  = 0x00000005,
16048 CPG_PERFWINDOW_SEL_DFY                   = 0x00000006,
16049 CPG_PERFWINDOW_SEL_DMA                   = 0x00000007,
16050 CPG_PERFWINDOW_SEL_SHADOW                = 0x00000008,
16051 CPG_PERFWINDOW_SEL_RB                    = 0x00000009,
16052 CPG_PERFWINDOW_SEL_CEDMA                 = 0x0000000a,
16053 CPG_PERFWINDOW_SEL_PRT_HDR_RPTR          = 0x0000000b,
16054 CPG_PERFWINDOW_SEL_PRT_SMP_RPTR          = 0x0000000c,
16055 CPG_PERFWINDOW_SEL_PQ1                   = 0x0000000d,
16056 CPG_PERFWINDOW_SEL_PQ2                   = 0x0000000e,
16057 CPG_PERFWINDOW_SEL_PQ3                   = 0x0000000f,
16058 CPG_PERFWINDOW_SEL_MEMWR                 = 0x00000010,
16059 CPG_PERFWINDOW_SEL_MEMRD                 = 0x00000011,
16060 CPG_PERFWINDOW_SEL_VGT0                  = 0x00000012,
16061 CPG_PERFWINDOW_SEL_VGT1                  = 0x00000013,
16062 CPG_PERFWINDOW_SEL_APPEND                = 0x00000014,
16063 CPG_PERFWINDOW_SEL_QURD                  = 0x00000015,
16064 CPG_PERFWINDOW_SEL_DDID                  = 0x00000016,
16065 CPG_PERFWINDOW_SEL_SR                    = 0x00000017,
16066 CPG_PERFWINDOW_SEL_QU_EOP                = 0x00000018,
16067 CPG_PERFWINDOW_SEL_QU_STRM               = 0x00000019,
16068 CPG_PERFWINDOW_SEL_QU_PIPE               = 0x0000001a,
16069 CPG_PERFWINDOW_SEL_RESERVED1             = 0x0000001b,
16070 CPG_PERFWINDOW_SEL_CPC_IC                = 0x0000001c,
16071 CPG_PERFWINDOW_SEL_RESERVED2             = 0x0000001d,
16072 CPG_PERFWINDOW_SEL_CPG_IC                = 0x0000001e,
16073 } CPG_PERFCOUNTWINDOW_SEL;
16074 
16075 /*
16076  * CPF_LATENCY_STATS_SEL enum
16077  */
16078 
16079 typedef enum CPF_LATENCY_STATS_SEL {
16080 CPF_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
16081 CPF_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
16082 CPF_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
16083 CPF_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
16084 CPF_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
16085 CPF_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
16086 CPF_LATENCY_STATS_SEL_READ_MAX           = 0x00000006,
16087 CPF_LATENCY_STATS_SEL_READ_MIN           = 0x00000007,
16088 CPF_LATENCY_STATS_SEL_READ_LAST          = 0x00000008,
16089 CPF_LATENCY_STATS_SEL_INVAL_MAX          = 0x00000009,
16090 CPF_LATENCY_STATS_SEL_INVAL_MIN          = 0x0000000a,
16091 CPF_LATENCY_STATS_SEL_INVAL_LAST         = 0x0000000b,
16092 } CPF_LATENCY_STATS_SEL;
16093 
16094 /*
16095  * CPG_LATENCY_STATS_SEL enum
16096  */
16097 
16098 typedef enum CPG_LATENCY_STATS_SEL {
16099 CPG_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
16100 CPG_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
16101 CPG_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
16102 CPG_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
16103 CPG_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
16104 CPG_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
16105 CPG_LATENCY_STATS_SEL_WRITE_MAX          = 0x00000006,
16106 CPG_LATENCY_STATS_SEL_WRITE_MIN          = 0x00000007,
16107 CPG_LATENCY_STATS_SEL_WRITE_LAST         = 0x00000008,
16108 CPG_LATENCY_STATS_SEL_READ_MAX           = 0x00000009,
16109 CPG_LATENCY_STATS_SEL_READ_MIN           = 0x0000000a,
16110 CPG_LATENCY_STATS_SEL_READ_LAST          = 0x0000000b,
16111 CPG_LATENCY_STATS_SEL_ATOMIC_MAX         = 0x0000000c,
16112 CPG_LATENCY_STATS_SEL_ATOMIC_MIN         = 0x0000000d,
16113 CPG_LATENCY_STATS_SEL_ATOMIC_LAST        = 0x0000000e,
16114 CPG_LATENCY_STATS_SEL_INVAL_MAX          = 0x0000000f,
16115 CPG_LATENCY_STATS_SEL_INVAL_MIN          = 0x00000010,
16116 CPG_LATENCY_STATS_SEL_INVAL_LAST         = 0x00000011,
16117 } CPG_LATENCY_STATS_SEL;
16118 
16119 /*
16120  * CPC_LATENCY_STATS_SEL enum
16121  */
16122 
16123 typedef enum CPC_LATENCY_STATS_SEL {
16124 CPC_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
16125 CPC_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
16126 CPC_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
16127 CPC_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
16128 CPC_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
16129 CPC_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
16130 CPC_LATENCY_STATS_SEL_INVAL_MAX          = 0x00000006,
16131 CPC_LATENCY_STATS_SEL_INVAL_MIN          = 0x00000007,
16132 CPC_LATENCY_STATS_SEL_INVAL_LAST         = 0x00000008,
16133 } CPC_LATENCY_STATS_SEL;
16134 
16135 /*
16136  * CP_DDID_CNTL_MODE enum
16137  */
16138 
16139 typedef enum CP_DDID_CNTL_MODE {
16140 STALL                                    = 0x00000000,
16141 OVERRUN                                  = 0x00000001,
16142 } CP_DDID_CNTL_MODE;
16143 
16144 /*
16145  * CP_DDID_CNTL_SIZE enum
16146  */
16147 
16148 typedef enum CP_DDID_CNTL_SIZE {
16149 SIZE_8K                                  = 0x00000000,
16150 SIZE_16K                                 = 0x00000001,
16151 } CP_DDID_CNTL_SIZE;
16152 
16153 /*
16154  * CP_DDID_CNTL_VMID_SEL enum
16155  */
16156 
16157 typedef enum CP_DDID_CNTL_VMID_SEL {
16158 DDID_VMID_PIPE                           = 0x00000000,
16159 DDID_VMID_CNTL                           = 0x00000001,
16160 } CP_DDID_CNTL_VMID_SEL;
16161 
16162 /*
16163  * SEM_RESPONSE value
16164  */
16165 
16166 #define SEM_ECC_ERROR                  0x00000000
16167 #define SEM_TRANS_ERROR                0x00000001
16168 #define SEM_RESP_FAILED                0x00000002
16169 #define SEM_RESP_PASSED                0x00000003
16170 
16171 /*
16172  * IQ_RETRY_TYPE value
16173  */
16174 
16175 #define IQ_QUEUE_SLEEP                 0x00000000
16176 #define IQ_OFFLOAD_RETRY               0x00000001
16177 #define IQ_SCH_WAVE_MSG                0x00000002
16178 #define IQ_SEM_REARM                   0x00000003
16179 #define IQ_DEQUEUE_RETRY               0x00000004
16180 
16181 /*
16182  * IQ_INTR_TYPE value
16183  */
16184 
16185 #define IQ_INTR_TYPE_PQ                0x00000000
16186 #define IQ_INTR_TYPE_IB                0x00000001
16187 #define IQ_INTR_TYPE_MQD               0x00000002
16188 
16189 /*
16190  * VMID_SIZE value
16191  */
16192 
16193 #define VMID_SZ                        0x00000004
16194 
16195 /*
16196  * CONFIG_SPACE value
16197  */
16198 
16199 #define CONFIG_SPACE_START             0x00002000
16200 #define CONFIG_SPACE_END               0x00009fff
16201 
16202 /*
16203  * CONFIG_SPACE1 value
16204  */
16205 
16206 #define CONFIG_SPACE1_START            0x00002000
16207 #define CONFIG_SPACE1_END              0x00002bff
16208 
16209 /*
16210  * CONFIG_SPACE2 value
16211  */
16212 
16213 #define CONFIG_SPACE2_START            0x00003000
16214 #define CONFIG_SPACE2_END              0x00009fff
16215 
16216 /*
16217  * UCONFIG_SPACE value
16218  */
16219 
16220 #define UCONFIG_SPACE_START            0x0000c000
16221 #define UCONFIG_SPACE_END              0x0000ffff
16222 
16223 /*
16224  * PERSISTENT_SPACE value
16225  */
16226 
16227 #define PERSISTENT_SPACE_START         0x00002c00
16228 #define PERSISTENT_SPACE_END           0x00002fff
16229 
16230 /*
16231  * CONTEXT_SPACE value
16232  */
16233 
16234 #define CONTEXT_SPACE_START            0x0000a000
16235 #define CONTEXT_SPACE_END              0x0000bfff
16236 
16237 /*******************************************************
16238  * SX Enums
16239  *******************************************************/
16240 
16241 /*
16242  * SX_BLEND_OPT enum
16243  */
16244 
16245 typedef enum SX_BLEND_OPT {
16246 BLEND_OPT_PRESERVE_NONE_IGNORE_ALL       = 0x00000000,
16247 BLEND_OPT_PRESERVE_ALL_IGNORE_NONE       = 0x00000001,
16248 BLEND_OPT_PRESERVE_C1_IGNORE_C0          = 0x00000002,
16249 BLEND_OPT_PRESERVE_C0_IGNORE_C1          = 0x00000003,
16250 BLEND_OPT_PRESERVE_A1_IGNORE_A0          = 0x00000004,
16251 BLEND_OPT_PRESERVE_A0_IGNORE_A1          = 0x00000005,
16252 BLEND_OPT_PRESERVE_NONE_IGNORE_A0        = 0x00000006,
16253 BLEND_OPT_PRESERVE_NONE_IGNORE_NONE      = 0x00000007,
16254 } SX_BLEND_OPT;
16255 
16256 /*
16257  * SX_OPT_COMB_FCN enum
16258  */
16259 
16260 typedef enum SX_OPT_COMB_FCN {
16261 OPT_COMB_NONE                            = 0x00000000,
16262 OPT_COMB_ADD                             = 0x00000001,
16263 OPT_COMB_SUBTRACT                        = 0x00000002,
16264 OPT_COMB_MIN                             = 0x00000003,
16265 OPT_COMB_MAX                             = 0x00000004,
16266 OPT_COMB_REVSUBTRACT                     = 0x00000005,
16267 OPT_COMB_BLEND_DISABLED                  = 0x00000006,
16268 OPT_COMB_SAFE_ADD                        = 0x00000007,
16269 } SX_OPT_COMB_FCN;
16270 
16271 /*
16272  * SX_DOWNCONVERT_FORMAT enum
16273  */
16274 
16275 typedef enum SX_DOWNCONVERT_FORMAT {
16276 SX_RT_EXPORT_NO_CONVERSION               = 0x00000000,
16277 SX_RT_EXPORT_32_R                        = 0x00000001,
16278 SX_RT_EXPORT_32_A                        = 0x00000002,
16279 SX_RT_EXPORT_10_11_11                    = 0x00000003,
16280 SX_RT_EXPORT_2_10_10_10                  = 0x00000004,
16281 SX_RT_EXPORT_8_8_8_8                     = 0x00000005,
16282 SX_RT_EXPORT_5_6_5                       = 0x00000006,
16283 SX_RT_EXPORT_1_5_5_5                     = 0x00000007,
16284 SX_RT_EXPORT_4_4_4_4                     = 0x00000008,
16285 SX_RT_EXPORT_16_16_GR                    = 0x00000009,
16286 SX_RT_EXPORT_16_16_AR                    = 0x0000000a,
16287 } SX_DOWNCONVERT_FORMAT;
16288 
16289 /*
16290  * SX_PERFCOUNTER_VALS enum
16291  */
16292 
16293 typedef enum SX_PERFCOUNTER_VALS {
16294 SX_PERF_SEL_PA_IDLE_CYCLES               = 0x00000000,
16295 SX_PERF_SEL_PA_REQ                       = 0x00000001,
16296 SX_PERF_SEL_PA_POS                       = 0x00000002,
16297 SX_PERF_SEL_CLOCK                        = 0x00000003,
16298 SX_PERF_SEL_GATE_EN1                     = 0x00000004,
16299 SX_PERF_SEL_GATE_EN2                     = 0x00000005,
16300 SX_PERF_SEL_GATE_EN3                     = 0x00000006,
16301 SX_PERF_SEL_GATE_EN4                     = 0x00000007,
16302 SX_PERF_SEL_SH_POS_STARVE                = 0x00000008,
16303 SX_PERF_SEL_SH_COLOR_STARVE              = 0x00000009,
16304 SX_PERF_SEL_SH_POS_STALL                 = 0x0000000a,
16305 SX_PERF_SEL_SH_COLOR_STALL               = 0x0000000b,
16306 SX_PERF_SEL_DB0_PIXELS                   = 0x0000000c,
16307 SX_PERF_SEL_DB0_HALF_QUADS               = 0x0000000d,
16308 SX_PERF_SEL_DB0_PIXEL_STALL              = 0x0000000e,
16309 SX_PERF_SEL_DB0_PIXEL_IDLE               = 0x0000000f,
16310 SX_PERF_SEL_DB0_PRED_PIXELS              = 0x00000010,
16311 SX_PERF_SEL_DB1_PIXELS                   = 0x00000011,
16312 SX_PERF_SEL_DB1_HALF_QUADS               = 0x00000012,
16313 SX_PERF_SEL_DB1_PIXEL_STALL              = 0x00000013,
16314 SX_PERF_SEL_DB1_PIXEL_IDLE               = 0x00000014,
16315 SX_PERF_SEL_DB1_PRED_PIXELS              = 0x00000015,
16316 SX_PERF_SEL_DB2_PIXELS                   = 0x00000016,
16317 SX_PERF_SEL_DB2_HALF_QUADS               = 0x00000017,
16318 SX_PERF_SEL_DB2_PIXEL_STALL              = 0x00000018,
16319 SX_PERF_SEL_DB2_PIXEL_IDLE               = 0x00000019,
16320 SX_PERF_SEL_DB2_PRED_PIXELS              = 0x0000001a,
16321 SX_PERF_SEL_DB3_PIXELS                   = 0x0000001b,
16322 SX_PERF_SEL_DB3_HALF_QUADS               = 0x0000001c,
16323 SX_PERF_SEL_DB3_PIXEL_STALL              = 0x0000001d,
16324 SX_PERF_SEL_DB3_PIXEL_IDLE               = 0x0000001e,
16325 SX_PERF_SEL_DB3_PRED_PIXELS              = 0x0000001f,
16326 SX_PERF_SEL_COL_BUSY                     = 0x00000020,
16327 SX_PERF_SEL_POS_BUSY                     = 0x00000021,
16328 SX_PERF_SEL_DB0_A2M_DISCARD_QUADS        = 0x00000022,
16329 SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS        = 0x00000023,
16330 SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST        = 0x00000024,
16331 SX_PERF_SEL_DB0_MRT0_DISCARD_SRC         = 0x00000025,
16332 SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS        = 0x00000026,
16333 SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS        = 0x00000027,
16334 SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS        = 0x00000028,
16335 SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST        = 0x00000029,
16336 SX_PERF_SEL_DB0_MRT1_DISCARD_SRC         = 0x0000002a,
16337 SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS        = 0x0000002b,
16338 SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS        = 0x0000002c,
16339 SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS        = 0x0000002d,
16340 SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST        = 0x0000002e,
16341 SX_PERF_SEL_DB0_MRT2_DISCARD_SRC         = 0x0000002f,
16342 SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS        = 0x00000030,
16343 SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS        = 0x00000031,
16344 SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS        = 0x00000032,
16345 SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST        = 0x00000033,
16346 SX_PERF_SEL_DB0_MRT3_DISCARD_SRC         = 0x00000034,
16347 SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS        = 0x00000035,
16348 SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS        = 0x00000036,
16349 SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS        = 0x00000037,
16350 SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST        = 0x00000038,
16351 SX_PERF_SEL_DB0_MRT4_DISCARD_SRC         = 0x00000039,
16352 SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS        = 0x0000003a,
16353 SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS        = 0x0000003b,
16354 SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS        = 0x0000003c,
16355 SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST        = 0x0000003d,
16356 SX_PERF_SEL_DB0_MRT5_DISCARD_SRC         = 0x0000003e,
16357 SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS        = 0x0000003f,
16358 SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS        = 0x00000040,
16359 SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS        = 0x00000041,
16360 SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST        = 0x00000042,
16361 SX_PERF_SEL_DB0_MRT6_DISCARD_SRC         = 0x00000043,
16362 SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS        = 0x00000044,
16363 SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS        = 0x00000045,
16364 SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS        = 0x00000046,
16365 SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST        = 0x00000047,
16366 SX_PERF_SEL_DB0_MRT7_DISCARD_SRC         = 0x00000048,
16367 SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS        = 0x00000049,
16368 SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS        = 0x0000004a,
16369 SX_PERF_SEL_DB1_A2M_DISCARD_QUADS        = 0x0000004b,
16370 SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS        = 0x0000004c,
16371 SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST        = 0x0000004d,
16372 SX_PERF_SEL_DB1_MRT0_DISCARD_SRC         = 0x0000004e,
16373 SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS        = 0x0000004f,
16374 SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS        = 0x00000050,
16375 SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS        = 0x00000051,
16376 SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST        = 0x00000052,
16377 SX_PERF_SEL_DB1_MRT1_DISCARD_SRC         = 0x00000053,
16378 SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS        = 0x00000054,
16379 SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS        = 0x00000055,
16380 SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS        = 0x00000056,
16381 SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST        = 0x00000057,
16382 SX_PERF_SEL_DB1_MRT2_DISCARD_SRC         = 0x00000058,
16383 SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS        = 0x00000059,
16384 SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS        = 0x0000005a,
16385 SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS        = 0x0000005b,
16386 SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST        = 0x0000005c,
16387 SX_PERF_SEL_DB1_MRT3_DISCARD_SRC         = 0x0000005d,
16388 SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS        = 0x0000005e,
16389 SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS        = 0x0000005f,
16390 SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS        = 0x00000060,
16391 SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST        = 0x00000061,
16392 SX_PERF_SEL_DB1_MRT4_DISCARD_SRC         = 0x00000062,
16393 SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS        = 0x00000063,
16394 SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS        = 0x00000064,
16395 SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS        = 0x00000065,
16396 SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST        = 0x00000066,
16397 SX_PERF_SEL_DB1_MRT5_DISCARD_SRC         = 0x00000067,
16398 SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS        = 0x00000068,
16399 SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS        = 0x00000069,
16400 SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS        = 0x0000006a,
16401 SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST        = 0x0000006b,
16402 SX_PERF_SEL_DB1_MRT6_DISCARD_SRC         = 0x0000006c,
16403 SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS        = 0x0000006d,
16404 SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS        = 0x0000006e,
16405 SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS        = 0x0000006f,
16406 SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST        = 0x00000070,
16407 SX_PERF_SEL_DB1_MRT7_DISCARD_SRC         = 0x00000071,
16408 SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS        = 0x00000072,
16409 SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS        = 0x00000073,
16410 SX_PERF_SEL_DB2_A2M_DISCARD_QUADS        = 0x00000074,
16411 SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS        = 0x00000075,
16412 SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST        = 0x00000076,
16413 SX_PERF_SEL_DB2_MRT0_DISCARD_SRC         = 0x00000077,
16414 SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS        = 0x00000078,
16415 SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS        = 0x00000079,
16416 SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS        = 0x0000007a,
16417 SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST        = 0x0000007b,
16418 SX_PERF_SEL_DB2_MRT1_DISCARD_SRC         = 0x0000007c,
16419 SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS        = 0x0000007d,
16420 SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS        = 0x0000007e,
16421 SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS        = 0x0000007f,
16422 SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST        = 0x00000080,
16423 SX_PERF_SEL_DB2_MRT2_DISCARD_SRC         = 0x00000081,
16424 SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS        = 0x00000082,
16425 SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS        = 0x00000083,
16426 SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS        = 0x00000084,
16427 SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST        = 0x00000085,
16428 SX_PERF_SEL_DB2_MRT3_DISCARD_SRC         = 0x00000086,
16429 SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS        = 0x00000087,
16430 SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS        = 0x00000088,
16431 SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS        = 0x00000089,
16432 SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST        = 0x0000008a,
16433 SX_PERF_SEL_DB2_MRT4_DISCARD_SRC         = 0x0000008b,
16434 SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS        = 0x0000008c,
16435 SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS        = 0x0000008d,
16436 SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS        = 0x0000008e,
16437 SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST        = 0x0000008f,
16438 SX_PERF_SEL_DB2_MRT5_DISCARD_SRC         = 0x00000090,
16439 SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS        = 0x00000091,
16440 SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS        = 0x00000092,
16441 SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS        = 0x00000093,
16442 SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST        = 0x00000094,
16443 SX_PERF_SEL_DB2_MRT6_DISCARD_SRC         = 0x00000095,
16444 SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS        = 0x00000096,
16445 SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS        = 0x00000097,
16446 SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS        = 0x00000098,
16447 SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST        = 0x00000099,
16448 SX_PERF_SEL_DB2_MRT7_DISCARD_SRC         = 0x0000009a,
16449 SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS        = 0x0000009b,
16450 SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS        = 0x0000009c,
16451 SX_PERF_SEL_DB3_A2M_DISCARD_QUADS        = 0x0000009d,
16452 SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS        = 0x0000009e,
16453 SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST        = 0x0000009f,
16454 SX_PERF_SEL_DB3_MRT0_DISCARD_SRC         = 0x000000a0,
16455 SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS        = 0x000000a1,
16456 SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS        = 0x000000a2,
16457 SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS        = 0x000000a3,
16458 SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST        = 0x000000a4,
16459 SX_PERF_SEL_DB3_MRT1_DISCARD_SRC         = 0x000000a5,
16460 SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS        = 0x000000a6,
16461 SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS        = 0x000000a7,
16462 SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS        = 0x000000a8,
16463 SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST        = 0x000000a9,
16464 SX_PERF_SEL_DB3_MRT2_DISCARD_SRC         = 0x000000aa,
16465 SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS        = 0x000000ab,
16466 SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS        = 0x000000ac,
16467 SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS        = 0x000000ad,
16468 SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST        = 0x000000ae,
16469 SX_PERF_SEL_DB3_MRT3_DISCARD_SRC         = 0x000000af,
16470 SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS        = 0x000000b0,
16471 SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS        = 0x000000b1,
16472 SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS        = 0x000000b2,
16473 SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST        = 0x000000b3,
16474 SX_PERF_SEL_DB3_MRT4_DISCARD_SRC         = 0x000000b4,
16475 SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS        = 0x000000b5,
16476 SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS        = 0x000000b6,
16477 SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS        = 0x000000b7,
16478 SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST        = 0x000000b8,
16479 SX_PERF_SEL_DB3_MRT5_DISCARD_SRC         = 0x000000b9,
16480 SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS        = 0x000000ba,
16481 SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS        = 0x000000bb,
16482 SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS        = 0x000000bc,
16483 SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST        = 0x000000bd,
16484 SX_PERF_SEL_DB3_MRT6_DISCARD_SRC         = 0x000000be,
16485 SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS        = 0x000000bf,
16486 SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS        = 0x000000c0,
16487 SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS        = 0x000000c1,
16488 SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST        = 0x000000c2,
16489 SX_PERF_SEL_DB3_MRT7_DISCARD_SRC         = 0x000000c3,
16490 SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS        = 0x000000c4,
16491 SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS        = 0x000000c5,
16492 SX_PERF_SEL_PA_REQ_LATENCY               = 0x000000c6,
16493 SX_PERF_SEL_POS_SCBD_STALL               = 0x000000c7,
16494 SX_PERF_SEL_COL_SCBD_STALL               = 0x000000c8,
16495 SX_PERF_SEL_CLOCK_DROP_STALL             = 0x000000c9,
16496 SX_PERF_SEL_GATE_EN5                     = 0x000000ca,
16497 SX_PERF_SEL_GATE_EN6                     = 0x000000cb,
16498 SX_PERF_SEL_DB0_SIZE                     = 0x000000cc,
16499 SX_PERF_SEL_DB1_SIZE                     = 0x000000cd,
16500 SX_PERF_SEL_DB2_SIZE                     = 0x000000ce,
16501 SX_PERF_SEL_DB3_SIZE                     = 0x000000cf,
16502 SX_PERF_SEL_SPLITMODE                    = 0x000000d0,
16503 SX_PERF_SEL_COL_SCBD0_STALL              = 0x000000d1,
16504 SX_PERF_SEL_COL_SCBD1_STALL              = 0x000000d2,
16505 SX_PERF_SEL_IDX_STALL_CYCLES             = 0x000000d3,
16506 SX_PERF_SEL_IDX_IDLE_CYCLES              = 0x000000d4,
16507 SX_PERF_SEL_IDX_REQ                      = 0x000000d5,
16508 SX_PERF_SEL_IDX_RET                      = 0x000000d6,
16509 SX_PERF_SEL_IDX_REQ_LATENCY              = 0x000000d7,
16510 SX_PERF_SEL_IDX_SCBD_STALL               = 0x000000d8,
16511 SX_PERF_SEL_GATE_EN7                     = 0x000000d9,
16512 SX_PERF_SEL_GATE_EN8                     = 0x000000da,
16513 SX_PERF_SEL_SH_IDX_STARVE                = 0x000000db,
16514 SX_PERF_SEL_IDX_BUSY                     = 0x000000dc,
16515 } SX_PERFCOUNTER_VALS;
16516 
16517 /*******************************************************
16518  * DB Enums
16519  *******************************************************/
16520 
16521 /*
16522  * ForceControl enum
16523  */
16524 
16525 typedef enum ForceControl {
16526 FORCE_OFF                                = 0x00000000,
16527 FORCE_ENABLE                             = 0x00000001,
16528 FORCE_DISABLE                            = 0x00000002,
16529 FORCE_RESERVED                           = 0x00000003,
16530 } ForceControl;
16531 
16532 /*
16533  * ZSamplePosition enum
16534  */
16535 
16536 typedef enum ZSamplePosition {
16537 Z_SAMPLE_CENTER                          = 0x00000000,
16538 Z_SAMPLE_CENTROID                        = 0x00000001,
16539 } ZSamplePosition;
16540 
16541 /*
16542  * ZOrder enum
16543  */
16544 
16545 typedef enum ZOrder {
16546 LATE_Z                                   = 0x00000000,
16547 EARLY_Z_THEN_LATE_Z                      = 0x00000001,
16548 RE_Z                                     = 0x00000002,
16549 EARLY_Z_THEN_RE_Z                        = 0x00000003,
16550 } ZOrder;
16551 
16552 /*
16553  * ZpassControl enum
16554  */
16555 
16556 typedef enum ZpassControl {
16557 ZPASS_DISABLE                            = 0x00000000,
16558 ZPASS_SAMPLES                            = 0x00000001,
16559 ZPASS_PIXELS                             = 0x00000002,
16560 } ZpassControl;
16561 
16562 /*
16563  * ZModeForce enum
16564  */
16565 
16566 typedef enum ZModeForce {
16567 NO_FORCE                                 = 0x00000000,
16568 FORCE_EARLY_Z                            = 0x00000001,
16569 FORCE_LATE_Z                             = 0x00000002,
16570 FORCE_RE_Z                               = 0x00000003,
16571 } ZModeForce;
16572 
16573 /*
16574  * ZLimitSumm enum
16575  */
16576 
16577 typedef enum ZLimitSumm {
16578 FORCE_SUMM_OFF                           = 0x00000000,
16579 FORCE_SUMM_MINZ                          = 0x00000001,
16580 FORCE_SUMM_MAXZ                          = 0x00000002,
16581 FORCE_SUMM_BOTH                          = 0x00000003,
16582 } ZLimitSumm;
16583 
16584 /*
16585  * CompareFrag enum
16586  */
16587 
16588 typedef enum CompareFrag {
16589 FRAG_NEVER                               = 0x00000000,
16590 FRAG_LESS                                = 0x00000001,
16591 FRAG_EQUAL                               = 0x00000002,
16592 FRAG_LEQUAL                              = 0x00000003,
16593 FRAG_GREATER                             = 0x00000004,
16594 FRAG_NOTEQUAL                            = 0x00000005,
16595 FRAG_GEQUAL                              = 0x00000006,
16596 FRAG_ALWAYS                              = 0x00000007,
16597 } CompareFrag;
16598 
16599 /*
16600  * StencilOp enum
16601  */
16602 
16603 typedef enum StencilOp {
16604 STENCIL_KEEP                             = 0x00000000,
16605 STENCIL_ZERO                             = 0x00000001,
16606 STENCIL_ONES                             = 0x00000002,
16607 STENCIL_REPLACE_TEST                     = 0x00000003,
16608 STENCIL_REPLACE_OP                       = 0x00000004,
16609 STENCIL_ADD_CLAMP                        = 0x00000005,
16610 STENCIL_SUB_CLAMP                        = 0x00000006,
16611 STENCIL_INVERT                           = 0x00000007,
16612 STENCIL_ADD_WRAP                         = 0x00000008,
16613 STENCIL_SUB_WRAP                         = 0x00000009,
16614 STENCIL_AND                              = 0x0000000a,
16615 STENCIL_OR                               = 0x0000000b,
16616 STENCIL_XOR                              = 0x0000000c,
16617 STENCIL_NAND                             = 0x0000000d,
16618 STENCIL_NOR                              = 0x0000000e,
16619 STENCIL_XNOR                             = 0x0000000f,
16620 } StencilOp;
16621 
16622 /*
16623  * ConservativeZExport enum
16624  */
16625 
16626 typedef enum ConservativeZExport {
16627 EXPORT_ANY_Z                             = 0x00000000,
16628 EXPORT_LESS_THAN_Z                       = 0x00000001,
16629 EXPORT_GREATER_THAN_Z                    = 0x00000002,
16630 EXPORT_RESERVED                          = 0x00000003,
16631 } ConservativeZExport;
16632 
16633 /*
16634  * DbPSLControl enum
16635  */
16636 
16637 typedef enum DbPSLControl {
16638 PSLC_AUTO                                = 0x00000000,
16639 PSLC_ON_HANG_ONLY                        = 0x00000001,
16640 PSLC_ASAP                                = 0x00000002,
16641 PSLC_COUNTDOWN                           = 0x00000003,
16642 } DbPSLControl;
16643 
16644 /*
16645  * DbPRTFaultBehavior enum
16646  */
16647 
16648 typedef enum DbPRTFaultBehavior {
16649 FAULT_ZERO                               = 0x00000000,
16650 FAULT_ONE                                = 0x00000001,
16651 FAULT_FAIL                               = 0x00000002,
16652 FAULT_PASS                               = 0x00000003,
16653 } DbPRTFaultBehavior;
16654 
16655 /*
16656  * PerfCounter_Vals enum
16657  */
16658 
16659 typedef enum PerfCounter_Vals {
16660 DB_PERF_SEL_SC_DB_tile_sends             = 0x00000000,
16661 DB_PERF_SEL_SC_DB_tile_busy              = 0x00000001,
16662 DB_PERF_SEL_SC_DB_tile_stalls            = 0x00000002,
16663 DB_PERF_SEL_SC_DB_tile_events            = 0x00000003,
16664 DB_PERF_SEL_SC_DB_tile_tiles             = 0x00000004,
16665 DB_PERF_SEL_SC_DB_tile_covered           = 0x00000005,
16666 DB_PERF_SEL_hiz_tc_read_starved          = 0x00000006,
16667 DB_PERF_SEL_hiz_tc_write_stall           = 0x00000007,
16668 DB_PERF_SEL_hiz_tile_culled              = 0x00000008,
16669 DB_PERF_SEL_his_tile_culled              = 0x00000009,
16670 DB_PERF_SEL_DB_SC_tile_sends             = 0x0000000a,
16671 DB_PERF_SEL_DB_SC_tile_busy              = 0x0000000b,
16672 DB_PERF_SEL_DB_SC_tile_stalls            = 0x0000000c,
16673 DB_PERF_SEL_DB_SC_tile_df_stalls         = 0x0000000d,
16674 DB_PERF_SEL_DB_SC_tile_tiles             = 0x0000000e,
16675 DB_PERF_SEL_DB_SC_tile_culled            = 0x0000000f,
16676 DB_PERF_SEL_DB_SC_tile_hier_kill         = 0x00000010,
16677 DB_PERF_SEL_DB_SC_tile_fast_ops          = 0x00000011,
16678 DB_PERF_SEL_DB_SC_tile_no_ops            = 0x00000012,
16679 DB_PERF_SEL_DB_SC_tile_tile_rate         = 0x00000013,
16680 DB_PERF_SEL_DB_SC_tile_ssaa_kill         = 0x00000014,
16681 DB_PERF_SEL_DB_SC_tile_fast_z_ops        = 0x00000015,
16682 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops  = 0x00000016,
16683 DB_PERF_SEL_SC_DB_quad_sends             = 0x00000017,
16684 DB_PERF_SEL_SC_DB_quad_busy              = 0x00000018,
16685 DB_PERF_SEL_SC_DB_quad_squads            = 0x00000019,
16686 DB_PERF_SEL_SC_DB_quad_tiles             = 0x0000001a,
16687 DB_PERF_SEL_SC_DB_quad_pixels            = 0x0000001b,
16688 DB_PERF_SEL_SC_DB_quad_killed_tiles      = 0x0000001c,
16689 DB_PERF_SEL_DB_SC_quad_sends             = 0x0000001d,
16690 DB_PERF_SEL_DB_SC_quad_busy              = 0x0000001e,
16691 DB_PERF_SEL_DB_SC_quad_stalls            = 0x0000001f,
16692 DB_PERF_SEL_DB_SC_quad_tiles             = 0x00000020,
16693 DB_PERF_SEL_DB_SC_quad_lit_quad          = 0x00000021,
16694 DB_PERF_SEL_DB_CB_tile_sends             = 0x00000022,
16695 DB_PERF_SEL_DB_CB_tile_busy              = 0x00000023,
16696 DB_PERF_SEL_DB_CB_tile_stalls            = 0x00000024,
16697 DB_PERF_SEL_SX_DB_quad_sends             = 0x00000025,
16698 DB_PERF_SEL_SX_DB_quad_busy              = 0x00000026,
16699 DB_PERF_SEL_SX_DB_quad_stalls            = 0x00000027,
16700 DB_PERF_SEL_SX_DB_quad_quads             = 0x00000028,
16701 DB_PERF_SEL_SX_DB_quad_pixels            = 0x00000029,
16702 DB_PERF_SEL_SX_DB_quad_exports           = 0x0000002a,
16703 DB_PERF_SEL_SH_quads_outstanding_sum     = 0x0000002b,
16704 DB_PERF_SEL_DB_CB_lquad_sends            = 0x0000002c,
16705 DB_PERF_SEL_DB_CB_lquad_busy             = 0x0000002d,
16706 DB_PERF_SEL_DB_CB_lquad_stalls           = 0x0000002e,
16707 DB_PERF_SEL_DB_CB_lquad_quads            = 0x0000002f,
16708 DB_PERF_SEL_tile_rd_sends                = 0x00000030,
16709 DB_PERF_SEL_mi_tile_rd_outstanding_sum   = 0x00000031,
16710 DB_PERF_SEL_quad_rd_sends                = 0x00000032,
16711 DB_PERF_SEL_quad_rd_busy                 = 0x00000033,
16712 DB_PERF_SEL_quad_rd_mi_stall             = 0x00000034,
16713 DB_PERF_SEL_quad_rd_rw_collision         = 0x00000035,
16714 DB_PERF_SEL_quad_rd_tag_stall            = 0x00000036,
16715 DB_PERF_SEL_quad_rd_32byte_reqs          = 0x00000037,
16716 DB_PERF_SEL_quad_rd_panic                = 0x00000038,
16717 DB_PERF_SEL_mi_quad_rd_outstanding_sum   = 0x00000039,
16718 DB_PERF_SEL_quad_rdret_sends             = 0x0000003a,
16719 DB_PERF_SEL_quad_rdret_busy              = 0x0000003b,
16720 DB_PERF_SEL_tile_wr_sends                = 0x0000003c,
16721 DB_PERF_SEL_tile_wr_acks                 = 0x0000003d,
16722 DB_PERF_SEL_mi_tile_wr_outstanding_sum   = 0x0000003e,
16723 DB_PERF_SEL_quad_wr_sends                = 0x0000003f,
16724 DB_PERF_SEL_quad_wr_busy                 = 0x00000040,
16725 DB_PERF_SEL_quad_wr_mi_stall             = 0x00000041,
16726 DB_PERF_SEL_quad_wr_coherency_stall      = 0x00000042,
16727 DB_PERF_SEL_quad_wr_acks                 = 0x00000043,
16728 DB_PERF_SEL_mi_quad_wr_outstanding_sum   = 0x00000044,
16729 DB_PERF_SEL_Tile_Cache_misses            = 0x00000045,
16730 DB_PERF_SEL_Tile_Cache_hits              = 0x00000046,
16731 DB_PERF_SEL_Tile_Cache_flushes           = 0x00000047,
16732 DB_PERF_SEL_Tile_Cache_surface_stall     = 0x00000048,
16733 DB_PERF_SEL_Tile_Cache_starves           = 0x00000049,
16734 DB_PERF_SEL_Tile_Cache_mem_return_starve  = 0x0000004a,
16735 DB_PERF_SEL_tcp_dispatcher_reads         = 0x0000004b,
16736 DB_PERF_SEL_tcp_prefetcher_reads         = 0x0000004c,
16737 DB_PERF_SEL_tcp_preloader_reads          = 0x0000004d,
16738 DB_PERF_SEL_tcp_dispatcher_flushes       = 0x0000004e,
16739 DB_PERF_SEL_tcp_prefetcher_flushes       = 0x0000004f,
16740 DB_PERF_SEL_tcp_preloader_flushes        = 0x00000050,
16741 DB_PERF_SEL_Depth_Tile_Cache_sends       = 0x00000051,
16742 DB_PERF_SEL_Depth_Tile_Cache_busy        = 0x00000052,
16743 DB_PERF_SEL_Depth_Tile_Cache_starves     = 0x00000053,
16744 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked  = 0x00000054,
16745 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall  = 0x00000055,
16746 DB_PERF_SEL_Depth_Tile_Cache_misses      = 0x00000056,
16747 DB_PERF_SEL_Depth_Tile_Cache_hits        = 0x00000057,
16748 DB_PERF_SEL_Depth_Tile_Cache_flushes     = 0x00000058,
16749 DB_PERF_SEL_Depth_Tile_Cache_noop_tile   = 0x00000059,
16750 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop  = 0x0000005a,
16751 DB_PERF_SEL_Depth_Tile_Cache_event       = 0x0000005b,
16752 DB_PERF_SEL_Depth_Tile_Cache_tile_frees  = 0x0000005c,
16753 DB_PERF_SEL_Depth_Tile_Cache_data_frees  = 0x0000005d,
16754 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve  = 0x0000005e,
16755 DB_PERF_SEL_Stencil_Cache_misses         = 0x0000005f,
16756 DB_PERF_SEL_Stencil_Cache_hits           = 0x00000060,
16757 DB_PERF_SEL_Stencil_Cache_flushes        = 0x00000061,
16758 DB_PERF_SEL_Stencil_Cache_starves        = 0x00000062,
16759 DB_PERF_SEL_Stencil_Cache_frees          = 0x00000063,
16760 DB_PERF_SEL_Z_Cache_separate_Z_misses    = 0x00000064,
16761 DB_PERF_SEL_Z_Cache_separate_Z_hits      = 0x00000065,
16762 DB_PERF_SEL_Z_Cache_separate_Z_flushes   = 0x00000066,
16763 DB_PERF_SEL_Z_Cache_separate_Z_starves   = 0x00000067,
16764 DB_PERF_SEL_Z_Cache_pmask_misses         = 0x00000068,
16765 DB_PERF_SEL_Z_Cache_pmask_hits           = 0x00000069,
16766 DB_PERF_SEL_Z_Cache_pmask_flushes        = 0x0000006a,
16767 DB_PERF_SEL_Z_Cache_pmask_starves        = 0x0000006b,
16768 DB_PERF_SEL_Z_Cache_frees                = 0x0000006c,
16769 DB_PERF_SEL_Plane_Cache_misses           = 0x0000006d,
16770 DB_PERF_SEL_Plane_Cache_hits             = 0x0000006e,
16771 DB_PERF_SEL_Plane_Cache_flushes          = 0x0000006f,
16772 DB_PERF_SEL_Plane_Cache_starves          = 0x00000070,
16773 DB_PERF_SEL_Plane_Cache_frees            = 0x00000071,
16774 DB_PERF_SEL_flush_expanded_stencil       = 0x00000072,
16775 DB_PERF_SEL_flush_compressed_stencil     = 0x00000073,
16776 DB_PERF_SEL_flush_single_stencil         = 0x00000074,
16777 DB_PERF_SEL_planes_flushed               = 0x00000075,
16778 DB_PERF_SEL_flush_1plane                 = 0x00000076,
16779 DB_PERF_SEL_flush_2plane                 = 0x00000077,
16780 DB_PERF_SEL_flush_3plane                 = 0x00000078,
16781 DB_PERF_SEL_flush_4plane                 = 0x00000079,
16782 DB_PERF_SEL_flush_5plane                 = 0x0000007a,
16783 DB_PERF_SEL_flush_6plane                 = 0x0000007b,
16784 DB_PERF_SEL_flush_7plane                 = 0x0000007c,
16785 DB_PERF_SEL_flush_8plane                 = 0x0000007d,
16786 DB_PERF_SEL_flush_9plane                 = 0x0000007e,
16787 DB_PERF_SEL_flush_10plane                = 0x0000007f,
16788 DB_PERF_SEL_flush_11plane                = 0x00000080,
16789 DB_PERF_SEL_flush_12plane                = 0x00000081,
16790 DB_PERF_SEL_flush_13plane                = 0x00000082,
16791 DB_PERF_SEL_flush_14plane                = 0x00000083,
16792 DB_PERF_SEL_flush_15plane                = 0x00000084,
16793 DB_PERF_SEL_flush_16plane                = 0x00000085,
16794 DB_PERF_SEL_flush_expanded_z             = 0x00000086,
16795 DB_PERF_SEL_earlyZ_waiting_for_postZ_done  = 0x00000087,
16796 DB_PERF_SEL_reZ_waiting_for_postZ_done   = 0x00000088,
16797 DB_PERF_SEL_dk_tile_sends                = 0x00000089,
16798 DB_PERF_SEL_dk_tile_busy                 = 0x0000008a,
16799 DB_PERF_SEL_dk_tile_quad_starves         = 0x0000008b,
16800 DB_PERF_SEL_dk_tile_stalls               = 0x0000008c,
16801 DB_PERF_SEL_dk_squad_sends               = 0x0000008d,
16802 DB_PERF_SEL_dk_squad_busy                = 0x0000008e,
16803 DB_PERF_SEL_dk_squad_stalls              = 0x0000008f,
16804 DB_PERF_SEL_Op_Pipe_Busy                 = 0x00000090,
16805 DB_PERF_SEL_Op_Pipe_MC_Read_stall        = 0x00000091,
16806 DB_PERF_SEL_qc_busy                      = 0x00000092,
16807 DB_PERF_SEL_qc_xfc                       = 0x00000093,
16808 DB_PERF_SEL_qc_conflicts                 = 0x00000094,
16809 DB_PERF_SEL_qc_full_stall                = 0x00000095,
16810 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ  = 0x00000096,
16811 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ  = 0x00000097,
16812 DB_PERF_SEL_tsc_insert_summarize_stall   = 0x00000098,
16813 DB_PERF_SEL_tl_busy                      = 0x00000099,
16814 DB_PERF_SEL_tl_dtc_read_starved          = 0x0000009a,
16815 DB_PERF_SEL_tl_z_fetch_stall             = 0x0000009b,
16816 DB_PERF_SEL_tl_stencil_stall             = 0x0000009c,
16817 DB_PERF_SEL_tl_z_decompress_stall        = 0x0000009d,
16818 DB_PERF_SEL_tl_stencil_locked_stall      = 0x0000009e,
16819 DB_PERF_SEL_tl_events                    = 0x0000009f,
16820 DB_PERF_SEL_tl_summarize_squads          = 0x000000a0,
16821 DB_PERF_SEL_tl_flush_expand_squads       = 0x000000a1,
16822 DB_PERF_SEL_tl_expand_squads             = 0x000000a2,
16823 DB_PERF_SEL_tl_preZ_squads               = 0x000000a3,
16824 DB_PERF_SEL_tl_postZ_squads              = 0x000000a4,
16825 DB_PERF_SEL_tl_preZ_noop_squads          = 0x000000a5,
16826 DB_PERF_SEL_tl_postZ_noop_squads         = 0x000000a6,
16827 DB_PERF_SEL_tl_tile_ops                  = 0x000000a7,
16828 DB_PERF_SEL_tl_in_xfc                    = 0x000000a8,
16829 DB_PERF_SEL_tl_in_single_stencil_expand_stall  = 0x000000a9,
16830 DB_PERF_SEL_tl_in_fast_z_stall           = 0x000000aa,
16831 DB_PERF_SEL_tl_out_xfc                   = 0x000000ab,
16832 DB_PERF_SEL_tl_out_squads                = 0x000000ac,
16833 DB_PERF_SEL_zf_plane_multicycle          = 0x000000ad,
16834 DB_PERF_SEL_PostZ_Samples_passing_Z      = 0x000000ae,
16835 DB_PERF_SEL_PostZ_Samples_failing_Z      = 0x000000af,
16836 DB_PERF_SEL_PostZ_Samples_failing_S      = 0x000000b0,
16837 DB_PERF_SEL_PreZ_Samples_passing_Z       = 0x000000b1,
16838 DB_PERF_SEL_PreZ_Samples_failing_Z       = 0x000000b2,
16839 DB_PERF_SEL_PreZ_Samples_failing_S       = 0x000000b3,
16840 DB_PERF_SEL_ts_tc_update_stall           = 0x000000b4,
16841 DB_PERF_SEL_sc_kick_start                = 0x000000b5,
16842 DB_PERF_SEL_sc_kick_end                  = 0x000000b6,
16843 DB_PERF_SEL_clock_reg_active             = 0x000000b7,
16844 DB_PERF_SEL_clock_main_active            = 0x000000b8,
16845 DB_PERF_SEL_clock_mem_export_active      = 0x000000b9,
16846 DB_PERF_SEL_esr_ps_out_busy              = 0x000000ba,
16847 DB_PERF_SEL_esr_ps_lqf_busy              = 0x000000bb,
16848 DB_PERF_SEL_esr_ps_lqf_stall             = 0x000000bc,
16849 DB_PERF_SEL_etr_out_send                 = 0x000000bd,
16850 DB_PERF_SEL_etr_out_busy                 = 0x000000be,
16851 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0x000000bf,
16852 DB_PERF_SEL_etr_out_cb_tile_stall        = 0x000000c0,
16853 DB_PERF_SEL_etr_out_esr_stall            = 0x000000c1,
16854 DB_PERF_SEL_esr_ps_sqq_busy              = 0x000000c2,
16855 DB_PERF_SEL_esr_ps_sqq_stall             = 0x000000c3,
16856 DB_PERF_SEL_esr_eot_fwd_busy             = 0x000000c4,
16857 DB_PERF_SEL_esr_eot_fwd_holding_squad    = 0x000000c5,
16858 DB_PERF_SEL_esr_eot_fwd_forward          = 0x000000c6,
16859 DB_PERF_SEL_esr_sqq_zi_busy              = 0x000000c7,
16860 DB_PERF_SEL_esr_sqq_zi_stall             = 0x000000c8,
16861 DB_PERF_SEL_postzl_sq_pt_busy            = 0x000000c9,
16862 DB_PERF_SEL_postzl_sq_pt_stall           = 0x000000ca,
16863 DB_PERF_SEL_postzl_se_busy               = 0x000000cb,
16864 DB_PERF_SEL_postzl_se_stall              = 0x000000cc,
16865 DB_PERF_SEL_postzl_partial_launch        = 0x000000cd,
16866 DB_PERF_SEL_postzl_full_launch           = 0x000000ce,
16867 DB_PERF_SEL_postzl_partial_waiting       = 0x000000cf,
16868 DB_PERF_SEL_postzl_tile_mem_stall        = 0x000000d0,
16869 DB_PERF_SEL_postzl_tile_init_stall       = 0x000000d1,
16870 DB_PERF_SEL_prezl_tile_mem_stall         = 0x000000d2,
16871 DB_PERF_SEL_prezl_tile_init_stall        = 0x000000d3,
16872 DB_PERF_SEL_dtt_sm_clash_stall           = 0x000000d4,
16873 DB_PERF_SEL_dtt_sm_slot_stall            = 0x000000d5,
16874 DB_PERF_SEL_dtt_sm_miss_stall            = 0x000000d6,
16875 DB_PERF_SEL_mi_rdreq_busy                = 0x000000d7,
16876 DB_PERF_SEL_mi_rdreq_stall               = 0x000000d8,
16877 DB_PERF_SEL_mi_wrreq_busy                = 0x000000d9,
16878 DB_PERF_SEL_mi_wrreq_stall               = 0x000000da,
16879 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop  = 0x000000db,
16880 DB_PERF_SEL_dkg_tile_rate_tile           = 0x000000dc,
16881 DB_PERF_SEL_prezl_src_in_sends           = 0x000000dd,
16882 DB_PERF_SEL_prezl_src_in_stall           = 0x000000de,
16883 DB_PERF_SEL_prezl_src_in_squads          = 0x000000df,
16884 DB_PERF_SEL_prezl_src_in_squads_unrolled  = 0x000000e0,
16885 DB_PERF_SEL_prezl_src_in_tile_rate       = 0x000000e1,
16886 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled  = 0x000000e2,
16887 DB_PERF_SEL_prezl_src_out_stall          = 0x000000e3,
16888 DB_PERF_SEL_postzl_src_in_sends          = 0x000000e4,
16889 DB_PERF_SEL_postzl_src_in_stall          = 0x000000e5,
16890 DB_PERF_SEL_postzl_src_in_squads         = 0x000000e6,
16891 DB_PERF_SEL_postzl_src_in_squads_unrolled  = 0x000000e7,
16892 DB_PERF_SEL_postzl_src_in_tile_rate      = 0x000000e8,
16893 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled  = 0x000000e9,
16894 DB_PERF_SEL_postzl_src_out_stall         = 0x000000ea,
16895 DB_PERF_SEL_esr_ps_src_in_sends          = 0x000000eb,
16896 DB_PERF_SEL_esr_ps_src_in_stall          = 0x000000ec,
16897 DB_PERF_SEL_esr_ps_src_in_squads         = 0x000000ed,
16898 DB_PERF_SEL_esr_ps_src_in_squads_unrolled  = 0x000000ee,
16899 DB_PERF_SEL_esr_ps_src_in_tile_rate      = 0x000000ef,
16900 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled  = 0x000000f0,
16901 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate  = 0x000000f1,
16902 DB_PERF_SEL_esr_ps_src_out_stall         = 0x000000f2,
16903 DB_PERF_SEL_depth_bounds_tile_culled     = 0x000000f3,
16904 DB_PERF_SEL_PreZ_Samples_failing_DB      = 0x000000f4,
16905 DB_PERF_SEL_PostZ_Samples_failing_DB     = 0x000000f5,
16906 DB_PERF_SEL_flush_compressed             = 0x000000f6,
16907 DB_PERF_SEL_flush_plane_le4              = 0x000000f7,
16908 DB_PERF_SEL_tiles_z_fully_summarized     = 0x000000f8,
16909 DB_PERF_SEL_tiles_stencil_fully_summarized  = 0x000000f9,
16910 DB_PERF_SEL_tiles_z_clear_on_expclear    = 0x000000fa,
16911 DB_PERF_SEL_tiles_s_clear_on_expclear    = 0x000000fb,
16912 DB_PERF_SEL_tiles_decomp_on_expclear     = 0x000000fc,
16913 DB_PERF_SEL_tiles_compressed_to_decompressed  = 0x000000fd,
16914 DB_PERF_SEL_Op_Pipe_Prez_Busy            = 0x000000fe,
16915 DB_PERF_SEL_Op_Pipe_Postz_Busy           = 0x000000ff,
16916 DB_PERF_SEL_di_dt_stall                  = 0x00000100,
16917 DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke  = 0x00000101,
16918 DB_PERF_SEL_DB_SC_s_tile_rate            = 0x00000102,
16919 DB_PERF_SEL_DB_SC_c_tile_rate            = 0x00000103,
16920 DB_PERF_SEL_DB_SC_z_tile_rate            = 0x00000104,
16921 Spare_261                                = 0x00000105,
16922 DB_PERF_SEL_DB_CB_lquad_export_quads     = 0x00000106,
16923 DB_PERF_SEL_DB_CB_lquad_double_format    = 0x00000107,
16924 DB_PERF_SEL_DB_CB_lquad_fast_format      = 0x00000108,
16925 DB_PERF_SEL_DB_CB_lquad_slow_format      = 0x00000109,
16926 DB_PERF_SEL_CB_DB_rdreq_sends            = 0x0000010a,
16927 DB_PERF_SEL_CB_DB_rdreq_prt_sends        = 0x0000010b,
16928 DB_PERF_SEL_CB_DB_wrreq_sends            = 0x0000010c,
16929 DB_PERF_SEL_CB_DB_wrreq_prt_sends        = 0x0000010d,
16930 DB_PERF_SEL_DB_CB_rdret_ack              = 0x0000010e,
16931 DB_PERF_SEL_DB_CB_rdret_nack             = 0x0000010f,
16932 DB_PERF_SEL_DB_CB_wrret_ack              = 0x00000110,
16933 DB_PERF_SEL_DB_CB_wrret_nack             = 0x00000111,
16934 DB_PERF_SEL_DFSM_Stall_opmode_change     = 0x00000112,
16935 DB_PERF_SEL_DFSM_Stall_cam_fifo          = 0x00000113,
16936 DB_PERF_SEL_DFSM_Stall_bypass_fifo       = 0x00000114,
16937 DB_PERF_SEL_DFSM_Stall_retained_tile_fifo  = 0x00000115,
16938 DB_PERF_SEL_DFSM_Stall_control_fifo      = 0x00000116,
16939 DB_PERF_SEL_DFSM_Stall_overflow_counter  = 0x00000117,
16940 DB_PERF_SEL_DFSM_Stall_pops_stall_overflow  = 0x00000118,
16941 DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush  = 0x00000119,
16942 DB_PERF_SEL_DFSM_Stall_middle_output     = 0x0000011a,
16943 DB_PERF_SEL_DFSM_Stall_stalling_general  = 0x0000011b,
16944 Spare_285                                = 0x0000011c,
16945 Spare_286                                = 0x0000011d,
16946 DB_PERF_SEL_DFSM_prez_killed_squad       = 0x0000011e,
16947 DB_PERF_SEL_DFSM_squads_in               = 0x0000011f,
16948 DB_PERF_SEL_DFSM_full_cleared_squads_out  = 0x00000120,
16949 DB_PERF_SEL_DFSM_quads_in                = 0x00000121,
16950 DB_PERF_SEL_DFSM_fully_cleared_quads_out  = 0x00000122,
16951 DB_PERF_SEL_DFSM_lit_pixels_in           = 0x00000123,
16952 DB_PERF_SEL_DFSM_fully_cleared_pixels_out  = 0x00000124,
16953 DB_PERF_SEL_DFSM_lit_samples_in          = 0x00000125,
16954 DB_PERF_SEL_DFSM_lit_samples_out         = 0x00000126,
16955 DB_PERF_SEL_DFSM_evicted_tiles_above_watermark  = 0x00000127,
16956 DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream  = 0x00000128,
16957 DB_PERF_SEL_DFSM_stalled_by_downstream   = 0x00000129,
16958 DB_PERF_SEL_DFSM_evicted_squads_above_watermark  = 0x0000012a,
16959 DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow  = 0x0000012b,
16960 DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO  = 0x0000012c,
16961 DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark  = 0x0000012d,
16962 DB_PERF_SEL_MI_tile_req_wrack_counter_stall  = 0x0000012e,
16963 DB_PERF_SEL_MI_quad_req_wrack_counter_stall  = 0x0000012f,
16964 DB_PERF_SEL_MI_zpc_req_wrack_counter_stall  = 0x00000130,
16965 DB_PERF_SEL_MI_psd_req_wrack_counter_stall  = 0x00000131,
16966 DB_PERF_SEL_unmapped_z_tile_culled       = 0x00000132,
16967 DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS  = 0x00000133,
16968 DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA  = 0x00000134,
16969 DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS  = 0x00000135,
16970 DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event  = 0x00000136,
16971 DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix   = 0x00000137,
16972 DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix  = 0x00000138,
16973 DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix  = 0x00000139,
16974 DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix  = 0x0000013a,
16975 DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending  = 0x0000013b,
16976 DB_PERF_SEL_DB_CB_context_dones          = 0x0000013c,
16977 DB_PERF_SEL_DB_CB_eop_dones              = 0x0000013d,
16978 DB_PERF_SEL_SX_DB_quad_all_pixels_killed  = 0x0000013e,
16979 DB_PERF_SEL_SX_DB_quad_all_pixels_enabled  = 0x0000013f,
16980 DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read  = 0x00000140,
16981 DB_PERF_SEL_SC_DB_tile_backface          = 0x00000141,
16982 DB_PERF_SEL_SC_DB_quad_quads             = 0x00000142,
16983 DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel  = 0x00000143,
16984 DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels  = 0x00000144,
16985 DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels  = 0x00000145,
16986 DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels  = 0x00000146,
16987 DB_PERF_SEL_DFSM_Flush_flushabit         = 0x00000147,
16988 DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo  = 0x00000148,
16989 DB_PERF_SEL_DFSM_Flush_flushabit_passthrough  = 0x00000149,
16990 DB_PERF_SEL_DFSM_Flush_flushabit_forceflush  = 0x0000014a,
16991 DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull  = 0x0000014b,
16992 DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark  = 0x0000014c,
16993 DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling  = 0x0000014d,
16994 DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark  = 0x0000014e,
16995 DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark  = 0x0000014f,
16996 DB_PERF_SEL_DFSM_Flush_flushall          = 0x00000150,
16997 DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush  = 0x00000151,
16998 DB_PERF_SEL_DFSM_Flush_flushall_opmodechange  = 0x00000152,
16999 DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange  = 0x00000153,
17000 DB_PERF_SEL_DFSM_Flush_flushall_watchdog  = 0x00000154,
17001 DB_PERF_SEL_DB_SC_quad_double_quad       = 0x00000155,
17002 DB_PERF_SEL_SX_DB_quad_export_quads      = 0x00000156,
17003 DB_PERF_SEL_SX_DB_quad_double_format     = 0x00000157,
17004 DB_PERF_SEL_SX_DB_quad_fast_format       = 0x00000158,
17005 DB_PERF_SEL_SX_DB_quad_slow_format       = 0x00000159,
17006 } PerfCounter_Vals;
17007 
17008 /*
17009  * RingCounterControl enum
17010  */
17011 
17012 typedef enum RingCounterControl {
17013 COUNTER_RING_SPLIT                       = 0x00000000,
17014 COUNTER_RING_0                           = 0x00000001,
17015 COUNTER_RING_1                           = 0x00000002,
17016 } RingCounterControl;
17017 
17018 /*
17019  * DbMemArbWatermarks enum
17020  */
17021 
17022 typedef enum DbMemArbWatermarks {
17023 TRANSFERRED_64_BYTES                     = 0x00000000,
17024 TRANSFERRED_128_BYTES                    = 0x00000001,
17025 TRANSFERRED_256_BYTES                    = 0x00000002,
17026 TRANSFERRED_512_BYTES                    = 0x00000003,
17027 TRANSFERRED_1024_BYTES                   = 0x00000004,
17028 TRANSFERRED_2048_BYTES                   = 0x00000005,
17029 TRANSFERRED_4096_BYTES                   = 0x00000006,
17030 TRANSFERRED_8192_BYTES                   = 0x00000007,
17031 } DbMemArbWatermarks;
17032 
17033 /*
17034  * DFSMFlushEvents enum
17035  */
17036 
17037 typedef enum DFSMFlushEvents {
17038 DB_FLUSH_AND_INV_DB_DATA_TS              = 0x00000000,
17039 DB_FLUSH_AND_INV_DB_META                 = 0x00000001,
17040 DB_CACHE_FLUSH                           = 0x00000002,
17041 DB_CACHE_FLUSH_TS                        = 0x00000003,
17042 DB_CACHE_FLUSH_AND_INV_EVENT             = 0x00000004,
17043 DB_CACHE_FLUSH_AND_INV_TS_EVENT          = 0x00000005,
17044 DB_VPORT_CHANGED_EVENT                   = 0x00000006,
17045 DB_CONTEXT_DONE_EVENT                    = 0x00000007,
17046 DB_BREAK_BATCH_EVENT                     = 0x00000008,
17047 DB_PSINVOKE_CHANGE_EVENT                 = 0x00000009,
17048 DB_CONTEXT_SUSPEND_EVENT                 = 0x0000000a,
17049 } DFSMFlushEvents;
17050 
17051 /*
17052  * PixelPipeCounterId enum
17053  */
17054 
17055 typedef enum PixelPipeCounterId {
17056 PIXEL_PIPE_OCCLUSION_COUNT_0             = 0x00000000,
17057 PIXEL_PIPE_OCCLUSION_COUNT_1             = 0x00000001,
17058 PIXEL_PIPE_OCCLUSION_COUNT_2             = 0x00000002,
17059 PIXEL_PIPE_OCCLUSION_COUNT_3             = 0x00000003,
17060 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0          = 0x00000004,
17061 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0          = 0x00000005,
17062 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1          = 0x00000006,
17063 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1          = 0x00000007,
17064 } PixelPipeCounterId;
17065 
17066 /*
17067  * PixelPipeStride enum
17068  */
17069 
17070 typedef enum PixelPipeStride {
17071 PIXEL_PIPE_STRIDE_32_BITS                = 0x00000000,
17072 PIXEL_PIPE_STRIDE_64_BITS                = 0x00000001,
17073 PIXEL_PIPE_STRIDE_128_BITS               = 0x00000002,
17074 PIXEL_PIPE_STRIDE_256_BITS               = 0x00000003,
17075 } PixelPipeStride;
17076 
17077 /*
17078  * FullTileWaveBreak enum
17079  */
17080 
17081 typedef enum FullTileWaveBreak {
17082 FULL_TILE_WAVE_BREAK_NBC_ONLY            = 0x00000000,
17083 FULL_TILE_WAVE_BREAK_BOTH                = 0x00000001,
17084 FULL_TILE_WAVE_BREAK_NONE                = 0x00000002,
17085 FULL_TILE_WAVE_BREAK_BC_ONLY             = 0x00000003,
17086 } FullTileWaveBreak;
17087 
17088 /*******************************************************
17089  * TA Enums
17090  *******************************************************/
17091 
17092 /*
17093  * TEX_BORDER_COLOR_TYPE enum
17094  */
17095 
17096 typedef enum TEX_BORDER_COLOR_TYPE {
17097 TEX_BorderColor_TransparentBlack         = 0x00000000,
17098 TEX_BorderColor_OpaqueBlack              = 0x00000001,
17099 TEX_BorderColor_OpaqueWhite              = 0x00000002,
17100 TEX_BorderColor_Register                 = 0x00000003,
17101 } TEX_BORDER_COLOR_TYPE;
17102 
17103 /*
17104  * TEX_BC_SWIZZLE enum
17105  */
17106 
17107 typedef enum TEX_BC_SWIZZLE {
17108 TEX_BC_Swizzle_XYZW                      = 0x00000000,
17109 TEX_BC_Swizzle_XWYZ                      = 0x00000001,
17110 TEX_BC_Swizzle_WZYX                      = 0x00000002,
17111 TEX_BC_Swizzle_WXYZ                      = 0x00000003,
17112 TEX_BC_Swizzle_ZYXW                      = 0x00000004,
17113 TEX_BC_Swizzle_YXWZ                      = 0x00000005,
17114 } TEX_BC_SWIZZLE;
17115 
17116 /*
17117  * TEX_CHROMA_KEY enum
17118  */
17119 
17120 typedef enum TEX_CHROMA_KEY {
17121 TEX_ChromaKey_Disabled                   = 0x00000000,
17122 TEX_ChromaKey_Kill                       = 0x00000001,
17123 TEX_ChromaKey_Blend                      = 0x00000002,
17124 TEX_ChromaKey_RESERVED_3                 = 0x00000003,
17125 } TEX_CHROMA_KEY;
17126 
17127 /*
17128  * TEX_CLAMP enum
17129  */
17130 
17131 typedef enum TEX_CLAMP {
17132 TEX_Clamp_Repeat                         = 0x00000000,
17133 TEX_Clamp_Mirror                         = 0x00000001,
17134 TEX_Clamp_ClampToLast                    = 0x00000002,
17135 TEX_Clamp_MirrorOnceToLast               = 0x00000003,
17136 TEX_Clamp_ClampHalfToBorder              = 0x00000004,
17137 TEX_Clamp_MirrorOnceHalfToBorder         = 0x00000005,
17138 TEX_Clamp_ClampToBorder                  = 0x00000006,
17139 TEX_Clamp_MirrorOnceToBorder             = 0x00000007,
17140 } TEX_CLAMP;
17141 
17142 /*
17143  * TEX_COORD_TYPE enum
17144  */
17145 
17146 typedef enum TEX_COORD_TYPE {
17147 TEX_CoordType_Unnormalized               = 0x00000000,
17148 TEX_CoordType_Normalized                 = 0x00000001,
17149 } TEX_COORD_TYPE;
17150 
17151 /*
17152  * TEX_DEPTH_COMPARE_FUNCTION enum
17153  */
17154 
17155 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
17156 TEX_DepthCompareFunction_Never           = 0x00000000,
17157 TEX_DepthCompareFunction_Less            = 0x00000001,
17158 TEX_DepthCompareFunction_Equal           = 0x00000002,
17159 TEX_DepthCompareFunction_LessEqual       = 0x00000003,
17160 TEX_DepthCompareFunction_Greater         = 0x00000004,
17161 TEX_DepthCompareFunction_NotEqual        = 0x00000005,
17162 TEX_DepthCompareFunction_GreaterEqual    = 0x00000006,
17163 TEX_DepthCompareFunction_Always          = 0x00000007,
17164 } TEX_DEPTH_COMPARE_FUNCTION;
17165 
17166 /*
17167  * TEX_DIM enum
17168  */
17169 
17170 typedef enum TEX_DIM {
17171 TEX_Dim_1D                               = 0x00000000,
17172 TEX_Dim_2D                               = 0x00000001,
17173 TEX_Dim_3D                               = 0x00000002,
17174 TEX_Dim_CubeMap                          = 0x00000003,
17175 TEX_Dim_1DArray                          = 0x00000004,
17176 TEX_Dim_2DArray                          = 0x00000005,
17177 TEX_Dim_2D_MSAA                          = 0x00000006,
17178 TEX_Dim_2DArray_MSAA                     = 0x00000007,
17179 } TEX_DIM;
17180 
17181 /*
17182  * TEX_FORMAT_COMP enum
17183  */
17184 
17185 typedef enum TEX_FORMAT_COMP {
17186 TEX_FormatComp_Unsigned                  = 0x00000000,
17187 TEX_FormatComp_Signed                    = 0x00000001,
17188 TEX_FormatComp_UnsignedBiased            = 0x00000002,
17189 TEX_FormatComp_RESERVED_3                = 0x00000003,
17190 } TEX_FORMAT_COMP;
17191 
17192 /*
17193  * TEX_MAX_ANISO_RATIO enum
17194  */
17195 
17196 typedef enum TEX_MAX_ANISO_RATIO {
17197 TEX_MaxAnisoRatio_1to1                   = 0x00000000,
17198 TEX_MaxAnisoRatio_2to1                   = 0x00000001,
17199 TEX_MaxAnisoRatio_4to1                   = 0x00000002,
17200 TEX_MaxAnisoRatio_8to1                   = 0x00000003,
17201 TEX_MaxAnisoRatio_16to1                  = 0x00000004,
17202 TEX_MaxAnisoRatio_RESERVED_5             = 0x00000005,
17203 TEX_MaxAnisoRatio_RESERVED_6             = 0x00000006,
17204 TEX_MaxAnisoRatio_RESERVED_7             = 0x00000007,
17205 } TEX_MAX_ANISO_RATIO;
17206 
17207 /*
17208  * TEX_MIP_FILTER enum
17209  */
17210 
17211 typedef enum TEX_MIP_FILTER {
17212 TEX_MipFilter_None                       = 0x00000000,
17213 TEX_MipFilter_Point                      = 0x00000001,
17214 TEX_MipFilter_Linear                     = 0x00000002,
17215 TEX_MipFilter_Point_Aniso_Adj            = 0x00000003,
17216 } TEX_MIP_FILTER;
17217 
17218 /*
17219  * TEX_REQUEST_SIZE enum
17220  */
17221 
17222 typedef enum TEX_REQUEST_SIZE {
17223 TEX_RequestSize_32B                      = 0x00000000,
17224 TEX_RequestSize_64B                      = 0x00000001,
17225 TEX_RequestSize_128B                     = 0x00000002,
17226 TEX_RequestSize_2X64B                    = 0x00000003,
17227 } TEX_REQUEST_SIZE;
17228 
17229 /*
17230  * TEX_SAMPLER_TYPE enum
17231  */
17232 
17233 typedef enum TEX_SAMPLER_TYPE {
17234 TEX_SamplerType_Invalid                  = 0x00000000,
17235 TEX_SamplerType_Valid                    = 0x00000001,
17236 } TEX_SAMPLER_TYPE;
17237 
17238 /*
17239  * TEX_XY_FILTER enum
17240  */
17241 
17242 typedef enum TEX_XY_FILTER {
17243 TEX_XYFilter_Point                       = 0x00000000,
17244 TEX_XYFilter_Linear                      = 0x00000001,
17245 TEX_XYFilter_AnisoPoint                  = 0x00000002,
17246 TEX_XYFilter_AnisoLinear                 = 0x00000003,
17247 } TEX_XY_FILTER;
17248 
17249 /*
17250  * TEX_Z_FILTER enum
17251  */
17252 
17253 typedef enum TEX_Z_FILTER {
17254 TEX_ZFilter_None                         = 0x00000000,
17255 TEX_ZFilter_Point                        = 0x00000001,
17256 TEX_ZFilter_Linear                       = 0x00000002,
17257 TEX_ZFilter_RESERVED_3                   = 0x00000003,
17258 } TEX_Z_FILTER;
17259 
17260 /*
17261  * VTX_CLAMP enum
17262  */
17263 
17264 typedef enum VTX_CLAMP {
17265 VTX_Clamp_ClampToZero                    = 0x00000000,
17266 VTX_Clamp_ClampToNAN                     = 0x00000001,
17267 } VTX_CLAMP;
17268 
17269 /*
17270  * VTX_FETCH_TYPE enum
17271  */
17272 
17273 typedef enum VTX_FETCH_TYPE {
17274 VTX_FetchType_VertexData                 = 0x00000000,
17275 VTX_FetchType_InstanceData               = 0x00000001,
17276 VTX_FetchType_NoIndexOffset              = 0x00000002,
17277 VTX_FetchType_RESERVED_3                 = 0x00000003,
17278 } VTX_FETCH_TYPE;
17279 
17280 /*
17281  * VTX_FORMAT_COMP_ALL enum
17282  */
17283 
17284 typedef enum VTX_FORMAT_COMP_ALL {
17285 VTX_FormatCompAll_Unsigned               = 0x00000000,
17286 VTX_FormatCompAll_Signed                 = 0x00000001,
17287 } VTX_FORMAT_COMP_ALL;
17288 
17289 /*
17290  * VTX_MEM_REQUEST_SIZE enum
17291  */
17292 
17293 typedef enum VTX_MEM_REQUEST_SIZE {
17294 VTX_MemRequestSize_32B                   = 0x00000000,
17295 VTX_MemRequestSize_64B                   = 0x00000001,
17296 } VTX_MEM_REQUEST_SIZE;
17297 
17298 /*
17299  * TVX_DATA_FORMAT enum
17300  */
17301 
17302 typedef enum TVX_DATA_FORMAT {
17303 TVX_FMT_INVALID                          = 0x00000000,
17304 TVX_FMT_8                                = 0x00000001,
17305 TVX_FMT_4_4                              = 0x00000002,
17306 TVX_FMT_3_3_2                            = 0x00000003,
17307 TVX_FMT_RESERVED_4                       = 0x00000004,
17308 TVX_FMT_16                               = 0x00000005,
17309 TVX_FMT_16_FLOAT                         = 0x00000006,
17310 TVX_FMT_8_8                              = 0x00000007,
17311 TVX_FMT_5_6_5                            = 0x00000008,
17312 TVX_FMT_6_5_5                            = 0x00000009,
17313 TVX_FMT_1_5_5_5                          = 0x0000000a,
17314 TVX_FMT_4_4_4_4                          = 0x0000000b,
17315 TVX_FMT_5_5_5_1                          = 0x0000000c,
17316 TVX_FMT_32                               = 0x0000000d,
17317 TVX_FMT_32_FLOAT                         = 0x0000000e,
17318 TVX_FMT_16_16                            = 0x0000000f,
17319 TVX_FMT_16_16_FLOAT                      = 0x00000010,
17320 TVX_FMT_8_24                             = 0x00000011,
17321 TVX_FMT_8_24_FLOAT                       = 0x00000012,
17322 TVX_FMT_24_8                             = 0x00000013,
17323 TVX_FMT_24_8_FLOAT                       = 0x00000014,
17324 TVX_FMT_10_11_11                         = 0x00000015,
17325 TVX_FMT_10_11_11_FLOAT                   = 0x00000016,
17326 TVX_FMT_11_11_10                         = 0x00000017,
17327 TVX_FMT_11_11_10_FLOAT                   = 0x00000018,
17328 TVX_FMT_2_10_10_10                       = 0x00000019,
17329 TVX_FMT_8_8_8_8                          = 0x0000001a,
17330 TVX_FMT_10_10_10_2                       = 0x0000001b,
17331 TVX_FMT_X24_8_32_FLOAT                   = 0x0000001c,
17332 TVX_FMT_32_32                            = 0x0000001d,
17333 TVX_FMT_32_32_FLOAT                      = 0x0000001e,
17334 TVX_FMT_16_16_16_16                      = 0x0000001f,
17335 TVX_FMT_16_16_16_16_FLOAT                = 0x00000020,
17336 TVX_FMT_RESERVED_33                      = 0x00000021,
17337 TVX_FMT_32_32_32_32                      = 0x00000022,
17338 TVX_FMT_32_32_32_32_FLOAT                = 0x00000023,
17339 TVX_FMT_RESERVED_36                      = 0x00000024,
17340 TVX_FMT_1                                = 0x00000025,
17341 TVX_FMT_1_REVERSED                       = 0x00000026,
17342 TVX_FMT_GB_GR                            = 0x00000027,
17343 TVX_FMT_BG_RG                            = 0x00000028,
17344 TVX_FMT_32_AS_8                          = 0x00000029,
17345 TVX_FMT_32_AS_8_8                        = 0x0000002a,
17346 TVX_FMT_5_9_9_9_SHAREDEXP                = 0x0000002b,
17347 TVX_FMT_8_8_8                            = 0x0000002c,
17348 TVX_FMT_16_16_16                         = 0x0000002d,
17349 TVX_FMT_16_16_16_FLOAT                   = 0x0000002e,
17350 TVX_FMT_32_32_32                         = 0x0000002f,
17351 TVX_FMT_32_32_32_FLOAT                   = 0x00000030,
17352 TVX_FMT_BC1                              = 0x00000031,
17353 TVX_FMT_BC2                              = 0x00000032,
17354 TVX_FMT_BC3                              = 0x00000033,
17355 TVX_FMT_BC4                              = 0x00000034,
17356 TVX_FMT_BC5                              = 0x00000035,
17357 TVX_FMT_APC0                             = 0x00000036,
17358 TVX_FMT_APC1                             = 0x00000037,
17359 TVX_FMT_APC2                             = 0x00000038,
17360 TVX_FMT_APC3                             = 0x00000039,
17361 TVX_FMT_APC4                             = 0x0000003a,
17362 TVX_FMT_APC5                             = 0x0000003b,
17363 TVX_FMT_APC6                             = 0x0000003c,
17364 TVX_FMT_APC7                             = 0x0000003d,
17365 TVX_FMT_CTX1                             = 0x0000003e,
17366 TVX_FMT_RESERVED_63                      = 0x0000003f,
17367 } TVX_DATA_FORMAT;
17368 
17369 /*
17370  * TVX_DST_SEL enum
17371  */
17372 
17373 typedef enum TVX_DST_SEL {
17374 TVX_DstSel_X                             = 0x00000000,
17375 TVX_DstSel_Y                             = 0x00000001,
17376 TVX_DstSel_Z                             = 0x00000002,
17377 TVX_DstSel_W                             = 0x00000003,
17378 TVX_DstSel_0f                            = 0x00000004,
17379 TVX_DstSel_1f                            = 0x00000005,
17380 TVX_DstSel_RESERVED_6                    = 0x00000006,
17381 TVX_DstSel_Mask                          = 0x00000007,
17382 } TVX_DST_SEL;
17383 
17384 /*
17385  * TVX_ENDIAN_SWAP enum
17386  */
17387 
17388 typedef enum TVX_ENDIAN_SWAP {
17389 TVX_EndianSwap_None                      = 0x00000000,
17390 TVX_EndianSwap_8in16                     = 0x00000001,
17391 TVX_EndianSwap_8in32                     = 0x00000002,
17392 TVX_EndianSwap_8in64                     = 0x00000003,
17393 } TVX_ENDIAN_SWAP;
17394 
17395 /*
17396  * TVX_INST enum
17397  */
17398 
17399 typedef enum TVX_INST {
17400 TVX_Inst_NormalVertexFetch               = 0x00000000,
17401 TVX_Inst_SemanticVertexFetch             = 0x00000001,
17402 TVX_Inst_RESERVED_2                      = 0x00000002,
17403 TVX_Inst_LD                              = 0x00000003,
17404 TVX_Inst_GetTextureResInfo               = 0x00000004,
17405 TVX_Inst_GetNumberOfSamples              = 0x00000005,
17406 TVX_Inst_GetLOD                          = 0x00000006,
17407 TVX_Inst_GetGradientsH                   = 0x00000007,
17408 TVX_Inst_GetGradientsV                   = 0x00000008,
17409 TVX_Inst_SetTextureOffsets               = 0x00000009,
17410 TVX_Inst_KeepGradients                   = 0x0000000a,
17411 TVX_Inst_SetGradientsH                   = 0x0000000b,
17412 TVX_Inst_SetGradientsV                   = 0x0000000c,
17413 TVX_Inst_Pass                            = 0x0000000d,
17414 TVX_Inst_GetBufferResInfo                = 0x0000000e,
17415 TVX_Inst_RESERVED_15                     = 0x0000000f,
17416 TVX_Inst_Sample                          = 0x00000010,
17417 TVX_Inst_Sample_L                        = 0x00000011,
17418 TVX_Inst_Sample_LB                       = 0x00000012,
17419 TVX_Inst_Sample_LZ                       = 0x00000013,
17420 TVX_Inst_Sample_G                        = 0x00000014,
17421 TVX_Inst_Gather4                         = 0x00000015,
17422 TVX_Inst_Sample_G_LB                     = 0x00000016,
17423 TVX_Inst_Gather4_O                       = 0x00000017,
17424 TVX_Inst_Sample_C                        = 0x00000018,
17425 TVX_Inst_Sample_C_L                      = 0x00000019,
17426 TVX_Inst_Sample_C_LB                     = 0x0000001a,
17427 TVX_Inst_Sample_C_LZ                     = 0x0000001b,
17428 TVX_Inst_Sample_C_G                      = 0x0000001c,
17429 TVX_Inst_Gather4_C                       = 0x0000001d,
17430 TVX_Inst_Sample_C_G_LB                   = 0x0000001e,
17431 TVX_Inst_Gather4_C_O                     = 0x0000001f,
17432 } TVX_INST;
17433 
17434 /*
17435  * TVX_NUM_FORMAT_ALL enum
17436  */
17437 
17438 typedef enum TVX_NUM_FORMAT_ALL {
17439 TVX_NumFormatAll_Norm                    = 0x00000000,
17440 TVX_NumFormatAll_Int                     = 0x00000001,
17441 TVX_NumFormatAll_Scaled                  = 0x00000002,
17442 TVX_NumFormatAll_RESERVED_3              = 0x00000003,
17443 } TVX_NUM_FORMAT_ALL;
17444 
17445 /*
17446  * TVX_SRC_SEL enum
17447  */
17448 
17449 typedef enum TVX_SRC_SEL {
17450 TVX_SrcSel_X                             = 0x00000000,
17451 TVX_SrcSel_Y                             = 0x00000001,
17452 TVX_SrcSel_Z                             = 0x00000002,
17453 TVX_SrcSel_W                             = 0x00000003,
17454 TVX_SrcSel_0f                            = 0x00000004,
17455 TVX_SrcSel_1f                            = 0x00000005,
17456 } TVX_SRC_SEL;
17457 
17458 /*
17459  * TVX_SRF_MODE_ALL enum
17460  */
17461 
17462 typedef enum TVX_SRF_MODE_ALL {
17463 TVX_SRFModeAll_ZCMO                      = 0x00000000,
17464 TVX_SRFModeAll_NZ                        = 0x00000001,
17465 } TVX_SRF_MODE_ALL;
17466 
17467 /*
17468  * TVX_TYPE enum
17469  */
17470 
17471 typedef enum TVX_TYPE {
17472 TVX_Type_InvalidTextureResource          = 0x00000000,
17473 TVX_Type_InvalidVertexBuffer             = 0x00000001,
17474 TVX_Type_ValidTextureResource            = 0x00000002,
17475 TVX_Type_ValidVertexBuffer               = 0x00000003,
17476 } TVX_TYPE;
17477 
17478 /*******************************************************
17479  * PA Enums
17480  *******************************************************/
17481 
17482 /*
17483  * PH_PERFCNT_SEL enum
17484  */
17485 
17486 typedef enum PH_PERFCNT_SEL {
17487 PH_SC0_SRPS_WINDOW_VALID                 = 0x00000000,
17488 PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000001,
17489 PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES          = 0x00000002,
17490 PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x00000003,
17491 PH_SC0_ARB_STALLED_FROM_BELOW            = 0x00000004,
17492 PH_SC0_ARB_STARVED_FROM_ABOVE            = 0x00000005,
17493 PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY  = 0x00000006,
17494 PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL  = 0x00000007,
17495 PH_SC0_ARB_BUSY                          = 0x00000008,
17496 PH_SC0_ARB_PA_BUSY_SOP                   = 0x00000009,
17497 PH_SC0_ARB_EOP_POP_SYNC_POP              = 0x0000000a,
17498 PH_SC0_ARB_EVENT_SYNC_POP                = 0x0000000b,
17499 PH_SC0_PS_ENG_MULTICYCLE_BUBBLE          = 0x0000000c,
17500 PH_SC0_EOP_SYNC_WINDOW                   = 0x0000000d,
17501 PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x0000000e,
17502 PH_SC0_BUSY_CNT_NOT_ZERO                 = 0x0000000f,
17503 PH_SC0_SEND                              = 0x00000010,
17504 PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000011,
17505 PH_SC0_CREDIT_AT_MAX                     = 0x00000012,
17506 PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x00000013,
17507 PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION  = 0x00000014,
17508 PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION  = 0x00000015,
17509 PH_SC0_GFX_PIPE0_TO_1_TRANSITION         = 0x00000016,
17510 PH_SC0_GFX_PIPE1_TO_0_TRANSITION         = 0x00000017,
17511 PH_SC0_PA0_DATA_FIFO_RD                  = 0x00000018,
17512 PH_SC0_PA0_DATA_FIFO_WE                  = 0x00000019,
17513 PH_SC0_PA0_FIFO_EMPTY                    = 0x0000001a,
17514 PH_SC0_PA0_FIFO_FULL                     = 0x0000001b,
17515 PH_SC0_PA0_NULL_WE                       = 0x0000001c,
17516 PH_SC0_PA0_EVENT_WE                      = 0x0000001d,
17517 PH_SC0_PA0_FPOV_WE                       = 0x0000001e,
17518 PH_SC0_PA0_LPOV_WE                       = 0x0000001f,
17519 PH_SC0_PA0_EOP_WE                        = 0x00000020,
17520 PH_SC0_PA0_DATA_FIFO_EOP_RD              = 0x00000021,
17521 PH_SC0_PA0_EOPG_WE                       = 0x00000022,
17522 PH_SC0_PA0_DEALLOC_4_0_RD                = 0x00000023,
17523 PH_SC0_PA1_DATA_FIFO_RD                  = 0x00000024,
17524 PH_SC0_PA1_DATA_FIFO_WE                  = 0x00000025,
17525 PH_SC0_PA1_FIFO_EMPTY                    = 0x00000026,
17526 PH_SC0_PA1_FIFO_FULL                     = 0x00000027,
17527 PH_SC0_PA1_NULL_WE                       = 0x00000028,
17528 PH_SC0_PA1_EVENT_WE                      = 0x00000029,
17529 PH_SC0_PA1_FPOV_WE                       = 0x0000002a,
17530 PH_SC0_PA1_LPOV_WE                       = 0x0000002b,
17531 PH_SC0_PA1_EOP_WE                        = 0x0000002c,
17532 PH_SC0_PA1_DATA_FIFO_EOP_RD              = 0x0000002d,
17533 PH_SC0_PA1_EOPG_WE                       = 0x0000002e,
17534 PH_SC0_PA1_DEALLOC_4_0_RD                = 0x0000002f,
17535 PH_SC0_PA2_DATA_FIFO_RD                  = 0x00000030,
17536 PH_SC0_PA2_DATA_FIFO_WE                  = 0x00000031,
17537 PH_SC0_PA2_FIFO_EMPTY                    = 0x00000032,
17538 PH_SC0_PA2_FIFO_FULL                     = 0x00000033,
17539 PH_SC0_PA2_NULL_WE                       = 0x00000034,
17540 PH_SC0_PA2_EVENT_WE                      = 0x00000035,
17541 PH_SC0_PA2_FPOV_WE                       = 0x00000036,
17542 PH_SC0_PA2_LPOV_WE                       = 0x00000037,
17543 PH_SC0_PA2_EOP_WE                        = 0x00000038,
17544 PH_SC0_PA2_DATA_FIFO_EOP_RD              = 0x00000039,
17545 PH_SC0_PA2_EOPG_WE                       = 0x0000003a,
17546 PH_SC0_PA2_DEALLOC_4_0_RD                = 0x0000003b,
17547 PH_SC0_PA3_DATA_FIFO_RD                  = 0x0000003c,
17548 PH_SC0_PA3_DATA_FIFO_WE                  = 0x0000003d,
17549 PH_SC0_PA3_FIFO_EMPTY                    = 0x0000003e,
17550 PH_SC0_PA3_FIFO_FULL                     = 0x0000003f,
17551 PH_SC0_PA3_NULL_WE                       = 0x00000040,
17552 PH_SC0_PA3_EVENT_WE                      = 0x00000041,
17553 PH_SC0_PA3_FPOV_WE                       = 0x00000042,
17554 PH_SC0_PA3_LPOV_WE                       = 0x00000043,
17555 PH_SC0_PA3_EOP_WE                        = 0x00000044,
17556 PH_SC0_PA3_DATA_FIFO_EOP_RD              = 0x00000045,
17557 PH_SC0_PA3_EOPG_WE                       = 0x00000046,
17558 PH_SC0_PA3_DEALLOC_4_0_RD                = 0x00000047,
17559 PH_SC0_PA4_DATA_FIFO_RD                  = 0x00000048,
17560 PH_SC0_PA4_DATA_FIFO_WE                  = 0x00000049,
17561 PH_SC0_PA4_FIFO_EMPTY                    = 0x0000004a,
17562 PH_SC0_PA4_FIFO_FULL                     = 0x0000004b,
17563 PH_SC0_PA4_NULL_WE                       = 0x0000004c,
17564 PH_SC0_PA4_EVENT_WE                      = 0x0000004d,
17565 PH_SC0_PA4_FPOV_WE                       = 0x0000004e,
17566 PH_SC0_PA4_LPOV_WE                       = 0x0000004f,
17567 PH_SC0_PA4_EOP_WE                        = 0x00000050,
17568 PH_SC0_PA4_DATA_FIFO_EOP_RD              = 0x00000051,
17569 PH_SC0_PA4_EOPG_WE                       = 0x00000052,
17570 PH_SC0_PA4_DEALLOC_4_0_RD                = 0x00000053,
17571 PH_SC0_PA5_DATA_FIFO_RD                  = 0x00000054,
17572 PH_SC0_PA5_DATA_FIFO_WE                  = 0x00000055,
17573 PH_SC0_PA5_FIFO_EMPTY                    = 0x00000056,
17574 PH_SC0_PA5_FIFO_FULL                     = 0x00000057,
17575 PH_SC0_PA5_NULL_WE                       = 0x00000058,
17576 PH_SC0_PA5_EVENT_WE                      = 0x00000059,
17577 PH_SC0_PA5_FPOV_WE                       = 0x0000005a,
17578 PH_SC0_PA5_LPOV_WE                       = 0x0000005b,
17579 PH_SC0_PA5_EOP_WE                        = 0x0000005c,
17580 PH_SC0_PA5_DATA_FIFO_EOP_RD              = 0x0000005d,
17581 PH_SC0_PA5_EOPG_WE                       = 0x0000005e,
17582 PH_SC0_PA5_DEALLOC_4_0_RD                = 0x0000005f,
17583 PH_SC0_PA6_DATA_FIFO_RD                  = 0x00000060,
17584 PH_SC0_PA6_DATA_FIFO_WE                  = 0x00000061,
17585 PH_SC0_PA6_FIFO_EMPTY                    = 0x00000062,
17586 PH_SC0_PA6_FIFO_FULL                     = 0x00000063,
17587 PH_SC0_PA6_NULL_WE                       = 0x00000064,
17588 PH_SC0_PA6_EVENT_WE                      = 0x00000065,
17589 PH_SC0_PA6_FPOV_WE                       = 0x00000066,
17590 PH_SC0_PA6_LPOV_WE                       = 0x00000067,
17591 PH_SC0_PA6_EOP_WE                        = 0x00000068,
17592 PH_SC0_PA6_DATA_FIFO_EOP_RD              = 0x00000069,
17593 PH_SC0_PA6_EOPG_WE                       = 0x0000006a,
17594 PH_SC0_PA6_DEALLOC_4_0_RD                = 0x0000006b,
17595 PH_SC0_PA7_DATA_FIFO_RD                  = 0x0000006c,
17596 PH_SC0_PA7_DATA_FIFO_WE                  = 0x0000006d,
17597 PH_SC0_PA7_FIFO_EMPTY                    = 0x0000006e,
17598 PH_SC0_PA7_FIFO_FULL                     = 0x0000006f,
17599 PH_SC0_PA7_NULL_WE                       = 0x00000070,
17600 PH_SC0_PA7_EVENT_WE                      = 0x00000071,
17601 PH_SC0_PA7_FPOV_WE                       = 0x00000072,
17602 PH_SC0_PA7_LPOV_WE                       = 0x00000073,
17603 PH_SC0_PA7_EOP_WE                        = 0x00000074,
17604 PH_SC0_PA7_DATA_FIFO_EOP_RD              = 0x00000075,
17605 PH_SC0_PA7_EOPG_WE                       = 0x00000076,
17606 PH_SC0_PA7_DEALLOC_4_0_RD                = 0x00000077,
17607 PH_SC1_SRPS_WINDOW_VALID                 = 0x00000078,
17608 PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000079,
17609 PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES          = 0x0000007a,
17610 PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x0000007b,
17611 PH_SC1_ARB_STALLED_FROM_BELOW            = 0x0000007c,
17612 PH_SC1_ARB_STARVED_FROM_ABOVE            = 0x0000007d,
17613 PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY  = 0x0000007e,
17614 PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL  = 0x0000007f,
17615 PH_SC1_ARB_BUSY                          = 0x00000080,
17616 PH_SC1_ARB_PA_BUSY_SOP                   = 0x00000081,
17617 PH_SC1_ARB_EOP_POP_SYNC_POP              = 0x00000082,
17618 PH_SC1_ARB_EVENT_SYNC_POP                = 0x00000083,
17619 PH_SC1_PS_ENG_MULTICYCLE_BUBBLE          = 0x00000084,
17620 PH_SC1_EOP_SYNC_WINDOW                   = 0x00000085,
17621 PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x00000086,
17622 PH_SC1_BUSY_CNT_NOT_ZERO                 = 0x00000087,
17623 PH_SC1_SEND                              = 0x00000088,
17624 PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000089,
17625 PH_SC1_CREDIT_AT_MAX                     = 0x0000008a,
17626 PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x0000008b,
17627 PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION  = 0x0000008c,
17628 PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION  = 0x0000008d,
17629 PH_SC1_GFX_PIPE0_TO_1_TRANSITION         = 0x0000008e,
17630 PH_SC1_GFX_PIPE1_TO_0_TRANSITION         = 0x0000008f,
17631 PH_SC1_PA0_DATA_FIFO_RD                  = 0x00000090,
17632 PH_SC1_PA0_DATA_FIFO_WE                  = 0x00000091,
17633 PH_SC1_PA0_FIFO_EMPTY                    = 0x00000092,
17634 PH_SC1_PA0_FIFO_FULL                     = 0x00000093,
17635 PH_SC1_PA0_NULL_WE                       = 0x00000094,
17636 PH_SC1_PA0_EVENT_WE                      = 0x00000095,
17637 PH_SC1_PA0_FPOV_WE                       = 0x00000096,
17638 PH_SC1_PA0_LPOV_WE                       = 0x00000097,
17639 PH_SC1_PA0_EOP_WE                        = 0x00000098,
17640 PH_SC1_PA0_DATA_FIFO_EOP_RD              = 0x00000099,
17641 PH_SC1_PA0_EOPG_WE                       = 0x0000009a,
17642 PH_SC1_PA0_DEALLOC_4_0_RD                = 0x0000009b,
17643 PH_SC1_PA1_DATA_FIFO_RD                  = 0x0000009c,
17644 PH_SC1_PA1_DATA_FIFO_WE                  = 0x0000009d,
17645 PH_SC1_PA1_FIFO_EMPTY                    = 0x0000009e,
17646 PH_SC1_PA1_FIFO_FULL                     = 0x0000009f,
17647 PH_SC1_PA1_NULL_WE                       = 0x000000a0,
17648 PH_SC1_PA1_EVENT_WE                      = 0x000000a1,
17649 PH_SC1_PA1_FPOV_WE                       = 0x000000a2,
17650 PH_SC1_PA1_LPOV_WE                       = 0x000000a3,
17651 PH_SC1_PA1_EOP_WE                        = 0x000000a4,
17652 PH_SC1_PA1_DATA_FIFO_EOP_RD              = 0x000000a5,
17653 PH_SC1_PA1_EOPG_WE                       = 0x000000a6,
17654 PH_SC1_PA1_DEALLOC_4_0_RD                = 0x000000a7,
17655 PH_SC1_PA2_DATA_FIFO_RD                  = 0x000000a8,
17656 PH_SC1_PA2_DATA_FIFO_WE                  = 0x000000a9,
17657 PH_SC1_PA2_FIFO_EMPTY                    = 0x000000aa,
17658 PH_SC1_PA2_FIFO_FULL                     = 0x000000ab,
17659 PH_SC1_PA2_NULL_WE                       = 0x000000ac,
17660 PH_SC1_PA2_EVENT_WE                      = 0x000000ad,
17661 PH_SC1_PA2_FPOV_WE                       = 0x000000ae,
17662 PH_SC1_PA2_LPOV_WE                       = 0x000000af,
17663 PH_SC1_PA2_EOP_WE                        = 0x000000b0,
17664 PH_SC1_PA2_DATA_FIFO_EOP_RD              = 0x000000b1,
17665 PH_SC1_PA2_EOPG_WE                       = 0x000000b2,
17666 PH_SC1_PA2_DEALLOC_4_0_RD                = 0x000000b3,
17667 PH_SC1_PA3_DATA_FIFO_RD                  = 0x000000b4,
17668 PH_SC1_PA3_DATA_FIFO_WE                  = 0x000000b5,
17669 PH_SC1_PA3_FIFO_EMPTY                    = 0x000000b6,
17670 PH_SC1_PA3_FIFO_FULL                     = 0x000000b7,
17671 PH_SC1_PA3_NULL_WE                       = 0x000000b8,
17672 PH_SC1_PA3_EVENT_WE                      = 0x000000b9,
17673 PH_SC1_PA3_FPOV_WE                       = 0x000000ba,
17674 PH_SC1_PA3_LPOV_WE                       = 0x000000bb,
17675 PH_SC1_PA3_EOP_WE                        = 0x000000bc,
17676 PH_SC1_PA3_DATA_FIFO_EOP_RD              = 0x000000bd,
17677 PH_SC1_PA3_EOPG_WE                       = 0x000000be,
17678 PH_SC1_PA3_DEALLOC_4_0_RD                = 0x000000bf,
17679 PH_SC1_PA4_DATA_FIFO_RD                  = 0x000000c0,
17680 PH_SC1_PA4_DATA_FIFO_WE                  = 0x000000c1,
17681 PH_SC1_PA4_FIFO_EMPTY                    = 0x000000c2,
17682 PH_SC1_PA4_FIFO_FULL                     = 0x000000c3,
17683 PH_SC1_PA4_NULL_WE                       = 0x000000c4,
17684 PH_SC1_PA4_EVENT_WE                      = 0x000000c5,
17685 PH_SC1_PA4_FPOV_WE                       = 0x000000c6,
17686 PH_SC1_PA4_LPOV_WE                       = 0x000000c7,
17687 PH_SC1_PA4_EOP_WE                        = 0x000000c8,
17688 PH_SC1_PA4_DATA_FIFO_EOP_RD              = 0x000000c9,
17689 PH_SC1_PA4_EOPG_WE                       = 0x000000ca,
17690 PH_SC1_PA4_DEALLOC_4_0_RD                = 0x000000cb,
17691 PH_SC1_PA5_DATA_FIFO_RD                  = 0x000000cc,
17692 PH_SC1_PA5_DATA_FIFO_WE                  = 0x000000cd,
17693 PH_SC1_PA5_FIFO_EMPTY                    = 0x000000ce,
17694 PH_SC1_PA5_FIFO_FULL                     = 0x000000cf,
17695 PH_SC1_PA5_NULL_WE                       = 0x000000d0,
17696 PH_SC1_PA5_EVENT_WE                      = 0x000000d1,
17697 PH_SC1_PA5_FPOV_WE                       = 0x000000d2,
17698 PH_SC1_PA5_LPOV_WE                       = 0x000000d3,
17699 PH_SC1_PA5_EOP_WE                        = 0x000000d4,
17700 PH_SC1_PA5_DATA_FIFO_EOP_RD              = 0x000000d5,
17701 PH_SC1_PA5_EOPG_WE                       = 0x000000d6,
17702 PH_SC1_PA5_DEALLOC_4_0_RD                = 0x000000d7,
17703 PH_SC1_PA6_DATA_FIFO_RD                  = 0x000000d8,
17704 PH_SC1_PA6_DATA_FIFO_WE                  = 0x000000d9,
17705 PH_SC1_PA6_FIFO_EMPTY                    = 0x000000da,
17706 PH_SC1_PA6_FIFO_FULL                     = 0x000000db,
17707 PH_SC1_PA6_NULL_WE                       = 0x000000dc,
17708 PH_SC1_PA6_EVENT_WE                      = 0x000000dd,
17709 PH_SC1_PA6_FPOV_WE                       = 0x000000de,
17710 PH_SC1_PA6_LPOV_WE                       = 0x000000df,
17711 PH_SC1_PA6_EOP_WE                        = 0x000000e0,
17712 PH_SC1_PA6_DATA_FIFO_EOP_RD              = 0x000000e1,
17713 PH_SC1_PA6_EOPG_WE                       = 0x000000e2,
17714 PH_SC1_PA6_DEALLOC_4_0_RD                = 0x000000e3,
17715 PH_SC1_PA7_DATA_FIFO_RD                  = 0x000000e4,
17716 PH_SC1_PA7_DATA_FIFO_WE                  = 0x000000e5,
17717 PH_SC1_PA7_FIFO_EMPTY                    = 0x000000e6,
17718 PH_SC1_PA7_FIFO_FULL                     = 0x000000e7,
17719 PH_SC1_PA7_NULL_WE                       = 0x000000e8,
17720 PH_SC1_PA7_EVENT_WE                      = 0x000000e9,
17721 PH_SC1_PA7_FPOV_WE                       = 0x000000ea,
17722 PH_SC1_PA7_LPOV_WE                       = 0x000000eb,
17723 PH_SC1_PA7_EOP_WE                        = 0x000000ec,
17724 PH_SC1_PA7_DATA_FIFO_EOP_RD              = 0x000000ed,
17725 PH_SC1_PA7_EOPG_WE                       = 0x000000ee,
17726 PH_SC1_PA7_DEALLOC_4_0_RD                = 0x000000ef,
17727 PH_SC2_SRPS_WINDOW_VALID                 = 0x000000f0,
17728 PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x000000f1,
17729 PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES          = 0x000000f2,
17730 PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x000000f3,
17731 PH_SC2_ARB_STALLED_FROM_BELOW            = 0x000000f4,
17732 PH_SC2_ARB_STARVED_FROM_ABOVE            = 0x000000f5,
17733 PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY  = 0x000000f6,
17734 PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL  = 0x000000f7,
17735 PH_SC2_ARB_BUSY                          = 0x000000f8,
17736 PH_SC2_ARB_PA_BUSY_SOP                   = 0x000000f9,
17737 PH_SC2_ARB_EOP_POP_SYNC_POP              = 0x000000fa,
17738 PH_SC2_ARB_EVENT_SYNC_POP                = 0x000000fb,
17739 PH_SC2_PS_ENG_MULTICYCLE_BUBBLE          = 0x000000fc,
17740 PH_SC2_EOP_SYNC_WINDOW                   = 0x000000fd,
17741 PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x000000fe,
17742 PH_SC2_BUSY_CNT_NOT_ZERO                 = 0x000000ff,
17743 PH_SC2_SEND                              = 0x00000100,
17744 PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000101,
17745 PH_SC2_CREDIT_AT_MAX                     = 0x00000102,
17746 PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x00000103,
17747 PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION  = 0x00000104,
17748 PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION  = 0x00000105,
17749 PH_SC2_GFX_PIPE0_TO_1_TRANSITION         = 0x00000106,
17750 PH_SC2_GFX_PIPE1_TO_0_TRANSITION         = 0x00000107,
17751 PH_SC2_PA0_DATA_FIFO_RD                  = 0x00000108,
17752 PH_SC2_PA0_DATA_FIFO_WE                  = 0x00000109,
17753 PH_SC2_PA0_FIFO_EMPTY                    = 0x0000010a,
17754 PH_SC2_PA0_FIFO_FULL                     = 0x0000010b,
17755 PH_SC2_PA0_NULL_WE                       = 0x0000010c,
17756 PH_SC2_PA0_EVENT_WE                      = 0x0000010d,
17757 PH_SC2_PA0_FPOV_WE                       = 0x0000010e,
17758 PH_SC2_PA0_LPOV_WE                       = 0x0000010f,
17759 PH_SC2_PA0_EOP_WE                        = 0x00000110,
17760 PH_SC2_PA0_DATA_FIFO_EOP_RD              = 0x00000111,
17761 PH_SC2_PA0_EOPG_WE                       = 0x00000112,
17762 PH_SC2_PA0_DEALLOC_4_0_RD                = 0x00000113,
17763 PH_SC2_PA1_DATA_FIFO_RD                  = 0x00000114,
17764 PH_SC2_PA1_DATA_FIFO_WE                  = 0x00000115,
17765 PH_SC2_PA1_FIFO_EMPTY                    = 0x00000116,
17766 PH_SC2_PA1_FIFO_FULL                     = 0x00000117,
17767 PH_SC2_PA1_NULL_WE                       = 0x00000118,
17768 PH_SC2_PA1_EVENT_WE                      = 0x00000119,
17769 PH_SC2_PA1_FPOV_WE                       = 0x0000011a,
17770 PH_SC2_PA1_LPOV_WE                       = 0x0000011b,
17771 PH_SC2_PA1_EOP_WE                        = 0x0000011c,
17772 PH_SC2_PA1_DATA_FIFO_EOP_RD              = 0x0000011d,
17773 PH_SC2_PA1_EOPG_WE                       = 0x0000011e,
17774 PH_SC2_PA1_DEALLOC_4_0_RD                = 0x0000011f,
17775 PH_SC2_PA2_DATA_FIFO_RD                  = 0x00000120,
17776 PH_SC2_PA2_DATA_FIFO_WE                  = 0x00000121,
17777 PH_SC2_PA2_FIFO_EMPTY                    = 0x00000122,
17778 PH_SC2_PA2_FIFO_FULL                     = 0x00000123,
17779 PH_SC2_PA2_NULL_WE                       = 0x00000124,
17780 PH_SC2_PA2_EVENT_WE                      = 0x00000125,
17781 PH_SC2_PA2_FPOV_WE                       = 0x00000126,
17782 PH_SC2_PA2_LPOV_WE                       = 0x00000127,
17783 PH_SC2_PA2_EOP_WE                        = 0x00000128,
17784 PH_SC2_PA2_DATA_FIFO_EOP_RD              = 0x00000129,
17785 PH_SC2_PA2_EOPG_WE                       = 0x0000012a,
17786 PH_SC2_PA2_DEALLOC_4_0_RD                = 0x0000012b,
17787 PH_SC2_PA3_DATA_FIFO_RD                  = 0x0000012c,
17788 PH_SC2_PA3_DATA_FIFO_WE                  = 0x0000012d,
17789 PH_SC2_PA3_FIFO_EMPTY                    = 0x0000012e,
17790 PH_SC2_PA3_FIFO_FULL                     = 0x0000012f,
17791 PH_SC2_PA3_NULL_WE                       = 0x00000130,
17792 PH_SC2_PA3_EVENT_WE                      = 0x00000131,
17793 PH_SC2_PA3_FPOV_WE                       = 0x00000132,
17794 PH_SC2_PA3_LPOV_WE                       = 0x00000133,
17795 PH_SC2_PA3_EOP_WE                        = 0x00000134,
17796 PH_SC2_PA3_DATA_FIFO_EOP_RD              = 0x00000135,
17797 PH_SC2_PA3_EOPG_WE                       = 0x00000136,
17798 PH_SC2_PA3_DEALLOC_4_0_RD                = 0x00000137,
17799 PH_SC2_PA4_DATA_FIFO_RD                  = 0x00000138,
17800 PH_SC2_PA4_DATA_FIFO_WE                  = 0x00000139,
17801 PH_SC2_PA4_FIFO_EMPTY                    = 0x0000013a,
17802 PH_SC2_PA4_FIFO_FULL                     = 0x0000013b,
17803 PH_SC2_PA4_NULL_WE                       = 0x0000013c,
17804 PH_SC2_PA4_EVENT_WE                      = 0x0000013d,
17805 PH_SC2_PA4_FPOV_WE                       = 0x0000013e,
17806 PH_SC2_PA4_LPOV_WE                       = 0x0000013f,
17807 PH_SC2_PA4_EOP_WE                        = 0x00000140,
17808 PH_SC2_PA4_DATA_FIFO_EOP_RD              = 0x00000141,
17809 PH_SC2_PA4_EOPG_WE                       = 0x00000142,
17810 PH_SC2_PA4_DEALLOC_4_0_RD                = 0x00000143,
17811 PH_SC2_PA5_DATA_FIFO_RD                  = 0x00000144,
17812 PH_SC2_PA5_DATA_FIFO_WE                  = 0x00000145,
17813 PH_SC2_PA5_FIFO_EMPTY                    = 0x00000146,
17814 PH_SC2_PA5_FIFO_FULL                     = 0x00000147,
17815 PH_SC2_PA5_NULL_WE                       = 0x00000148,
17816 PH_SC2_PA5_EVENT_WE                      = 0x00000149,
17817 PH_SC2_PA5_FPOV_WE                       = 0x0000014a,
17818 PH_SC2_PA5_LPOV_WE                       = 0x0000014b,
17819 PH_SC2_PA5_EOP_WE                        = 0x0000014c,
17820 PH_SC2_PA5_DATA_FIFO_EOP_RD              = 0x0000014d,
17821 PH_SC2_PA5_EOPG_WE                       = 0x0000014e,
17822 PH_SC2_PA5_DEALLOC_4_0_RD                = 0x0000014f,
17823 PH_SC2_PA6_DATA_FIFO_RD                  = 0x00000150,
17824 PH_SC2_PA6_DATA_FIFO_WE                  = 0x00000151,
17825 PH_SC2_PA6_FIFO_EMPTY                    = 0x00000152,
17826 PH_SC2_PA6_FIFO_FULL                     = 0x00000153,
17827 PH_SC2_PA6_NULL_WE                       = 0x00000154,
17828 PH_SC2_PA6_EVENT_WE                      = 0x00000155,
17829 PH_SC2_PA6_FPOV_WE                       = 0x00000156,
17830 PH_SC2_PA6_LPOV_WE                       = 0x00000157,
17831 PH_SC2_PA6_EOP_WE                        = 0x00000158,
17832 PH_SC2_PA6_DATA_FIFO_EOP_RD              = 0x00000159,
17833 PH_SC2_PA6_EOPG_WE                       = 0x0000015a,
17834 PH_SC2_PA6_DEALLOC_4_0_RD                = 0x0000015b,
17835 PH_SC2_PA7_DATA_FIFO_RD                  = 0x0000015c,
17836 PH_SC2_PA7_DATA_FIFO_WE                  = 0x0000015d,
17837 PH_SC2_PA7_FIFO_EMPTY                    = 0x0000015e,
17838 PH_SC2_PA7_FIFO_FULL                     = 0x0000015f,
17839 PH_SC2_PA7_NULL_WE                       = 0x00000160,
17840 PH_SC2_PA7_EVENT_WE                      = 0x00000161,
17841 PH_SC2_PA7_FPOV_WE                       = 0x00000162,
17842 PH_SC2_PA7_LPOV_WE                       = 0x00000163,
17843 PH_SC2_PA7_EOP_WE                        = 0x00000164,
17844 PH_SC2_PA7_DATA_FIFO_EOP_RD              = 0x00000165,
17845 PH_SC2_PA7_EOPG_WE                       = 0x00000166,
17846 PH_SC2_PA7_DEALLOC_4_0_RD                = 0x00000167,
17847 PH_SC3_SRPS_WINDOW_VALID                 = 0x00000168,
17848 PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000169,
17849 PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES          = 0x0000016a,
17850 PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x0000016b,
17851 PH_SC3_ARB_STALLED_FROM_BELOW            = 0x0000016c,
17852 PH_SC3_ARB_STARVED_FROM_ABOVE            = 0x0000016d,
17853 PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY  = 0x0000016e,
17854 PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL  = 0x0000016f,
17855 PH_SC3_ARB_BUSY                          = 0x00000170,
17856 PH_SC3_ARB_PA_BUSY_SOP                   = 0x00000171,
17857 PH_SC3_ARB_EOP_POP_SYNC_POP              = 0x00000172,
17858 PH_SC3_ARB_EVENT_SYNC_POP                = 0x00000173,
17859 PH_SC3_PS_ENG_MULTICYCLE_BUBBLE          = 0x00000174,
17860 PH_SC3_EOP_SYNC_WINDOW                   = 0x00000175,
17861 PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x00000176,
17862 PH_SC3_BUSY_CNT_NOT_ZERO                 = 0x00000177,
17863 PH_SC3_SEND                              = 0x00000178,
17864 PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000179,
17865 PH_SC3_CREDIT_AT_MAX                     = 0x0000017a,
17866 PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x0000017b,
17867 PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION  = 0x0000017c,
17868 PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION  = 0x0000017d,
17869 PH_SC3_GFX_PIPE0_TO_1_TRANSITION         = 0x0000017e,
17870 PH_SC3_GFX_PIPE1_TO_0_TRANSITION         = 0x0000017f,
17871 PH_SC3_PA0_DATA_FIFO_RD                  = 0x00000180,
17872 PH_SC3_PA0_DATA_FIFO_WE                  = 0x00000181,
17873 PH_SC3_PA0_FIFO_EMPTY                    = 0x00000182,
17874 PH_SC3_PA0_FIFO_FULL                     = 0x00000183,
17875 PH_SC3_PA0_NULL_WE                       = 0x00000184,
17876 PH_SC3_PA0_EVENT_WE                      = 0x00000185,
17877 PH_SC3_PA0_FPOV_WE                       = 0x00000186,
17878 PH_SC3_PA0_LPOV_WE                       = 0x00000187,
17879 PH_SC3_PA0_EOP_WE                        = 0x00000188,
17880 PH_SC3_PA0_DATA_FIFO_EOP_RD              = 0x00000189,
17881 PH_SC3_PA0_EOPG_WE                       = 0x0000018a,
17882 PH_SC3_PA0_DEALLOC_4_0_RD                = 0x0000018b,
17883 PH_SC3_PA1_DATA_FIFO_RD                  = 0x0000018c,
17884 PH_SC3_PA1_DATA_FIFO_WE                  = 0x0000018d,
17885 PH_SC3_PA1_FIFO_EMPTY                    = 0x0000018e,
17886 PH_SC3_PA1_FIFO_FULL                     = 0x0000018f,
17887 PH_SC3_PA1_NULL_WE                       = 0x00000190,
17888 PH_SC3_PA1_EVENT_WE                      = 0x00000191,
17889 PH_SC3_PA1_FPOV_WE                       = 0x00000192,
17890 PH_SC3_PA1_LPOV_WE                       = 0x00000193,
17891 PH_SC3_PA1_EOP_WE                        = 0x00000194,
17892 PH_SC3_PA1_DATA_FIFO_EOP_RD              = 0x00000195,
17893 PH_SC3_PA1_EOPG_WE                       = 0x00000196,
17894 PH_SC3_PA1_DEALLOC_4_0_RD                = 0x00000197,
17895 PH_SC3_PA2_DATA_FIFO_RD                  = 0x00000198,
17896 PH_SC3_PA2_DATA_FIFO_WE                  = 0x00000199,
17897 PH_SC3_PA2_FIFO_EMPTY                    = 0x0000019a,
17898 PH_SC3_PA2_FIFO_FULL                     = 0x0000019b,
17899 PH_SC3_PA2_NULL_WE                       = 0x0000019c,
17900 PH_SC3_PA2_EVENT_WE                      = 0x0000019d,
17901 PH_SC3_PA2_FPOV_WE                       = 0x0000019e,
17902 PH_SC3_PA2_LPOV_WE                       = 0x0000019f,
17903 PH_SC3_PA2_EOP_WE                        = 0x000001a0,
17904 PH_SC3_PA2_DATA_FIFO_EOP_RD              = 0x000001a1,
17905 PH_SC3_PA2_EOPG_WE                       = 0x000001a2,
17906 PH_SC3_PA2_DEALLOC_4_0_RD                = 0x000001a3,
17907 PH_SC3_PA3_DATA_FIFO_RD                  = 0x000001a4,
17908 PH_SC3_PA3_DATA_FIFO_WE                  = 0x000001a5,
17909 PH_SC3_PA3_FIFO_EMPTY                    = 0x000001a6,
17910 PH_SC3_PA3_FIFO_FULL                     = 0x000001a7,
17911 PH_SC3_PA3_NULL_WE                       = 0x000001a8,
17912 PH_SC3_PA3_EVENT_WE                      = 0x000001a9,
17913 PH_SC3_PA3_FPOV_WE                       = 0x000001aa,
17914 PH_SC3_PA3_LPOV_WE                       = 0x000001ab,
17915 PH_SC3_PA3_EOP_WE                        = 0x000001ac,
17916 PH_SC3_PA3_DATA_FIFO_EOP_RD              = 0x000001ad,
17917 PH_SC3_PA3_EOPG_WE                       = 0x000001ae,
17918 PH_SC3_PA3_DEALLOC_4_0_RD                = 0x000001af,
17919 PH_SC3_PA4_DATA_FIFO_RD                  = 0x000001b0,
17920 PH_SC3_PA4_DATA_FIFO_WE                  = 0x000001b1,
17921 PH_SC3_PA4_FIFO_EMPTY                    = 0x000001b2,
17922 PH_SC3_PA4_FIFO_FULL                     = 0x000001b3,
17923 PH_SC3_PA4_NULL_WE                       = 0x000001b4,
17924 PH_SC3_PA4_EVENT_WE                      = 0x000001b5,
17925 PH_SC3_PA4_FPOV_WE                       = 0x000001b6,
17926 PH_SC3_PA4_LPOV_WE                       = 0x000001b7,
17927 PH_SC3_PA4_EOP_WE                        = 0x000001b8,
17928 PH_SC3_PA4_DATA_FIFO_EOP_RD              = 0x000001b9,
17929 PH_SC3_PA4_EOPG_WE                       = 0x000001ba,
17930 PH_SC3_PA4_DEALLOC_4_0_RD                = 0x000001bb,
17931 PH_SC3_PA5_DATA_FIFO_RD                  = 0x000001bc,
17932 PH_SC3_PA5_DATA_FIFO_WE                  = 0x000001bd,
17933 PH_SC3_PA5_FIFO_EMPTY                    = 0x000001be,
17934 PH_SC3_PA5_FIFO_FULL                     = 0x000001bf,
17935 PH_SC3_PA5_NULL_WE                       = 0x000001c0,
17936 PH_SC3_PA5_EVENT_WE                      = 0x000001c1,
17937 PH_SC3_PA5_FPOV_WE                       = 0x000001c2,
17938 PH_SC3_PA5_LPOV_WE                       = 0x000001c3,
17939 PH_SC3_PA5_EOP_WE                        = 0x000001c4,
17940 PH_SC3_PA5_DATA_FIFO_EOP_RD              = 0x000001c5,
17941 PH_SC3_PA5_EOPG_WE                       = 0x000001c6,
17942 PH_SC3_PA5_DEALLOC_4_0_RD                = 0x000001c7,
17943 PH_SC3_PA6_DATA_FIFO_RD                  = 0x000001c8,
17944 PH_SC3_PA6_DATA_FIFO_WE                  = 0x000001c9,
17945 PH_SC3_PA6_FIFO_EMPTY                    = 0x000001ca,
17946 PH_SC3_PA6_FIFO_FULL                     = 0x000001cb,
17947 PH_SC3_PA6_NULL_WE                       = 0x000001cc,
17948 PH_SC3_PA6_EVENT_WE                      = 0x000001cd,
17949 PH_SC3_PA6_FPOV_WE                       = 0x000001ce,
17950 PH_SC3_PA6_LPOV_WE                       = 0x000001cf,
17951 PH_SC3_PA6_EOP_WE                        = 0x000001d0,
17952 PH_SC3_PA6_DATA_FIFO_EOP_RD              = 0x000001d1,
17953 PH_SC3_PA6_EOPG_WE                       = 0x000001d2,
17954 PH_SC3_PA6_DEALLOC_4_0_RD                = 0x000001d3,
17955 PH_SC3_PA7_DATA_FIFO_RD                  = 0x000001d4,
17956 PH_SC3_PA7_DATA_FIFO_WE                  = 0x000001d5,
17957 PH_SC3_PA7_FIFO_EMPTY                    = 0x000001d6,
17958 PH_SC3_PA7_FIFO_FULL                     = 0x000001d7,
17959 PH_SC3_PA7_NULL_WE                       = 0x000001d8,
17960 PH_SC3_PA7_EVENT_WE                      = 0x000001d9,
17961 PH_SC3_PA7_FPOV_WE                       = 0x000001da,
17962 PH_SC3_PA7_LPOV_WE                       = 0x000001db,
17963 PH_SC3_PA7_EOP_WE                        = 0x000001dc,
17964 PH_SC3_PA7_DATA_FIFO_EOP_RD              = 0x000001dd,
17965 PH_SC3_PA7_EOPG_WE                       = 0x000001de,
17966 PH_SC3_PA7_DEALLOC_4_0_RD                = 0x000001df,
17967 PH_SC4_SRPS_WINDOW_VALID                 = 0x000001e0,
17968 PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x000001e1,
17969 PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES          = 0x000001e2,
17970 PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x000001e3,
17971 PH_SC4_ARB_STALLED_FROM_BELOW            = 0x000001e4,
17972 PH_SC4_ARB_STARVED_FROM_ABOVE            = 0x000001e5,
17973 PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY  = 0x000001e6,
17974 PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL  = 0x000001e7,
17975 PH_SC4_ARB_BUSY                          = 0x000001e8,
17976 PH_SC4_ARB_PA_BUSY_SOP                   = 0x000001e9,
17977 PH_SC4_ARB_EOP_POP_SYNC_POP              = 0x000001ea,
17978 PH_SC4_ARB_EVENT_SYNC_POP                = 0x000001eb,
17979 PH_SC4_PS_ENG_MULTICYCLE_BUBBLE          = 0x000001ec,
17980 PH_SC4_EOP_SYNC_WINDOW                   = 0x000001ed,
17981 PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x000001ee,
17982 PH_SC4_BUSY_CNT_NOT_ZERO                 = 0x000001ef,
17983 PH_SC4_SEND                              = 0x000001f0,
17984 PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000001f1,
17985 PH_SC4_CREDIT_AT_MAX                     = 0x000001f2,
17986 PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x000001f3,
17987 PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION  = 0x000001f4,
17988 PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION  = 0x000001f5,
17989 PH_SC4_GFX_PIPE0_TO_1_TRANSITION         = 0x000001f6,
17990 PH_SC4_GFX_PIPE1_TO_0_TRANSITION         = 0x000001f7,
17991 PH_SC4_PA0_DATA_FIFO_RD                  = 0x000001f8,
17992 PH_SC4_PA0_DATA_FIFO_WE                  = 0x000001f9,
17993 PH_SC4_PA0_FIFO_EMPTY                    = 0x000001fa,
17994 PH_SC4_PA0_FIFO_FULL                     = 0x000001fb,
17995 PH_SC4_PA0_NULL_WE                       = 0x000001fc,
17996 PH_SC4_PA0_EVENT_WE                      = 0x000001fd,
17997 PH_SC4_PA0_FPOV_WE                       = 0x000001fe,
17998 PH_SC4_PA0_LPOV_WE                       = 0x000001ff,
17999 PH_SC4_PA0_EOP_WE                        = 0x00000200,
18000 PH_SC4_PA0_DATA_FIFO_EOP_RD              = 0x00000201,
18001 PH_SC4_PA0_EOPG_WE                       = 0x00000202,
18002 PH_SC4_PA0_DEALLOC_4_0_RD                = 0x00000203,
18003 PH_SC4_PA1_DATA_FIFO_RD                  = 0x00000204,
18004 PH_SC4_PA1_DATA_FIFO_WE                  = 0x00000205,
18005 PH_SC4_PA1_FIFO_EMPTY                    = 0x00000206,
18006 PH_SC4_PA1_FIFO_FULL                     = 0x00000207,
18007 PH_SC4_PA1_NULL_WE                       = 0x00000208,
18008 PH_SC4_PA1_EVENT_WE                      = 0x00000209,
18009 PH_SC4_PA1_FPOV_WE                       = 0x0000020a,
18010 PH_SC4_PA1_LPOV_WE                       = 0x0000020b,
18011 PH_SC4_PA1_EOP_WE                        = 0x0000020c,
18012 PH_SC4_PA1_DATA_FIFO_EOP_RD              = 0x0000020d,
18013 PH_SC4_PA1_EOPG_WE                       = 0x0000020e,
18014 PH_SC4_PA1_DEALLOC_4_0_RD                = 0x0000020f,
18015 PH_SC4_PA2_DATA_FIFO_RD                  = 0x00000210,
18016 PH_SC4_PA2_DATA_FIFO_WE                  = 0x00000211,
18017 PH_SC4_PA2_FIFO_EMPTY                    = 0x00000212,
18018 PH_SC4_PA2_FIFO_FULL                     = 0x00000213,
18019 PH_SC4_PA2_NULL_WE                       = 0x00000214,
18020 PH_SC4_PA2_EVENT_WE                      = 0x00000215,
18021 PH_SC4_PA2_FPOV_WE                       = 0x00000216,
18022 PH_SC4_PA2_LPOV_WE                       = 0x00000217,
18023 PH_SC4_PA2_EOP_WE                        = 0x00000218,
18024 PH_SC4_PA2_DATA_FIFO_EOP_RD              = 0x00000219,
18025 PH_SC4_PA2_EOPG_WE                       = 0x0000021a,
18026 PH_SC4_PA2_DEALLOC_4_0_RD                = 0x0000021b,
18027 PH_SC4_PA3_DATA_FIFO_RD                  = 0x0000021c,
18028 PH_SC4_PA3_DATA_FIFO_WE                  = 0x0000021d,
18029 PH_SC4_PA3_FIFO_EMPTY                    = 0x0000021e,
18030 PH_SC4_PA3_FIFO_FULL                     = 0x0000021f,
18031 PH_SC4_PA3_NULL_WE                       = 0x00000220,
18032 PH_SC4_PA3_EVENT_WE                      = 0x00000221,
18033 PH_SC4_PA3_FPOV_WE                       = 0x00000222,
18034 PH_SC4_PA3_LPOV_WE                       = 0x00000223,
18035 PH_SC4_PA3_EOP_WE                        = 0x00000224,
18036 PH_SC4_PA3_DATA_FIFO_EOP_RD              = 0x00000225,
18037 PH_SC4_PA3_EOPG_WE                       = 0x00000226,
18038 PH_SC4_PA3_DEALLOC_4_0_RD                = 0x00000227,
18039 PH_SC4_PA4_DATA_FIFO_RD                  = 0x00000228,
18040 PH_SC4_PA4_DATA_FIFO_WE                  = 0x00000229,
18041 PH_SC4_PA4_FIFO_EMPTY                    = 0x0000022a,
18042 PH_SC4_PA4_FIFO_FULL                     = 0x0000022b,
18043 PH_SC4_PA4_NULL_WE                       = 0x0000022c,
18044 PH_SC4_PA4_EVENT_WE                      = 0x0000022d,
18045 PH_SC4_PA4_FPOV_WE                       = 0x0000022e,
18046 PH_SC4_PA4_LPOV_WE                       = 0x0000022f,
18047 PH_SC4_PA4_EOP_WE                        = 0x00000230,
18048 PH_SC4_PA4_DATA_FIFO_EOP_RD              = 0x00000231,
18049 PH_SC4_PA4_EOPG_WE                       = 0x00000232,
18050 PH_SC4_PA4_DEALLOC_4_0_RD                = 0x00000233,
18051 PH_SC4_PA5_DATA_FIFO_RD                  = 0x00000234,
18052 PH_SC4_PA5_DATA_FIFO_WE                  = 0x00000235,
18053 PH_SC4_PA5_FIFO_EMPTY                    = 0x00000236,
18054 PH_SC4_PA5_FIFO_FULL                     = 0x00000237,
18055 PH_SC4_PA5_NULL_WE                       = 0x00000238,
18056 PH_SC4_PA5_EVENT_WE                      = 0x00000239,
18057 PH_SC4_PA5_FPOV_WE                       = 0x0000023a,
18058 PH_SC4_PA5_LPOV_WE                       = 0x0000023b,
18059 PH_SC4_PA5_EOP_WE                        = 0x0000023c,
18060 PH_SC4_PA5_DATA_FIFO_EOP_RD              = 0x0000023d,
18061 PH_SC4_PA5_EOPG_WE                       = 0x0000023e,
18062 PH_SC4_PA5_DEALLOC_4_0_RD                = 0x0000023f,
18063 PH_SC4_PA6_DATA_FIFO_RD                  = 0x00000240,
18064 PH_SC4_PA6_DATA_FIFO_WE                  = 0x00000241,
18065 PH_SC4_PA6_FIFO_EMPTY                    = 0x00000242,
18066 PH_SC4_PA6_FIFO_FULL                     = 0x00000243,
18067 PH_SC4_PA6_NULL_WE                       = 0x00000244,
18068 PH_SC4_PA6_EVENT_WE                      = 0x00000245,
18069 PH_SC4_PA6_FPOV_WE                       = 0x00000246,
18070 PH_SC4_PA6_LPOV_WE                       = 0x00000247,
18071 PH_SC4_PA6_EOP_WE                        = 0x00000248,
18072 PH_SC4_PA6_DATA_FIFO_EOP_RD              = 0x00000249,
18073 PH_SC4_PA6_EOPG_WE                       = 0x0000024a,
18074 PH_SC4_PA6_DEALLOC_4_0_RD                = 0x0000024b,
18075 PH_SC4_PA7_DATA_FIFO_RD                  = 0x0000024c,
18076 PH_SC4_PA7_DATA_FIFO_WE                  = 0x0000024d,
18077 PH_SC4_PA7_FIFO_EMPTY                    = 0x0000024e,
18078 PH_SC4_PA7_FIFO_FULL                     = 0x0000024f,
18079 PH_SC4_PA7_NULL_WE                       = 0x00000250,
18080 PH_SC4_PA7_EVENT_WE                      = 0x00000251,
18081 PH_SC4_PA7_FPOV_WE                       = 0x00000252,
18082 PH_SC4_PA7_LPOV_WE                       = 0x00000253,
18083 PH_SC4_PA7_EOP_WE                        = 0x00000254,
18084 PH_SC4_PA7_DATA_FIFO_EOP_RD              = 0x00000255,
18085 PH_SC4_PA7_EOPG_WE                       = 0x00000256,
18086 PH_SC4_PA7_DEALLOC_4_0_RD                = 0x00000257,
18087 PH_SC5_SRPS_WINDOW_VALID                 = 0x00000258,
18088 PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000259,
18089 PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES          = 0x0000025a,
18090 PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x0000025b,
18091 PH_SC5_ARB_STALLED_FROM_BELOW            = 0x0000025c,
18092 PH_SC5_ARB_STARVED_FROM_ABOVE            = 0x0000025d,
18093 PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY  = 0x0000025e,
18094 PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL  = 0x0000025f,
18095 PH_SC5_ARB_BUSY                          = 0x00000260,
18096 PH_SC5_ARB_PA_BUSY_SOP                   = 0x00000261,
18097 PH_SC5_ARB_EOP_POP_SYNC_POP              = 0x00000262,
18098 PH_SC5_ARB_EVENT_SYNC_POP                = 0x00000263,
18099 PH_SC5_PS_ENG_MULTICYCLE_BUBBLE          = 0x00000264,
18100 PH_SC5_EOP_SYNC_WINDOW                   = 0x00000265,
18101 PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x00000266,
18102 PH_SC5_BUSY_CNT_NOT_ZERO                 = 0x00000267,
18103 PH_SC5_SEND                              = 0x00000268,
18104 PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000269,
18105 PH_SC5_CREDIT_AT_MAX                     = 0x0000026a,
18106 PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x0000026b,
18107 PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION  = 0x0000026c,
18108 PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION  = 0x0000026d,
18109 PH_SC5_GFX_PIPE0_TO_1_TRANSITION         = 0x0000026e,
18110 PH_SC5_GFX_PIPE1_TO_0_TRANSITION         = 0x0000026f,
18111 PH_SC5_PA0_DATA_FIFO_RD                  = 0x00000270,
18112 PH_SC5_PA0_DATA_FIFO_WE                  = 0x00000271,
18113 PH_SC5_PA0_FIFO_EMPTY                    = 0x00000272,
18114 PH_SC5_PA0_FIFO_FULL                     = 0x00000273,
18115 PH_SC5_PA0_NULL_WE                       = 0x00000274,
18116 PH_SC5_PA0_EVENT_WE                      = 0x00000275,
18117 PH_SC5_PA0_FPOV_WE                       = 0x00000276,
18118 PH_SC5_PA0_LPOV_WE                       = 0x00000277,
18119 PH_SC5_PA0_EOP_WE                        = 0x00000278,
18120 PH_SC5_PA0_DATA_FIFO_EOP_RD              = 0x00000279,
18121 PH_SC5_PA0_EOPG_WE                       = 0x0000027a,
18122 PH_SC5_PA0_DEALLOC_4_0_RD                = 0x0000027b,
18123 PH_SC5_PA1_DATA_FIFO_RD                  = 0x0000027c,
18124 PH_SC5_PA1_DATA_FIFO_WE                  = 0x0000027d,
18125 PH_SC5_PA1_FIFO_EMPTY                    = 0x0000027e,
18126 PH_SC5_PA1_FIFO_FULL                     = 0x0000027f,
18127 PH_SC5_PA1_NULL_WE                       = 0x00000280,
18128 PH_SC5_PA1_EVENT_WE                      = 0x00000281,
18129 PH_SC5_PA1_FPOV_WE                       = 0x00000282,
18130 PH_SC5_PA1_LPOV_WE                       = 0x00000283,
18131 PH_SC5_PA1_EOP_WE                        = 0x00000284,
18132 PH_SC5_PA1_DATA_FIFO_EOP_RD              = 0x00000285,
18133 PH_SC5_PA1_EOPG_WE                       = 0x00000286,
18134 PH_SC5_PA1_DEALLOC_4_0_RD                = 0x00000287,
18135 PH_SC5_PA2_DATA_FIFO_RD                  = 0x00000288,
18136 PH_SC5_PA2_DATA_FIFO_WE                  = 0x00000289,
18137 PH_SC5_PA2_FIFO_EMPTY                    = 0x0000028a,
18138 PH_SC5_PA2_FIFO_FULL                     = 0x0000028b,
18139 PH_SC5_PA2_NULL_WE                       = 0x0000028c,
18140 PH_SC5_PA2_EVENT_WE                      = 0x0000028d,
18141 PH_SC5_PA2_FPOV_WE                       = 0x0000028e,
18142 PH_SC5_PA2_LPOV_WE                       = 0x0000028f,
18143 PH_SC5_PA2_EOP_WE                        = 0x00000290,
18144 PH_SC5_PA2_DATA_FIFO_EOP_RD              = 0x00000291,
18145 PH_SC5_PA2_EOPG_WE                       = 0x00000292,
18146 PH_SC5_PA2_DEALLOC_4_0_RD                = 0x00000293,
18147 PH_SC5_PA3_DATA_FIFO_RD                  = 0x00000294,
18148 PH_SC5_PA3_DATA_FIFO_WE                  = 0x00000295,
18149 PH_SC5_PA3_FIFO_EMPTY                    = 0x00000296,
18150 PH_SC5_PA3_FIFO_FULL                     = 0x00000297,
18151 PH_SC5_PA3_NULL_WE                       = 0x00000298,
18152 PH_SC5_PA3_EVENT_WE                      = 0x00000299,
18153 PH_SC5_PA3_FPOV_WE                       = 0x0000029a,
18154 PH_SC5_PA3_LPOV_WE                       = 0x0000029b,
18155 PH_SC5_PA3_EOP_WE                        = 0x0000029c,
18156 PH_SC5_PA3_DATA_FIFO_EOP_RD              = 0x0000029d,
18157 PH_SC5_PA3_EOPG_WE                       = 0x0000029e,
18158 PH_SC5_PA3_DEALLOC_4_0_RD                = 0x0000029f,
18159 PH_SC5_PA4_DATA_FIFO_RD                  = 0x000002a0,
18160 PH_SC5_PA4_DATA_FIFO_WE                  = 0x000002a1,
18161 PH_SC5_PA4_FIFO_EMPTY                    = 0x000002a2,
18162 PH_SC5_PA4_FIFO_FULL                     = 0x000002a3,
18163 PH_SC5_PA4_NULL_WE                       = 0x000002a4,
18164 PH_SC5_PA4_EVENT_WE                      = 0x000002a5,
18165 PH_SC5_PA4_FPOV_WE                       = 0x000002a6,
18166 PH_SC5_PA4_LPOV_WE                       = 0x000002a7,
18167 PH_SC5_PA4_EOP_WE                        = 0x000002a8,
18168 PH_SC5_PA4_DATA_FIFO_EOP_RD              = 0x000002a9,
18169 PH_SC5_PA4_EOPG_WE                       = 0x000002aa,
18170 PH_SC5_PA4_DEALLOC_4_0_RD                = 0x000002ab,
18171 PH_SC5_PA5_DATA_FIFO_RD                  = 0x000002ac,
18172 PH_SC5_PA5_DATA_FIFO_WE                  = 0x000002ad,
18173 PH_SC5_PA5_FIFO_EMPTY                    = 0x000002ae,
18174 PH_SC5_PA5_FIFO_FULL                     = 0x000002af,
18175 PH_SC5_PA5_NULL_WE                       = 0x000002b0,
18176 PH_SC5_PA5_EVENT_WE                      = 0x000002b1,
18177 PH_SC5_PA5_FPOV_WE                       = 0x000002b2,
18178 PH_SC5_PA5_LPOV_WE                       = 0x000002b3,
18179 PH_SC5_PA5_EOP_WE                        = 0x000002b4,
18180 PH_SC5_PA5_DATA_FIFO_EOP_RD              = 0x000002b5,
18181 PH_SC5_PA5_EOPG_WE                       = 0x000002b6,
18182 PH_SC5_PA5_DEALLOC_4_0_RD                = 0x000002b7,
18183 PH_SC5_PA6_DATA_FIFO_RD                  = 0x000002b8,
18184 PH_SC5_PA6_DATA_FIFO_WE                  = 0x000002b9,
18185 PH_SC5_PA6_FIFO_EMPTY                    = 0x000002ba,
18186 PH_SC5_PA6_FIFO_FULL                     = 0x000002bb,
18187 PH_SC5_PA6_NULL_WE                       = 0x000002bc,
18188 PH_SC5_PA6_EVENT_WE                      = 0x000002bd,
18189 PH_SC5_PA6_FPOV_WE                       = 0x000002be,
18190 PH_SC5_PA6_LPOV_WE                       = 0x000002bf,
18191 PH_SC5_PA6_EOP_WE                        = 0x000002c0,
18192 PH_SC5_PA6_DATA_FIFO_EOP_RD              = 0x000002c1,
18193 PH_SC5_PA6_EOPG_WE                       = 0x000002c2,
18194 PH_SC5_PA6_DEALLOC_4_0_RD                = 0x000002c3,
18195 PH_SC5_PA7_DATA_FIFO_RD                  = 0x000002c4,
18196 PH_SC5_PA7_DATA_FIFO_WE                  = 0x000002c5,
18197 PH_SC5_PA7_FIFO_EMPTY                    = 0x000002c6,
18198 PH_SC5_PA7_FIFO_FULL                     = 0x000002c7,
18199 PH_SC5_PA7_NULL_WE                       = 0x000002c8,
18200 PH_SC5_PA7_EVENT_WE                      = 0x000002c9,
18201 PH_SC5_PA7_FPOV_WE                       = 0x000002ca,
18202 PH_SC5_PA7_LPOV_WE                       = 0x000002cb,
18203 PH_SC5_PA7_EOP_WE                        = 0x000002cc,
18204 PH_SC5_PA7_DATA_FIFO_EOP_RD              = 0x000002cd,
18205 PH_SC5_PA7_EOPG_WE                       = 0x000002ce,
18206 PH_SC5_PA7_DEALLOC_4_0_RD                = 0x000002cf,
18207 PH_SC6_SRPS_WINDOW_VALID                 = 0x000002d0,
18208 PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x000002d1,
18209 PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES          = 0x000002d2,
18210 PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x000002d3,
18211 PH_SC6_ARB_STALLED_FROM_BELOW            = 0x000002d4,
18212 PH_SC6_ARB_STARVED_FROM_ABOVE            = 0x000002d5,
18213 PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY  = 0x000002d6,
18214 PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL  = 0x000002d7,
18215 PH_SC6_ARB_BUSY                          = 0x000002d8,
18216 PH_SC6_ARB_PA_BUSY_SOP                   = 0x000002d9,
18217 PH_SC6_ARB_EOP_POP_SYNC_POP              = 0x000002da,
18218 PH_SC6_ARB_EVENT_SYNC_POP                = 0x000002db,
18219 PH_SC6_PS_ENG_MULTICYCLE_BUBBLE          = 0x000002dc,
18220 PH_SC6_EOP_SYNC_WINDOW                   = 0x000002dd,
18221 PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x000002de,
18222 PH_SC6_BUSY_CNT_NOT_ZERO                 = 0x000002df,
18223 PH_SC6_SEND                              = 0x000002e0,
18224 PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000002e1,
18225 PH_SC6_CREDIT_AT_MAX                     = 0x000002e2,
18226 PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x000002e3,
18227 PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION  = 0x000002e4,
18228 PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION  = 0x000002e5,
18229 PH_SC6_GFX_PIPE0_TO_1_TRANSITION         = 0x000002e6,
18230 PH_SC6_GFX_PIPE1_TO_0_TRANSITION         = 0x000002e7,
18231 PH_SC6_PA0_DATA_FIFO_RD                  = 0x000002e8,
18232 PH_SC6_PA0_DATA_FIFO_WE                  = 0x000002e9,
18233 PH_SC6_PA0_FIFO_EMPTY                    = 0x000002ea,
18234 PH_SC6_PA0_FIFO_FULL                     = 0x000002eb,
18235 PH_SC6_PA0_NULL_WE                       = 0x000002ec,
18236 PH_SC6_PA0_EVENT_WE                      = 0x000002ed,
18237 PH_SC6_PA0_FPOV_WE                       = 0x000002ee,
18238 PH_SC6_PA0_LPOV_WE                       = 0x000002ef,
18239 PH_SC6_PA0_EOP_WE                        = 0x000002f0,
18240 PH_SC6_PA0_DATA_FIFO_EOP_RD              = 0x000002f1,
18241 PH_SC6_PA0_EOPG_WE                       = 0x000002f2,
18242 PH_SC6_PA0_DEALLOC_4_0_RD                = 0x000002f3,
18243 PH_SC6_PA1_DATA_FIFO_RD                  = 0x000002f4,
18244 PH_SC6_PA1_DATA_FIFO_WE                  = 0x000002f5,
18245 PH_SC6_PA1_FIFO_EMPTY                    = 0x000002f6,
18246 PH_SC6_PA1_FIFO_FULL                     = 0x000002f7,
18247 PH_SC6_PA1_NULL_WE                       = 0x000002f8,
18248 PH_SC6_PA1_EVENT_WE                      = 0x000002f9,
18249 PH_SC6_PA1_FPOV_WE                       = 0x000002fa,
18250 PH_SC6_PA1_LPOV_WE                       = 0x000002fb,
18251 PH_SC6_PA1_EOP_WE                        = 0x000002fc,
18252 PH_SC6_PA1_DATA_FIFO_EOP_RD              = 0x000002fd,
18253 PH_SC6_PA1_EOPG_WE                       = 0x000002fe,
18254 PH_SC6_PA1_DEALLOC_4_0_RD                = 0x000002ff,
18255 PH_SC6_PA2_DATA_FIFO_RD                  = 0x00000300,
18256 PH_SC6_PA2_DATA_FIFO_WE                  = 0x00000301,
18257 PH_SC6_PA2_FIFO_EMPTY                    = 0x00000302,
18258 PH_SC6_PA2_FIFO_FULL                     = 0x00000303,
18259 PH_SC6_PA2_NULL_WE                       = 0x00000304,
18260 PH_SC6_PA2_EVENT_WE                      = 0x00000305,
18261 PH_SC6_PA2_FPOV_WE                       = 0x00000306,
18262 PH_SC6_PA2_LPOV_WE                       = 0x00000307,
18263 PH_SC6_PA2_EOP_WE                        = 0x00000308,
18264 PH_SC6_PA2_DATA_FIFO_EOP_RD              = 0x00000309,
18265 PH_SC6_PA2_EOPG_WE                       = 0x0000030a,
18266 PH_SC6_PA2_DEALLOC_4_0_RD                = 0x0000030b,
18267 PH_SC6_PA3_DATA_FIFO_RD                  = 0x0000030c,
18268 PH_SC6_PA3_DATA_FIFO_WE                  = 0x0000030d,
18269 PH_SC6_PA3_FIFO_EMPTY                    = 0x0000030e,
18270 PH_SC6_PA3_FIFO_FULL                     = 0x0000030f,
18271 PH_SC6_PA3_NULL_WE                       = 0x00000310,
18272 PH_SC6_PA3_EVENT_WE                      = 0x00000311,
18273 PH_SC6_PA3_FPOV_WE                       = 0x00000312,
18274 PH_SC6_PA3_LPOV_WE                       = 0x00000313,
18275 PH_SC6_PA3_EOP_WE                        = 0x00000314,
18276 PH_SC6_PA3_DATA_FIFO_EOP_RD              = 0x00000315,
18277 PH_SC6_PA3_EOPG_WE                       = 0x00000316,
18278 PH_SC6_PA3_DEALLOC_4_0_RD                = 0x00000317,
18279 PH_SC6_PA4_DATA_FIFO_RD                  = 0x00000318,
18280 PH_SC6_PA4_DATA_FIFO_WE                  = 0x00000319,
18281 PH_SC6_PA4_FIFO_EMPTY                    = 0x0000031a,
18282 PH_SC6_PA4_FIFO_FULL                     = 0x0000031b,
18283 PH_SC6_PA4_NULL_WE                       = 0x0000031c,
18284 PH_SC6_PA4_EVENT_WE                      = 0x0000031d,
18285 PH_SC6_PA4_FPOV_WE                       = 0x0000031e,
18286 PH_SC6_PA4_LPOV_WE                       = 0x0000031f,
18287 PH_SC6_PA4_EOP_WE                        = 0x00000320,
18288 PH_SC6_PA4_DATA_FIFO_EOP_RD              = 0x00000321,
18289 PH_SC6_PA4_EOPG_WE                       = 0x00000322,
18290 PH_SC6_PA4_DEALLOC_4_0_RD                = 0x00000323,
18291 PH_SC6_PA5_DATA_FIFO_RD                  = 0x00000324,
18292 PH_SC6_PA5_DATA_FIFO_WE                  = 0x00000325,
18293 PH_SC6_PA5_FIFO_EMPTY                    = 0x00000326,
18294 PH_SC6_PA5_FIFO_FULL                     = 0x00000327,
18295 PH_SC6_PA5_NULL_WE                       = 0x00000328,
18296 PH_SC6_PA5_EVENT_WE                      = 0x00000329,
18297 PH_SC6_PA5_FPOV_WE                       = 0x0000032a,
18298 PH_SC6_PA5_LPOV_WE                       = 0x0000032b,
18299 PH_SC6_PA5_EOP_WE                        = 0x0000032c,
18300 PH_SC6_PA5_DATA_FIFO_EOP_RD              = 0x0000032d,
18301 PH_SC6_PA5_EOPG_WE                       = 0x0000032e,
18302 PH_SC6_PA5_DEALLOC_4_0_RD                = 0x0000032f,
18303 PH_SC6_PA6_DATA_FIFO_RD                  = 0x00000330,
18304 PH_SC6_PA6_DATA_FIFO_WE                  = 0x00000331,
18305 PH_SC6_PA6_FIFO_EMPTY                    = 0x00000332,
18306 PH_SC6_PA6_FIFO_FULL                     = 0x00000333,
18307 PH_SC6_PA6_NULL_WE                       = 0x00000334,
18308 PH_SC6_PA6_EVENT_WE                      = 0x00000335,
18309 PH_SC6_PA6_FPOV_WE                       = 0x00000336,
18310 PH_SC6_PA6_LPOV_WE                       = 0x00000337,
18311 PH_SC6_PA6_EOP_WE                        = 0x00000338,
18312 PH_SC6_PA6_DATA_FIFO_EOP_RD              = 0x00000339,
18313 PH_SC6_PA6_EOPG_WE                       = 0x0000033a,
18314 PH_SC6_PA6_DEALLOC_4_0_RD                = 0x0000033b,
18315 PH_SC6_PA7_DATA_FIFO_RD                  = 0x0000033c,
18316 PH_SC6_PA7_DATA_FIFO_WE                  = 0x0000033d,
18317 PH_SC6_PA7_FIFO_EMPTY                    = 0x0000033e,
18318 PH_SC6_PA7_FIFO_FULL                     = 0x0000033f,
18319 PH_SC6_PA7_NULL_WE                       = 0x00000340,
18320 PH_SC6_PA7_EVENT_WE                      = 0x00000341,
18321 PH_SC6_PA7_FPOV_WE                       = 0x00000342,
18322 PH_SC6_PA7_LPOV_WE                       = 0x00000343,
18323 PH_SC6_PA7_EOP_WE                        = 0x00000344,
18324 PH_SC6_PA7_DATA_FIFO_EOP_RD              = 0x00000345,
18325 PH_SC6_PA7_EOPG_WE                       = 0x00000346,
18326 PH_SC6_PA7_DEALLOC_4_0_RD                = 0x00000347,
18327 PH_SC7_SRPS_WINDOW_VALID                 = 0x00000348,
18328 PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000349,
18329 PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES          = 0x0000034a,
18330 PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x0000034b,
18331 PH_SC7_ARB_STALLED_FROM_BELOW            = 0x0000034c,
18332 PH_SC7_ARB_STARVED_FROM_ABOVE            = 0x0000034d,
18333 PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY  = 0x0000034e,
18334 PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL  = 0x0000034f,
18335 PH_SC7_ARB_BUSY                          = 0x00000350,
18336 PH_SC7_ARB_PA_BUSY_SOP                   = 0x00000351,
18337 PH_SC7_ARB_EOP_POP_SYNC_POP              = 0x00000352,
18338 PH_SC7_ARB_EVENT_SYNC_POP                = 0x00000353,
18339 PH_SC7_PS_ENG_MULTICYCLE_BUBBLE          = 0x00000354,
18340 PH_SC7_EOP_SYNC_WINDOW                   = 0x00000355,
18341 PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x00000356,
18342 PH_SC7_BUSY_CNT_NOT_ZERO                 = 0x00000357,
18343 PH_SC7_SEND                              = 0x00000358,
18344 PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000359,
18345 PH_SC7_CREDIT_AT_MAX                     = 0x0000035a,
18346 PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x0000035b,
18347 PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION  = 0x0000035c,
18348 PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION  = 0x0000035d,
18349 PH_SC7_GFX_PIPE0_TO_1_TRANSITION         = 0x0000035e,
18350 PH_SC7_GFX_PIPE1_TO_0_TRANSITION         = 0x0000035f,
18351 PH_SC7_PA0_DATA_FIFO_RD                  = 0x00000360,
18352 PH_SC7_PA0_DATA_FIFO_WE                  = 0x00000361,
18353 PH_SC7_PA0_FIFO_EMPTY                    = 0x00000362,
18354 PH_SC7_PA0_FIFO_FULL                     = 0x00000363,
18355 PH_SC7_PA0_NULL_WE                       = 0x00000364,
18356 PH_SC7_PA0_EVENT_WE                      = 0x00000365,
18357 PH_SC7_PA0_FPOV_WE                       = 0x00000366,
18358 PH_SC7_PA0_LPOV_WE                       = 0x00000367,
18359 PH_SC7_PA0_EOP_WE                        = 0x00000368,
18360 PH_SC7_PA0_DATA_FIFO_EOP_RD              = 0x00000369,
18361 PH_SC7_PA0_EOPG_WE                       = 0x0000036a,
18362 PH_SC7_PA0_DEALLOC_4_0_RD                = 0x0000036b,
18363 PH_SC7_PA1_DATA_FIFO_RD                  = 0x0000036c,
18364 PH_SC7_PA1_DATA_FIFO_WE                  = 0x0000036d,
18365 PH_SC7_PA1_FIFO_EMPTY                    = 0x0000036e,
18366 PH_SC7_PA1_FIFO_FULL                     = 0x0000036f,
18367 PH_SC7_PA1_NULL_WE                       = 0x00000370,
18368 PH_SC7_PA1_EVENT_WE                      = 0x00000371,
18369 PH_SC7_PA1_FPOV_WE                       = 0x00000372,
18370 PH_SC7_PA1_LPOV_WE                       = 0x00000373,
18371 PH_SC7_PA1_EOP_WE                        = 0x00000374,
18372 PH_SC7_PA1_DATA_FIFO_EOP_RD              = 0x00000375,
18373 PH_SC7_PA1_EOPG_WE                       = 0x00000376,
18374 PH_SC7_PA1_DEALLOC_4_0_RD                = 0x00000377,
18375 PH_SC7_PA2_DATA_FIFO_RD                  = 0x00000378,
18376 PH_SC7_PA2_DATA_FIFO_WE                  = 0x00000379,
18377 PH_SC7_PA2_FIFO_EMPTY                    = 0x0000037a,
18378 PH_SC7_PA2_FIFO_FULL                     = 0x0000037b,
18379 PH_SC7_PA2_NULL_WE                       = 0x0000037c,
18380 PH_SC7_PA2_EVENT_WE                      = 0x0000037d,
18381 PH_SC7_PA2_FPOV_WE                       = 0x0000037e,
18382 PH_SC7_PA2_LPOV_WE                       = 0x0000037f,
18383 PH_SC7_PA2_EOP_WE                        = 0x00000380,
18384 PH_SC7_PA2_DATA_FIFO_EOP_RD              = 0x00000381,
18385 PH_SC7_PA2_EOPG_WE                       = 0x00000382,
18386 PH_SC7_PA2_DEALLOC_4_0_RD                = 0x00000383,
18387 PH_SC7_PA3_DATA_FIFO_RD                  = 0x00000384,
18388 PH_SC7_PA3_DATA_FIFO_WE                  = 0x00000385,
18389 PH_SC7_PA3_FIFO_EMPTY                    = 0x00000386,
18390 PH_SC7_PA3_FIFO_FULL                     = 0x00000387,
18391 PH_SC7_PA3_NULL_WE                       = 0x00000388,
18392 PH_SC7_PA3_EVENT_WE                      = 0x00000389,
18393 PH_SC7_PA3_FPOV_WE                       = 0x0000038a,
18394 PH_SC7_PA3_LPOV_WE                       = 0x0000038b,
18395 PH_SC7_PA3_EOP_WE                        = 0x0000038c,
18396 PH_SC7_PA3_DATA_FIFO_EOP_RD              = 0x0000038d,
18397 PH_SC7_PA3_EOPG_WE                       = 0x0000038e,
18398 PH_SC7_PA3_DEALLOC_4_0_RD                = 0x0000038f,
18399 PH_SC7_PA4_DATA_FIFO_RD                  = 0x00000390,
18400 PH_SC7_PA4_DATA_FIFO_WE                  = 0x00000391,
18401 PH_SC7_PA4_FIFO_EMPTY                    = 0x00000392,
18402 PH_SC7_PA4_FIFO_FULL                     = 0x00000393,
18403 PH_SC7_PA4_NULL_WE                       = 0x00000394,
18404 PH_SC7_PA4_EVENT_WE                      = 0x00000395,
18405 PH_SC7_PA4_FPOV_WE                       = 0x00000396,
18406 PH_SC7_PA4_LPOV_WE                       = 0x00000397,
18407 PH_SC7_PA4_EOP_WE                        = 0x00000398,
18408 PH_SC7_PA4_DATA_FIFO_EOP_RD              = 0x00000399,
18409 PH_SC7_PA4_EOPG_WE                       = 0x0000039a,
18410 PH_SC7_PA4_DEALLOC_4_0_RD                = 0x0000039b,
18411 PH_SC7_PA5_DATA_FIFO_RD                  = 0x0000039c,
18412 PH_SC7_PA5_DATA_FIFO_WE                  = 0x0000039d,
18413 PH_SC7_PA5_FIFO_EMPTY                    = 0x0000039e,
18414 PH_SC7_PA5_FIFO_FULL                     = 0x0000039f,
18415 PH_SC7_PA5_NULL_WE                       = 0x000003a0,
18416 PH_SC7_PA5_EVENT_WE                      = 0x000003a1,
18417 PH_SC7_PA5_FPOV_WE                       = 0x000003a2,
18418 PH_SC7_PA5_LPOV_WE                       = 0x000003a3,
18419 PH_SC7_PA5_EOP_WE                        = 0x000003a4,
18420 PH_SC7_PA5_DATA_FIFO_EOP_RD              = 0x000003a5,
18421 PH_SC7_PA5_EOPG_WE                       = 0x000003a6,
18422 PH_SC7_PA5_DEALLOC_4_0_RD                = 0x000003a7,
18423 PH_SC7_PA6_DATA_FIFO_RD                  = 0x000003a8,
18424 PH_SC7_PA6_DATA_FIFO_WE                  = 0x000003a9,
18425 PH_SC7_PA6_FIFO_EMPTY                    = 0x000003aa,
18426 PH_SC7_PA6_FIFO_FULL                     = 0x000003ab,
18427 PH_SC7_PA6_NULL_WE                       = 0x000003ac,
18428 PH_SC7_PA6_EVENT_WE                      = 0x000003ad,
18429 PH_SC7_PA6_FPOV_WE                       = 0x000003ae,
18430 PH_SC7_PA6_LPOV_WE                       = 0x000003af,
18431 PH_SC7_PA6_EOP_WE                        = 0x000003b0,
18432 PH_SC7_PA6_DATA_FIFO_EOP_RD              = 0x000003b1,
18433 PH_SC7_PA6_EOPG_WE                       = 0x000003b2,
18434 PH_SC7_PA6_DEALLOC_4_0_RD                = 0x000003b3,
18435 PH_SC7_PA7_DATA_FIFO_RD                  = 0x000003b4,
18436 PH_SC7_PA7_DATA_FIFO_WE                  = 0x000003b5,
18437 PH_SC7_PA7_FIFO_EMPTY                    = 0x000003b6,
18438 PH_SC7_PA7_FIFO_FULL                     = 0x000003b7,
18439 PH_SC7_PA7_NULL_WE                       = 0x000003b8,
18440 PH_SC7_PA7_EVENT_WE                      = 0x000003b9,
18441 PH_SC7_PA7_FPOV_WE                       = 0x000003ba,
18442 PH_SC7_PA7_LPOV_WE                       = 0x000003bb,
18443 PH_SC7_PA7_EOP_WE                        = 0x000003bc,
18444 PH_SC7_PA7_DATA_FIFO_EOP_RD              = 0x000003bd,
18445 PH_SC7_PA7_EOPG_WE                       = 0x000003be,
18446 PH_SC7_PA7_DEALLOC_4_0_RD                = 0x000003bf,
18447 } PH_PERFCNT_SEL;
18448 
18449 /*
18450  * SU_PERFCNT_SEL enum
18451  */
18452 
18453 typedef enum SU_PERFCNT_SEL {
18454 PERF_PAPC_PASX_REQ                       = 0x00000000,
18455 PERF_PAPC_PASX_DISABLE_PIPE              = 0x00000001,
18456 PERF_PAPC_PASX_FIRST_VECTOR              = 0x00000002,
18457 PERF_PAPC_PASX_SECOND_VECTOR             = 0x00000003,
18458 PERF_PAPC_PASX_FIRST_DEAD                = 0x00000004,
18459 PERF_PAPC_PASX_SECOND_DEAD               = 0x00000005,
18460 PERF_PAPC_PASX_VTX_KILL_DISCARD          = 0x00000006,
18461 PERF_PAPC_PASX_VTX_NAN_DISCARD           = 0x00000007,
18462 PERF_PAPC_PA_INPUT_PRIM                  = 0x00000008,
18463 PERF_PAPC_PA_INPUT_NULL_PRIM             = 0x00000009,
18464 PERF_PAPC_PA_INPUT_EVENT_FLAG            = 0x0000000a,
18465 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT       = 0x0000000b,
18466 PERF_PAPC_PA_INPUT_END_OF_PACKET         = 0x0000000c,
18467 PERF_PAPC_PA_INPUT_EXTENDED_EVENT        = 0x0000000d,
18468 PERF_PAPC_CLPR_CULL_PRIM                 = 0x0000000e,
18469 PERF_PAPC_CLPR_VVUCP_CULL_PRIM           = 0x0000000f,
18470 PERF_PAPC_CLPR_VV_CULL_PRIM              = 0x00000010,
18471 PERF_PAPC_CLPR_UCP_CULL_PRIM             = 0x00000011,
18472 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM        = 0x00000012,
18473 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM         = 0x00000013,
18474 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM         = 0x00000014,
18475 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM           = 0x00000015,
18476 PERF_PAPC_CLPR_VV_CLIP_PRIM              = 0x00000016,
18477 PERF_PAPC_CLPR_UCP_CLIP_PRIM             = 0x00000017,
18478 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE      = 0x00000018,
18479 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1          = 0x00000019,
18480 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2          = 0x0000001a,
18481 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3          = 0x0000001b,
18482 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4          = 0x0000001c,
18483 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8        = 0x0000001d,
18484 PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12       = 0x0000001e,
18485 PERF_PAPC_CLPR_CLIP_PLANE_NEAR           = 0x0000001f,
18486 PERF_PAPC_CLPR_CLIP_PLANE_FAR            = 0x00000020,
18487 PERF_PAPC_CLPR_CLIP_PLANE_LEFT           = 0x00000021,
18488 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT          = 0x00000022,
18489 PERF_PAPC_CLPR_CLIP_PLANE_TOP            = 0x00000023,
18490 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM         = 0x00000024,
18491 PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM        = 0x00000025,
18492 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM     = 0x00000026,
18493 PERF_PAPC_CLSM_NULL_PRIM                 = 0x00000027,
18494 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM      = 0x00000028,
18495 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM         = 0x00000029,
18496 PERF_PAPC_CLSM_OUT_PRIM_CNT_1            = 0x0000002a,
18497 PERF_PAPC_CLSM_OUT_PRIM_CNT_2            = 0x0000002b,
18498 PERF_PAPC_CLSM_OUT_PRIM_CNT_3            = 0x0000002c,
18499 PERF_PAPC_CLSM_OUT_PRIM_CNT_4            = 0x0000002d,
18500 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8          = 0x0000002e,
18501 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13         = 0x0000002f,
18502 PERF_PAPC_CLIPGA_VTE_KILL_PRIM           = 0x00000030,
18503 PERF_PAPC_SU_INPUT_PRIM                  = 0x00000031,
18504 PERF_PAPC_SU_INPUT_CLIP_PRIM             = 0x00000032,
18505 PERF_PAPC_SU_INPUT_NULL_PRIM             = 0x00000033,
18506 PERF_PAPC_SU_INPUT_PRIM_DUAL             = 0x00000034,
18507 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL        = 0x00000035,
18508 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM         = 0x00000036,
18509 PERF_PAPC_SU_BACK_FACE_CULL_PRIM         = 0x00000037,
18510 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM        = 0x00000038,
18511 PERF_PAPC_SU_POLYMODE_FACE_CULL          = 0x00000039,
18512 PERF_PAPC_SU_POLYMODE_BACK_CULL          = 0x0000003a,
18513 PERF_PAPC_SU_POLYMODE_FRONT_CULL         = 0x0000003b,
18514 PERF_PAPC_SU_POLYMODE_INVALID_FILL       = 0x0000003c,
18515 PERF_PAPC_SU_OUTPUT_PRIM                 = 0x0000003d,
18516 PERF_PAPC_SU_OUTPUT_CLIP_PRIM            = 0x0000003e,
18517 PERF_PAPC_SU_OUTPUT_NULL_PRIM            = 0x0000003f,
18518 PERF_PAPC_SU_OUTPUT_EVENT_FLAG           = 0x00000040,
18519 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT      = 0x00000041,
18520 PERF_PAPC_SU_OUTPUT_END_OF_PACKET        = 0x00000042,
18521 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE        = 0x00000043,
18522 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK        = 0x00000044,
18523 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT       = 0x00000045,
18524 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE      = 0x00000046,
18525 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK      = 0x00000047,
18526 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT     = 0x00000048,
18527 PERF_PAPC_SU_OUTPUT_PRIM_DUAL            = 0x00000049,
18528 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL       = 0x0000004a,
18529 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL        = 0x0000004b,
18530 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL   = 0x0000004c,
18531 PERF_PAPC_PASX_REQ_IDLE                  = 0x0000004d,
18532 PERF_PAPC_PASX_REQ_BUSY                  = 0x0000004e,
18533 PERF_PAPC_PASX_REQ_STALLED               = 0x0000004f,
18534 PERF_PAPC_PASX_REC_IDLE                  = 0x00000050,
18535 PERF_PAPC_PASX_REC_BUSY                  = 0x00000051,
18536 PERF_PAPC_PASX_REC_STARVED_SX            = 0x00000052,
18537 PERF_PAPC_PASX_REC_STALLED               = 0x00000053,
18538 PERF_PAPC_PASX_REC_STALLED_POS_MEM       = 0x00000054,
18539 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN      = 0x00000055,
18540 PERF_PAPC_CCGSM_IDLE                     = 0x00000056,
18541 PERF_PAPC_CCGSM_BUSY                     = 0x00000057,
18542 PERF_PAPC_CCGSM_STALLED                  = 0x00000058,
18543 PERF_PAPC_CLPRIM_IDLE                    = 0x00000059,
18544 PERF_PAPC_CLPRIM_BUSY                    = 0x0000005a,
18545 PERF_PAPC_CLPRIM_STALLED                 = 0x0000005b,
18546 PERF_PAPC_CLPRIM_STARVED_CCGSM           = 0x0000005c,
18547 PERF_PAPC_CLIPSM_IDLE                    = 0x0000005d,
18548 PERF_PAPC_CLIPSM_BUSY                    = 0x0000005e,
18549 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH     = 0x0000005f,
18550 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ       = 0x00000060,
18551 PERF_PAPC_CLIPSM_WAIT_CLIPGA             = 0x00000061,
18552 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP     = 0x00000062,
18553 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM         = 0x00000063,
18554 PERF_PAPC_CLIPGA_IDLE                    = 0x00000064,
18555 PERF_PAPC_CLIPGA_BUSY                    = 0x00000065,
18556 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP        = 0x00000066,
18557 PERF_PAPC_CLIPGA_STALLED                 = 0x00000067,
18558 PERF_PAPC_CLIP_IDLE                      = 0x00000068,
18559 PERF_PAPC_CLIP_BUSY                      = 0x00000069,
18560 PERF_PAPC_SU_IDLE                        = 0x0000006a,
18561 PERF_PAPC_SU_BUSY                        = 0x0000006b,
18562 PERF_PAPC_SU_STARVED_CLIP                = 0x0000006c,
18563 PERF_PAPC_SU_STALLED_SC                  = 0x0000006d,
18564 PERF_PAPC_CL_DYN_SCLK_VLD                = 0x0000006e,
18565 PERF_PAPC_SU_DYN_SCLK_VLD                = 0x0000006f,
18566 PERF_PAPC_PA_REG_SCLK_VLD                = 0x00000070,
18567 PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL  = 0x00000071,
18568 PERF_PAPC_PASX_SE0_REQ                   = 0x00000072,
18569 PERF_PAPC_PASX_SE1_REQ                   = 0x00000073,
18570 PERF_PAPC_PASX_SE0_FIRST_VECTOR          = 0x00000074,
18571 PERF_PAPC_PASX_SE0_SECOND_VECTOR         = 0x00000075,
18572 PERF_PAPC_PASX_SE1_FIRST_VECTOR          = 0x00000076,
18573 PERF_PAPC_PASX_SE1_SECOND_VECTOR         = 0x00000077,
18574 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL        = 0x00000078,
18575 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL        = 0x00000079,
18576 PERF_PAPC_SU_SE01_PRIM_FILTER_CULL       = 0x0000007a,
18577 PERF_PAPC_SU_SE0_OUTPUT_PRIM             = 0x0000007b,
18578 PERF_PAPC_SU_SE1_OUTPUT_PRIM             = 0x0000007c,
18579 PERF_PAPC_SU_SE01_OUTPUT_PRIM            = 0x0000007d,
18580 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM        = 0x0000007e,
18581 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM        = 0x0000007f,
18582 PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM       = 0x00000080,
18583 PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT  = 0x00000081,
18584 PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT  = 0x00000082,
18585 PERF_PAPC_SU_SE0_STALLED_SC              = 0x00000083,
18586 PERF_PAPC_SU_SE1_STALLED_SC              = 0x00000084,
18587 PERF_PAPC_SU_SE01_STALLED_SC             = 0x00000085,
18588 PERF_PAPC_CLSM_CLIPPING_PRIM             = 0x00000086,
18589 PERF_PAPC_SU_CULLED_PRIM                 = 0x00000087,
18590 PERF_PAPC_SU_OUTPUT_EOPG                 = 0x00000088,
18591 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL        = 0x00000089,
18592 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL        = 0x0000008a,
18593 PERF_PAPC_SU_SE2_OUTPUT_PRIM             = 0x0000008b,
18594 PERF_PAPC_SU_SE3_OUTPUT_PRIM             = 0x0000008c,
18595 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM        = 0x0000008d,
18596 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM        = 0x0000008e,
18597 PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET    = 0x0000008f,
18598 PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET    = 0x00000090,
18599 PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET    = 0x00000091,
18600 PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET    = 0x00000092,
18601 PERF_PAPC_SU_SE0_OUTPUT_EOPG             = 0x00000093,
18602 PERF_PAPC_SU_SE1_OUTPUT_EOPG             = 0x00000094,
18603 PERF_PAPC_SU_SE2_OUTPUT_EOPG             = 0x00000095,
18604 PERF_PAPC_SU_SE3_OUTPUT_EOPG             = 0x00000096,
18605 PERF_PAPC_SU_SE2_STALLED_SC              = 0x00000097,
18606 PERF_PAPC_SU_SE3_STALLED_SC              = 0x00000098,
18607 PERF_SU_SMALL_PRIM_FILTER_CULL_CNT       = 0x00000099,
18608 PERF_SMALL_PRIM_CULL_PRIM_1X1            = 0x0000009a,
18609 PERF_SMALL_PRIM_CULL_PRIM_2X1            = 0x0000009b,
18610 PERF_SMALL_PRIM_CULL_PRIM_1X2            = 0x0000009c,
18611 PERF_SMALL_PRIM_CULL_PRIM_2X2            = 0x0000009d,
18612 PERF_SMALL_PRIM_CULL_PRIM_3X1            = 0x0000009e,
18613 PERF_SMALL_PRIM_CULL_PRIM_1X3            = 0x0000009f,
18614 PERF_SMALL_PRIM_CULL_PRIM_3X2            = 0x000000a0,
18615 PERF_SMALL_PRIM_CULL_PRIM_2X3            = 0x000000a1,
18616 PERF_SMALL_PRIM_CULL_PRIM_NX1            = 0x000000a2,
18617 PERF_SMALL_PRIM_CULL_PRIM_1XN            = 0x000000a3,
18618 PERF_SMALL_PRIM_CULL_PRIM_NX2            = 0x000000a4,
18619 PERF_SMALL_PRIM_CULL_PRIM_2XN            = 0x000000a5,
18620 PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT  = 0x000000a6,
18621 PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT  = 0x000000a7,
18622 PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT  = 0x000000a8,
18623 PERF_SC0_QUALIFIED_SEND_BUSY_EVENT       = 0x000000a9,
18624 PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT   = 0x000000aa,
18625 PERF_SC1_QUALIFIED_SEND_BUSY_EVENT       = 0x000000ab,
18626 PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT   = 0x000000ac,
18627 PERF_SC2_QUALIFIED_SEND_BUSY_EVENT       = 0x000000ad,
18628 PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT   = 0x000000ae,
18629 PERF_SC3_QUALIFIED_SEND_BUSY_EVENT       = 0x000000af,
18630 PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT   = 0x000000b0,
18631 PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1  = 0x000000b1,
18632 PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT  = 0x000000b2,
18633 PERF_UTC_SIDEBAND_DRIVER_BUSY            = 0x000000b3,
18634 PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1   = 0x000000b4,
18635 PERF_UTC_INDEX_DRIVER_STALLING_CLIENT    = 0x000000b5,
18636 PERF_UTC_INDEX_DRIVER_BUSY               = 0x000000b6,
18637 PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1  = 0x000000b7,
18638 PERF_UTC_POSITION_DRIVER_STALLING_CLIENT  = 0x000000b8,
18639 PERF_UTC_POSITION_DRIVER_BUSY            = 0x000000b9,
18640 PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1  = 0x000000ba,
18641 PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER  = 0x000000bb,
18642 PERF_UTC_SIDEBAND_RECEIVER_BUSY          = 0x000000bc,
18643 PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1   = 0x000000bd,
18644 PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER  = 0x000000be,
18645 PERF_UTC_INDEX_RECEIVER_BUSY             = 0x000000bf,
18646 PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1  = 0x000000c0,
18647 PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER  = 0x000000c1,
18648 PERF_UTC_POSITION_RECEIVER_BUSY          = 0x000000c2,
18649 PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE  = 0x000000c3,
18650 PERF_TCIF_STALLING_CLIENT_NO_CREDITS     = 0x000000c4,
18651 PERF_TCIF_BUSY                           = 0x000000c5,
18652 PERF_TCIF_SIDEBAND_RDREQ                 = 0x000000c6,
18653 PERF_TCIF_INDEX_RDREQ                    = 0x000000c7,
18654 PERF_TCIF_POSITION_RDREQ                 = 0x000000c8,
18655 PERF_SIDEBAND_WAITING_ON_UTCL1           = 0x000000c9,
18656 PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY  = 0x000000ca,
18657 PERF_WRITING_TO_SIDEBAND_MEMORY          = 0x000000cb,
18658 PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD  = 0x000000cc,
18659 PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD  = 0x000000cd,
18660 PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD  = 0x000000ce,
18661 PERF_SIDEBAND_WAITING_ON_RETURNED_DATA   = 0x000000cf,
18662 PERF_SIDEBAND_POP_BIT_FIFO_FULL          = 0x000000d0,
18663 PERF_SIDEBAND_FIFO_VMID_FIFO_FULL        = 0x000000d1,
18664 PERF_SIDEBAND_INVALID_REFETCH            = 0x000000d2,
18665 PERF_SIDEBAND_QUALIFIED_BUSY             = 0x000000d3,
18666 PERF_SIDEBAND_QUALIFIED_STARVED          = 0x000000d4,
18667 PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_   = 0x000000d5,
18668 PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_  = 0x000000d6,
18669 PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_  = 0x000000d7,
18670 PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_  = 0x000000d8,
18671 PERF_INDEX_REQUEST_WAITING_ON_TOKENS     = 0x000000d9,
18672 PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO  = 0x000000da,
18673 PERF_INDEX_REQUEST_QUALIFIED_BUSY        = 0x000000db,
18674 PERF_INDEX_REQUEST_QUALIFIED_STARVED     = 0x000000dc,
18675 PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE  = 0x000000dd,
18676 PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO  = 0x000000de,
18677 PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE  = 0x000000df,
18678 PERF_INDEX_RECEIVE_QUALIFIED_BUSY        = 0x000000e0,
18679 PERF_INDEX_RECEIVE_QUALIFIED_STARVED     = 0x000000e1,
18680 PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE  = 0x000000e2,
18681 PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE  = 0x000000e3,
18682 PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE  = 0x000000e4,
18683 PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE  = 0x000000e5,
18684 PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE  = 0x000000e6,
18685 PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE  = 0x000000e7,
18686 PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE  = 0x000000e8,
18687 PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE  = 0x000000e9,
18688 PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE  = 0x000000ea,
18689 PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE  = 0x000000eb,
18690 PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE  = 0x000000ec,
18691 PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE  = 0x000000ed,
18692 PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE  = 0x000000ee,
18693 PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE  = 0x000000ef,
18694 PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE  = 0x000000f0,
18695 PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE  = 0x000000f1,
18696 PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE  = 0x000000f2,
18697 PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO  = 0x000000f3,
18698 PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO  = 0x000000f4,
18699 PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO  = 0x000000f5,
18700 PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO  = 0x000000f6,
18701 PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO  = 0x000000f7,
18702 PERF_POS_REQ_STALLED_BY_NO_TOKENS        = 0x000000f8,
18703 PERF_POS_REQ_STARVED_BY_NO_PRIM          = 0x000000f9,
18704 PERF_POS_REQ_STALLED_BY_UTCL1            = 0x000000fa,
18705 PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE  = 0x000000fb,
18706 PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE  = 0x000000fc,
18707 PERF_POS_REQ_QUALIFIED_BUSY              = 0x000000fd,
18708 PERF_POS_REQ_QUALIFIED_STARVED           = 0x000000fe,
18709 PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM  = 0x000000ff,
18710 PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM  = 0x00000100,
18711 PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM  = 0x00000101,
18712 PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM  = 0x00000102,
18713 PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO     = 0x00000103,
18714 PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO  = 0x00000104,
18715 PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE  = 0x00000105,
18716 PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE    = 0x00000106,
18717 PERF_POS_RET_QUALIFIED_BUSY              = 0x00000107,
18718 PERF_POS_RET_QUALIFIED_STARVED           = 0x00000108,
18719 PERF_POS_RET_1_CACHELINE_POSITION_USED   = 0x00000109,
18720 PERF_POS_RET_2_CACHELINE_POSITION_USED   = 0x0000010a,
18721 PERF_POS_RET_3_CACHELINE_POSITION_USED   = 0x0000010b,
18722 PERF_POS_RET_4_CACHELINE_POSITION_USED   = 0x0000010c,
18723 PERF_TC_INDEX_LATENCY_BIN0               = 0x0000010d,
18724 PERF_TC_INDEX_LATENCY_BIN1               = 0x0000010e,
18725 PERF_TC_INDEX_LATENCY_BIN2               = 0x0000010f,
18726 PERF_TC_INDEX_LATENCY_BIN3               = 0x00000110,
18727 PERF_TC_INDEX_LATENCY_BIN4               = 0x00000111,
18728 PERF_TC_INDEX_LATENCY_BIN5               = 0x00000112,
18729 PERF_TC_INDEX_LATENCY_BIN6               = 0x00000113,
18730 PERF_TC_INDEX_LATENCY_BIN7               = 0x00000114,
18731 PERF_TC_INDEX_LATENCY_BIN8               = 0x00000115,
18732 PERF_TC_INDEX_LATENCY_BIN9               = 0x00000116,
18733 PERF_TC_INDEX_LATENCY_BIN10              = 0x00000117,
18734 PERF_TC_INDEX_LATENCY_BIN11              = 0x00000118,
18735 PERF_TC_INDEX_LATENCY_BIN12              = 0x00000119,
18736 PERF_TC_INDEX_LATENCY_BIN13              = 0x0000011a,
18737 PERF_TC_INDEX_LATENCY_BIN14              = 0x0000011b,
18738 PERF_TC_INDEX_LATENCY_BIN15              = 0x0000011c,
18739 PERF_TC_POSITION_LATENCY_BIN0            = 0x0000011d,
18740 PERF_TC_POSITION_LATENCY_BIN1            = 0x0000011e,
18741 PERF_TC_POSITION_LATENCY_BIN2            = 0x0000011f,
18742 PERF_TC_POSITION_LATENCY_BIN3            = 0x00000120,
18743 PERF_TC_POSITION_LATENCY_BIN4            = 0x00000121,
18744 PERF_TC_POSITION_LATENCY_BIN5            = 0x00000122,
18745 PERF_TC_POSITION_LATENCY_BIN6            = 0x00000123,
18746 PERF_TC_POSITION_LATENCY_BIN7            = 0x00000124,
18747 PERF_TC_POSITION_LATENCY_BIN8            = 0x00000125,
18748 PERF_TC_POSITION_LATENCY_BIN9            = 0x00000126,
18749 PERF_TC_POSITION_LATENCY_BIN10           = 0x00000127,
18750 PERF_TC_POSITION_LATENCY_BIN11           = 0x00000128,
18751 PERF_TC_POSITION_LATENCY_BIN12           = 0x00000129,
18752 PERF_TC_POSITION_LATENCY_BIN13           = 0x0000012a,
18753 PERF_TC_POSITION_LATENCY_BIN14           = 0x0000012b,
18754 PERF_TC_POSITION_LATENCY_BIN15           = 0x0000012c,
18755 PERF_TC_STREAM0_DATA_AVAILABLE           = 0x0000012d,
18756 PERF_TC_STREAM1_DATA_AVAILABLE           = 0x0000012e,
18757 PERF_TC_STREAM2_DATA_AVAILABLE           = 0x0000012f,
18758 PERF_PAWD_DEALLOC_FIFO_IS_FULL           = 0x00000130,
18759 PERF_PAWD_DEALLOC_WAITING_TO_BE_READ     = 0x00000131,
18760 PERF_SHOOTDOWN_WAIT_ON_UTCL1             = 0x00000132,
18761 PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND      = 0x00000133,
18762 PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX         = 0x00000134,
18763 PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION      = 0x00000135,
18764 PERF_SHOOTDOWN_WAIT_ALL_CLEAN            = 0x00000136,
18765 PERF_SHOOTDOWN_WAIT_DEASSERT             = 0x00000137,
18766 PERF_UTCL1_TRANSLATION_MISS_CLIENT0      = 0x00000138,
18767 PERF_UTCL1_TRANSLATION_MISS_CLIENT1      = 0x00000139,
18768 PERF_UTCL1_TRANSLATION_MISS_CLIENT2      = 0x0000013a,
18769 PERF_UTCL1_PERMISSION_MISS_CLIENT0       = 0x0000013b,
18770 PERF_UTCL1_PERMISSION_MISS_CLIENT1       = 0x0000013c,
18771 PERF_UTCL1_PERMISSION_MISS_CLIENT2       = 0x0000013d,
18772 PERF_UTCL1_TRANSLATION_HIT_CLIENT0       = 0x0000013e,
18773 PERF_UTCL1_TRANSLATION_HIT_CLIENT1       = 0x0000013f,
18774 PERF_UTCL1_TRANSLATION_HIT_CLIENT2       = 0x00000140,
18775 PERF_UTCL1_REQUEST_CLIENT0               = 0x00000141,
18776 PERF_UTCL1_REQUEST_CLIENT1               = 0x00000142,
18777 PERF_UTCL1_REQUEST_CLIENT2               = 0x00000143,
18778 PERF_UTCL1_STALL_MISSFIFO_FULL           = 0x00000144,
18779 PERF_UTCL1_STALL_INFLIGHT_MAX            = 0x00000145,
18780 PERF_UTCL1_STALL_LRU_INFLIGHT            = 0x00000146,
18781 PERF_UTCL1_STALL_MULTI_MISS              = 0x00000147,
18782 PERF_UTCL1_LFIFO_FULL                    = 0x00000148,
18783 PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0   = 0x00000149,
18784 PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1   = 0x0000014a,
18785 PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2   = 0x0000014b,
18786 PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x0000014c,
18787 PERF_UTCL1_UTCL2_REQ                     = 0x0000014d,
18788 PERF_UTCL1_UTCL2_RET                     = 0x0000014e,
18789 PERF_UTCL1_UTCL2_INFLIGHT                = 0x0000014f,
18790 PERF_CLIENT_UTCL1_INFLIGHT               = 0x00000150,
18791 PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED  = 0x00000151,
18792 PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND  = 0x00000152,
18793 PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND  = 0x00000153,
18794 PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED  = 0x00000154,
18795 PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND  = 0x00000155,
18796 PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND  = 0x00000156,
18797 PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED  = 0x00000157,
18798 PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND  = 0x00000158,
18799 PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND  = 0x00000159,
18800 PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED  = 0x0000015a,
18801 PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND  = 0x0000015b,
18802 PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND  = 0x0000015c,
18803 PERF_PA_VERTEX_FIFO_FULL                 = 0x0000015d,
18804 PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL       = 0x0000015e,
18805 PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL      = 0x0000015f,
18806 PERF_PA_FETCH_TO_SXIF_FIFO_FULL          = 0x00000160,
18807 ENGG_CSB_MACHINE_IS_STARVED              = 0x00000163,
18808 ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY   = 0x00000164,
18809 ENGG_CSB_MACHINE_STALLED_BY_SPI          = 0x00000165,
18810 ENGG_CSB_GE_INPUT_FIFO_FULL              = 0x00000166,
18811 ENGG_CSB_SPI_INPUT_FIFO_FULL             = 0x00000167,
18812 ENGG_CSB_OBJECTID_INPUT_FIFO_FULL        = 0x00000168,
18813 ENGG_CSB_PRIM_COUNT_EQ0                  = 0x00000169,
18814 ENGG_CSB_GE_SENDING_SUBGROUP             = 0x0000016a,
18815 ENGG_CSB_DELAY_BIN00                     = 0x0000016b,
18816 ENGG_CSB_DELAY_BIN01                     = 0x0000016c,
18817 ENGG_CSB_DELAY_BIN02                     = 0x0000016d,
18818 ENGG_CSB_DELAY_BIN03                     = 0x0000016e,
18819 ENGG_CSB_DELAY_BIN04                     = 0x0000016f,
18820 ENGG_CSB_DELAY_BIN05                     = 0x00000170,
18821 ENGG_CSB_DELAY_BIN06                     = 0x00000171,
18822 ENGG_CSB_DELAY_BIN07                     = 0x00000172,
18823 ENGG_CSB_DELAY_BIN08                     = 0x00000173,
18824 ENGG_CSB_DELAY_BIN09                     = 0x00000174,
18825 ENGG_CSB_DELAY_BIN10                     = 0x00000175,
18826 ENGG_CSB_DELAY_BIN11                     = 0x00000176,
18827 ENGG_CSB_DELAY_BIN12                     = 0x00000177,
18828 ENGG_CSB_DELAY_BIN13                     = 0x00000178,
18829 ENGG_CSB_DELAY_BIN14                     = 0x00000179,
18830 ENGG_CSB_DELAY_BIN15                     = 0x0000017a,
18831 ENGG_CSB_SPI_DELAY_BIN00                 = 0x0000017b,
18832 ENGG_CSB_SPI_DELAY_BIN01                 = 0x0000017c,
18833 ENGG_CSB_SPI_DELAY_BIN02                 = 0x0000017d,
18834 ENGG_CSB_SPI_DELAY_BIN03                 = 0x0000017e,
18835 ENGG_CSB_SPI_DELAY_BIN04                 = 0x0000017f,
18836 ENGG_CSB_SPI_DELAY_BIN05                 = 0x00000180,
18837 ENGG_CSB_SPI_DELAY_BIN06                 = 0x00000181,
18838 ENGG_CSB_SPI_DELAY_BIN07                 = 0x00000182,
18839 ENGG_CSB_SPI_DELAY_BIN08                 = 0x00000183,
18840 ENGG_CSB_SPI_DELAY_BIN09                 = 0x00000184,
18841 ENGG_CSB_SPI_DELAY_BIN10                 = 0x00000185,
18842 ENGG_CSB_SPI_DELAY_BIN11                 = 0x00000186,
18843 ENGG_CSB_SPI_DELAY_BIN12                 = 0x00000187,
18844 ENGG_CSB_SPI_DELAY_BIN13                 = 0x00000188,
18845 ENGG_CSB_SPI_DELAY_BIN14                 = 0x00000189,
18846 ENGG_CSB_SPI_DELAY_BIN15                 = 0x0000018a,
18847 ENGG_INDEX_REQ_STARVED                   = 0x0000018b,
18848 ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL  = 0x0000018c,
18849 ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL  = 0x0000018d,
18850 ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS     = 0x0000018e,
18851 ENGG_INDEX_RET_REQ2RTN_FIFO_FULL         = 0x0000018f,
18852 ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY        = 0x00000190,
18853 ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL      = 0x00000191,
18854 ENGG_INDEX_RET_SXRX_STARVED_BY_CSB       = 0x00000192,
18855 ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS     = 0x00000193,
18856 ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO  = 0x00000194,
18857 ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO  = 0x00000195,
18858 ENGG_INDEX_RET_SXRX_READING_EVENT        = 0x00000196,
18859 ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP  = 0x00000197,
18860 ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0  = 0x00000198,
18861 ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL  = 0x00000199,
18862 ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL  = 0x0000019a,
18863 ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL  = 0x0000019b,
18864 ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL  = 0x0000019c,
18865 ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS  = 0x0000019d,
18866 ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS  = 0x0000019e,
18867 ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS  = 0x0000019f,
18868 ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO  = 0x000001a0,
18869 ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO  = 0x000001a1,
18870 ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM    = 0x000001a2,
18871 ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE  = 0x000001a3,
18872 ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE  = 0x000001a4,
18873 ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY        = 0x000001a5,
18874 ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED     = 0x000001a6,
18875 ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM  = 0x000001a7,
18876 ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM  = 0x000001a8,
18877 ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM  = 0x000001a9,
18878 ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM  = 0x000001aa,
18879 ENGG_POS_REQ_STARVED                     = 0x000001ab,
18880 ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO  = 0x000001ac,
18881 } SU_PERFCNT_SEL;
18882 
18883 /*
18884  * SC_PERFCNT_SEL enum
18885  */
18886 
18887 typedef enum SC_PERFCNT_SEL {
18888 SC_SRPS_WINDOW_VALID                     = 0x00000000,
18889 SC_PSSW_WINDOW_VALID                     = 0x00000001,
18890 SC_TPQZ_WINDOW_VALID                     = 0x00000002,
18891 SC_QZQP_WINDOW_VALID                     = 0x00000003,
18892 SC_TRPK_WINDOW_VALID                     = 0x00000004,
18893 SC_SRPS_WINDOW_VALID_BUSY                = 0x00000005,
18894 SC_PSSW_WINDOW_VALID_BUSY                = 0x00000006,
18895 SC_TPQZ_WINDOW_VALID_BUSY                = 0x00000007,
18896 SC_QZQP_WINDOW_VALID_BUSY                = 0x00000008,
18897 SC_TRPK_WINDOW_VALID_BUSY                = 0x00000009,
18898 SC_STARVED_BY_PA                         = 0x0000000a,
18899 SC_STALLED_BY_PRIMFIFO                   = 0x0000000b,
18900 SC_STALLED_BY_DB_TILE                    = 0x0000000c,
18901 SC_STARVED_BY_DB_TILE                    = 0x0000000d,
18902 SC_STALLED_BY_TILEORDERFIFO              = 0x0000000e,
18903 SC_STALLED_BY_TILEFIFO                   = 0x0000000f,
18904 SC_STALLED_BY_DB_QUAD                    = 0x00000010,
18905 SC_STARVED_BY_DB_QUAD                    = 0x00000011,
18906 SC_STALLED_BY_QUADFIFO                   = 0x00000012,
18907 SC_STALLED_BY_BCI                        = 0x00000013,
18908 SC_STALLED_BY_SPI                        = 0x00000014,
18909 SC_SCISSOR_DISCARD                       = 0x00000015,
18910 SC_BB_DISCARD                            = 0x00000016,
18911 SC_SUPERTILE_COUNT                       = 0x00000017,
18912 SC_SUPERTILE_PER_PRIM_H0                 = 0x00000018,
18913 SC_SUPERTILE_PER_PRIM_H1                 = 0x00000019,
18914 SC_SUPERTILE_PER_PRIM_H2                 = 0x0000001a,
18915 SC_SUPERTILE_PER_PRIM_H3                 = 0x0000001b,
18916 SC_SUPERTILE_PER_PRIM_H4                 = 0x0000001c,
18917 SC_SUPERTILE_PER_PRIM_H5                 = 0x0000001d,
18918 SC_SUPERTILE_PER_PRIM_H6                 = 0x0000001e,
18919 SC_SUPERTILE_PER_PRIM_H7                 = 0x0000001f,
18920 SC_SUPERTILE_PER_PRIM_H8                 = 0x00000020,
18921 SC_SUPERTILE_PER_PRIM_H9                 = 0x00000021,
18922 SC_SUPERTILE_PER_PRIM_H10                = 0x00000022,
18923 SC_SUPERTILE_PER_PRIM_H11                = 0x00000023,
18924 SC_SUPERTILE_PER_PRIM_H12                = 0x00000024,
18925 SC_SUPERTILE_PER_PRIM_H13                = 0x00000025,
18926 SC_SUPERTILE_PER_PRIM_H14                = 0x00000026,
18927 SC_SUPERTILE_PER_PRIM_H15                = 0x00000027,
18928 SC_SUPERTILE_PER_PRIM_H16                = 0x00000028,
18929 SC_TILE_PER_PRIM_H0                      = 0x00000029,
18930 SC_TILE_PER_PRIM_H1                      = 0x0000002a,
18931 SC_TILE_PER_PRIM_H2                      = 0x0000002b,
18932 SC_TILE_PER_PRIM_H3                      = 0x0000002c,
18933 SC_TILE_PER_PRIM_H4                      = 0x0000002d,
18934 SC_TILE_PER_PRIM_H5                      = 0x0000002e,
18935 SC_TILE_PER_PRIM_H6                      = 0x0000002f,
18936 SC_TILE_PER_PRIM_H7                      = 0x00000030,
18937 SC_TILE_PER_PRIM_H8                      = 0x00000031,
18938 SC_TILE_PER_PRIM_H9                      = 0x00000032,
18939 SC_TILE_PER_PRIM_H10                     = 0x00000033,
18940 SC_TILE_PER_PRIM_H11                     = 0x00000034,
18941 SC_TILE_PER_PRIM_H12                     = 0x00000035,
18942 SC_TILE_PER_PRIM_H13                     = 0x00000036,
18943 SC_TILE_PER_PRIM_H14                     = 0x00000037,
18944 SC_TILE_PER_PRIM_H15                     = 0x00000038,
18945 SC_TILE_PER_PRIM_H16                     = 0x00000039,
18946 SC_TILE_PER_SUPERTILE_H0                 = 0x0000003a,
18947 SC_TILE_PER_SUPERTILE_H1                 = 0x0000003b,
18948 SC_TILE_PER_SUPERTILE_H2                 = 0x0000003c,
18949 SC_TILE_PER_SUPERTILE_H3                 = 0x0000003d,
18950 SC_TILE_PER_SUPERTILE_H4                 = 0x0000003e,
18951 SC_TILE_PER_SUPERTILE_H5                 = 0x0000003f,
18952 SC_TILE_PER_SUPERTILE_H6                 = 0x00000040,
18953 SC_TILE_PER_SUPERTILE_H7                 = 0x00000041,
18954 SC_TILE_PER_SUPERTILE_H8                 = 0x00000042,
18955 SC_TILE_PER_SUPERTILE_H9                 = 0x00000043,
18956 SC_TILE_PER_SUPERTILE_H10                = 0x00000044,
18957 SC_TILE_PER_SUPERTILE_H11                = 0x00000045,
18958 SC_TILE_PER_SUPERTILE_H12                = 0x00000046,
18959 SC_TILE_PER_SUPERTILE_H13                = 0x00000047,
18960 SC_TILE_PER_SUPERTILE_H14                = 0x00000048,
18961 SC_TILE_PER_SUPERTILE_H15                = 0x00000049,
18962 SC_TILE_PER_SUPERTILE_H16                = 0x0000004a,
18963 SC_TILE_PICKED_H1                        = 0x0000004b,
18964 SC_TILE_PICKED_H2                        = 0x0000004c,
18965 SC_TILE_PICKED_H3                        = 0x0000004d,
18966 SC_TILE_PICKED_H4                        = 0x0000004e,
18967 SC_QZ0_TILE_COUNT                        = 0x0000004f,
18968 SC_QZ1_TILE_COUNT                        = 0x00000050,
18969 SC_QZ2_TILE_COUNT                        = 0x00000051,
18970 SC_QZ3_TILE_COUNT                        = 0x00000052,
18971 SC_QZ0_TILE_COVERED_COUNT                = 0x00000053,
18972 SC_QZ1_TILE_COVERED_COUNT                = 0x00000054,
18973 SC_QZ2_TILE_COVERED_COUNT                = 0x00000055,
18974 SC_QZ3_TILE_COVERED_COUNT                = 0x00000056,
18975 SC_QZ0_TILE_NOT_COVERED_COUNT            = 0x00000057,
18976 SC_QZ1_TILE_NOT_COVERED_COUNT            = 0x00000058,
18977 SC_QZ2_TILE_NOT_COVERED_COUNT            = 0x00000059,
18978 SC_QZ3_TILE_NOT_COVERED_COUNT            = 0x0000005a,
18979 SC_QZ0_QUAD_PER_TILE_H0                  = 0x0000005b,
18980 SC_QZ0_QUAD_PER_TILE_H1                  = 0x0000005c,
18981 SC_QZ0_QUAD_PER_TILE_H2                  = 0x0000005d,
18982 SC_QZ0_QUAD_PER_TILE_H3                  = 0x0000005e,
18983 SC_QZ0_QUAD_PER_TILE_H4                  = 0x0000005f,
18984 SC_QZ0_QUAD_PER_TILE_H5                  = 0x00000060,
18985 SC_QZ0_QUAD_PER_TILE_H6                  = 0x00000061,
18986 SC_QZ0_QUAD_PER_TILE_H7                  = 0x00000062,
18987 SC_QZ0_QUAD_PER_TILE_H8                  = 0x00000063,
18988 SC_QZ0_QUAD_PER_TILE_H9                  = 0x00000064,
18989 SC_QZ0_QUAD_PER_TILE_H10                 = 0x00000065,
18990 SC_QZ0_QUAD_PER_TILE_H11                 = 0x00000066,
18991 SC_QZ0_QUAD_PER_TILE_H12                 = 0x00000067,
18992 SC_QZ0_QUAD_PER_TILE_H13                 = 0x00000068,
18993 SC_QZ0_QUAD_PER_TILE_H14                 = 0x00000069,
18994 SC_QZ0_QUAD_PER_TILE_H15                 = 0x0000006a,
18995 SC_QZ0_QUAD_PER_TILE_H16                 = 0x0000006b,
18996 SC_QZ1_QUAD_PER_TILE_H0                  = 0x0000006c,
18997 SC_QZ1_QUAD_PER_TILE_H1                  = 0x0000006d,
18998 SC_QZ1_QUAD_PER_TILE_H2                  = 0x0000006e,
18999 SC_QZ1_QUAD_PER_TILE_H3                  = 0x0000006f,
19000 SC_QZ1_QUAD_PER_TILE_H4                  = 0x00000070,
19001 SC_QZ1_QUAD_PER_TILE_H5                  = 0x00000071,
19002 SC_QZ1_QUAD_PER_TILE_H6                  = 0x00000072,
19003 SC_QZ1_QUAD_PER_TILE_H7                  = 0x00000073,
19004 SC_QZ1_QUAD_PER_TILE_H8                  = 0x00000074,
19005 SC_QZ1_QUAD_PER_TILE_H9                  = 0x00000075,
19006 SC_QZ1_QUAD_PER_TILE_H10                 = 0x00000076,
19007 SC_QZ1_QUAD_PER_TILE_H11                 = 0x00000077,
19008 SC_QZ1_QUAD_PER_TILE_H12                 = 0x00000078,
19009 SC_QZ1_QUAD_PER_TILE_H13                 = 0x00000079,
19010 SC_QZ1_QUAD_PER_TILE_H14                 = 0x0000007a,
19011 SC_QZ1_QUAD_PER_TILE_H15                 = 0x0000007b,
19012 SC_QZ1_QUAD_PER_TILE_H16                 = 0x0000007c,
19013 SC_QZ2_QUAD_PER_TILE_H0                  = 0x0000007d,
19014 SC_QZ2_QUAD_PER_TILE_H1                  = 0x0000007e,
19015 SC_QZ2_QUAD_PER_TILE_H2                  = 0x0000007f,
19016 SC_QZ2_QUAD_PER_TILE_H3                  = 0x00000080,
19017 SC_QZ2_QUAD_PER_TILE_H4                  = 0x00000081,
19018 SC_QZ2_QUAD_PER_TILE_H5                  = 0x00000082,
19019 SC_QZ2_QUAD_PER_TILE_H6                  = 0x00000083,
19020 SC_QZ2_QUAD_PER_TILE_H7                  = 0x00000084,
19021 SC_QZ2_QUAD_PER_TILE_H8                  = 0x00000085,
19022 SC_QZ2_QUAD_PER_TILE_H9                  = 0x00000086,
19023 SC_QZ2_QUAD_PER_TILE_H10                 = 0x00000087,
19024 SC_QZ2_QUAD_PER_TILE_H11                 = 0x00000088,
19025 SC_QZ2_QUAD_PER_TILE_H12                 = 0x00000089,
19026 SC_QZ2_QUAD_PER_TILE_H13                 = 0x0000008a,
19027 SC_QZ2_QUAD_PER_TILE_H14                 = 0x0000008b,
19028 SC_QZ2_QUAD_PER_TILE_H15                 = 0x0000008c,
19029 SC_QZ2_QUAD_PER_TILE_H16                 = 0x0000008d,
19030 SC_QZ3_QUAD_PER_TILE_H0                  = 0x0000008e,
19031 SC_QZ3_QUAD_PER_TILE_H1                  = 0x0000008f,
19032 SC_QZ3_QUAD_PER_TILE_H2                  = 0x00000090,
19033 SC_QZ3_QUAD_PER_TILE_H3                  = 0x00000091,
19034 SC_QZ3_QUAD_PER_TILE_H4                  = 0x00000092,
19035 SC_QZ3_QUAD_PER_TILE_H5                  = 0x00000093,
19036 SC_QZ3_QUAD_PER_TILE_H6                  = 0x00000094,
19037 SC_QZ3_QUAD_PER_TILE_H7                  = 0x00000095,
19038 SC_QZ3_QUAD_PER_TILE_H8                  = 0x00000096,
19039 SC_QZ3_QUAD_PER_TILE_H9                  = 0x00000097,
19040 SC_QZ3_QUAD_PER_TILE_H10                 = 0x00000098,
19041 SC_QZ3_QUAD_PER_TILE_H11                 = 0x00000099,
19042 SC_QZ3_QUAD_PER_TILE_H12                 = 0x0000009a,
19043 SC_QZ3_QUAD_PER_TILE_H13                 = 0x0000009b,
19044 SC_QZ3_QUAD_PER_TILE_H14                 = 0x0000009c,
19045 SC_QZ3_QUAD_PER_TILE_H15                 = 0x0000009d,
19046 SC_QZ3_QUAD_PER_TILE_H16                 = 0x0000009e,
19047 SC_QZ0_QUAD_COUNT                        = 0x0000009f,
19048 SC_QZ1_QUAD_COUNT                        = 0x000000a0,
19049 SC_QZ2_QUAD_COUNT                        = 0x000000a1,
19050 SC_QZ3_QUAD_COUNT                        = 0x000000a2,
19051 SC_P0_HIZ_TILE_COUNT                     = 0x000000a3,
19052 SC_P1_HIZ_TILE_COUNT                     = 0x000000a4,
19053 SC_P2_HIZ_TILE_COUNT                     = 0x000000a5,
19054 SC_P3_HIZ_TILE_COUNT                     = 0x000000a6,
19055 SC_P0_HIZ_QUAD_PER_TILE_H0               = 0x000000a7,
19056 SC_P0_HIZ_QUAD_PER_TILE_H1               = 0x000000a8,
19057 SC_P0_HIZ_QUAD_PER_TILE_H2               = 0x000000a9,
19058 SC_P0_HIZ_QUAD_PER_TILE_H3               = 0x000000aa,
19059 SC_P0_HIZ_QUAD_PER_TILE_H4               = 0x000000ab,
19060 SC_P0_HIZ_QUAD_PER_TILE_H5               = 0x000000ac,
19061 SC_P0_HIZ_QUAD_PER_TILE_H6               = 0x000000ad,
19062 SC_P0_HIZ_QUAD_PER_TILE_H7               = 0x000000ae,
19063 SC_P0_HIZ_QUAD_PER_TILE_H8               = 0x000000af,
19064 SC_P0_HIZ_QUAD_PER_TILE_H9               = 0x000000b0,
19065 SC_P0_HIZ_QUAD_PER_TILE_H10              = 0x000000b1,
19066 SC_P0_HIZ_QUAD_PER_TILE_H11              = 0x000000b2,
19067 SC_P0_HIZ_QUAD_PER_TILE_H12              = 0x000000b3,
19068 SC_P0_HIZ_QUAD_PER_TILE_H13              = 0x000000b4,
19069 SC_P0_HIZ_QUAD_PER_TILE_H14              = 0x000000b5,
19070 SC_P0_HIZ_QUAD_PER_TILE_H15              = 0x000000b6,
19071 SC_P0_HIZ_QUAD_PER_TILE_H16              = 0x000000b7,
19072 SC_P1_HIZ_QUAD_PER_TILE_H0               = 0x000000b8,
19073 SC_P1_HIZ_QUAD_PER_TILE_H1               = 0x000000b9,
19074 SC_P1_HIZ_QUAD_PER_TILE_H2               = 0x000000ba,
19075 SC_P1_HIZ_QUAD_PER_TILE_H3               = 0x000000bb,
19076 SC_P1_HIZ_QUAD_PER_TILE_H4               = 0x000000bc,
19077 SC_P1_HIZ_QUAD_PER_TILE_H5               = 0x000000bd,
19078 SC_P1_HIZ_QUAD_PER_TILE_H6               = 0x000000be,
19079 SC_P1_HIZ_QUAD_PER_TILE_H7               = 0x000000bf,
19080 SC_P1_HIZ_QUAD_PER_TILE_H8               = 0x000000c0,
19081 SC_P1_HIZ_QUAD_PER_TILE_H9               = 0x000000c1,
19082 SC_P1_HIZ_QUAD_PER_TILE_H10              = 0x000000c2,
19083 SC_P1_HIZ_QUAD_PER_TILE_H11              = 0x000000c3,
19084 SC_P1_HIZ_QUAD_PER_TILE_H12              = 0x000000c4,
19085 SC_P1_HIZ_QUAD_PER_TILE_H13              = 0x000000c5,
19086 SC_P1_HIZ_QUAD_PER_TILE_H14              = 0x000000c6,
19087 SC_P1_HIZ_QUAD_PER_TILE_H15              = 0x000000c7,
19088 SC_P1_HIZ_QUAD_PER_TILE_H16              = 0x000000c8,
19089 SC_P2_HIZ_QUAD_PER_TILE_H0               = 0x000000c9,
19090 SC_P2_HIZ_QUAD_PER_TILE_H1               = 0x000000ca,
19091 SC_P2_HIZ_QUAD_PER_TILE_H2               = 0x000000cb,
19092 SC_P2_HIZ_QUAD_PER_TILE_H3               = 0x000000cc,
19093 SC_P2_HIZ_QUAD_PER_TILE_H4               = 0x000000cd,
19094 SC_P2_HIZ_QUAD_PER_TILE_H5               = 0x000000ce,
19095 SC_P2_HIZ_QUAD_PER_TILE_H6               = 0x000000cf,
19096 SC_P2_HIZ_QUAD_PER_TILE_H7               = 0x000000d0,
19097 SC_P2_HIZ_QUAD_PER_TILE_H8               = 0x000000d1,
19098 SC_P2_HIZ_QUAD_PER_TILE_H9               = 0x000000d2,
19099 SC_P2_HIZ_QUAD_PER_TILE_H10              = 0x000000d3,
19100 SC_P2_HIZ_QUAD_PER_TILE_H11              = 0x000000d4,
19101 SC_P2_HIZ_QUAD_PER_TILE_H12              = 0x000000d5,
19102 SC_P2_HIZ_QUAD_PER_TILE_H13              = 0x000000d6,
19103 SC_P2_HIZ_QUAD_PER_TILE_H14              = 0x000000d7,
19104 SC_P2_HIZ_QUAD_PER_TILE_H15              = 0x000000d8,
19105 SC_P2_HIZ_QUAD_PER_TILE_H16              = 0x000000d9,
19106 SC_P3_HIZ_QUAD_PER_TILE_H0               = 0x000000da,
19107 SC_P3_HIZ_QUAD_PER_TILE_H1               = 0x000000db,
19108 SC_P3_HIZ_QUAD_PER_TILE_H2               = 0x000000dc,
19109 SC_P3_HIZ_QUAD_PER_TILE_H3               = 0x000000dd,
19110 SC_P3_HIZ_QUAD_PER_TILE_H4               = 0x000000de,
19111 SC_P3_HIZ_QUAD_PER_TILE_H5               = 0x000000df,
19112 SC_P3_HIZ_QUAD_PER_TILE_H6               = 0x000000e0,
19113 SC_P3_HIZ_QUAD_PER_TILE_H7               = 0x000000e1,
19114 SC_P3_HIZ_QUAD_PER_TILE_H8               = 0x000000e2,
19115 SC_P3_HIZ_QUAD_PER_TILE_H9               = 0x000000e3,
19116 SC_P3_HIZ_QUAD_PER_TILE_H10              = 0x000000e4,
19117 SC_P3_HIZ_QUAD_PER_TILE_H11              = 0x000000e5,
19118 SC_P3_HIZ_QUAD_PER_TILE_H12              = 0x000000e6,
19119 SC_P3_HIZ_QUAD_PER_TILE_H13              = 0x000000e7,
19120 SC_P3_HIZ_QUAD_PER_TILE_H14              = 0x000000e8,
19121 SC_P3_HIZ_QUAD_PER_TILE_H15              = 0x000000e9,
19122 SC_P3_HIZ_QUAD_PER_TILE_H16              = 0x000000ea,
19123 SC_P0_HIZ_QUAD_COUNT                     = 0x000000eb,
19124 SC_P1_HIZ_QUAD_COUNT                     = 0x000000ec,
19125 SC_P2_HIZ_QUAD_COUNT                     = 0x000000ed,
19126 SC_P3_HIZ_QUAD_COUNT                     = 0x000000ee,
19127 SC_P0_DETAIL_QUAD_COUNT                  = 0x000000ef,
19128 SC_P1_DETAIL_QUAD_COUNT                  = 0x000000f0,
19129 SC_P2_DETAIL_QUAD_COUNT                  = 0x000000f1,
19130 SC_P3_DETAIL_QUAD_COUNT                  = 0x000000f2,
19131 SC_P0_DETAIL_QUAD_WITH_1_PIX             = 0x000000f3,
19132 SC_P0_DETAIL_QUAD_WITH_2_PIX             = 0x000000f4,
19133 SC_P0_DETAIL_QUAD_WITH_3_PIX             = 0x000000f5,
19134 SC_P0_DETAIL_QUAD_WITH_4_PIX             = 0x000000f6,
19135 SC_P1_DETAIL_QUAD_WITH_1_PIX             = 0x000000f7,
19136 SC_P1_DETAIL_QUAD_WITH_2_PIX             = 0x000000f8,
19137 SC_P1_DETAIL_QUAD_WITH_3_PIX             = 0x000000f9,
19138 SC_P1_DETAIL_QUAD_WITH_4_PIX             = 0x000000fa,
19139 SC_P2_DETAIL_QUAD_WITH_1_PIX             = 0x000000fb,
19140 SC_P2_DETAIL_QUAD_WITH_2_PIX             = 0x000000fc,
19141 SC_P2_DETAIL_QUAD_WITH_3_PIX             = 0x000000fd,
19142 SC_P2_DETAIL_QUAD_WITH_4_PIX             = 0x000000fe,
19143 SC_P3_DETAIL_QUAD_WITH_1_PIX             = 0x000000ff,
19144 SC_P3_DETAIL_QUAD_WITH_2_PIX             = 0x00000100,
19145 SC_P3_DETAIL_QUAD_WITH_3_PIX             = 0x00000101,
19146 SC_P3_DETAIL_QUAD_WITH_4_PIX             = 0x00000102,
19147 SC_EARLYZ_QUAD_COUNT                     = 0x00000103,
19148 SC_EARLYZ_QUAD_WITH_1_PIX                = 0x00000104,
19149 SC_EARLYZ_QUAD_WITH_2_PIX                = 0x00000105,
19150 SC_EARLYZ_QUAD_WITH_3_PIX                = 0x00000106,
19151 SC_EARLYZ_QUAD_WITH_4_PIX                = 0x00000107,
19152 SC_PKR_QUAD_PER_ROW_H1                   = 0x00000108,
19153 SC_PKR_QUAD_PER_ROW_H2                   = 0x00000109,
19154 SC_PKR_4X2_QUAD_SPLIT                    = 0x0000010a,
19155 SC_PKR_4X2_FILL_QUAD                     = 0x0000010b,
19156 SC_PKR_END_OF_VECTOR                     = 0x0000010c,
19157 SC_PKR_CONTROL_XFER                      = 0x0000010d,
19158 SC_PKR_DBHANG_FORCE_EOV                  = 0x0000010e,
19159 SC_REG_SCLK_BUSY                         = 0x0000010f,
19160 SC_GRP0_DYN_SCLK_BUSY                    = 0x00000110,
19161 SC_GRP1_DYN_SCLK_BUSY                    = 0x00000111,
19162 SC_GRP2_DYN_SCLK_BUSY                    = 0x00000112,
19163 SC_GRP3_DYN_SCLK_BUSY                    = 0x00000113,
19164 SC_GRP4_DYN_SCLK_BUSY                    = 0x00000114,
19165 SC_PA0_SC_DATA_FIFO_RD                   = 0x00000115,
19166 SC_PA0_SC_DATA_FIFO_WE                   = 0x00000116,
19167 SC_PA1_SC_DATA_FIFO_RD                   = 0x00000117,
19168 SC_PA1_SC_DATA_FIFO_WE                   = 0x00000118,
19169 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES   = 0x00000119,
19170 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES           = 0x0000011a,
19171 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM      = 0x0000011b,
19172 SC_PS_ARB_STALLED_FROM_BELOW             = 0x0000011c,
19173 SC_PS_ARB_STARVED_FROM_ABOVE             = 0x0000011d,
19174 SC_PS_ARB_SC_BUSY                        = 0x0000011e,
19175 SC_PS_ARB_PA_SC_BUSY                     = 0x0000011f,
19176 SC_PA2_SC_DATA_FIFO_RD                   = 0x00000120,
19177 SC_PA2_SC_DATA_FIFO_WE                   = 0x00000121,
19178 SC_PA3_SC_DATA_FIFO_RD                   = 0x00000122,
19179 SC_PA3_SC_DATA_FIFO_WE                   = 0x00000123,
19180 SC_PA_SC_DEALLOC_0_0_WE                  = 0x00000124,
19181 SC_PA_SC_DEALLOC_0_1_WE                  = 0x00000125,
19182 SC_PA_SC_DEALLOC_1_0_WE                  = 0x00000126,
19183 SC_PA_SC_DEALLOC_1_1_WE                  = 0x00000127,
19184 SC_PA_SC_DEALLOC_2_0_WE                  = 0x00000128,
19185 SC_PA_SC_DEALLOC_2_1_WE                  = 0x00000129,
19186 SC_PA_SC_DEALLOC_3_0_WE                  = 0x0000012a,
19187 SC_PA_SC_DEALLOC_3_1_WE                  = 0x0000012b,
19188 SC_PA0_SC_EOP_WE                         = 0x0000012c,
19189 SC_PA0_SC_EOPG_WE                        = 0x0000012d,
19190 SC_PA0_SC_EVENT_WE                       = 0x0000012e,
19191 SC_PA1_SC_EOP_WE                         = 0x0000012f,
19192 SC_PA1_SC_EOPG_WE                        = 0x00000130,
19193 SC_PA1_SC_EVENT_WE                       = 0x00000131,
19194 SC_PA2_SC_EOP_WE                         = 0x00000132,
19195 SC_PA2_SC_EOPG_WE                        = 0x00000133,
19196 SC_PA2_SC_EVENT_WE                       = 0x00000134,
19197 SC_PA3_SC_EOP_WE                         = 0x00000135,
19198 SC_PA3_SC_EOPG_WE                        = 0x00000136,
19199 SC_PA3_SC_EVENT_WE                       = 0x00000137,
19200 SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO  = 0x00000138,
19201 SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH          = 0x00000139,
19202 SC_PS_ARB_NULL_PRIM_BUBBLE_POP           = 0x0000013a,
19203 SC_PS_ARB_EOP_POP_SYNC_POP               = 0x0000013b,
19204 SC_PS_ARB_EVENT_SYNC_POP                 = 0x0000013c,
19205 SC_SC_PS_ENG_MULTICYCLE_BUBBLE           = 0x0000013d,
19206 SC_PA0_SC_FPOV_WE                        = 0x0000013e,
19207 SC_PA1_SC_FPOV_WE                        = 0x0000013f,
19208 SC_PA2_SC_FPOV_WE                        = 0x00000140,
19209 SC_PA3_SC_FPOV_WE                        = 0x00000141,
19210 SC_PA0_SC_LPOV_WE                        = 0x00000142,
19211 SC_PA1_SC_LPOV_WE                        = 0x00000143,
19212 SC_PA2_SC_LPOV_WE                        = 0x00000144,
19213 SC_PA3_SC_LPOV_WE                        = 0x00000145,
19214 SC_SC_SPI_DEALLOC_0_0                    = 0x00000146,
19215 SC_SC_SPI_DEALLOC_0_1                    = 0x00000147,
19216 SC_SC_SPI_DEALLOC_0_2                    = 0x00000148,
19217 SC_SC_SPI_DEALLOC_1_0                    = 0x00000149,
19218 SC_SC_SPI_DEALLOC_1_1                    = 0x0000014a,
19219 SC_SC_SPI_DEALLOC_1_2                    = 0x0000014b,
19220 SC_SC_SPI_DEALLOC_2_0                    = 0x0000014c,
19221 SC_SC_SPI_DEALLOC_2_1                    = 0x0000014d,
19222 SC_SC_SPI_DEALLOC_2_2                    = 0x0000014e,
19223 SC_SC_SPI_DEALLOC_3_0                    = 0x0000014f,
19224 SC_SC_SPI_DEALLOC_3_1                    = 0x00000150,
19225 SC_SC_SPI_DEALLOC_3_2                    = 0x00000151,
19226 SC_SC_SPI_FPOV_0                         = 0x00000152,
19227 SC_SC_SPI_FPOV_1                         = 0x00000153,
19228 SC_SC_SPI_FPOV_2                         = 0x00000154,
19229 SC_SC_SPI_FPOV_3                         = 0x00000155,
19230 SC_SC_SPI_EVENT                          = 0x00000156,
19231 SC_PS_TS_EVENT_FIFO_PUSH                 = 0x00000157,
19232 SC_PS_TS_EVENT_FIFO_POP                  = 0x00000158,
19233 SC_PS_CTX_DONE_FIFO_PUSH                 = 0x00000159,
19234 SC_PS_CTX_DONE_FIFO_POP                  = 0x0000015a,
19235 SC_MULTICYCLE_BUBBLE_FREEZE              = 0x0000015b,
19236 SC_EOP_SYNC_WINDOW                       = 0x0000015c,
19237 SC_PA0_SC_NULL_WE                        = 0x0000015d,
19238 SC_PA0_SC_NULL_DEALLOC_WE                = 0x0000015e,
19239 SC_PA0_SC_DATA_FIFO_EOPG_RD              = 0x0000015f,
19240 SC_PA0_SC_DATA_FIFO_EOP_RD               = 0x00000160,
19241 SC_PA0_SC_DEALLOC_0_RD                   = 0x00000161,
19242 SC_PA0_SC_DEALLOC_1_RD                   = 0x00000162,
19243 SC_PA1_SC_DATA_FIFO_EOPG_RD              = 0x00000163,
19244 SC_PA1_SC_DATA_FIFO_EOP_RD               = 0x00000164,
19245 SC_PA1_SC_DEALLOC_0_RD                   = 0x00000165,
19246 SC_PA1_SC_DEALLOC_1_RD                   = 0x00000166,
19247 SC_PA1_SC_NULL_WE                        = 0x00000167,
19248 SC_PA1_SC_NULL_DEALLOC_WE                = 0x00000168,
19249 SC_PA2_SC_DATA_FIFO_EOPG_RD              = 0x00000169,
19250 SC_PA2_SC_DATA_FIFO_EOP_RD               = 0x0000016a,
19251 SC_PA2_SC_DEALLOC_0_RD                   = 0x0000016b,
19252 SC_PA2_SC_DEALLOC_1_RD                   = 0x0000016c,
19253 SC_PA2_SC_NULL_WE                        = 0x0000016d,
19254 SC_PA2_SC_NULL_DEALLOC_WE                = 0x0000016e,
19255 SC_PA3_SC_DATA_FIFO_EOPG_RD              = 0x0000016f,
19256 SC_PA3_SC_DATA_FIFO_EOP_RD               = 0x00000170,
19257 SC_PA3_SC_DEALLOC_0_RD                   = 0x00000171,
19258 SC_PA3_SC_DEALLOC_1_RD                   = 0x00000172,
19259 SC_PA3_SC_NULL_WE                        = 0x00000173,
19260 SC_PA3_SC_NULL_DEALLOC_WE                = 0x00000174,
19261 SC_PS_PA0_SC_FIFO_EMPTY                  = 0x00000175,
19262 SC_PS_PA0_SC_FIFO_FULL                   = 0x00000176,
19263 SC_RESERVED_0                            = 0x00000177,
19264 SC_PS_PA1_SC_FIFO_EMPTY                  = 0x00000178,
19265 SC_PS_PA1_SC_FIFO_FULL                   = 0x00000179,
19266 SC_RESERVED_1                            = 0x0000017a,
19267 SC_PS_PA2_SC_FIFO_EMPTY                  = 0x0000017b,
19268 SC_PS_PA2_SC_FIFO_FULL                   = 0x0000017c,
19269 SC_RESERVED_2                            = 0x0000017d,
19270 SC_PS_PA3_SC_FIFO_EMPTY                  = 0x0000017e,
19271 SC_PS_PA3_SC_FIFO_FULL                   = 0x0000017f,
19272 SC_RESERVED_3                            = 0x00000180,
19273 SC_BUSY_PROCESSING_MULTICYCLE_PRIM       = 0x00000181,
19274 SC_BUSY_CNT_NOT_ZERO                     = 0x00000182,
19275 SC_BM_BUSY                               = 0x00000183,
19276 SC_BACKEND_BUSY                          = 0x00000184,
19277 SC_SCF_SCB_INTERFACE_BUSY                = 0x00000185,
19278 SC_SCB_BUSY                              = 0x00000186,
19279 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY  = 0x00000187,
19280 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL  = 0x00000188,
19281 SC_PBB_BIN_HIST_NUM_PRIMS                = 0x00000189,
19282 SC_PBB_BATCH_HIST_NUM_PRIMS              = 0x0000018a,
19283 SC_PBB_BIN_HIST_NUM_CONTEXTS             = 0x0000018b,
19284 SC_PBB_BATCH_HIST_NUM_CONTEXTS           = 0x0000018c,
19285 SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES    = 0x0000018d,
19286 SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES  = 0x0000018e,
19287 SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS     = 0x0000018f,
19288 SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS  = 0x00000190,
19289 SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM      = 0x00000191,
19290 SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW    = 0x00000192,
19291 SC_PBB_BUSY                              = 0x00000193,
19292 SC_PBB_BUSY_AND_NO_SENDS                 = 0x00000194,
19293 SC_PBB_STALLS_PA_DUE_TO_NO_TILES         = 0x00000195,
19294 SC_PBB_NUM_BINS                          = 0x00000196,
19295 SC_PBB_END_OF_BIN                        = 0x00000197,
19296 SC_PBB_END_OF_BATCH                      = 0x00000198,
19297 SC_PBB_PRIMBIN_PROCESSED                 = 0x00000199,
19298 SC_PBB_PRIM_ADDED_TO_BATCH               = 0x0000019a,
19299 SC_PBB_NONBINNED_PRIM                    = 0x0000019b,
19300 SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB       = 0x0000019c,
19301 SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB       = 0x0000019d,
19302 SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION  = 0x0000019e,
19303 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW  = 0x0000019f,
19304 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN  = 0x000001a0,
19305 SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE  = 0x000001a1,
19306 SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE  = 0x000001a2,
19307 SC_PBB_BATCH_BREAK_DUE_TO_PRIM           = 0x000001a3,
19308 SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE     = 0x000001a4,
19309 SC_PBB_BATCH_BREAK_DUE_TO_EVENT          = 0x000001a5,
19310 SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT     = 0x000001a6,
19311 SC_POPS_INTRA_WAVE_OVERLAPS              = 0x000001a7,
19312 SC_POPS_FORCE_EOV                        = 0x000001a8,
19313 SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX  = 0x000001a9,
19314 SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP  = 0x000001aa,
19315 SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE     = 0x000001ab,
19316 SC_FULL_FULL_QUAD                        = 0x000001ac,
19317 SC_FULL_HALF_QUAD                        = 0x000001ad,
19318 SC_FULL_QTR_QUAD                         = 0x000001ae,
19319 SC_HALF_FULL_QUAD                        = 0x000001af,
19320 SC_HALF_HALF_QUAD                        = 0x000001b0,
19321 SC_HALF_QTR_QUAD                         = 0x000001b1,
19322 SC_QTR_FULL_QUAD                         = 0x000001b2,
19323 SC_QTR_HALF_QUAD                         = 0x000001b3,
19324 SC_QTR_QTR_QUAD                          = 0x000001b4,
19325 SC_GRP5_DYN_SCLK_BUSY                    = 0x000001b5,
19326 SC_GRP6_DYN_SCLK_BUSY                    = 0x000001b6,
19327 SC_GRP7_DYN_SCLK_BUSY                    = 0x000001b7,
19328 SC_GRP8_DYN_SCLK_BUSY                    = 0x000001b8,
19329 SC_GRP9_DYN_SCLK_BUSY                    = 0x000001b9,
19330 SC_PS_TO_BE_SCLK_GATE_STALL              = 0x000001ba,
19331 SC_PA_TO_PBB_SCLK_GATE_STALL_STALL       = 0x000001bb,
19332 SC_PK_BUSY                               = 0x000001bc,
19333 SC_PK_MAX_DEALLOC_FORCE_EOV              = 0x000001bd,
19334 SC_PK_DEALLOC_WAVE_BREAK                 = 0x000001be,
19335 SC_SPI_SEND                              = 0x000001bf,
19336 SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000001c0,
19337 SC_SPI_CREDIT_AT_MAX                     = 0x000001c1,
19338 SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x000001c2,
19339 SC_BCI_SEND                              = 0x000001c3,
19340 SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000001c4,
19341 SC_BCI_CREDIT_AT_MAX                     = 0x000001c5,
19342 SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x000001c6,
19343 SC_SPIBC_FULL_FREEZE                     = 0x000001c7,
19344 SC_PW_BM_PASS_EMPTY_PRIM                 = 0x000001c8,
19345 SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM  = 0x000001c9,
19346 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0  = 0x000001ca,
19347 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1  = 0x000001cb,
19348 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2  = 0x000001cc,
19349 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3  = 0x000001cd,
19350 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4  = 0x000001ce,
19351 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5  = 0x000001cf,
19352 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6  = 0x000001d0,
19353 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7  = 0x000001d1,
19354 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8  = 0x000001d2,
19355 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9  = 0x000001d3,
19356 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10  = 0x000001d4,
19357 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11  = 0x000001d5,
19358 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12  = 0x000001d6,
19359 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13  = 0x000001d7,
19360 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14  = 0x000001d8,
19361 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15  = 0x000001d9,
19362 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16  = 0x000001da,
19363 SC_DB0_TILE_INTERFACE_BUSY               = 0x000001db,
19364 SC_DB0_TILE_INTERFACE_SEND               = 0x000001dc,
19365 SC_DB0_TILE_INTERFACE_SEND_EVENT         = 0x000001dd,
19366 SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT  = 0x000001de,
19367 SC_DB0_TILE_INTERFACE_SEND_SOP           = 0x000001df,
19368 SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000001e0,
19369 SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX      = 0x000001e1,
19370 SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND  = 0x000001e2,
19371 SC_DB1_TILE_INTERFACE_BUSY               = 0x000001e3,
19372 SC_DB1_TILE_INTERFACE_SEND               = 0x000001e4,
19373 SC_DB1_TILE_INTERFACE_SEND_EVENT         = 0x000001e5,
19374 SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT  = 0x000001e6,
19375 SC_DB1_TILE_INTERFACE_SEND_SOP           = 0x000001e7,
19376 SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000001e8,
19377 SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX      = 0x000001e9,
19378 SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND  = 0x000001ea,
19379 SC_BACKEND_PRIM_FIFO_FULL                = 0x000001eb,
19380 SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER  = 0x000001ec,
19381 SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH  = 0x000001ed,
19382 SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH  = 0x000001ee,
19383 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT  = 0x000001ef,
19384 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT  = 0x000001f0,
19385 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV  = 0x000001f1,
19386 SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE    = 0x000001f2,
19387 SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE  = 0x000001f3,
19388 SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT  = 0x000001f4,
19389 } SC_PERFCNT_SEL;
19390 
19391 /*
19392  * SePairXsel enum
19393  */
19394 
19395 typedef enum SePairXsel {
19396 RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE   = 0x00000000,
19397 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE  = 0x00000001,
19398 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE  = 0x00000002,
19399 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE  = 0x00000003,
19400 } SePairXsel;
19401 
19402 /*
19403  * SePairYsel enum
19404  */
19405 
19406 typedef enum SePairYsel {
19407 RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE   = 0x00000000,
19408 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE  = 0x00000001,
19409 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE  = 0x00000002,
19410 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE  = 0x00000003,
19411 } SePairYsel;
19412 
19413 /*
19414  * SePairMap enum
19415  */
19416 
19417 typedef enum SePairMap {
19418 RASTER_CONFIG_SE_PAIR_MAP_0              = 0x00000000,
19419 RASTER_CONFIG_SE_PAIR_MAP_1              = 0x00000001,
19420 RASTER_CONFIG_SE_PAIR_MAP_2              = 0x00000002,
19421 RASTER_CONFIG_SE_PAIR_MAP_3              = 0x00000003,
19422 } SePairMap;
19423 
19424 /*
19425  * SeXsel enum
19426  */
19427 
19428 typedef enum SeXsel {
19429 RASTER_CONFIG_SE_XSEL_8_WIDE_TILE        = 0x00000000,
19430 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE       = 0x00000001,
19431 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE       = 0x00000002,
19432 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE       = 0x00000003,
19433 } SeXsel;
19434 
19435 /*
19436  * SeYsel enum
19437  */
19438 
19439 typedef enum SeYsel {
19440 RASTER_CONFIG_SE_YSEL_8_WIDE_TILE        = 0x00000000,
19441 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE       = 0x00000001,
19442 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE       = 0x00000002,
19443 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE       = 0x00000003,
19444 } SeYsel;
19445 
19446 /*
19447  * SeMap enum
19448  */
19449 
19450 typedef enum SeMap {
19451 RASTER_CONFIG_SE_MAP_0                   = 0x00000000,
19452 RASTER_CONFIG_SE_MAP_1                   = 0x00000001,
19453 RASTER_CONFIG_SE_MAP_2                   = 0x00000002,
19454 RASTER_CONFIG_SE_MAP_3                   = 0x00000003,
19455 } SeMap;
19456 
19457 /*
19458  * ScXsel enum
19459  */
19460 
19461 typedef enum ScXsel {
19462 RASTER_CONFIG_SC_XSEL_8_WIDE_TILE        = 0x00000000,
19463 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE       = 0x00000001,
19464 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE       = 0x00000002,
19465 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE       = 0x00000003,
19466 } ScXsel;
19467 
19468 /*
19469  * ScYsel enum
19470  */
19471 
19472 typedef enum ScYsel {
19473 RASTER_CONFIG_SC_YSEL_8_WIDE_TILE        = 0x00000000,
19474 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE       = 0x00000001,
19475 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE       = 0x00000002,
19476 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE       = 0x00000003,
19477 } ScYsel;
19478 
19479 /*
19480  * ScMap enum
19481  */
19482 
19483 typedef enum ScMap {
19484 RASTER_CONFIG_SC_MAP_0                   = 0x00000000,
19485 RASTER_CONFIG_SC_MAP_1                   = 0x00000001,
19486 RASTER_CONFIG_SC_MAP_2                   = 0x00000002,
19487 RASTER_CONFIG_SC_MAP_3                   = 0x00000003,
19488 } ScMap;
19489 
19490 /*
19491  * PkrXsel2 enum
19492  */
19493 
19494 typedef enum PkrXsel2 {
19495 RASTER_CONFIG_PKR_XSEL2_0                = 0x00000000,
19496 RASTER_CONFIG_PKR_XSEL2_1                = 0x00000001,
19497 RASTER_CONFIG_PKR_XSEL2_2                = 0x00000002,
19498 RASTER_CONFIG_PKR_XSEL2_3                = 0x00000003,
19499 } PkrXsel2;
19500 
19501 /*
19502  * PkrXsel enum
19503  */
19504 
19505 typedef enum PkrXsel {
19506 RASTER_CONFIG_PKR_XSEL_0                 = 0x00000000,
19507 RASTER_CONFIG_PKR_XSEL_1                 = 0x00000001,
19508 RASTER_CONFIG_PKR_XSEL_2                 = 0x00000002,
19509 RASTER_CONFIG_PKR_XSEL_3                 = 0x00000003,
19510 } PkrXsel;
19511 
19512 /*
19513  * PkrYsel enum
19514  */
19515 
19516 typedef enum PkrYsel {
19517 RASTER_CONFIG_PKR_YSEL_0                 = 0x00000000,
19518 RASTER_CONFIG_PKR_YSEL_1                 = 0x00000001,
19519 RASTER_CONFIG_PKR_YSEL_2                 = 0x00000002,
19520 RASTER_CONFIG_PKR_YSEL_3                 = 0x00000003,
19521 } PkrYsel;
19522 
19523 /*
19524  * PkrMap enum
19525  */
19526 
19527 typedef enum PkrMap {
19528 RASTER_CONFIG_PKR_MAP_0                  = 0x00000000,
19529 RASTER_CONFIG_PKR_MAP_1                  = 0x00000001,
19530 RASTER_CONFIG_PKR_MAP_2                  = 0x00000002,
19531 RASTER_CONFIG_PKR_MAP_3                  = 0x00000003,
19532 } PkrMap;
19533 
19534 /*
19535  * RbXsel enum
19536  */
19537 
19538 typedef enum RbXsel {
19539 RASTER_CONFIG_RB_XSEL_0                  = 0x00000000,
19540 RASTER_CONFIG_RB_XSEL_1                  = 0x00000001,
19541 } RbXsel;
19542 
19543 /*
19544  * RbYsel enum
19545  */
19546 
19547 typedef enum RbYsel {
19548 RASTER_CONFIG_RB_YSEL_0                  = 0x00000000,
19549 RASTER_CONFIG_RB_YSEL_1                  = 0x00000001,
19550 } RbYsel;
19551 
19552 /*
19553  * RbXsel2 enum
19554  */
19555 
19556 typedef enum RbXsel2 {
19557 RASTER_CONFIG_RB_XSEL2_0                 = 0x00000000,
19558 RASTER_CONFIG_RB_XSEL2_1                 = 0x00000001,
19559 RASTER_CONFIG_RB_XSEL2_2                 = 0x00000002,
19560 RASTER_CONFIG_RB_XSEL2_3                 = 0x00000003,
19561 } RbXsel2;
19562 
19563 /*
19564  * RbMap enum
19565  */
19566 
19567 typedef enum RbMap {
19568 RASTER_CONFIG_RB_MAP_0                   = 0x00000000,
19569 RASTER_CONFIG_RB_MAP_1                   = 0x00000001,
19570 RASTER_CONFIG_RB_MAP_2                   = 0x00000002,
19571 RASTER_CONFIG_RB_MAP_3                   = 0x00000003,
19572 } RbMap;
19573 
19574 /*
19575  * BinningMode enum
19576  */
19577 
19578 typedef enum BinningMode {
19579 BINNING_ALLOWED                          = 0x00000000,
19580 FORCE_BINNING_ON                         = 0x00000001,
19581 DISABLE_BINNING_USE_NEW_SC               = 0x00000002,
19582 DISABLE_BINNING_USE_LEGACY_SC            = 0x00000003,
19583 } BinningMode;
19584 
19585 /*
19586  * BinSizeExtend enum
19587  */
19588 
19589 typedef enum BinSizeExtend {
19590 BIN_SIZE_32_PIXELS                       = 0x00000000,
19591 BIN_SIZE_64_PIXELS                       = 0x00000001,
19592 BIN_SIZE_128_PIXELS                      = 0x00000002,
19593 BIN_SIZE_256_PIXELS                      = 0x00000003,
19594 BIN_SIZE_512_PIXELS                      = 0x00000004,
19595 } BinSizeExtend;
19596 
19597 /*
19598  * BinMapMode enum
19599  */
19600 
19601 typedef enum BinMapMode {
19602 BIN_MAP_MODE_NONE                        = 0x00000000,
19603 BIN_MAP_MODE_RTA_INDEX                   = 0x00000001,
19604 BIN_MAP_MODE_POPS                        = 0x00000002,
19605 } BinMapMode;
19606 
19607 /*
19608  * BinEventCntl enum
19609  */
19610 
19611 typedef enum BinEventCntl {
19612 BINNER_BREAK_BATCH                       = 0x00000000,
19613 BINNER_PIPELINE                          = 0x00000001,
19614 BINNER_DROP                              = 0x00000002,
19615 BINNER_DROP_ASSERT                       = 0x00000003,
19616 } BinEventCntl;
19617 
19618 /*
19619  * CovToShaderSel enum
19620  */
19621 
19622 typedef enum CovToShaderSel {
19623 INPUT_COVERAGE                           = 0x00000000,
19624 INPUT_INNER_COVERAGE                     = 0x00000001,
19625 INPUT_DEPTH_COVERAGE                     = 0x00000002,
19626 #ifndef __NetBSD__		/* XXX &@!#!^ */
19627 RAW                                      = 0x00000003,
19628 #endif
19629 } CovToShaderSel;
19630 
19631 /*
19632  * ScUncertaintyRegionMode enum
19633  */
19634 
19635 typedef enum ScUncertaintyRegionMode {
19636 SC_HALF_LSB                              = 0x00000000,
19637 SC_LSB_ONE_SIDED                         = 0x00000001,
19638 SC_LSB_TWO_SIDED                         = 0x00000002,
19639 } ScUncertaintyRegionMode;
19640 
19641 /*******************************************************
19642  * RMI Enums
19643  *******************************************************/
19644 
19645 /*
19646  * RMIPerfSel enum
19647  */
19648 
19649 typedef enum RMIPerfSel {
19650 RMI_PERF_SEL_NONE                        = 0x00000000,
19651 RMI_PERF_SEL_BUSY                        = 0x00000001,
19652 RMI_PERF_SEL_REG_CLK_VLD                 = 0x00000002,
19653 RMI_PERF_SEL_DYN_CLK_CMN_VLD             = 0x00000003,
19654 RMI_PERF_SEL_DYN_CLK_RB_VLD              = 0x00000004,
19655 RMI_PERF_SEL_DYN_CLK_PERF_VLD            = 0x00000005,
19656 RMI_PERF_SEL_PERF_WINDOW                 = 0x00000006,
19657 RMI_PERF_SEL_EVENT_SEND                  = 0x00000007,
19658 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0  = 0x00000008,
19659 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1  = 0x00000009,
19660 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2  = 0x0000000a,
19661 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3  = 0x0000000b,
19662 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4  = 0x0000000c,
19663 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5  = 0x0000000d,
19664 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6  = 0x0000000e,
19665 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7  = 0x0000000f,
19666 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8  = 0x00000010,
19667 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9  = 0x00000011,
19668 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10  = 0x00000012,
19669 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11  = 0x00000013,
19670 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12  = 0x00000014,
19671 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13  = 0x00000015,
19672 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14  = 0x00000016,
19673 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15  = 0x00000017,
19674 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL  = 0x00000018,
19675 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0  = 0x00000019,
19676 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1  = 0x0000001a,
19677 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2  = 0x0000001b,
19678 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3  = 0x0000001c,
19679 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4  = 0x0000001d,
19680 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5  = 0x0000001e,
19681 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6  = 0x0000001f,
19682 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7  = 0x00000020,
19683 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8  = 0x00000021,
19684 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9  = 0x00000022,
19685 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10  = 0x00000023,
19686 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11  = 0x00000024,
19687 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12  = 0x00000025,
19688 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13  = 0x00000026,
19689 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14  = 0x00000027,
19690 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15  = 0x00000028,
19691 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL  = 0x00000029,
19692 RMI_PERF_SEL_UTCL1_TRANSLATION_MISS      = 0x0000002a,
19693 RMI_PERF_SEL_UTCL1_PERMISSION_MISS       = 0x0000002b,
19694 RMI_PERF_SEL_UTCL1_TRANSLATION_HIT       = 0x0000002c,
19695 RMI_PERF_SEL_UTCL1_REQUEST               = 0x0000002d,
19696 RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX    = 0x0000002e,
19697 RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT    = 0x0000002f,
19698 RMI_PERF_SEL_UTCL1_LFIFO_FULL            = 0x00000030,
19699 RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES   = 0x00000031,
19700 RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x00000032,
19701 RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL   = 0x00000033,
19702 RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL         = 0x00000034,
19703 RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS      = 0x00000035,
19704 RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID        = 0x00000036,
19705 RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY  = 0x00000037,
19706 RMI_PERF_SEL_RB_RMI_WRREQ_CID0           = 0x00000038,
19707 RMI_PERF_SEL_RB_RMI_WRREQ_CID1           = 0x00000039,
19708 RMI_PERF_SEL_RB_RMI_WRREQ_CID2           = 0x0000003a,
19709 RMI_PERF_SEL_RB_RMI_WRREQ_CID3           = 0x0000003b,
19710 RMI_PERF_SEL_RB_RMI_WRREQ_CID4           = 0x0000003c,
19711 RMI_PERF_SEL_RB_RMI_WRREQ_CID5           = 0x0000003d,
19712 RMI_PERF_SEL_RB_RMI_WRREQ_CID6           = 0x0000003e,
19713 RMI_PERF_SEL_RB_RMI_WRREQ_CID7           = 0x0000003f,
19714 RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID  = 0x00000040,
19715 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID  = 0x00000041,
19716 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID  = 0x00000042,
19717 RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY      = 0x00000043,
19718 RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID  = 0x00000044,
19719 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0     = 0x00000045,
19720 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1     = 0x00000046,
19721 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2     = 0x00000047,
19722 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3     = 0x00000048,
19723 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4     = 0x00000049,
19724 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5     = 0x0000004a,
19725 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6     = 0x0000004b,
19726 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7     = 0x0000004c,
19727 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0    = 0x0000004d,
19728 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1    = 0x0000004e,
19729 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2    = 0x0000004f,
19730 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3    = 0x00000050,
19731 RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID     = 0x00000051,
19732 RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID        = 0x00000052,
19733 RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY  = 0x00000053,
19734 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0        = 0x00000054,
19735 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1        = 0x00000055,
19736 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2        = 0x00000056,
19737 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3        = 0x00000057,
19738 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4        = 0x00000058,
19739 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5        = 0x00000059,
19740 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6        = 0x0000005a,
19741 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7        = 0x0000005b,
19742 RMI_PERF_SEL_RB_RMI_RDREQ_CID0           = 0x0000005c,
19743 RMI_PERF_SEL_RB_RMI_RDREQ_CID1           = 0x0000005d,
19744 RMI_PERF_SEL_RB_RMI_RDREQ_CID2           = 0x0000005e,
19745 RMI_PERF_SEL_RB_RMI_RDREQ_CID3           = 0x0000005f,
19746 RMI_PERF_SEL_RB_RMI_RDREQ_CID4           = 0x00000060,
19747 RMI_PERF_SEL_RB_RMI_RDREQ_CID5           = 0x00000061,
19748 RMI_PERF_SEL_RB_RMI_RDREQ_CID6           = 0x00000062,
19749 RMI_PERF_SEL_RB_RMI_RDREQ_CID7           = 0x00000063,
19750 RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID  = 0x00000064,
19751 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID  = 0x00000065,
19752 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID  = 0x00000066,
19753 RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY      = 0x00000067,
19754 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID  = 0x00000068,
19755 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0  = 0x00000069,
19756 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1  = 0x0000006a,
19757 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2  = 0x0000006b,
19758 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3  = 0x0000006c,
19759 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4  = 0x0000006d,
19760 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5  = 0x0000006e,
19761 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6  = 0x0000006f,
19762 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7  = 0x00000070,
19763 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0  = 0x00000071,
19764 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1  = 0x00000072,
19765 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2  = 0x00000073,
19766 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3  = 0x00000074,
19767 RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX          = 0x00000075,
19768 RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY        = 0x00000076,
19769 RMI_PERF_SEL_RB_RMI_WR_IDLE              = 0x00000077,
19770 RMI_PERF_SEL_RB_RMI_WR_STARVE            = 0x00000078,
19771 RMI_PERF_SEL_RB_RMI_WR_STALL             = 0x00000079,
19772 RMI_PERF_SEL_RB_RMI_WR_BUSY              = 0x0000007a,
19773 RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY         = 0x0000007b,
19774 RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX          = 0x0000007c,
19775 RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY        = 0x0000007d,
19776 RMI_PERF_SEL_RB_RMI_RD_IDLE              = 0x0000007e,
19777 RMI_PERF_SEL_RB_RMI_RD_STARVE            = 0x0000007f,
19778 RMI_PERF_SEL_RB_RMI_RD_STALL             = 0x00000080,
19779 RMI_PERF_SEL_RB_RMI_RD_BUSY              = 0x00000081,
19780 RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY         = 0x00000082,
19781 RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID  = 0x00000083,
19782 RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID  = 0x00000084,
19783 RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID        = 0x00000085,
19784 RMI_PERF_SEL_RMI_TC_REQ_BUSY             = 0x00000086,
19785 RMI_PERF_SEL_RMI_TC_WRREQ_CID0           = 0x00000087,
19786 RMI_PERF_SEL_RMI_TC_WRREQ_CID1           = 0x00000088,
19787 RMI_PERF_SEL_RMI_TC_WRREQ_CID2           = 0x00000089,
19788 RMI_PERF_SEL_RMI_TC_WRREQ_CID3           = 0x0000008a,
19789 RMI_PERF_SEL_RMI_TC_WRREQ_CID4           = 0x0000008b,
19790 RMI_PERF_SEL_RMI_TC_WRREQ_CID5           = 0x0000008c,
19791 RMI_PERF_SEL_RMI_TC_WRREQ_CID6           = 0x0000008d,
19792 RMI_PERF_SEL_RMI_TC_WRREQ_CID7           = 0x0000008e,
19793 RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID  = 0x0000008f,
19794 RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID  = 0x00000090,
19795 RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID        = 0x00000091,
19796 RMI_PERF_SEL_RMI_TC_RDREQ_CID0           = 0x00000092,
19797 RMI_PERF_SEL_RMI_TC_RDREQ_CID1           = 0x00000093,
19798 RMI_PERF_SEL_RMI_TC_RDREQ_CID2           = 0x00000094,
19799 RMI_PERF_SEL_RMI_TC_RDREQ_CID3           = 0x00000095,
19800 RMI_PERF_SEL_RMI_TC_RDREQ_CID4           = 0x00000096,
19801 RMI_PERF_SEL_RMI_TC_RDREQ_CID5           = 0x00000097,
19802 RMI_PERF_SEL_RMI_TC_RDREQ_CID6           = 0x00000098,
19803 RMI_PERF_SEL_RMI_TC_RDREQ_CID7           = 0x00000099,
19804 RMI_PERF_SEL_RMI_TC_STALL_RDREQ          = 0x0000009a,
19805 RMI_PERF_SEL_RMI_TC_STALL_WRREQ          = 0x0000009b,
19806 RMI_PERF_SEL_RMI_TC_STALL_ALLREQ         = 0x0000009c,
19807 RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND  = 0x0000009d,
19808 RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND  = 0x0000009e,
19809 RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID  = 0x0000009f,
19810 RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID  = 0x000000a0,
19811 RMI_PERF_SEL_UTCL1_BUSY                  = 0x000000a1,
19812 RMI_PERF_SEL_RMI_UTC_REQ                 = 0x000000a2,
19813 RMI_PERF_SEL_RMI_UTC_BUSY                = 0x000000a3,
19814 RMI_PERF_SEL_UTCL1_UTCL2_REQ             = 0x000000a4,
19815 RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2    = 0x000000a5,
19816 RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY     = 0x000000a6,
19817 RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT       = 0x000000a7,
19818 RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT       = 0x000000a8,
19819 RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS     = 0x000000a9,
19820 RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT  = 0x000000aa,
19821 RMI_PERF_SEL_XNACK_FIFO_NUM_USED         = 0x000000ab,
19822 RMI_PERF_SEL_LAT_FIFO_NUM_USED           = 0x000000ac,
19823 RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ       = 0x000000ad,
19824 RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ    = 0x000000ae,
19825 RMI_PERF_SEL_XNACK_FIFO_FULL             = 0x000000af,
19826 RMI_PERF_SEL_XNACK_FIFO_BUSY             = 0x000000b0,
19827 RMI_PERF_SEL_LAT_FIFO_FULL               = 0x000000b1,
19828 RMI_PERF_SEL_SKID_FIFO_DEPTH             = 0x000000b2,
19829 RMI_PERF_SEL_TCIW_INFLIGHT_COUNT         = 0x000000b3,
19830 RMI_PERF_SEL_PRT_FIFO_NUM_USED           = 0x000000b4,
19831 RMI_PERF_SEL_PRT_FIFO_REQ                = 0x000000b5,
19832 RMI_PERF_SEL_PRT_FIFO_BUSY               = 0x000000b6,
19833 RMI_PERF_SEL_TCIW_REQ                    = 0x000000b7,
19834 RMI_PERF_SEL_TCIW_BUSY                   = 0x000000b8,
19835 RMI_PERF_SEL_SKID_FIFO_REQ               = 0x000000b9,
19836 RMI_PERF_SEL_SKID_FIFO_BUSY              = 0x000000ba,
19837 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0  = 0x000000bb,
19838 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1  = 0x000000bc,
19839 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2  = 0x000000bd,
19840 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3  = 0x000000be,
19841 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR       = 0x000000bf,
19842 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR      = 0x000000c0,
19843 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB      = 0x000000c1,
19844 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB     = 0x000000c2,
19845 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR  = 0x000000c3,
19846 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR  = 0x000000c4,
19847 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB  = 0x000000c5,
19848 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB  = 0x000000c6,
19849 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR  = 0x000000c7,
19850 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR  = 0x000000c8,
19851 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB  = 0x000000c9,
19852 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB  = 0x000000ca,
19853 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR  = 0x000000cb,
19854 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR  = 0x000000cc,
19855 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB  = 0x000000cd,
19856 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB  = 0x000000ce,
19857 RMI_PERF_SEL_POP_DEMUX_RTS_RTR           = 0x000000cf,
19858 RMI_PERF_SEL_POP_DEMUX_RTSB_RTR          = 0x000000d0,
19859 RMI_PERF_SEL_POP_DEMUX_RTS_RTRB          = 0x000000d1,
19860 RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB         = 0x000000d2,
19861 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR        = 0x000000d3,
19862 RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC        = 0x000000d4,
19863 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR       = 0x000000d5,
19864 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB       = 0x000000d6,
19865 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB      = 0x000000d7,
19866 RMI_PERF_SEL_UTC_POP_RTS_RTR             = 0x000000d8,
19867 RMI_PERF_SEL_UTC_POP_RTSB_RTR            = 0x000000d9,
19868 RMI_PERF_SEL_UTC_POP_RTS_RTRB            = 0x000000da,
19869 RMI_PERF_SEL_UTC_POP_RTSB_RTRB           = 0x000000db,
19870 RMI_PERF_SEL_POP_XNACK_RTS_RTR           = 0x000000dc,
19871 RMI_PERF_SEL_POP_XNACK_RTSB_RTR          = 0x000000dd,
19872 RMI_PERF_SEL_POP_XNACK_RTS_RTRB          = 0x000000de,
19873 RMI_PERF_SEL_POP_XNACK_RTSB_RTRB         = 0x000000df,
19874 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR      = 0x000000e0,
19875 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR     = 0x000000e1,
19876 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB     = 0x000000e2,
19877 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB    = 0x000000e3,
19878 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR  = 0x000000e4,
19879 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR  = 0x000000e5,
19880 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB  = 0x000000e6,
19881 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB  = 0x000000e7,
19882 RMI_PERF_SEL_SKID_FIFO_IN_RTS            = 0x000000e8,
19883 RMI_PERF_SEL_SKID_FIFO_IN_RTSB           = 0x000000e9,
19884 RMI_PERF_SEL_SKID_FIFO_OUT_RTS           = 0x000000ea,
19885 RMI_PERF_SEL_SKID_FIFO_OUT_RTSB          = 0x000000eb,
19886 RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR  = 0x000000ec,
19887 RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR  = 0x000000ed,
19888 RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR   = 0x000000ee,
19889 RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR   = 0x000000ef,
19890 RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR    = 0x000000f0,
19891 RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR    = 0x000000f1,
19892 RMI_PERF_SEL_REORDER_FIFO_REQ            = 0x000000f2,
19893 RMI_PERF_SEL_REORDER_FIFO_BUSY           = 0x000000f3,
19894 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID  = 0x000000f4,
19895 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0     = 0x000000f5,
19896 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1     = 0x000000f6,
19897 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2     = 0x000000f7,
19898 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3     = 0x000000f8,
19899 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4     = 0x000000f9,
19900 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5     = 0x000000fa,
19901 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6     = 0x000000fb,
19902 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7     = 0x000000fc,
19903 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0    = 0x000000fd,
19904 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1    = 0x000000fe,
19905 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2    = 0x000000ff,
19906 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3    = 0x00000100,
19907 } RMIPerfSel;
19908 
19909 /*******************************************************
19910  * PMM Enums
19911  *******************************************************/
19912 
19913 /*
19914  * GCRPerfSel enum
19915  */
19916 
19917 typedef enum GCRPerfSel {
19918 GCR_PERF_SEL_NONE                        = 0x00000000,
19919 GCR_PERF_SEL_SDMA0_ALL_REQ               = 0x00000001,
19920 GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ         = 0x00000002,
19921 GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ   = 0x00000003,
19922 GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ     = 0x00000004,
19923 GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ   = 0x00000005,
19924 GCR_PERF_SEL_SDMA0_GL2_ALL_REQ           = 0x00000006,
19925 GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ         = 0x00000007,
19926 GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ   = 0x00000008,
19927 GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ     = 0x00000009,
19928 GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ   = 0x0000000a,
19929 GCR_PERF_SEL_SDMA0_GL1_ALL_REQ           = 0x0000000b,
19930 GCR_PERF_SEL_SDMA0_METADATA_REQ          = 0x0000000c,
19931 GCR_PERF_SEL_SDMA0_SQC_DATA_REQ          = 0x0000000d,
19932 GCR_PERF_SEL_SDMA0_SQC_INST_REQ          = 0x0000000e,
19933 GCR_PERF_SEL_SDMA0_TCP_REQ               = 0x0000000f,
19934 GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ  = 0x00000010,
19935 GCR_PERF_SEL_SDMA1_ALL_REQ               = 0x00000011,
19936 GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ         = 0x00000012,
19937 GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ   = 0x00000013,
19938 GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ     = 0x00000014,
19939 GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ   = 0x00000015,
19940 GCR_PERF_SEL_SDMA1_GL2_ALL_REQ           = 0x00000016,
19941 GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ         = 0x00000017,
19942 GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ   = 0x00000018,
19943 GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ     = 0x00000019,
19944 GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ   = 0x0000001a,
19945 GCR_PERF_SEL_SDMA1_GL1_ALL_REQ           = 0x0000001b,
19946 GCR_PERF_SEL_SDMA1_METADATA_REQ          = 0x0000001c,
19947 GCR_PERF_SEL_SDMA1_SQC_DATA_REQ          = 0x0000001d,
19948 GCR_PERF_SEL_SDMA1_SQC_INST_REQ          = 0x0000001e,
19949 GCR_PERF_SEL_SDMA1_TCP_REQ               = 0x0000001f,
19950 GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ  = 0x00000020,
19951 GCR_PERF_SEL_CPG_ALL_REQ                 = 0x00000021,
19952 GCR_PERF_SEL_CPG_GL2_RANGE_REQ           = 0x00000022,
19953 GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ     = 0x00000023,
19954 GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ       = 0x00000024,
19955 GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ     = 0x00000025,
19956 GCR_PERF_SEL_CPG_GL2_ALL_REQ             = 0x00000026,
19957 GCR_PERF_SEL_CPG_GL1_RANGE_REQ           = 0x00000027,
19958 GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ     = 0x00000028,
19959 GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ       = 0x00000029,
19960 GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ     = 0x0000002a,
19961 GCR_PERF_SEL_CPG_GL1_ALL_REQ             = 0x0000002b,
19962 GCR_PERF_SEL_CPG_METADATA_REQ            = 0x0000002c,
19963 GCR_PERF_SEL_CPG_SQC_DATA_REQ            = 0x0000002d,
19964 GCR_PERF_SEL_CPG_SQC_INST_REQ            = 0x0000002e,
19965 GCR_PERF_SEL_CPG_TCP_REQ                 = 0x0000002f,
19966 GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ   = 0x00000030,
19967 GCR_PERF_SEL_CPC_ALL_REQ                 = 0x00000031,
19968 GCR_PERF_SEL_CPC_GL2_RANGE_REQ           = 0x00000032,
19969 GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ     = 0x00000033,
19970 GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ       = 0x00000034,
19971 GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ     = 0x00000035,
19972 GCR_PERF_SEL_CPC_GL2_ALL_REQ             = 0x00000036,
19973 GCR_PERF_SEL_CPC_GL1_RANGE_REQ           = 0x00000037,
19974 GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ     = 0x00000038,
19975 GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ       = 0x00000039,
19976 GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ     = 0x0000003a,
19977 GCR_PERF_SEL_CPC_GL1_ALL_REQ             = 0x0000003b,
19978 GCR_PERF_SEL_CPC_METADATA_REQ            = 0x0000003c,
19979 GCR_PERF_SEL_CPC_SQC_DATA_REQ            = 0x0000003d,
19980 GCR_PERF_SEL_CPC_SQC_INST_REQ            = 0x0000003e,
19981 GCR_PERF_SEL_CPC_TCP_REQ                 = 0x0000003f,
19982 GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ   = 0x00000040,
19983 GCR_PERF_SEL_CPF_ALL_REQ                 = 0x00000041,
19984 GCR_PERF_SEL_CPF_GL2_RANGE_REQ           = 0x00000042,
19985 GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ     = 0x00000043,
19986 GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ       = 0x00000044,
19987 GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ     = 0x00000045,
19988 GCR_PERF_SEL_CPF_GL2_ALL_REQ             = 0x00000046,
19989 GCR_PERF_SEL_CPF_GL1_RANGE_REQ           = 0x00000047,
19990 GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ     = 0x00000048,
19991 GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ       = 0x00000049,
19992 GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ     = 0x0000004a,
19993 GCR_PERF_SEL_CPF_GL1_ALL_REQ             = 0x0000004b,
19994 GCR_PERF_SEL_CPF_METADATA_REQ            = 0x0000004c,
19995 GCR_PERF_SEL_CPF_SQC_DATA_REQ            = 0x0000004d,
19996 GCR_PERF_SEL_CPF_SQC_INST_REQ            = 0x0000004e,
19997 GCR_PERF_SEL_CPF_TCP_REQ                 = 0x0000004f,
19998 GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ   = 0x00000050,
19999 GCR_PERF_SEL_VIRT_REQ                    = 0x00000051,
20000 GCR_PERF_SEL_PHY_REQ                     = 0x00000052,
20001 GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ     = 0x00000053,
20002 GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ     = 0x00000054,
20003 GCR_PERF_SEL_ALL_REQ                     = 0x00000055,
20004 GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ  = 0x00000056,
20005 GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ  = 0x00000057,
20006 GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ  = 0x00000058,
20007 GCR_PERF_SEL_UTCL2_REQ                   = 0x00000059,
20008 GCR_PERF_SEL_UTCL2_RET                   = 0x0000005a,
20009 GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT   = 0x0000005b,
20010 GCR_PERF_SEL_UTCL2_INFLIGHT_REQ          = 0x0000005c,
20011 GCR_PERF_SEL_UTCL2_FILTERED_RET          = 0x0000005d,
20012 } GCRPerfSel;
20013 
20014 /*******************************************************
20015  * UTCL1 Enums
20016  *******************************************************/
20017 
20018 /*
20019  * UTCL1PerfSel enum
20020  */
20021 
20022 typedef enum UTCL1PerfSel {
20023 UTCL1_PERF_SEL_NONE                      = 0x00000000,
20024 UTCL1_PERF_SEL_REQS                      = 0x00000001,
20025 UTCL1_PERF_SEL_HITS                      = 0x00000002,
20026 UTCL1_PERF_SEL_MISSES                    = 0x00000003,
20027 UTCL1_PERF_SEL_BYPASS_REQS               = 0x00000004,
20028 UTCL1_PERF_SEL_HIT_INV_FILTER_REQS       = 0x00000005,
20029 UTCL1_PERF_SEL_NUM_SMALLK_PAGES          = 0x00000006,
20030 UTCL1_PERF_SEL_NUM_BIGK_PAGES            = 0x00000007,
20031 UTCL1_PERF_SEL_TOTAL_UTCL2_REQS          = 0x00000008,
20032 UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM  = 0x00000009,
20033 UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS    = 0x0000000a,
20034 UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL       = 0x0000000b,
20035 UTCL1_PERF_SEL_STALL_MH_CAM_FULL         = 0x0000000c,
20036 UTCL1_PERF_SEL_NONRANGE_INV_REQS         = 0x0000000d,
20037 UTCL1_PERF_SEL_RANGE_INV_REQS            = 0x0000000e,
20038 } UTCL1PerfSel;
20039 
20040 /*******************************************************
20041  * SDMA Enums
20042  *******************************************************/
20043 
20044 /*
20045  * SDMA_PERF_SEL enum
20046  */
20047 
20048 typedef enum SDMA_PERF_SEL {
20049 SDMA_PERF_SEL_CYCLE                      = 0x00000000,
20050 SDMA_PERF_SEL_IDLE                       = 0x00000001,
20051 SDMA_PERF_SEL_REG_IDLE                   = 0x00000002,
20052 SDMA_PERF_SEL_RB_EMPTY                   = 0x00000003,
20053 SDMA_PERF_SEL_RB_FULL                    = 0x00000004,
20054 SDMA_PERF_SEL_RB_WPTR_WRAP               = 0x00000005,
20055 SDMA_PERF_SEL_RB_RPTR_WRAP               = 0x00000006,
20056 SDMA_PERF_SEL_RB_WPTR_POLL_READ          = 0x00000007,
20057 SDMA_PERF_SEL_RB_RPTR_WB                 = 0x00000008,
20058 SDMA_PERF_SEL_RB_CMD_IDLE                = 0x00000009,
20059 SDMA_PERF_SEL_RB_CMD_FULL                = 0x0000000a,
20060 SDMA_PERF_SEL_IB_CMD_IDLE                = 0x0000000b,
20061 SDMA_PERF_SEL_IB_CMD_FULL                = 0x0000000c,
20062 SDMA_PERF_SEL_EX_IDLE                    = 0x0000000d,
20063 SDMA_PERF_SEL_SRBM_REG_SEND              = 0x0000000e,
20064 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE  = 0x0000000f,
20065 SDMA_PERF_SEL_MC_WR_IDLE                 = 0x00000010,
20066 SDMA_PERF_SEL_MC_WR_COUNT                = 0x00000011,
20067 SDMA_PERF_SEL_MC_RD_IDLE                 = 0x00000012,
20068 SDMA_PERF_SEL_MC_RD_COUNT                = 0x00000013,
20069 SDMA_PERF_SEL_MC_RD_RET_STALL            = 0x00000014,
20070 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE         = 0x00000015,
20071 SDMA_PERF_SEL_SEM_IDLE                   = 0x00000018,
20072 SDMA_PERF_SEL_SEM_REQ_STALL              = 0x00000019,
20073 SDMA_PERF_SEL_SEM_REQ_COUNT              = 0x0000001a,
20074 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE        = 0x0000001b,
20075 SDMA_PERF_SEL_SEM_RESP_FAIL              = 0x0000001c,
20076 SDMA_PERF_SEL_SEM_RESP_PASS              = 0x0000001d,
20077 SDMA_PERF_SEL_INT_IDLE                   = 0x0000001e,
20078 SDMA_PERF_SEL_INT_REQ_STALL              = 0x0000001f,
20079 SDMA_PERF_SEL_INT_REQ_COUNT              = 0x00000020,
20080 SDMA_PERF_SEL_INT_RESP_ACCEPTED          = 0x00000021,
20081 SDMA_PERF_SEL_INT_RESP_RETRY             = 0x00000022,
20082 SDMA_PERF_SEL_NUM_PACKET                 = 0x00000023,
20083 SDMA_PERF_SEL_CE_WREQ_IDLE               = 0x00000025,
20084 SDMA_PERF_SEL_CE_WR_IDLE                 = 0x00000026,
20085 SDMA_PERF_SEL_CE_SPLIT_IDLE              = 0x00000027,
20086 SDMA_PERF_SEL_CE_RREQ_IDLE               = 0x00000028,
20087 SDMA_PERF_SEL_CE_OUT_IDLE                = 0x00000029,
20088 SDMA_PERF_SEL_CE_IN_IDLE                 = 0x0000002a,
20089 SDMA_PERF_SEL_CE_DST_IDLE                = 0x0000002b,
20090 SDMA_PERF_SEL_CE_AFIFO_FULL              = 0x0000002e,
20091 SDMA_PERF_SEL_CE_INFO_FULL               = 0x00000031,
20092 SDMA_PERF_SEL_CE_INFO1_FULL              = 0x00000032,
20093 SDMA_PERF_SEL_CE_RD_STALL                = 0x00000033,
20094 SDMA_PERF_SEL_CE_WR_STALL                = 0x00000034,
20095 SDMA_PERF_SEL_GFX_SELECT                 = 0x00000035,
20096 SDMA_PERF_SEL_RLC0_SELECT                = 0x00000036,
20097 SDMA_PERF_SEL_RLC1_SELECT                = 0x00000037,
20098 SDMA_PERF_SEL_PAGE_SELECT                = 0x00000038,
20099 SDMA_PERF_SEL_CTX_CHANGE                 = 0x00000039,
20100 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED         = 0x0000003a,
20101 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION       = 0x0000003b,
20102 SDMA_PERF_SEL_DOORBELL                   = 0x0000003c,
20103 SDMA_PERF_SEL_RD_BA_RTR                  = 0x0000003d,
20104 SDMA_PERF_SEL_WR_BA_RTR                  = 0x0000003e,
20105 SDMA_PERF_SEL_F32_L1_WR_VLD              = 0x0000003f,
20106 SDMA_PERF_SEL_CE_L1_WR_VLD               = 0x00000040,
20107 SDMA_PERF_SEL_CPF_SDMA_INVREQ            = 0x00000041,
20108 SDMA_PERF_SEL_SDMA_CPF_INVACK            = 0x00000042,
20109 SDMA_PERF_SEL_UTCL2_SDMA_INVREQ          = 0x00000043,
20110 SDMA_PERF_SEL_SDMA_UTCL2_INVACK          = 0x00000044,
20111 SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL      = 0x00000045,
20112 SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL      = 0x00000046,
20113 SDMA_PERF_SEL_UTCL2_RET_XNACK            = 0x00000047,
20114 SDMA_PERF_SEL_UTCL2_RET_ACK              = 0x00000048,
20115 SDMA_PERF_SEL_UTCL2_FREE                 = 0x00000049,
20116 SDMA_PERF_SEL_SDMA_UTCL2_SEND            = 0x0000004a,
20117 SDMA_PERF_SEL_DMA_L1_WR_SEND             = 0x0000004b,
20118 SDMA_PERF_SEL_DMA_L1_RD_SEND             = 0x0000004c,
20119 SDMA_PERF_SEL_DMA_MC_WR_SEND             = 0x0000004d,
20120 SDMA_PERF_SEL_DMA_MC_RD_SEND             = 0x0000004e,
20121 SDMA_PERF_SEL_GPUVM_INVREQ_HIGH          = 0x0000004f,
20122 SDMA_PERF_SEL_GPUVM_INVREQ_LOW           = 0x00000050,
20123 SDMA_PERF_SEL_L1_WRL2_IDLE               = 0x00000051,
20124 SDMA_PERF_SEL_L1_RDL2_IDLE               = 0x00000052,
20125 SDMA_PERF_SEL_L1_WRMC_IDLE               = 0x00000053,
20126 SDMA_PERF_SEL_L1_RDMC_IDLE               = 0x00000054,
20127 SDMA_PERF_SEL_L1_WR_INV_IDLE             = 0x00000055,
20128 SDMA_PERF_SEL_L1_RD_INV_IDLE             = 0x00000056,
20129 SDMA_PERF_SEL_META_L2_REQ_SEND           = 0x00000057,
20130 SDMA_PERF_SEL_L2_META_RET_VLD            = 0x00000058,
20131 SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND         = 0x00000059,
20132 SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN          = 0x0000005a,
20133 SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND         = 0x0000005b,
20134 SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN          = 0x0000005c,
20135 SDMA_PERF_SEL_META_REQ_SEND              = 0x0000005d,
20136 SDMA_PERF_SEL_META_RTN_VLD               = 0x0000005e,
20137 SDMA_PERF_SEL_TLBI_SEND                  = 0x0000005f,
20138 SDMA_PERF_SEL_TLBI_RTN                   = 0x00000060,
20139 SDMA_PERF_SEL_GCR_SEND                   = 0x00000061,
20140 SDMA_PERF_SEL_GCR_RTN                    = 0x00000062,
20141 SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER    = 0x00000063,
20142 SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER    = 0x00000064,
20143 } SDMA_PERF_SEL;
20144 
20145 /*******************************************************
20146  * ADDRLIB Enums
20147  *******************************************************/
20148 
20149 /*
20150  * NUM_PIPES_BC_ENUM enum
20151  */
20152 
20153 typedef enum NUM_PIPES_BC_ENUM {
20154 ADDR_NUM_PIPES_BC_P8                     = 0x00000000,
20155 ADDR_NUM_PIPES_BC_P16                    = 0x00000001,
20156 } NUM_PIPES_BC_ENUM;
20157 
20158 /*
20159  * NUM_BANKS_BC_ENUM enum
20160  */
20161 
20162 typedef enum NUM_BANKS_BC_ENUM {
20163 ADDR_NUM_BANKS_BC_BANKS_1                = 0x00000000,
20164 ADDR_NUM_BANKS_BC_BANKS_2                = 0x00000001,
20165 ADDR_NUM_BANKS_BC_BANKS_4                = 0x00000002,
20166 ADDR_NUM_BANKS_BC_BANKS_8                = 0x00000003,
20167 ADDR_NUM_BANKS_BC_BANKS_16               = 0x00000004,
20168 } NUM_BANKS_BC_ENUM;
20169 
20170 /*
20171  * SWIZZLE_TYPE_ENUM enum
20172  */
20173 
20174 typedef enum SWIZZLE_TYPE_ENUM {
20175 SW_Z                                     = 0x00000000,
20176 SW_S                                     = 0x00000001,
20177 SW_D                                     = 0x00000002,
20178 SW_R                                     = 0x00000003,
20179 SW_L                                     = 0x00000004,
20180 } SWIZZLE_TYPE_ENUM;
20181 
20182 /*
20183  * TC_MICRO_TILE_MODE enum
20184  */
20185 
20186 typedef enum TC_MICRO_TILE_MODE {
20187 MICRO_TILE_MODE_LINEAR                   = 0x00000000,
20188 MICRO_TILE_MODE_RENDER_TARGET            = 0x00000001,
20189 MICRO_TILE_MODE_STD_2D                   = 0x00000002,
20190 MICRO_TILE_MODE_STD_3D                   = 0x00000003,
20191 MICRO_TILE_MODE_DISPLAY_2D               = 0x00000004,
20192 MICRO_TILE_MODE_DISPLAY_3D               = 0x00000005,
20193 MICRO_TILE_MODE_Z                        = 0x00000006,
20194 } TC_MICRO_TILE_MODE;
20195 
20196 /*
20197  * SWIZZLE_MODE_ENUM enum
20198  */
20199 
20200 typedef enum SWIZZLE_MODE_ENUM {
20201 SW_LINEAR                                = 0x00000000,
20202 SW_256B_S                                = 0x00000001,
20203 SW_256B_D                                = 0x00000002,
20204 SW_256B_R                                = 0x00000003,
20205 SW_4KB_Z                                 = 0x00000004,
20206 SW_4KB_S                                 = 0x00000005,
20207 SW_4KB_D                                 = 0x00000006,
20208 SW_4KB_R                                 = 0x00000007,
20209 SW_64KB_Z                                = 0x00000008,
20210 SW_64KB_S                                = 0x00000009,
20211 SW_64KB_D                                = 0x0000000a,
20212 SW_64KB_R                                = 0x0000000b,
20213 SW_VAR_Z                                 = 0x0000000c,
20214 SW_VAR_S                                 = 0x0000000d,
20215 SW_VAR_D                                 = 0x0000000e,
20216 SW_VAR_R                                 = 0x0000000f,
20217 SW_64KB_Z_T                              = 0x00000010,
20218 SW_64KB_S_T                              = 0x00000011,
20219 SW_64KB_D_T                              = 0x00000012,
20220 SW_64KB_R_T                              = 0x00000013,
20221 SW_4KB_Z_X                               = 0x00000014,
20222 SW_4KB_S_X                               = 0x00000015,
20223 SW_4KB_D_X                               = 0x00000016,
20224 SW_4KB_R_X                               = 0x00000017,
20225 SW_64KB_Z_X                              = 0x00000018,
20226 SW_64KB_S_X                              = 0x00000019,
20227 SW_64KB_D_X                              = 0x0000001a,
20228 SW_64KB_R_X                              = 0x0000001b,
20229 SW_VAR_Z_X                               = 0x0000001c,
20230 SW_VAR_S_X                               = 0x0000001d,
20231 SW_VAR_D_X                               = 0x0000001e,
20232 SW_VAR_R_X                               = 0x0000001f,
20233 } SWIZZLE_MODE_ENUM;
20234 
20235 /*
20236  * SurfaceEndian enum
20237  */
20238 
20239 typedef enum SurfaceEndian {
20240 ENDIAN_NONE                              = 0x00000000,
20241 ENDIAN_8IN16                             = 0x00000001,
20242 ENDIAN_8IN32                             = 0x00000002,
20243 ENDIAN_8IN64                             = 0x00000003,
20244 } SurfaceEndian;
20245 
20246 /*
20247  * ArrayMode enum
20248  */
20249 
20250 typedef enum ArrayMode {
20251 ARRAY_LINEAR_GENERAL                     = 0x00000000,
20252 ARRAY_LINEAR_ALIGNED                     = 0x00000001,
20253 ARRAY_1D_TILED_THIN1                     = 0x00000002,
20254 ARRAY_1D_TILED_THICK                     = 0x00000003,
20255 ARRAY_2D_TILED_THIN1                     = 0x00000004,
20256 ARRAY_PRT_TILED_THIN1                    = 0x00000005,
20257 ARRAY_PRT_2D_TILED_THIN1                 = 0x00000006,
20258 ARRAY_2D_TILED_THICK                     = 0x00000007,
20259 ARRAY_2D_TILED_XTHICK                    = 0x00000008,
20260 ARRAY_PRT_TILED_THICK                    = 0x00000009,
20261 ARRAY_PRT_2D_TILED_THICK                 = 0x0000000a,
20262 ARRAY_PRT_3D_TILED_THIN1                 = 0x0000000b,
20263 ARRAY_3D_TILED_THIN1                     = 0x0000000c,
20264 ARRAY_3D_TILED_THICK                     = 0x0000000d,
20265 ARRAY_3D_TILED_XTHICK                    = 0x0000000e,
20266 ARRAY_PRT_3D_TILED_THICK                 = 0x0000000f,
20267 } ArrayMode;
20268 
20269 /*
20270  * NumPipes enum
20271  */
20272 
20273 typedef enum NumPipes {
20274 ADDR_CONFIG_1_PIPE                       = 0x00000000,
20275 ADDR_CONFIG_2_PIPE                       = 0x00000001,
20276 ADDR_CONFIG_4_PIPE                       = 0x00000002,
20277 ADDR_CONFIG_8_PIPE                       = 0x00000003,
20278 ADDR_CONFIG_16_PIPE                      = 0x00000004,
20279 ADDR_CONFIG_32_PIPE                      = 0x00000005,
20280 ADDR_CONFIG_64_PIPE                      = 0x00000006,
20281 } NumPipes;
20282 
20283 /*
20284  * NumBanksConfig enum
20285  */
20286 
20287 typedef enum NumBanksConfig {
20288 ADDR_CONFIG_1_BANK                       = 0x00000000,
20289 ADDR_CONFIG_2_BANK                       = 0x00000001,
20290 ADDR_CONFIG_4_BANK                       = 0x00000002,
20291 ADDR_CONFIG_8_BANK                       = 0x00000003,
20292 ADDR_CONFIG_16_BANK                      = 0x00000004,
20293 } NumBanksConfig;
20294 
20295 /*
20296  * PipeInterleaveSize enum
20297  */
20298 
20299 typedef enum PipeInterleaveSize {
20300 ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
20301 ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
20302 ADDR_CONFIG_PIPE_INTERLEAVE_1KB          = 0x00000002,
20303 ADDR_CONFIG_PIPE_INTERLEAVE_2KB          = 0x00000003,
20304 } PipeInterleaveSize;
20305 
20306 /*
20307  * BankInterleaveSize enum
20308  */
20309 
20310 typedef enum BankInterleaveSize {
20311 ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
20312 ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
20313 ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
20314 ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
20315 } BankInterleaveSize;
20316 
20317 /*
20318  * NumShaderEngines enum
20319  */
20320 
20321 typedef enum NumShaderEngines {
20322 ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
20323 ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
20324 ADDR_CONFIG_4_SHADER_ENGINE              = 0x00000002,
20325 ADDR_CONFIG_8_SHADER_ENGINE              = 0x00000003,
20326 } NumShaderEngines;
20327 
20328 /*
20329  * NumRbPerShaderEngine enum
20330  */
20331 
20332 typedef enum NumRbPerShaderEngine {
20333 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE       = 0x00000000,
20334 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE       = 0x00000001,
20335 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE       = 0x00000002,
20336 } NumRbPerShaderEngine;
20337 
20338 /*
20339  * NumGPUs enum
20340  */
20341 
20342 typedef enum NumGPUs {
20343 ADDR_CONFIG_1_GPU                        = 0x00000000,
20344 ADDR_CONFIG_2_GPU                        = 0x00000001,
20345 ADDR_CONFIG_4_GPU                        = 0x00000002,
20346 ADDR_CONFIG_8_GPU                        = 0x00000003,
20347 } NumGPUs;
20348 
20349 /*
20350  * NumMaxCompressedFragments enum
20351  */
20352 
20353 typedef enum NumMaxCompressedFragments {
20354 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS   = 0x00000000,
20355 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS   = 0x00000001,
20356 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS   = 0x00000002,
20357 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS   = 0x00000003,
20358 } NumMaxCompressedFragments;
20359 
20360 /*
20361  * ShaderEngineTileSize enum
20362  */
20363 
20364 typedef enum ShaderEngineTileSize {
20365 ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
20366 ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
20367 } ShaderEngineTileSize;
20368 
20369 /*
20370  * MultiGPUTileSize enum
20371  */
20372 
20373 typedef enum MultiGPUTileSize {
20374 ADDR_CONFIG_GPU_TILE_16                  = 0x00000000,
20375 ADDR_CONFIG_GPU_TILE_32                  = 0x00000001,
20376 ADDR_CONFIG_GPU_TILE_64                  = 0x00000002,
20377 ADDR_CONFIG_GPU_TILE_128                 = 0x00000003,
20378 } MultiGPUTileSize;
20379 
20380 /*
20381  * RowSize enum
20382  */
20383 
20384 typedef enum RowSize {
20385 ADDR_CONFIG_1KB_ROW                      = 0x00000000,
20386 ADDR_CONFIG_2KB_ROW                      = 0x00000001,
20387 ADDR_CONFIG_4KB_ROW                      = 0x00000002,
20388 } RowSize;
20389 
20390 /*
20391  * NumLowerPipes enum
20392  */
20393 
20394 typedef enum NumLowerPipes {
20395 ADDR_CONFIG_1_LOWER_PIPES                = 0x00000000,
20396 ADDR_CONFIG_2_LOWER_PIPES                = 0x00000001,
20397 } NumLowerPipes;
20398 
20399 /*
20400  * ColorTransform enum
20401  */
20402 
20403 typedef enum ColorTransform {
20404 DCC_CT_AUTO                              = 0x00000000,
20405 DCC_CT_NONE                              = 0x00000001,
20406 ABGR_TO_A_BG_G_RB                        = 0x00000002,
20407 BGRA_TO_BG_G_RB_A                        = 0x00000003,
20408 } ColorTransform;
20409 
20410 /*
20411  * CompareRef enum
20412  */
20413 
20414 typedef enum CompareRef {
20415 REF_NEVER                                = 0x00000000,
20416 REF_LESS                                 = 0x00000001,
20417 REF_EQUAL                                = 0x00000002,
20418 REF_LEQUAL                               = 0x00000003,
20419 REF_GREATER                              = 0x00000004,
20420 REF_NOTEQUAL                             = 0x00000005,
20421 REF_GEQUAL                               = 0x00000006,
20422 REF_ALWAYS                               = 0x00000007,
20423 } CompareRef;
20424 
20425 /*
20426  * ReadSize enum
20427  */
20428 
20429 typedef enum ReadSize {
20430 READ_256_BITS                            = 0x00000000,
20431 READ_512_BITS                            = 0x00000001,
20432 } ReadSize;
20433 
20434 /*
20435  * DepthFormat enum
20436  */
20437 
20438 typedef enum DepthFormat {
20439 DEPTH_INVALID                            = 0x00000000,
20440 DEPTH_16                                 = 0x00000001,
20441 DEPTH_X8_24                              = 0x00000002,
20442 DEPTH_8_24                               = 0x00000003,
20443 DEPTH_X8_24_FLOAT                        = 0x00000004,
20444 DEPTH_8_24_FLOAT                         = 0x00000005,
20445 DEPTH_32_FLOAT                           = 0x00000006,
20446 DEPTH_X24_8_32_FLOAT                     = 0x00000007,
20447 } DepthFormat;
20448 
20449 /*
20450  * ZFormat enum
20451  */
20452 
20453 typedef enum ZFormat {
20454 Z_INVALID                                = 0x00000000,
20455 Z_16                                     = 0x00000001,
20456 Z_24                                     = 0x00000002,
20457 Z_32_FLOAT                               = 0x00000003,
20458 } ZFormat;
20459 
20460 /*
20461  * StencilFormat enum
20462  */
20463 
20464 typedef enum StencilFormat {
20465 STENCIL_INVALID                          = 0x00000000,
20466 STENCIL_8                                = 0x00000001,
20467 } StencilFormat;
20468 
20469 /*
20470  * CmaskMode enum
20471  */
20472 
20473 typedef enum CmaskMode {
20474 CMASK_CLEAR_NONE                         = 0x00000000,
20475 CMASK_CLEAR_ONE                          = 0x00000001,
20476 CMASK_CLEAR_ALL                          = 0x00000002,
20477 CMASK_ANY_EXPANDED                       = 0x00000003,
20478 CMASK_ALPHA0_FRAG1                       = 0x00000004,
20479 CMASK_ALPHA0_FRAG2                       = 0x00000005,
20480 CMASK_ALPHA0_FRAG4                       = 0x00000006,
20481 CMASK_ALPHA0_FRAGS                       = 0x00000007,
20482 CMASK_ALPHA1_FRAG1                       = 0x00000008,
20483 CMASK_ALPHA1_FRAG2                       = 0x00000009,
20484 CMASK_ALPHA1_FRAG4                       = 0x0000000a,
20485 CMASK_ALPHA1_FRAGS                       = 0x0000000b,
20486 CMASK_ALPHAX_FRAG1                       = 0x0000000c,
20487 CMASK_ALPHAX_FRAG2                       = 0x0000000d,
20488 CMASK_ALPHAX_FRAG4                       = 0x0000000e,
20489 CMASK_ALPHAX_FRAGS                       = 0x0000000f,
20490 } CmaskMode;
20491 
20492 /*
20493  * QuadExportFormat enum
20494  */
20495 
20496 typedef enum QuadExportFormat {
20497 EXPORT_UNUSED                            = 0x00000000,
20498 EXPORT_32_R                              = 0x00000001,
20499 EXPORT_32_GR                             = 0x00000002,
20500 EXPORT_32_AR                             = 0x00000003,
20501 EXPORT_FP16_ABGR                         = 0x00000004,
20502 EXPORT_UNSIGNED16_ABGR                   = 0x00000005,
20503 EXPORT_SIGNED16_ABGR                     = 0x00000006,
20504 EXPORT_32_ABGR                           = 0x00000007,
20505 EXPORT_32BPP_8PIX                        = 0x00000008,
20506 EXPORT_16_16_UNSIGNED_8PIX               = 0x00000009,
20507 EXPORT_16_16_SIGNED_8PIX                 = 0x0000000a,
20508 EXPORT_16_16_FLOAT_8PIX                  = 0x0000000b,
20509 } QuadExportFormat;
20510 
20511 /*
20512  * QuadExportFormatOld enum
20513  */
20514 
20515 typedef enum QuadExportFormatOld {
20516 EXPORT_4P_32BPC_ABGR                     = 0x00000000,
20517 EXPORT_4P_16BPC_ABGR                     = 0x00000001,
20518 EXPORT_4P_32BPC_GR                       = 0x00000002,
20519 EXPORT_4P_32BPC_AR                       = 0x00000003,
20520 EXPORT_2P_32BPC_ABGR                     = 0x00000004,
20521 EXPORT_8P_32BPC_R                        = 0x00000005,
20522 } QuadExportFormatOld;
20523 
20524 /*
20525  * ColorFormat enum
20526  */
20527 
20528 typedef enum ColorFormat {
20529 COLOR_INVALID                            = 0x00000000,
20530 COLOR_8                                  = 0x00000001,
20531 COLOR_16                                 = 0x00000002,
20532 COLOR_8_8                                = 0x00000003,
20533 COLOR_32                                 = 0x00000004,
20534 COLOR_16_16                              = 0x00000005,
20535 COLOR_10_11_11                           = 0x00000006,
20536 COLOR_11_11_10                           = 0x00000007,
20537 COLOR_10_10_10_2                         = 0x00000008,
20538 COLOR_2_10_10_10                         = 0x00000009,
20539 COLOR_8_8_8_8                            = 0x0000000a,
20540 COLOR_32_32                              = 0x0000000b,
20541 COLOR_16_16_16_16                        = 0x0000000c,
20542 COLOR_RESERVED_13                        = 0x0000000d,
20543 COLOR_32_32_32_32                        = 0x0000000e,
20544 COLOR_RESERVED_15                        = 0x0000000f,
20545 COLOR_5_6_5                              = 0x00000010,
20546 COLOR_1_5_5_5                            = 0x00000011,
20547 COLOR_5_5_5_1                            = 0x00000012,
20548 COLOR_4_4_4_4                            = 0x00000013,
20549 COLOR_8_24                               = 0x00000014,
20550 COLOR_24_8                               = 0x00000015,
20551 COLOR_X24_8_32_FLOAT                     = 0x00000016,
20552 COLOR_RESERVED_23                        = 0x00000017,
20553 COLOR_RESERVED_24                        = 0x00000018,
20554 COLOR_RESERVED_25                        = 0x00000019,
20555 COLOR_RESERVED_26                        = 0x0000001a,
20556 COLOR_RESERVED_27                        = 0x0000001b,
20557 COLOR_RESERVED_28                        = 0x0000001c,
20558 COLOR_RESERVED_29                        = 0x0000001d,
20559 COLOR_RESERVED_30                        = 0x0000001e,
20560 COLOR_2_10_10_10_6E4                     = 0x0000001f,
20561 } ColorFormat;
20562 
20563 /*
20564  * SurfaceFormat enum
20565  */
20566 
20567 typedef enum SurfaceFormat {
20568 FMT_INVALID                              = 0x00000000,
20569 FMT_8                                    = 0x00000001,
20570 FMT_16                                   = 0x00000002,
20571 FMT_8_8                                  = 0x00000003,
20572 FMT_32                                   = 0x00000004,
20573 FMT_16_16                                = 0x00000005,
20574 FMT_10_11_11                             = 0x00000006,
20575 FMT_11_11_10                             = 0x00000007,
20576 FMT_10_10_10_2                           = 0x00000008,
20577 FMT_2_10_10_10                           = 0x00000009,
20578 FMT_8_8_8_8                              = 0x0000000a,
20579 FMT_32_32                                = 0x0000000b,
20580 FMT_16_16_16_16                          = 0x0000000c,
20581 FMT_32_32_32                             = 0x0000000d,
20582 FMT_32_32_32_32                          = 0x0000000e,
20583 FMT_RESERVED_4                           = 0x0000000f,
20584 FMT_5_6_5                                = 0x00000010,
20585 FMT_1_5_5_5                              = 0x00000011,
20586 FMT_5_5_5_1                              = 0x00000012,
20587 FMT_4_4_4_4                              = 0x00000013,
20588 FMT_8_24                                 = 0x00000014,
20589 FMT_24_8                                 = 0x00000015,
20590 FMT_X24_8_32_FLOAT                       = 0x00000016,
20591 FMT_RESERVED_33                          = 0x00000017,
20592 FMT_11_11_10_FLOAT                       = 0x00000018,
20593 FMT_16_FLOAT                             = 0x00000019,
20594 FMT_32_FLOAT                             = 0x0000001a,
20595 FMT_16_16_FLOAT                          = 0x0000001b,
20596 FMT_8_24_FLOAT                           = 0x0000001c,
20597 FMT_24_8_FLOAT                           = 0x0000001d,
20598 FMT_32_32_FLOAT                          = 0x0000001e,
20599 FMT_10_11_11_FLOAT                       = 0x0000001f,
20600 FMT_16_16_16_16_FLOAT                    = 0x00000020,
20601 FMT_3_3_2                                = 0x00000021,
20602 FMT_6_5_5                                = 0x00000022,
20603 FMT_32_32_32_32_FLOAT                    = 0x00000023,
20604 FMT_RESERVED_36                          = 0x00000024,
20605 FMT_1                                    = 0x00000025,
20606 FMT_1_REVERSED                           = 0x00000026,
20607 FMT_GB_GR                                = 0x00000027,
20608 FMT_BG_RG                                = 0x00000028,
20609 FMT_32_AS_8                              = 0x00000029,
20610 FMT_32_AS_8_8                            = 0x0000002a,
20611 FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
20612 FMT_8_8_8                                = 0x0000002c,
20613 FMT_16_16_16                             = 0x0000002d,
20614 FMT_16_16_16_FLOAT                       = 0x0000002e,
20615 FMT_4_4                                  = 0x0000002f,
20616 FMT_32_32_32_FLOAT                       = 0x00000030,
20617 FMT_BC1                                  = 0x00000031,
20618 FMT_BC2                                  = 0x00000032,
20619 FMT_BC3                                  = 0x00000033,
20620 FMT_BC4                                  = 0x00000034,
20621 FMT_BC5                                  = 0x00000035,
20622 FMT_BC6                                  = 0x00000036,
20623 FMT_BC7                                  = 0x00000037,
20624 FMT_32_AS_32_32_32_32                    = 0x00000038,
20625 FMT_APC3                                 = 0x00000039,
20626 FMT_APC4                                 = 0x0000003a,
20627 FMT_APC5                                 = 0x0000003b,
20628 FMT_APC6                                 = 0x0000003c,
20629 FMT_APC7                                 = 0x0000003d,
20630 FMT_CTX1                                 = 0x0000003e,
20631 FMT_RESERVED_63                          = 0x0000003f,
20632 } SurfaceFormat;
20633 
20634 /*
20635  * IMG_NUM_FORMAT_FMASK enum
20636  */
20637 
20638 typedef enum IMG_NUM_FORMAT_FMASK {
20639 IMG_NUM_FORMAT_FMASK_8_2_1               = 0x00000000,
20640 IMG_NUM_FORMAT_FMASK_8_4_1               = 0x00000001,
20641 IMG_NUM_FORMAT_FMASK_8_8_1               = 0x00000002,
20642 IMG_NUM_FORMAT_FMASK_8_2_2               = 0x00000003,
20643 IMG_NUM_FORMAT_FMASK_8_4_2               = 0x00000004,
20644 IMG_NUM_FORMAT_FMASK_8_4_4               = 0x00000005,
20645 IMG_NUM_FORMAT_FMASK_16_16_1             = 0x00000006,
20646 IMG_NUM_FORMAT_FMASK_16_8_2              = 0x00000007,
20647 IMG_NUM_FORMAT_FMASK_32_16_2             = 0x00000008,
20648 IMG_NUM_FORMAT_FMASK_32_8_4              = 0x00000009,
20649 IMG_NUM_FORMAT_FMASK_32_8_8              = 0x0000000a,
20650 IMG_NUM_FORMAT_FMASK_64_16_4             = 0x0000000b,
20651 IMG_NUM_FORMAT_FMASK_64_16_8             = 0x0000000c,
20652 IMG_NUM_FORMAT_FMASK_RESERVED_13         = 0x0000000d,
20653 IMG_NUM_FORMAT_FMASK_RESERVED_14         = 0x0000000e,
20654 IMG_NUM_FORMAT_FMASK_RESERVED_15         = 0x0000000f,
20655 } IMG_NUM_FORMAT_FMASK;
20656 
20657 /*
20658  * IMG_NUM_FORMAT_N_IN_16 enum
20659  */
20660 
20661 typedef enum IMG_NUM_FORMAT_N_IN_16 {
20662 IMG_NUM_FORMAT_N_IN_16_RESERVED_0        = 0x00000000,
20663 IMG_NUM_FORMAT_N_IN_16_UNORM_10          = 0x00000001,
20664 IMG_NUM_FORMAT_N_IN_16_UNORM_9           = 0x00000002,
20665 IMG_NUM_FORMAT_N_IN_16_RESERVED_3        = 0x00000003,
20666 IMG_NUM_FORMAT_N_IN_16_UINT_10           = 0x00000004,
20667 IMG_NUM_FORMAT_N_IN_16_UINT_9            = 0x00000005,
20668 IMG_NUM_FORMAT_N_IN_16_RESERVED_6        = 0x00000006,
20669 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10     = 0x00000007,
20670 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9      = 0x00000008,
20671 IMG_NUM_FORMAT_N_IN_16_RESERVED_9        = 0x00000009,
20672 IMG_NUM_FORMAT_N_IN_16_RESERVED_10       = 0x0000000a,
20673 IMG_NUM_FORMAT_N_IN_16_RESERVED_11       = 0x0000000b,
20674 IMG_NUM_FORMAT_N_IN_16_RESERVED_12       = 0x0000000c,
20675 IMG_NUM_FORMAT_N_IN_16_RESERVED_13       = 0x0000000d,
20676 IMG_NUM_FORMAT_N_IN_16_RESERVED_14       = 0x0000000e,
20677 IMG_NUM_FORMAT_N_IN_16_RESERVED_15       = 0x0000000f,
20678 } IMG_NUM_FORMAT_N_IN_16;
20679 
20680 /*
20681  * TileType enum
20682  */
20683 
20684 typedef enum TileType {
20685 ARRAY_COLOR_TILE                         = 0x00000000,
20686 ARRAY_DEPTH_TILE                         = 0x00000001,
20687 } TileType;
20688 
20689 /*
20690  * NonDispTilingOrder enum
20691  */
20692 
20693 typedef enum NonDispTilingOrder {
20694 ADDR_SURF_MICRO_TILING_DISPLAY           = 0x00000000,
20695 ADDR_SURF_MICRO_TILING_NON_DISPLAY       = 0x00000001,
20696 } NonDispTilingOrder;
20697 
20698 /*
20699  * MicroTileMode enum
20700  */
20701 
20702 typedef enum MicroTileMode {
20703 ADDR_SURF_DISPLAY_MICRO_TILING           = 0x00000000,
20704 ADDR_SURF_THIN_MICRO_TILING              = 0x00000001,
20705 ADDR_SURF_DEPTH_MICRO_TILING             = 0x00000002,
20706 ADDR_SURF_ROTATED_MICRO_TILING           = 0x00000003,
20707 ADDR_SURF_THICK_MICRO_TILING             = 0x00000004,
20708 } MicroTileMode;
20709 
20710 /*
20711  * TileSplit enum
20712  */
20713 
20714 typedef enum TileSplit {
20715 ADDR_SURF_TILE_SPLIT_64B                 = 0x00000000,
20716 ADDR_SURF_TILE_SPLIT_128B                = 0x00000001,
20717 ADDR_SURF_TILE_SPLIT_256B                = 0x00000002,
20718 ADDR_SURF_TILE_SPLIT_512B                = 0x00000003,
20719 ADDR_SURF_TILE_SPLIT_1KB                 = 0x00000004,
20720 ADDR_SURF_TILE_SPLIT_2KB                 = 0x00000005,
20721 ADDR_SURF_TILE_SPLIT_4KB                 = 0x00000006,
20722 } TileSplit;
20723 
20724 /*
20725  * SampleSplit enum
20726  */
20727 
20728 typedef enum SampleSplit {
20729 ADDR_SURF_SAMPLE_SPLIT_1                 = 0x00000000,
20730 ADDR_SURF_SAMPLE_SPLIT_2                 = 0x00000001,
20731 ADDR_SURF_SAMPLE_SPLIT_4                 = 0x00000002,
20732 ADDR_SURF_SAMPLE_SPLIT_8                 = 0x00000003,
20733 } SampleSplit;
20734 
20735 /*
20736  * PipeConfig enum
20737  */
20738 
20739 typedef enum PipeConfig {
20740 ADDR_SURF_P2                             = 0x00000000,
20741 ADDR_SURF_P2_RESERVED0                   = 0x00000001,
20742 ADDR_SURF_P2_RESERVED1                   = 0x00000002,
20743 ADDR_SURF_P2_RESERVED2                   = 0x00000003,
20744 ADDR_SURF_P4_8x16                        = 0x00000004,
20745 ADDR_SURF_P4_16x16                       = 0x00000005,
20746 ADDR_SURF_P4_16x32                       = 0x00000006,
20747 ADDR_SURF_P4_32x32                       = 0x00000007,
20748 ADDR_SURF_P8_16x16_8x16                  = 0x00000008,
20749 ADDR_SURF_P8_16x32_8x16                  = 0x00000009,
20750 ADDR_SURF_P8_32x32_8x16                  = 0x0000000a,
20751 ADDR_SURF_P8_16x32_16x16                 = 0x0000000b,
20752 ADDR_SURF_P8_32x32_16x16                 = 0x0000000c,
20753 ADDR_SURF_P8_32x32_16x32                 = 0x0000000d,
20754 ADDR_SURF_P8_32x64_32x32                 = 0x0000000e,
20755 ADDR_SURF_P8_RESERVED0                   = 0x0000000f,
20756 ADDR_SURF_P16_32x32_8x16                 = 0x00000010,
20757 ADDR_SURF_P16_32x32_16x16                = 0x00000011,
20758 ADDR_SURF_P16                            = 0x00000012,
20759 } PipeConfig;
20760 
20761 /*
20762  * SeEnable enum
20763  */
20764 
20765 typedef enum SeEnable {
20766 ADDR_CONFIG_DISABLE_SE                   = 0x00000000,
20767 ADDR_CONFIG_ENABLE_SE                    = 0x00000001,
20768 } SeEnable;
20769 
20770 /*
20771  * NumBanks enum
20772  */
20773 
20774 typedef enum NumBanks {
20775 ADDR_SURF_2_BANK                         = 0x00000000,
20776 ADDR_SURF_4_BANK                         = 0x00000001,
20777 ADDR_SURF_8_BANK                         = 0x00000002,
20778 ADDR_SURF_16_BANK                        = 0x00000003,
20779 } NumBanks;
20780 
20781 /*
20782  * BankWidth enum
20783  */
20784 
20785 typedef enum BankWidth {
20786 ADDR_SURF_BANK_WIDTH_1                   = 0x00000000,
20787 ADDR_SURF_BANK_WIDTH_2                   = 0x00000001,
20788 ADDR_SURF_BANK_WIDTH_4                   = 0x00000002,
20789 ADDR_SURF_BANK_WIDTH_8                   = 0x00000003,
20790 } BankWidth;
20791 
20792 /*
20793  * BankHeight enum
20794  */
20795 
20796 typedef enum BankHeight {
20797 ADDR_SURF_BANK_HEIGHT_1                  = 0x00000000,
20798 ADDR_SURF_BANK_HEIGHT_2                  = 0x00000001,
20799 ADDR_SURF_BANK_HEIGHT_4                  = 0x00000002,
20800 ADDR_SURF_BANK_HEIGHT_8                  = 0x00000003,
20801 } BankHeight;
20802 
20803 /*
20804  * BankWidthHeight enum
20805  */
20806 
20807 typedef enum BankWidthHeight {
20808 ADDR_SURF_BANK_WH_1                      = 0x00000000,
20809 ADDR_SURF_BANK_WH_2                      = 0x00000001,
20810 ADDR_SURF_BANK_WH_4                      = 0x00000002,
20811 ADDR_SURF_BANK_WH_8                      = 0x00000003,
20812 } BankWidthHeight;
20813 
20814 /*
20815  * MacroTileAspect enum
20816  */
20817 
20818 typedef enum MacroTileAspect {
20819 ADDR_SURF_MACRO_ASPECT_1                 = 0x00000000,
20820 ADDR_SURF_MACRO_ASPECT_2                 = 0x00000001,
20821 ADDR_SURF_MACRO_ASPECT_4                 = 0x00000002,
20822 ADDR_SURF_MACRO_ASPECT_8                 = 0x00000003,
20823 } MacroTileAspect;
20824 
20825 /*
20826  * PipeTiling enum
20827  */
20828 
20829 typedef enum PipeTiling {
20830 CONFIG_1_PIPE                            = 0x00000000,
20831 CONFIG_2_PIPE                            = 0x00000001,
20832 CONFIG_4_PIPE                            = 0x00000002,
20833 CONFIG_8_PIPE                            = 0x00000003,
20834 } PipeTiling;
20835 
20836 /*
20837  * BankTiling enum
20838  */
20839 
20840 typedef enum BankTiling {
20841 CONFIG_4_BANK                            = 0x00000000,
20842 CONFIG_8_BANK                            = 0x00000001,
20843 } BankTiling;
20844 
20845 /*
20846  * GroupInterleave enum
20847  */
20848 
20849 typedef enum GroupInterleave {
20850 CONFIG_256B_GROUP                        = 0x00000000,
20851 CONFIG_512B_GROUP                        = 0x00000001,
20852 } GroupInterleave;
20853 
20854 /*
20855  * RowTiling enum
20856  */
20857 
20858 typedef enum RowTiling {
20859 CONFIG_1KB_ROW                           = 0x00000000,
20860 CONFIG_2KB_ROW                           = 0x00000001,
20861 CONFIG_4KB_ROW                           = 0x00000002,
20862 CONFIG_8KB_ROW                           = 0x00000003,
20863 CONFIG_1KB_ROW_OPT                       = 0x00000004,
20864 CONFIG_2KB_ROW_OPT                       = 0x00000005,
20865 CONFIG_4KB_ROW_OPT                       = 0x00000006,
20866 CONFIG_8KB_ROW_OPT                       = 0x00000007,
20867 } RowTiling;
20868 
20869 /*
20870  * BankSwapBytes enum
20871  */
20872 
20873 typedef enum BankSwapBytes {
20874 CONFIG_128B_SWAPS                        = 0x00000000,
20875 CONFIG_256B_SWAPS                        = 0x00000001,
20876 CONFIG_512B_SWAPS                        = 0x00000002,
20877 CONFIG_1KB_SWAPS                         = 0x00000003,
20878 } BankSwapBytes;
20879 
20880 /*
20881  * SampleSplitBytes enum
20882  */
20883 
20884 typedef enum SampleSplitBytes {
20885 CONFIG_1KB_SPLIT                         = 0x00000000,
20886 CONFIG_2KB_SPLIT                         = 0x00000001,
20887 CONFIG_4KB_SPLIT                         = 0x00000002,
20888 CONFIG_8KB_SPLIT                         = 0x00000003,
20889 } SampleSplitBytes;
20890 
20891 /*
20892  * SurfaceNumber enum
20893  */
20894 
20895 typedef enum SurfaceNumber {
20896 NUMBER_UNORM                             = 0x00000000,
20897 NUMBER_SNORM                             = 0x00000001,
20898 NUMBER_USCALED                           = 0x00000002,
20899 NUMBER_SSCALED                           = 0x00000003,
20900 NUMBER_UINT                              = 0x00000004,
20901 NUMBER_SINT                              = 0x00000005,
20902 NUMBER_SRGB                              = 0x00000006,
20903 NUMBER_FLOAT                             = 0x00000007,
20904 } SurfaceNumber;
20905 
20906 /*
20907  * SurfaceSwap enum
20908  */
20909 
20910 typedef enum SurfaceSwap {
20911 SWAP_STD                                 = 0x00000000,
20912 SWAP_ALT                                 = 0x00000001,
20913 SWAP_STD_REV                             = 0x00000002,
20914 SWAP_ALT_REV                             = 0x00000003,
20915 } SurfaceSwap;
20916 
20917 /*
20918  * RoundMode enum
20919  */
20920 
20921 typedef enum RoundMode {
20922 ROUND_BY_HALF                            = 0x00000000,
20923 ROUND_TRUNCATE                           = 0x00000001,
20924 } RoundMode;
20925 
20926 /*
20927  * BUF_FMT enum
20928  */
20929 
20930 typedef enum BUF_FMT {
20931 BUF_FMT_INVALID                          = 0x00000000,
20932 BUF_FMT_8_UNORM                          = 0x00000001,
20933 BUF_FMT_8_SNORM                          = 0x00000002,
20934 BUF_FMT_8_USCALED                        = 0x00000003,
20935 BUF_FMT_8_SSCALED                        = 0x00000004,
20936 BUF_FMT_8_UINT                           = 0x00000005,
20937 BUF_FMT_8_SINT                           = 0x00000006,
20938 BUF_FMT_16_UNORM                         = 0x00000007,
20939 BUF_FMT_16_SNORM                         = 0x00000008,
20940 BUF_FMT_16_USCALED                       = 0x00000009,
20941 BUF_FMT_16_SSCALED                       = 0x0000000a,
20942 BUF_FMT_16_UINT                          = 0x0000000b,
20943 BUF_FMT_16_SINT                          = 0x0000000c,
20944 BUF_FMT_16_FLOAT                         = 0x0000000d,
20945 BUF_FMT_8_8_UNORM                        = 0x0000000e,
20946 BUF_FMT_8_8_SNORM                        = 0x0000000f,
20947 BUF_FMT_8_8_USCALED                      = 0x00000010,
20948 BUF_FMT_8_8_SSCALED                      = 0x00000011,
20949 BUF_FMT_8_8_UINT                         = 0x00000012,
20950 BUF_FMT_8_8_SINT                         = 0x00000013,
20951 BUF_FMT_32_UINT                          = 0x00000014,
20952 BUF_FMT_32_SINT                          = 0x00000015,
20953 BUF_FMT_32_FLOAT                         = 0x00000016,
20954 BUF_FMT_16_16_UNORM                      = 0x00000017,
20955 BUF_FMT_16_16_SNORM                      = 0x00000018,
20956 BUF_FMT_16_16_USCALED                    = 0x00000019,
20957 BUF_FMT_16_16_SSCALED                    = 0x0000001a,
20958 BUF_FMT_16_16_UINT                       = 0x0000001b,
20959 BUF_FMT_16_16_SINT                       = 0x0000001c,
20960 BUF_FMT_16_16_FLOAT                      = 0x0000001d,
20961 BUF_FMT_10_11_11_UNORM                   = 0x0000001e,
20962 BUF_FMT_10_11_11_SNORM                   = 0x0000001f,
20963 BUF_FMT_10_11_11_USCALED                 = 0x00000020,
20964 BUF_FMT_10_11_11_SSCALED                 = 0x00000021,
20965 BUF_FMT_10_11_11_UINT                    = 0x00000022,
20966 BUF_FMT_10_11_11_SINT                    = 0x00000023,
20967 BUF_FMT_10_11_11_FLOAT                   = 0x00000024,
20968 BUF_FMT_11_11_10_UNORM                   = 0x00000025,
20969 BUF_FMT_11_11_10_SNORM                   = 0x00000026,
20970 BUF_FMT_11_11_10_USCALED                 = 0x00000027,
20971 BUF_FMT_11_11_10_SSCALED                 = 0x00000028,
20972 BUF_FMT_11_11_10_UINT                    = 0x00000029,
20973 BUF_FMT_11_11_10_SINT                    = 0x0000002a,
20974 BUF_FMT_11_11_10_FLOAT                   = 0x0000002b,
20975 BUF_FMT_10_10_10_2_UNORM                 = 0x0000002c,
20976 BUF_FMT_10_10_10_2_SNORM                 = 0x0000002d,
20977 BUF_FMT_10_10_10_2_USCALED               = 0x0000002e,
20978 BUF_FMT_10_10_10_2_SSCALED               = 0x0000002f,
20979 BUF_FMT_10_10_10_2_UINT                  = 0x00000030,
20980 BUF_FMT_10_10_10_2_SINT                  = 0x00000031,
20981 BUF_FMT_2_10_10_10_UNORM                 = 0x00000032,
20982 BUF_FMT_2_10_10_10_SNORM                 = 0x00000033,
20983 BUF_FMT_2_10_10_10_USCALED               = 0x00000034,
20984 BUF_FMT_2_10_10_10_SSCALED               = 0x00000035,
20985 BUF_FMT_2_10_10_10_UINT                  = 0x00000036,
20986 BUF_FMT_2_10_10_10_SINT                  = 0x00000037,
20987 BUF_FMT_8_8_8_8_UNORM                    = 0x00000038,
20988 BUF_FMT_8_8_8_8_SNORM                    = 0x00000039,
20989 BUF_FMT_8_8_8_8_USCALED                  = 0x0000003a,
20990 BUF_FMT_8_8_8_8_SSCALED                  = 0x0000003b,
20991 BUF_FMT_8_8_8_8_UINT                     = 0x0000003c,
20992 BUF_FMT_8_8_8_8_SINT                     = 0x0000003d,
20993 BUF_FMT_32_32_UINT                       = 0x0000003e,
20994 BUF_FMT_32_32_SINT                       = 0x0000003f,
20995 BUF_FMT_32_32_FLOAT                      = 0x00000040,
20996 BUF_FMT_16_16_16_16_UNORM                = 0x00000041,
20997 BUF_FMT_16_16_16_16_SNORM                = 0x00000042,
20998 BUF_FMT_16_16_16_16_USCALED              = 0x00000043,
20999 BUF_FMT_16_16_16_16_SSCALED              = 0x00000044,
21000 BUF_FMT_16_16_16_16_UINT                 = 0x00000045,
21001 BUF_FMT_16_16_16_16_SINT                 = 0x00000046,
21002 BUF_FMT_16_16_16_16_FLOAT                = 0x00000047,
21003 BUF_FMT_32_32_32_UINT                    = 0x00000048,
21004 BUF_FMT_32_32_32_SINT                    = 0x00000049,
21005 BUF_FMT_32_32_32_FLOAT                   = 0x0000004a,
21006 BUF_FMT_32_32_32_32_UINT                 = 0x0000004b,
21007 BUF_FMT_32_32_32_32_SINT                 = 0x0000004c,
21008 BUF_FMT_32_32_32_32_FLOAT                = 0x0000004d,
21009 BUF_FMT_RESERVED_78                      = 0x0000004e,
21010 BUF_FMT_RESERVED_79                      = 0x0000004f,
21011 BUF_FMT_RESERVED_80                      = 0x00000050,
21012 BUF_FMT_RESERVED_81                      = 0x00000051,
21013 BUF_FMT_RESERVED_82                      = 0x00000052,
21014 BUF_FMT_RESERVED_83                      = 0x00000053,
21015 BUF_FMT_RESERVED_84                      = 0x00000054,
21016 BUF_FMT_RESERVED_85                      = 0x00000055,
21017 BUF_FMT_RESERVED_86                      = 0x00000056,
21018 BUF_FMT_RESERVED_87                      = 0x00000057,
21019 BUF_FMT_RESERVED_88                      = 0x00000058,
21020 BUF_FMT_RESERVED_89                      = 0x00000059,
21021 BUF_FMT_RESERVED_90                      = 0x0000005a,
21022 BUF_FMT_RESERVED_91                      = 0x0000005b,
21023 BUF_FMT_RESERVED_92                      = 0x0000005c,
21024 BUF_FMT_RESERVED_93                      = 0x0000005d,
21025 BUF_FMT_RESERVED_94                      = 0x0000005e,
21026 BUF_FMT_RESERVED_95                      = 0x0000005f,
21027 BUF_FMT_RESERVED_96                      = 0x00000060,
21028 BUF_FMT_RESERVED_97                      = 0x00000061,
21029 BUF_FMT_RESERVED_98                      = 0x00000062,
21030 BUF_FMT_RESERVED_99                      = 0x00000063,
21031 BUF_FMT_RESERVED_100                     = 0x00000064,
21032 BUF_FMT_RESERVED_101                     = 0x00000065,
21033 BUF_FMT_RESERVED_102                     = 0x00000066,
21034 BUF_FMT_RESERVED_103                     = 0x00000067,
21035 BUF_FMT_RESERVED_104                     = 0x00000068,
21036 BUF_FMT_RESERVED_105                     = 0x00000069,
21037 BUF_FMT_RESERVED_106                     = 0x0000006a,
21038 BUF_FMT_RESERVED_107                     = 0x0000006b,
21039 BUF_FMT_RESERVED_108                     = 0x0000006c,
21040 BUF_FMT_RESERVED_109                     = 0x0000006d,
21041 BUF_FMT_RESERVED_110                     = 0x0000006e,
21042 BUF_FMT_RESERVED_111                     = 0x0000006f,
21043 BUF_FMT_RESERVED_112                     = 0x00000070,
21044 BUF_FMT_RESERVED_113                     = 0x00000071,
21045 BUF_FMT_RESERVED_114                     = 0x00000072,
21046 BUF_FMT_RESERVED_115                     = 0x00000073,
21047 BUF_FMT_RESERVED_116                     = 0x00000074,
21048 BUF_FMT_RESERVED_117                     = 0x00000075,
21049 BUF_FMT_RESERVED_118                     = 0x00000076,
21050 BUF_FMT_RESERVED_119                     = 0x00000077,
21051 BUF_FMT_RESERVED_120                     = 0x00000078,
21052 BUF_FMT_RESERVED_121                     = 0x00000079,
21053 BUF_FMT_RESERVED_122                     = 0x0000007a,
21054 BUF_FMT_RESERVED_123                     = 0x0000007b,
21055 BUF_FMT_RESERVED_124                     = 0x0000007c,
21056 BUF_FMT_RESERVED_125                     = 0x0000007d,
21057 BUF_FMT_RESERVED_126                     = 0x0000007e,
21058 BUF_FMT_RESERVED_127                     = 0x0000007f,
21059 } BUF_FMT;
21060 
21061 /*
21062  * IMG_FMT enum
21063  */
21064 
21065 typedef enum IMG_FMT {
21066 IMG_FMT_INVALID                          = 0x00000000,
21067 IMG_FMT_8_UNORM                          = 0x00000001,
21068 IMG_FMT_8_SNORM                          = 0x00000002,
21069 IMG_FMT_8_USCALED                        = 0x00000003,
21070 IMG_FMT_8_SSCALED                        = 0x00000004,
21071 IMG_FMT_8_UINT                           = 0x00000005,
21072 IMG_FMT_8_SINT                           = 0x00000006,
21073 IMG_FMT_16_UNORM                         = 0x00000007,
21074 IMG_FMT_16_SNORM                         = 0x00000008,
21075 IMG_FMT_16_USCALED                       = 0x00000009,
21076 IMG_FMT_16_SSCALED                       = 0x0000000a,
21077 IMG_FMT_16_UINT                          = 0x0000000b,
21078 IMG_FMT_16_SINT                          = 0x0000000c,
21079 IMG_FMT_16_FLOAT                         = 0x0000000d,
21080 IMG_FMT_8_8_UNORM                        = 0x0000000e,
21081 IMG_FMT_8_8_SNORM                        = 0x0000000f,
21082 IMG_FMT_8_8_USCALED                      = 0x00000010,
21083 IMG_FMT_8_8_SSCALED                      = 0x00000011,
21084 IMG_FMT_8_8_UINT                         = 0x00000012,
21085 IMG_FMT_8_8_SINT                         = 0x00000013,
21086 IMG_FMT_32_UINT                          = 0x00000014,
21087 IMG_FMT_32_SINT                          = 0x00000015,
21088 IMG_FMT_32_FLOAT                         = 0x00000016,
21089 IMG_FMT_16_16_UNORM                      = 0x00000017,
21090 IMG_FMT_16_16_SNORM                      = 0x00000018,
21091 IMG_FMT_16_16_USCALED                    = 0x00000019,
21092 IMG_FMT_16_16_SSCALED                    = 0x0000001a,
21093 IMG_FMT_16_16_UINT                       = 0x0000001b,
21094 IMG_FMT_16_16_SINT                       = 0x0000001c,
21095 IMG_FMT_16_16_FLOAT                      = 0x0000001d,
21096 IMG_FMT_10_11_11_UNORM                   = 0x0000001e,
21097 IMG_FMT_10_11_11_SNORM                   = 0x0000001f,
21098 IMG_FMT_10_11_11_USCALED                 = 0x00000020,
21099 IMG_FMT_10_11_11_SSCALED                 = 0x00000021,
21100 IMG_FMT_10_11_11_UINT                    = 0x00000022,
21101 IMG_FMT_10_11_11_SINT                    = 0x00000023,
21102 IMG_FMT_10_11_11_FLOAT                   = 0x00000024,
21103 IMG_FMT_11_11_10_UNORM                   = 0x00000025,
21104 IMG_FMT_11_11_10_SNORM                   = 0x00000026,
21105 IMG_FMT_11_11_10_USCALED                 = 0x00000027,
21106 IMG_FMT_11_11_10_SSCALED                 = 0x00000028,
21107 IMG_FMT_11_11_10_UINT                    = 0x00000029,
21108 IMG_FMT_11_11_10_SINT                    = 0x0000002a,
21109 IMG_FMT_11_11_10_FLOAT                   = 0x0000002b,
21110 IMG_FMT_10_10_10_2_UNORM                 = 0x0000002c,
21111 IMG_FMT_10_10_10_2_SNORM                 = 0x0000002d,
21112 IMG_FMT_10_10_10_2_USCALED               = 0x0000002e,
21113 IMG_FMT_10_10_10_2_SSCALED               = 0x0000002f,
21114 IMG_FMT_10_10_10_2_UINT                  = 0x00000030,
21115 IMG_FMT_10_10_10_2_SINT                  = 0x00000031,
21116 IMG_FMT_2_10_10_10_UNORM                 = 0x00000032,
21117 IMG_FMT_2_10_10_10_SNORM                 = 0x00000033,
21118 IMG_FMT_2_10_10_10_USCALED               = 0x00000034,
21119 IMG_FMT_2_10_10_10_SSCALED               = 0x00000035,
21120 IMG_FMT_2_10_10_10_UINT                  = 0x00000036,
21121 IMG_FMT_2_10_10_10_SINT                  = 0x00000037,
21122 IMG_FMT_8_8_8_8_UNORM                    = 0x00000038,
21123 IMG_FMT_8_8_8_8_SNORM                    = 0x00000039,
21124 IMG_FMT_8_8_8_8_USCALED                  = 0x0000003a,
21125 IMG_FMT_8_8_8_8_SSCALED                  = 0x0000003b,
21126 IMG_FMT_8_8_8_8_UINT                     = 0x0000003c,
21127 IMG_FMT_8_8_8_8_SINT                     = 0x0000003d,
21128 IMG_FMT_32_32_UINT                       = 0x0000003e,
21129 IMG_FMT_32_32_SINT                       = 0x0000003f,
21130 IMG_FMT_32_32_FLOAT                      = 0x00000040,
21131 IMG_FMT_16_16_16_16_UNORM                = 0x00000041,
21132 IMG_FMT_16_16_16_16_SNORM                = 0x00000042,
21133 IMG_FMT_16_16_16_16_USCALED              = 0x00000043,
21134 IMG_FMT_16_16_16_16_SSCALED              = 0x00000044,
21135 IMG_FMT_16_16_16_16_UINT                 = 0x00000045,
21136 IMG_FMT_16_16_16_16_SINT                 = 0x00000046,
21137 IMG_FMT_16_16_16_16_FLOAT                = 0x00000047,
21138 IMG_FMT_32_32_32_UINT                    = 0x00000048,
21139 IMG_FMT_32_32_32_SINT                    = 0x00000049,
21140 IMG_FMT_32_32_32_FLOAT                   = 0x0000004a,
21141 IMG_FMT_32_32_32_32_UINT                 = 0x0000004b,
21142 IMG_FMT_32_32_32_32_SINT                 = 0x0000004c,
21143 IMG_FMT_32_32_32_32_FLOAT                = 0x0000004d,
21144 IMG_FMT_RESERVED_78                      = 0x0000004e,
21145 IMG_FMT_RESERVED_79                      = 0x0000004f,
21146 IMG_FMT_RESERVED_80                      = 0x00000050,
21147 IMG_FMT_RESERVED_81                      = 0x00000051,
21148 IMG_FMT_RESERVED_82                      = 0x00000052,
21149 IMG_FMT_RESERVED_83                      = 0x00000053,
21150 IMG_FMT_RESERVED_84                      = 0x00000054,
21151 IMG_FMT_RESERVED_85                      = 0x00000055,
21152 IMG_FMT_RESERVED_86                      = 0x00000056,
21153 IMG_FMT_RESERVED_87                      = 0x00000057,
21154 IMG_FMT_RESERVED_88                      = 0x00000058,
21155 IMG_FMT_RESERVED_89                      = 0x00000059,
21156 IMG_FMT_RESERVED_90                      = 0x0000005a,
21157 IMG_FMT_RESERVED_91                      = 0x0000005b,
21158 IMG_FMT_RESERVED_92                      = 0x0000005c,
21159 IMG_FMT_RESERVED_93                      = 0x0000005d,
21160 IMG_FMT_RESERVED_94                      = 0x0000005e,
21161 IMG_FMT_RESERVED_95                      = 0x0000005f,
21162 IMG_FMT_RESERVED_96                      = 0x00000060,
21163 IMG_FMT_RESERVED_97                      = 0x00000061,
21164 IMG_FMT_RESERVED_98                      = 0x00000062,
21165 IMG_FMT_RESERVED_99                      = 0x00000063,
21166 IMG_FMT_RESERVED_100                     = 0x00000064,
21167 IMG_FMT_RESERVED_101                     = 0x00000065,
21168 IMG_FMT_RESERVED_102                     = 0x00000066,
21169 IMG_FMT_RESERVED_103                     = 0x00000067,
21170 IMG_FMT_RESERVED_104                     = 0x00000068,
21171 IMG_FMT_RESERVED_105                     = 0x00000069,
21172 IMG_FMT_RESERVED_106                     = 0x0000006a,
21173 IMG_FMT_RESERVED_107                     = 0x0000006b,
21174 IMG_FMT_RESERVED_108                     = 0x0000006c,
21175 IMG_FMT_RESERVED_109                     = 0x0000006d,
21176 IMG_FMT_RESERVED_110                     = 0x0000006e,
21177 IMG_FMT_RESERVED_111                     = 0x0000006f,
21178 IMG_FMT_RESERVED_112                     = 0x00000070,
21179 IMG_FMT_RESERVED_113                     = 0x00000071,
21180 IMG_FMT_RESERVED_114                     = 0x00000072,
21181 IMG_FMT_RESERVED_115                     = 0x00000073,
21182 IMG_FMT_RESERVED_116                     = 0x00000074,
21183 IMG_FMT_RESERVED_117                     = 0x00000075,
21184 IMG_FMT_RESERVED_118                     = 0x00000076,
21185 IMG_FMT_RESERVED_119                     = 0x00000077,
21186 IMG_FMT_RESERVED_120                     = 0x00000078,
21187 IMG_FMT_RESERVED_121                     = 0x00000079,
21188 IMG_FMT_RESERVED_122                     = 0x0000007a,
21189 IMG_FMT_RESERVED_123                     = 0x0000007b,
21190 IMG_FMT_RESERVED_124                     = 0x0000007c,
21191 IMG_FMT_RESERVED_125                     = 0x0000007d,
21192 IMG_FMT_RESERVED_126                     = 0x0000007e,
21193 IMG_FMT_RESERVED_127                     = 0x0000007f,
21194 IMG_FMT_8_SRGB                           = 0x00000080,
21195 IMG_FMT_8_8_SRGB                         = 0x00000081,
21196 IMG_FMT_8_8_8_8_SRGB                     = 0x00000082,
21197 IMG_FMT_6E4_FLOAT                        = 0x00000083,
21198 IMG_FMT_5_9_9_9_FLOAT                    = 0x00000084,
21199 IMG_FMT_5_6_5_UNORM                      = 0x00000085,
21200 IMG_FMT_1_5_5_5_UNORM                    = 0x00000086,
21201 IMG_FMT_5_5_5_1_UNORM                    = 0x00000087,
21202 IMG_FMT_4_4_4_4_UNORM                    = 0x00000088,
21203 IMG_FMT_4_4_UNORM                        = 0x00000089,
21204 IMG_FMT_1_UNORM                          = 0x0000008a,
21205 IMG_FMT_1_REVERSED_UNORM                 = 0x0000008b,
21206 IMG_FMT_32_FLOAT_CLAMP                   = 0x0000008c,
21207 IMG_FMT_8_24_UNORM                       = 0x0000008d,
21208 IMG_FMT_8_24_UINT                        = 0x0000008e,
21209 IMG_FMT_24_8_UNORM                       = 0x0000008f,
21210 IMG_FMT_24_8_UINT                        = 0x00000090,
21211 IMG_FMT_X24_8_32_UINT                    = 0x00000091,
21212 IMG_FMT_X24_8_32_FLOAT                   = 0x00000092,
21213 IMG_FMT_GB_GR_UNORM                      = 0x00000093,
21214 IMG_FMT_GB_GR_SNORM                      = 0x00000094,
21215 IMG_FMT_GB_GR_UINT                       = 0x00000095,
21216 IMG_FMT_GB_GR_SRGB                       = 0x00000096,
21217 IMG_FMT_BG_RG_UNORM                      = 0x00000097,
21218 IMG_FMT_BG_RG_SNORM                      = 0x00000098,
21219 IMG_FMT_BG_RG_UINT                       = 0x00000099,
21220 IMG_FMT_BG_RG_SRGB                       = 0x0000009a,
21221 IMG_FMT_RESERVED_155                     = 0x0000009b,
21222 IMG_FMT_FMASK8_S2_F1                     = 0x0000009c,
21223 IMG_FMT_FMASK8_S4_F1                     = 0x0000009d,
21224 IMG_FMT_FMASK8_S8_F1                     = 0x0000009e,
21225 IMG_FMT_FMASK8_S2_F2                     = 0x0000009f,
21226 IMG_FMT_FMASK8_S4_F2                     = 0x000000a0,
21227 IMG_FMT_FMASK8_S4_F4                     = 0x000000a1,
21228 IMG_FMT_FMASK16_S16_F1                   = 0x000000a2,
21229 IMG_FMT_FMASK16_S8_F2                    = 0x000000a3,
21230 IMG_FMT_FMASK32_S16_F2                   = 0x000000a4,
21231 IMG_FMT_FMASK32_S8_F4                    = 0x000000a5,
21232 IMG_FMT_FMASK32_S8_F8                    = 0x000000a6,
21233 IMG_FMT_FMASK64_S16_F4                   = 0x000000a7,
21234 IMG_FMT_FMASK64_S16_F8                   = 0x000000a8,
21235 IMG_FMT_BC1_UNORM                        = 0x000000a9,
21236 IMG_FMT_BC1_SRGB                         = 0x000000aa,
21237 IMG_FMT_BC2_UNORM                        = 0x000000ab,
21238 IMG_FMT_BC2_SRGB                         = 0x000000ac,
21239 IMG_FMT_BC3_UNORM                        = 0x000000ad,
21240 IMG_FMT_BC3_SRGB                         = 0x000000ae,
21241 IMG_FMT_BC4_UNORM                        = 0x000000af,
21242 IMG_FMT_BC4_SNORM                        = 0x000000b0,
21243 IMG_FMT_BC5_UNORM                        = 0x000000b1,
21244 IMG_FMT_BC5_SNORM                        = 0x000000b2,
21245 IMG_FMT_BC6_UFLOAT                       = 0x000000b3,
21246 IMG_FMT_BC6_SFLOAT                       = 0x000000b4,
21247 IMG_FMT_BC7_UNORM                        = 0x000000b5,
21248 IMG_FMT_BC7_SRGB                         = 0x000000b6,
21249 IMG_FMT_MM_8_UNORM                       = 0x00000109,
21250 IMG_FMT_MM_8_UINT                        = 0x0000010a,
21251 IMG_FMT_MM_8_8_UNORM                     = 0x0000010b,
21252 IMG_FMT_MM_8_8_UINT                      = 0x0000010c,
21253 IMG_FMT_MM_8_8_8_8_UNORM                 = 0x0000010d,
21254 IMG_FMT_MM_8_8_8_8_UINT                  = 0x0000010e,
21255 IMG_FMT_MM_VYUY8_UNORM                   = 0x0000010f,
21256 IMG_FMT_MM_VYUY8_UINT                    = 0x00000110,
21257 IMG_FMT_MM_10_11_11_UNORM                = 0x00000111,
21258 IMG_FMT_MM_10_11_11_UINT                 = 0x00000112,
21259 IMG_FMT_MM_2_10_10_10_UNORM              = 0x00000113,
21260 IMG_FMT_MM_2_10_10_10_UINT               = 0x00000114,
21261 IMG_FMT_MM_16_16_16_16_UNORM             = 0x00000115,
21262 IMG_FMT_MM_16_16_16_16_UINT              = 0x00000116,
21263 IMG_FMT_MM_10_IN_16_UNORM                = 0x00000117,
21264 IMG_FMT_MM_10_IN_16_UINT                 = 0x00000118,
21265 IMG_FMT_MM_10_IN_16_16_UNORM             = 0x00000119,
21266 IMG_FMT_MM_10_IN_16_16_UINT              = 0x0000011a,
21267 IMG_FMT_MM_10_IN_16_16_16_16_UNORM       = 0x0000011b,
21268 IMG_FMT_MM_10_IN_16_16_16_16_UINT        = 0x0000011c,
21269 IMG_FMT_RESERVED_285                     = 0x0000011d,
21270 IMG_FMT_RESERVED_286                     = 0x0000011e,
21271 IMG_FMT_RESERVED_287                     = 0x0000011f,
21272 IMG_FMT_RESERVED_288                     = 0x00000120,
21273 IMG_FMT_RESERVED_289                     = 0x00000121,
21274 IMG_FMT_RESERVED_290                     = 0x00000122,
21275 IMG_FMT_RESERVED_291                     = 0x00000123,
21276 IMG_FMT_RESERVED_292                     = 0x00000124,
21277 IMG_FMT_RESERVED_293                     = 0x00000125,
21278 IMG_FMT_RESERVED_294                     = 0x00000126,
21279 IMG_FMT_RESERVED_295                     = 0x00000127,
21280 IMG_FMT_RESERVED_296                     = 0x00000128,
21281 IMG_FMT_RESERVED_297                     = 0x00000129,
21282 IMG_FMT_RESERVED_298                     = 0x0000012a,
21283 IMG_FMT_RESERVED_299                     = 0x0000012b,
21284 IMG_FMT_RESERVED_300                     = 0x0000012c,
21285 IMG_FMT_RESERVED_301                     = 0x0000012d,
21286 IMG_FMT_RESERVED_302                     = 0x0000012e,
21287 IMG_FMT_RESERVED_303                     = 0x0000012f,
21288 IMG_FMT_RESERVED_304                     = 0x00000130,
21289 IMG_FMT_RESERVED_305                     = 0x00000131,
21290 IMG_FMT_RESERVED_306                     = 0x00000132,
21291 IMG_FMT_RESERVED_307                     = 0x00000133,
21292 IMG_FMT_RESERVED_308                     = 0x00000134,
21293 IMG_FMT_RESERVED_309                     = 0x00000135,
21294 IMG_FMT_RESERVED_310                     = 0x00000136,
21295 IMG_FMT_RESERVED_311                     = 0x00000137,
21296 IMG_FMT_RESERVED_312                     = 0x00000138,
21297 IMG_FMT_RESERVED_313                     = 0x00000139,
21298 IMG_FMT_RESERVED_314                     = 0x0000013a,
21299 IMG_FMT_RESERVED_315                     = 0x0000013b,
21300 IMG_FMT_RESERVED_316                     = 0x0000013c,
21301 IMG_FMT_RESERVED_317                     = 0x0000013d,
21302 IMG_FMT_RESERVED_318                     = 0x0000013e,
21303 IMG_FMT_RESERVED_319                     = 0x0000013f,
21304 IMG_FMT_RESERVED_320                     = 0x00000140,
21305 IMG_FMT_RESERVED_321                     = 0x00000141,
21306 IMG_FMT_RESERVED_322                     = 0x00000142,
21307 IMG_FMT_RESERVED_323                     = 0x00000143,
21308 IMG_FMT_RESERVED_324                     = 0x00000144,
21309 IMG_FMT_RESERVED_325                     = 0x00000145,
21310 IMG_FMT_RESERVED_326                     = 0x00000146,
21311 IMG_FMT_RESERVED_327                     = 0x00000147,
21312 IMG_FMT_RESERVED_328                     = 0x00000148,
21313 IMG_FMT_RESERVED_329                     = 0x00000149,
21314 IMG_FMT_RESERVED_330                     = 0x0000014a,
21315 IMG_FMT_RESERVED_331                     = 0x0000014b,
21316 IMG_FMT_RESERVED_332                     = 0x0000014c,
21317 IMG_FMT_RESERVED_333                     = 0x0000014d,
21318 IMG_FMT_RESERVED_334                     = 0x0000014e,
21319 IMG_FMT_RESERVED_335                     = 0x0000014f,
21320 IMG_FMT_RESERVED_336                     = 0x00000150,
21321 IMG_FMT_RESERVED_337                     = 0x00000151,
21322 IMG_FMT_RESERVED_338                     = 0x00000152,
21323 IMG_FMT_RESERVED_339                     = 0x00000153,
21324 IMG_FMT_RESERVED_340                     = 0x00000154,
21325 IMG_FMT_RESERVED_341                     = 0x00000155,
21326 IMG_FMT_RESERVED_342                     = 0x00000156,
21327 IMG_FMT_RESERVED_343                     = 0x00000157,
21328 IMG_FMT_RESERVED_344                     = 0x00000158,
21329 IMG_FMT_RESERVED_345                     = 0x00000159,
21330 IMG_FMT_RESERVED_346                     = 0x0000015a,
21331 IMG_FMT_RESERVED_347                     = 0x0000015b,
21332 IMG_FMT_RESERVED_348                     = 0x0000015c,
21333 IMG_FMT_RESERVED_349                     = 0x0000015d,
21334 IMG_FMT_RESERVED_350                     = 0x0000015e,
21335 IMG_FMT_RESERVED_351                     = 0x0000015f,
21336 IMG_FMT_RESERVED_352                     = 0x00000160,
21337 IMG_FMT_RESERVED_353                     = 0x00000161,
21338 IMG_FMT_RESERVED_354                     = 0x00000162,
21339 IMG_FMT_RESERVED_355                     = 0x00000163,
21340 IMG_FMT_RESERVED_356                     = 0x00000164,
21341 IMG_FMT_RESERVED_357                     = 0x00000165,
21342 IMG_FMT_RESERVED_358                     = 0x00000166,
21343 IMG_FMT_RESERVED_359                     = 0x00000167,
21344 IMG_FMT_RESERVED_360                     = 0x00000168,
21345 IMG_FMT_RESERVED_361                     = 0x00000169,
21346 IMG_FMT_RESERVED_362                     = 0x0000016a,
21347 IMG_FMT_RESERVED_363                     = 0x0000016b,
21348 IMG_FMT_RESERVED_364                     = 0x0000016c,
21349 IMG_FMT_RESERVED_365                     = 0x0000016d,
21350 IMG_FMT_RESERVED_366                     = 0x0000016e,
21351 IMG_FMT_RESERVED_367                     = 0x0000016f,
21352 IMG_FMT_RESERVED_368                     = 0x00000170,
21353 IMG_FMT_RESERVED_369                     = 0x00000171,
21354 IMG_FMT_RESERVED_370                     = 0x00000172,
21355 IMG_FMT_RESERVED_371                     = 0x00000173,
21356 IMG_FMT_RESERVED_372                     = 0x00000174,
21357 IMG_FMT_RESERVED_373                     = 0x00000175,
21358 IMG_FMT_RESERVED_374                     = 0x00000176,
21359 IMG_FMT_RESERVED_375                     = 0x00000177,
21360 IMG_FMT_RESERVED_376                     = 0x00000178,
21361 IMG_FMT_RESERVED_377                     = 0x00000179,
21362 IMG_FMT_RESERVED_378                     = 0x0000017a,
21363 IMG_FMT_RESERVED_379                     = 0x0000017b,
21364 IMG_FMT_RESERVED_380                     = 0x0000017c,
21365 IMG_FMT_RESERVED_381                     = 0x0000017d,
21366 IMG_FMT_RESERVED_382                     = 0x0000017e,
21367 IMG_FMT_RESERVED_383                     = 0x0000017f,
21368 IMG_FMT_RESERVED_384                     = 0x00000180,
21369 IMG_FMT_RESERVED_385                     = 0x00000181,
21370 IMG_FMT_RESERVED_386                     = 0x00000182,
21371 IMG_FMT_RESERVED_387                     = 0x00000183,
21372 IMG_FMT_RESERVED_388                     = 0x00000184,
21373 IMG_FMT_RESERVED_389                     = 0x00000185,
21374 IMG_FMT_RESERVED_390                     = 0x00000186,
21375 IMG_FMT_RESERVED_391                     = 0x00000187,
21376 IMG_FMT_RESERVED_392                     = 0x00000188,
21377 IMG_FMT_RESERVED_393                     = 0x00000189,
21378 IMG_FMT_RESERVED_394                     = 0x0000018a,
21379 IMG_FMT_RESERVED_395                     = 0x0000018b,
21380 IMG_FMT_RESERVED_396                     = 0x0000018c,
21381 IMG_FMT_RESERVED_397                     = 0x0000018d,
21382 IMG_FMT_RESERVED_398                     = 0x0000018e,
21383 IMG_FMT_RESERVED_399                     = 0x0000018f,
21384 IMG_FMT_RESERVED_400                     = 0x00000190,
21385 IMG_FMT_RESERVED_401                     = 0x00000191,
21386 IMG_FMT_RESERVED_402                     = 0x00000192,
21387 IMG_FMT_RESERVED_403                     = 0x00000193,
21388 IMG_FMT_RESERVED_404                     = 0x00000194,
21389 IMG_FMT_RESERVED_405                     = 0x00000195,
21390 IMG_FMT_RESERVED_406                     = 0x00000196,
21391 IMG_FMT_RESERVED_407                     = 0x00000197,
21392 IMG_FMT_RESERVED_408                     = 0x00000198,
21393 IMG_FMT_RESERVED_409                     = 0x00000199,
21394 IMG_FMT_RESERVED_410                     = 0x0000019a,
21395 IMG_FMT_RESERVED_411                     = 0x0000019b,
21396 IMG_FMT_RESERVED_412                     = 0x0000019c,
21397 IMG_FMT_RESERVED_413                     = 0x0000019d,
21398 IMG_FMT_RESERVED_414                     = 0x0000019e,
21399 IMG_FMT_RESERVED_415                     = 0x0000019f,
21400 IMG_FMT_RESERVED_416                     = 0x000001a0,
21401 IMG_FMT_RESERVED_417                     = 0x000001a1,
21402 IMG_FMT_RESERVED_418                     = 0x000001a2,
21403 IMG_FMT_RESERVED_419                     = 0x000001a3,
21404 IMG_FMT_RESERVED_420                     = 0x000001a4,
21405 IMG_FMT_RESERVED_421                     = 0x000001a5,
21406 IMG_FMT_RESERVED_422                     = 0x000001a6,
21407 IMG_FMT_RESERVED_423                     = 0x000001a7,
21408 IMG_FMT_RESERVED_424                     = 0x000001a8,
21409 IMG_FMT_RESERVED_425                     = 0x000001a9,
21410 IMG_FMT_RESERVED_426                     = 0x000001aa,
21411 IMG_FMT_RESERVED_427                     = 0x000001ab,
21412 IMG_FMT_RESERVED_428                     = 0x000001ac,
21413 IMG_FMT_RESERVED_429                     = 0x000001ad,
21414 IMG_FMT_RESERVED_430                     = 0x000001ae,
21415 IMG_FMT_RESERVED_431                     = 0x000001af,
21416 IMG_FMT_RESERVED_432                     = 0x000001b0,
21417 IMG_FMT_RESERVED_433                     = 0x000001b1,
21418 IMG_FMT_RESERVED_434                     = 0x000001b2,
21419 IMG_FMT_RESERVED_435                     = 0x000001b3,
21420 IMG_FMT_RESERVED_436                     = 0x000001b4,
21421 IMG_FMT_RESERVED_437                     = 0x000001b5,
21422 IMG_FMT_RESERVED_438                     = 0x000001b6,
21423 IMG_FMT_RESERVED_439                     = 0x000001b7,
21424 IMG_FMT_RESERVED_440                     = 0x000001b8,
21425 IMG_FMT_RESERVED_441                     = 0x000001b9,
21426 IMG_FMT_RESERVED_442                     = 0x000001ba,
21427 IMG_FMT_RESERVED_443                     = 0x000001bb,
21428 IMG_FMT_RESERVED_444                     = 0x000001bc,
21429 IMG_FMT_RESERVED_445                     = 0x000001bd,
21430 IMG_FMT_RESERVED_446                     = 0x000001be,
21431 IMG_FMT_RESERVED_447                     = 0x000001bf,
21432 IMG_FMT_RESERVED_448                     = 0x000001c0,
21433 IMG_FMT_RESERVED_449                     = 0x000001c1,
21434 IMG_FMT_RESERVED_450                     = 0x000001c2,
21435 IMG_FMT_RESERVED_451                     = 0x000001c3,
21436 IMG_FMT_RESERVED_452                     = 0x000001c4,
21437 IMG_FMT_RESERVED_453                     = 0x000001c5,
21438 IMG_FMT_RESERVED_454                     = 0x000001c6,
21439 IMG_FMT_RESERVED_455                     = 0x000001c7,
21440 IMG_FMT_RESERVED_456                     = 0x000001c8,
21441 IMG_FMT_RESERVED_457                     = 0x000001c9,
21442 IMG_FMT_RESERVED_458                     = 0x000001ca,
21443 IMG_FMT_RESERVED_459                     = 0x000001cb,
21444 IMG_FMT_RESERVED_460                     = 0x000001cc,
21445 IMG_FMT_RESERVED_461                     = 0x000001cd,
21446 IMG_FMT_RESERVED_462                     = 0x000001ce,
21447 IMG_FMT_RESERVED_463                     = 0x000001cf,
21448 IMG_FMT_RESERVED_464                     = 0x000001d0,
21449 IMG_FMT_RESERVED_465                     = 0x000001d1,
21450 IMG_FMT_RESERVED_466                     = 0x000001d2,
21451 IMG_FMT_RESERVED_467                     = 0x000001d3,
21452 IMG_FMT_RESERVED_468                     = 0x000001d4,
21453 IMG_FMT_RESERVED_469                     = 0x000001d5,
21454 IMG_FMT_RESERVED_470                     = 0x000001d6,
21455 IMG_FMT_RESERVED_471                     = 0x000001d7,
21456 IMG_FMT_RESERVED_472                     = 0x000001d8,
21457 IMG_FMT_RESERVED_473                     = 0x000001d9,
21458 IMG_FMT_RESERVED_474                     = 0x000001da,
21459 IMG_FMT_RESERVED_475                     = 0x000001db,
21460 IMG_FMT_RESERVED_476                     = 0x000001dc,
21461 IMG_FMT_RESERVED_477                     = 0x000001dd,
21462 IMG_FMT_RESERVED_478                     = 0x000001de,
21463 IMG_FMT_RESERVED_479                     = 0x000001df,
21464 IMG_FMT_RESERVED_480                     = 0x000001e0,
21465 IMG_FMT_RESERVED_481                     = 0x000001e1,
21466 IMG_FMT_RESERVED_482                     = 0x000001e2,
21467 IMG_FMT_RESERVED_483                     = 0x000001e3,
21468 IMG_FMT_RESERVED_484                     = 0x000001e4,
21469 IMG_FMT_RESERVED_485                     = 0x000001e5,
21470 IMG_FMT_RESERVED_486                     = 0x000001e6,
21471 IMG_FMT_RESERVED_487                     = 0x000001e7,
21472 IMG_FMT_RESERVED_488                     = 0x000001e8,
21473 IMG_FMT_RESERVED_489                     = 0x000001e9,
21474 IMG_FMT_RESERVED_490                     = 0x000001ea,
21475 IMG_FMT_RESERVED_491                     = 0x000001eb,
21476 IMG_FMT_RESERVED_492                     = 0x000001ec,
21477 IMG_FMT_RESERVED_493                     = 0x000001ed,
21478 IMG_FMT_RESERVED_494                     = 0x000001ee,
21479 IMG_FMT_RESERVED_495                     = 0x000001ef,
21480 IMG_FMT_RESERVED_496                     = 0x000001f0,
21481 IMG_FMT_RESERVED_497                     = 0x000001f1,
21482 IMG_FMT_RESERVED_498                     = 0x000001f2,
21483 IMG_FMT_RESERVED_499                     = 0x000001f3,
21484 IMG_FMT_RESERVED_500                     = 0x000001f4,
21485 IMG_FMT_RESERVED_501                     = 0x000001f5,
21486 IMG_FMT_RESERVED_502                     = 0x000001f6,
21487 IMG_FMT_RESERVED_503                     = 0x000001f7,
21488 IMG_FMT_RESERVED_504                     = 0x000001f8,
21489 IMG_FMT_RESERVED_505                     = 0x000001f9,
21490 IMG_FMT_RESERVED_506                     = 0x000001fa,
21491 IMG_FMT_RESERVED_507                     = 0x000001fb,
21492 IMG_FMT_RESERVED_508                     = 0x000001fc,
21493 IMG_FMT_RESERVED_509                     = 0x000001fd,
21494 IMG_FMT_RESERVED_510                     = 0x000001fe,
21495 IMG_FMT_RESERVED_511                     = 0x000001ff,
21496 } IMG_FMT;
21497 
21498 /*
21499  * BUF_DATA_FORMAT enum
21500  */
21501 
21502 typedef enum BUF_DATA_FORMAT {
21503 BUF_DATA_FORMAT_INVALID                  = 0x00000000,
21504 BUF_DATA_FORMAT_8                        = 0x00000001,
21505 BUF_DATA_FORMAT_16                       = 0x00000002,
21506 BUF_DATA_FORMAT_8_8                      = 0x00000003,
21507 BUF_DATA_FORMAT_32                       = 0x00000004,
21508 BUF_DATA_FORMAT_16_16                    = 0x00000005,
21509 BUF_DATA_FORMAT_10_11_11                 = 0x00000006,
21510 BUF_DATA_FORMAT_11_11_10                 = 0x00000007,
21511 BUF_DATA_FORMAT_10_10_10_2               = 0x00000008,
21512 BUF_DATA_FORMAT_2_10_10_10               = 0x00000009,
21513 BUF_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
21514 BUF_DATA_FORMAT_32_32                    = 0x0000000b,
21515 BUF_DATA_FORMAT_16_16_16_16              = 0x0000000c,
21516 BUF_DATA_FORMAT_32_32_32                 = 0x0000000d,
21517 BUF_DATA_FORMAT_32_32_32_32              = 0x0000000e,
21518 BUF_DATA_FORMAT_RESERVED_15              = 0x0000000f,
21519 } BUF_DATA_FORMAT;
21520 
21521 /*
21522  * IMG_DATA_FORMAT enum
21523  */
21524 
21525 typedef enum IMG_DATA_FORMAT {
21526 IMG_DATA_FORMAT_INVALID                  = 0x00000000,
21527 IMG_DATA_FORMAT_8                        = 0x00000001,
21528 IMG_DATA_FORMAT_16                       = 0x00000002,
21529 IMG_DATA_FORMAT_8_8                      = 0x00000003,
21530 IMG_DATA_FORMAT_32                       = 0x00000004,
21531 IMG_DATA_FORMAT_16_16                    = 0x00000005,
21532 IMG_DATA_FORMAT_10_11_11                 = 0x00000006,
21533 IMG_DATA_FORMAT_11_11_10                 = 0x00000007,
21534 IMG_DATA_FORMAT_10_10_10_2               = 0x00000008,
21535 IMG_DATA_FORMAT_2_10_10_10               = 0x00000009,
21536 IMG_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
21537 IMG_DATA_FORMAT_32_32                    = 0x0000000b,
21538 IMG_DATA_FORMAT_16_16_16_16              = 0x0000000c,
21539 IMG_DATA_FORMAT_32_32_32                 = 0x0000000d,
21540 IMG_DATA_FORMAT_32_32_32_32              = 0x0000000e,
21541 IMG_DATA_FORMAT_RESERVED_15              = 0x0000000f,
21542 IMG_DATA_FORMAT_5_6_5                    = 0x00000010,
21543 IMG_DATA_FORMAT_1_5_5_5                  = 0x00000011,
21544 IMG_DATA_FORMAT_5_5_5_1                  = 0x00000012,
21545 IMG_DATA_FORMAT_4_4_4_4                  = 0x00000013,
21546 IMG_DATA_FORMAT_8_24                     = 0x00000014,
21547 IMG_DATA_FORMAT_24_8                     = 0x00000015,
21548 IMG_DATA_FORMAT_X24_8_32                 = 0x00000016,
21549 IMG_DATA_FORMAT_RESERVED_23              = 0x00000017,
21550 IMG_DATA_FORMAT_RESERVED_24              = 0x00000018,
21551 IMG_DATA_FORMAT_RESERVED_25              = 0x00000019,
21552 IMG_DATA_FORMAT_RESERVED_26              = 0x0000001a,
21553 IMG_DATA_FORMAT_RESERVED_27              = 0x0000001b,
21554 IMG_DATA_FORMAT_RESERVED_28              = 0x0000001c,
21555 IMG_DATA_FORMAT_RESERVED_29              = 0x0000001d,
21556 IMG_DATA_FORMAT_RESERVED_30              = 0x0000001e,
21557 IMG_DATA_FORMAT_6E4                      = 0x0000001f,
21558 IMG_DATA_FORMAT_GB_GR                    = 0x00000020,
21559 IMG_DATA_FORMAT_BG_RG                    = 0x00000021,
21560 IMG_DATA_FORMAT_5_9_9_9                  = 0x00000022,
21561 IMG_DATA_FORMAT_BC1                      = 0x00000023,
21562 IMG_DATA_FORMAT_BC2                      = 0x00000024,
21563 IMG_DATA_FORMAT_BC3                      = 0x00000025,
21564 IMG_DATA_FORMAT_BC4                      = 0x00000026,
21565 IMG_DATA_FORMAT_BC5                      = 0x00000027,
21566 IMG_DATA_FORMAT_BC6                      = 0x00000028,
21567 IMG_DATA_FORMAT_BC7                      = 0x00000029,
21568 IMG_DATA_FORMAT_RESERVED_42              = 0x0000002a,
21569 IMG_DATA_FORMAT_RESERVED_43              = 0x0000002b,
21570 IMG_DATA_FORMAT_FMASK8_S2_F1             = 0x0000002c,
21571 IMG_DATA_FORMAT_FMASK8_S4_F1             = 0x0000002d,
21572 IMG_DATA_FORMAT_FMASK8_S8_F1             = 0x0000002e,
21573 IMG_DATA_FORMAT_FMASK8_S2_F2             = 0x0000002f,
21574 IMG_DATA_FORMAT_FMASK8_S4_F2             = 0x00000030,
21575 IMG_DATA_FORMAT_FMASK8_S4_F4             = 0x00000031,
21576 IMG_DATA_FORMAT_FMASK16_S16_F1           = 0x00000032,
21577 IMG_DATA_FORMAT_FMASK16_S8_F2            = 0x00000033,
21578 IMG_DATA_FORMAT_FMASK32_S16_F2           = 0x00000034,
21579 IMG_DATA_FORMAT_FMASK32_S8_F4            = 0x00000035,
21580 IMG_DATA_FORMAT_FMASK32_S8_F8            = 0x00000036,
21581 IMG_DATA_FORMAT_FMASK64_S16_F4           = 0x00000037,
21582 IMG_DATA_FORMAT_FMASK64_S16_F8           = 0x00000038,
21583 IMG_DATA_FORMAT_4_4                      = 0x00000039,
21584 IMG_DATA_FORMAT_6_5_5                    = 0x0000003a,
21585 IMG_DATA_FORMAT_1                        = 0x0000003b,
21586 IMG_DATA_FORMAT_1_REVERSED               = 0x0000003c,
21587 IMG_DATA_FORMAT_RESERVED_61              = 0x0000003d,
21588 IMG_DATA_FORMAT_RESERVED_62              = 0x0000003e,
21589 IMG_DATA_FORMAT_32_AS_32_32_32_32        = 0x0000003f,
21590 IMG_DATA_FORMAT_RESERVED_75              = 0x0000004b,
21591 IMG_DATA_FORMAT_MM_8                     = 0x0000004c,
21592 IMG_DATA_FORMAT_MM_8_8                   = 0x0000004d,
21593 IMG_DATA_FORMAT_MM_8_8_8_8               = 0x0000004e,
21594 IMG_DATA_FORMAT_MM_VYUY8                 = 0x0000004f,
21595 IMG_DATA_FORMAT_MM_10_11_11              = 0x00000050,
21596 IMG_DATA_FORMAT_MM_2_10_10_10            = 0x00000051,
21597 IMG_DATA_FORMAT_MM_16_16_16_16           = 0x00000052,
21598 IMG_DATA_FORMAT_MM_10_IN_16              = 0x00000053,
21599 IMG_DATA_FORMAT_MM_10_IN_16_16           = 0x00000054,
21600 IMG_DATA_FORMAT_MM_10_IN_16_16_16_16     = 0x00000055,
21601 IMG_DATA_FORMAT_RESERVED_86              = 0x00000056,
21602 IMG_DATA_FORMAT_RESERVED_87              = 0x00000057,
21603 IMG_DATA_FORMAT_RESERVED_88              = 0x00000058,
21604 IMG_DATA_FORMAT_RESERVED_89              = 0x00000059,
21605 IMG_DATA_FORMAT_RESERVED_90              = 0x0000005a,
21606 IMG_DATA_FORMAT_RESERVED_91              = 0x0000005b,
21607 IMG_DATA_FORMAT_RESERVED_92              = 0x0000005c,
21608 IMG_DATA_FORMAT_RESERVED_93              = 0x0000005d,
21609 IMG_DATA_FORMAT_RESERVED_94              = 0x0000005e,
21610 IMG_DATA_FORMAT_RESERVED_95              = 0x0000005f,
21611 IMG_DATA_FORMAT_RESERVED_96              = 0x00000060,
21612 IMG_DATA_FORMAT_RESERVED_97              = 0x00000061,
21613 IMG_DATA_FORMAT_RESERVED_98              = 0x00000062,
21614 IMG_DATA_FORMAT_RESERVED_99              = 0x00000063,
21615 IMG_DATA_FORMAT_RESERVED_100             = 0x00000064,
21616 IMG_DATA_FORMAT_RESERVED_101             = 0x00000065,
21617 IMG_DATA_FORMAT_RESERVED_102             = 0x00000066,
21618 IMG_DATA_FORMAT_RESERVED_103             = 0x00000067,
21619 IMG_DATA_FORMAT_RESERVED_104             = 0x00000068,
21620 IMG_DATA_FORMAT_RESERVED_105             = 0x00000069,
21621 IMG_DATA_FORMAT_RESERVED_106             = 0x0000006a,
21622 IMG_DATA_FORMAT_RESERVED_107             = 0x0000006b,
21623 IMG_DATA_FORMAT_RESERVED_108             = 0x0000006c,
21624 IMG_DATA_FORMAT_RESERVED_109             = 0x0000006d,
21625 IMG_DATA_FORMAT_RESERVED_110             = 0x0000006e,
21626 IMG_DATA_FORMAT_RESERVED_111             = 0x0000006f,
21627 IMG_DATA_FORMAT_RESERVED_112             = 0x00000070,
21628 IMG_DATA_FORMAT_RESERVED_113             = 0x00000071,
21629 IMG_DATA_FORMAT_RESERVED_114             = 0x00000072,
21630 IMG_DATA_FORMAT_RESERVED_115             = 0x00000073,
21631 IMG_DATA_FORMAT_RESERVED_116             = 0x00000074,
21632 IMG_DATA_FORMAT_RESERVED_117             = 0x00000075,
21633 IMG_DATA_FORMAT_RESERVED_118             = 0x00000076,
21634 IMG_DATA_FORMAT_RESERVED_119             = 0x00000077,
21635 IMG_DATA_FORMAT_RESERVED_120             = 0x00000078,
21636 IMG_DATA_FORMAT_RESERVED_121             = 0x00000079,
21637 IMG_DATA_FORMAT_RESERVED_122             = 0x0000007a,
21638 IMG_DATA_FORMAT_RESERVED_123             = 0x0000007b,
21639 IMG_DATA_FORMAT_RESERVED_124             = 0x0000007c,
21640 IMG_DATA_FORMAT_RESERVED_125             = 0x0000007d,
21641 IMG_DATA_FORMAT_RESERVED_126             = 0x0000007e,
21642 IMG_DATA_FORMAT_RESERVED_127             = 0x0000007f,
21643 } IMG_DATA_FORMAT;
21644 
21645 /*
21646  * BUF_NUM_FORMAT enum
21647  */
21648 
21649 typedef enum BUF_NUM_FORMAT {
21650 BUF_NUM_FORMAT_UNORM                     = 0x00000000,
21651 BUF_NUM_FORMAT_SNORM                     = 0x00000001,
21652 BUF_NUM_FORMAT_USCALED                   = 0x00000002,
21653 BUF_NUM_FORMAT_SSCALED                   = 0x00000003,
21654 BUF_NUM_FORMAT_UINT                      = 0x00000004,
21655 BUF_NUM_FORMAT_SINT                      = 0x00000005,
21656 BUF_NUM_FORMAT_SNORM_NZ                  = 0x00000006,
21657 BUF_NUM_FORMAT_FLOAT                     = 0x00000007,
21658 } BUF_NUM_FORMAT;
21659 
21660 /*
21661  * IMG_NUM_FORMAT enum
21662  */
21663 
21664 typedef enum IMG_NUM_FORMAT {
21665 IMG_NUM_FORMAT_UNORM                     = 0x00000000,
21666 IMG_NUM_FORMAT_SNORM                     = 0x00000001,
21667 IMG_NUM_FORMAT_USCALED                   = 0x00000002,
21668 IMG_NUM_FORMAT_SSCALED                   = 0x00000003,
21669 IMG_NUM_FORMAT_UINT                      = 0x00000004,
21670 IMG_NUM_FORMAT_SINT                      = 0x00000005,
21671 IMG_NUM_FORMAT_SNORM_NZ                  = 0x00000006,
21672 IMG_NUM_FORMAT_FLOAT                     = 0x00000007,
21673 IMG_NUM_FORMAT_RESERVED_8                = 0x00000008,
21674 IMG_NUM_FORMAT_SRGB                      = 0x00000009,
21675 IMG_NUM_FORMAT_UBNORM                    = 0x0000000a,
21676 IMG_NUM_FORMAT_UBNORM_NZ                 = 0x0000000b,
21677 IMG_NUM_FORMAT_UBINT                     = 0x0000000c,
21678 IMG_NUM_FORMAT_UBSCALED                  = 0x0000000d,
21679 IMG_NUM_FORMAT_RESERVED_14               = 0x0000000e,
21680 IMG_NUM_FORMAT_RESERVED_15               = 0x0000000f,
21681 } IMG_NUM_FORMAT;
21682 
21683 /*******************************************************
21684  * IH Enums
21685  *******************************************************/
21686 
21687 /*
21688  * IH_PERF_SEL enum
21689  */
21690 
21691 typedef enum IH_PERF_SEL {
21692 IH_PERF_SEL_CYCLE                        = 0x00000000,
21693 IH_PERF_SEL_IDLE                         = 0x00000001,
21694 IH_PERF_SEL_INPUT_IDLE                   = 0x00000002,
21695 IH_PERF_SEL_BUFFER_IDLE                  = 0x00000003,
21696 IH_PERF_SEL_RB0_FULL                     = 0x00000004,
21697 IH_PERF_SEL_RB0_OVERFLOW                 = 0x00000005,
21698 IH_PERF_SEL_RB0_WPTR_WRITEBACK           = 0x00000006,
21699 IH_PERF_SEL_RB0_WPTR_WRAP                = 0x00000007,
21700 IH_PERF_SEL_RB0_RPTR_WRAP                = 0x00000008,
21701 IH_PERF_SEL_MC_WR_IDLE                   = 0x00000009,
21702 IH_PERF_SEL_MC_WR_COUNT                  = 0x0000000a,
21703 IH_PERF_SEL_MC_WR_STALL                  = 0x0000000b,
21704 IH_PERF_SEL_MC_WR_CLEAN_PENDING          = 0x0000000c,
21705 IH_PERF_SEL_MC_WR_CLEAN_STALL            = 0x0000000d,
21706 IH_PERF_SEL_BIF_LINE0_RISING             = 0x0000000e,
21707 IH_PERF_SEL_BIF_LINE0_FALLING            = 0x0000000f,
21708 IH_PERF_SEL_RB1_FULL                     = 0x00000010,
21709 IH_PERF_SEL_RB1_OVERFLOW                 = 0x00000011,
21710 IH_PERF_SEL_COOKIE_REC_ERROR             = 0x00000012,
21711 IH_PERF_SEL_RB1_WPTR_WRAP                = 0x00000013,
21712 IH_PERF_SEL_RB1_RPTR_WRAP                = 0x00000014,
21713 IH_PERF_SEL_RB2_FULL                     = 0x00000015,
21714 IH_PERF_SEL_RB2_OVERFLOW                 = 0x00000016,
21715 IH_PERF_SEL_CLIENT_CREDIT_ERROR          = 0x00000017,
21716 IH_PERF_SEL_RB2_WPTR_WRAP                = 0x00000018,
21717 IH_PERF_SEL_RB2_RPTR_WRAP                = 0x00000019,
21718 IH_PERF_SEL_STORM_CLIENT_INT_DROP        = 0x0000001a,
21719 IH_PERF_SEL_SELF_IV_VALID                = 0x0000001b,
21720 IH_PERF_SEL_BUFFER_FIFO_FULL             = 0x0000001c,
21721 IH_PERF_SEL_RB0_FULL_VF0                 = 0x0000001d,
21722 IH_PERF_SEL_RB0_FULL_VF1                 = 0x0000001e,
21723 IH_PERF_SEL_RB0_FULL_VF2                 = 0x0000001f,
21724 IH_PERF_SEL_RB0_FULL_VF3                 = 0x00000020,
21725 IH_PERF_SEL_RB0_FULL_VF4                 = 0x00000021,
21726 IH_PERF_SEL_RB0_FULL_VF5                 = 0x00000022,
21727 IH_PERF_SEL_RB0_FULL_VF6                 = 0x00000023,
21728 IH_PERF_SEL_RB0_FULL_VF7                 = 0x00000024,
21729 IH_PERF_SEL_RB0_FULL_VF8                 = 0x00000025,
21730 IH_PERF_SEL_RB0_FULL_VF9                 = 0x00000026,
21731 IH_PERF_SEL_RB0_FULL_VF10                = 0x00000027,
21732 IH_PERF_SEL_RB0_FULL_VF11                = 0x00000028,
21733 IH_PERF_SEL_RB0_FULL_VF12                = 0x00000029,
21734 IH_PERF_SEL_RB0_FULL_VF13                = 0x0000002a,
21735 IH_PERF_SEL_RB0_FULL_VF14                = 0x0000002b,
21736 IH_PERF_SEL_RB0_FULL_VF15                = 0x0000002c,
21737 IH_PERF_SEL_RB0_FULL_VF16                = 0x0000002d,
21738 IH_PERF_SEL_RB0_FULL_VF17                = 0x0000002e,
21739 IH_PERF_SEL_RB0_FULL_VF18                = 0x0000002f,
21740 IH_PERF_SEL_RB0_FULL_VF19                = 0x00000030,
21741 IH_PERF_SEL_RB0_FULL_VF20                = 0x00000031,
21742 IH_PERF_SEL_RB0_FULL_VF21                = 0x00000032,
21743 IH_PERF_SEL_RB0_FULL_VF22                = 0x00000033,
21744 IH_PERF_SEL_RB0_FULL_VF23                = 0x00000034,
21745 IH_PERF_SEL_RB0_FULL_VF24                = 0x00000035,
21746 IH_PERF_SEL_RB0_FULL_VF25                = 0x00000036,
21747 IH_PERF_SEL_RB0_FULL_VF26                = 0x00000037,
21748 IH_PERF_SEL_RB0_FULL_VF27                = 0x00000038,
21749 IH_PERF_SEL_RB0_FULL_VF28                = 0x00000039,
21750 IH_PERF_SEL_RB0_FULL_VF29                = 0x0000003a,
21751 IH_PERF_SEL_RB0_FULL_VF30                = 0x0000003b,
21752 IH_PERF_SEL_RB0_OVERFLOW_VF0             = 0x0000003c,
21753 IH_PERF_SEL_RB0_OVERFLOW_VF1             = 0x0000003d,
21754 IH_PERF_SEL_RB0_OVERFLOW_VF2             = 0x0000003e,
21755 IH_PERF_SEL_RB0_OVERFLOW_VF3             = 0x0000003f,
21756 IH_PERF_SEL_RB0_OVERFLOW_VF4             = 0x00000040,
21757 IH_PERF_SEL_RB0_OVERFLOW_VF5             = 0x00000041,
21758 IH_PERF_SEL_RB0_OVERFLOW_VF6             = 0x00000042,
21759 IH_PERF_SEL_RB0_OVERFLOW_VF7             = 0x00000043,
21760 IH_PERF_SEL_RB0_OVERFLOW_VF8             = 0x00000044,
21761 IH_PERF_SEL_RB0_OVERFLOW_VF9             = 0x00000045,
21762 IH_PERF_SEL_RB0_OVERFLOW_VF10            = 0x00000046,
21763 IH_PERF_SEL_RB0_OVERFLOW_VF11            = 0x00000047,
21764 IH_PERF_SEL_RB0_OVERFLOW_VF12            = 0x00000048,
21765 IH_PERF_SEL_RB0_OVERFLOW_VF13            = 0x00000049,
21766 IH_PERF_SEL_RB0_OVERFLOW_VF14            = 0x0000004a,
21767 IH_PERF_SEL_RB0_OVERFLOW_VF15            = 0x0000004b,
21768 IH_PERF_SEL_RB0_OVERFLOW_VF16            = 0x0000004c,
21769 IH_PERF_SEL_RB0_OVERFLOW_VF17            = 0x0000004d,
21770 IH_PERF_SEL_RB0_OVERFLOW_VF18            = 0x0000004e,
21771 IH_PERF_SEL_RB0_OVERFLOW_VF19            = 0x0000004f,
21772 IH_PERF_SEL_RB0_OVERFLOW_VF20            = 0x00000050,
21773 IH_PERF_SEL_RB0_OVERFLOW_VF21            = 0x00000051,
21774 IH_PERF_SEL_RB0_OVERFLOW_VF22            = 0x00000052,
21775 IH_PERF_SEL_RB0_OVERFLOW_VF23            = 0x00000053,
21776 IH_PERF_SEL_RB0_OVERFLOW_VF24            = 0x00000054,
21777 IH_PERF_SEL_RB0_OVERFLOW_VF25            = 0x00000055,
21778 IH_PERF_SEL_RB0_OVERFLOW_VF26            = 0x00000056,
21779 IH_PERF_SEL_RB0_OVERFLOW_VF27            = 0x00000057,
21780 IH_PERF_SEL_RB0_OVERFLOW_VF28            = 0x00000058,
21781 IH_PERF_SEL_RB0_OVERFLOW_VF29            = 0x00000059,
21782 IH_PERF_SEL_RB0_OVERFLOW_VF30            = 0x0000005a,
21783 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0       = 0x0000005b,
21784 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1       = 0x0000005c,
21785 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2       = 0x0000005d,
21786 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3       = 0x0000005e,
21787 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4       = 0x0000005f,
21788 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5       = 0x00000060,
21789 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6       = 0x00000061,
21790 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7       = 0x00000062,
21791 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8       = 0x00000063,
21792 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9       = 0x00000064,
21793 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10      = 0x00000065,
21794 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11      = 0x00000066,
21795 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12      = 0x00000067,
21796 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13      = 0x00000068,
21797 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14      = 0x00000069,
21798 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15      = 0x0000006a,
21799 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16      = 0x0000006b,
21800 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17      = 0x0000006c,
21801 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18      = 0x0000006d,
21802 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19      = 0x0000006e,
21803 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20      = 0x0000006f,
21804 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21      = 0x00000070,
21805 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22      = 0x00000071,
21806 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23      = 0x00000072,
21807 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24      = 0x00000073,
21808 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25      = 0x00000074,
21809 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26      = 0x00000075,
21810 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27      = 0x00000076,
21811 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28      = 0x00000077,
21812 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29      = 0x00000078,
21813 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30      = 0x00000079,
21814 IH_PERF_SEL_RB0_WPTR_WRAP_VF0            = 0x0000007a,
21815 IH_PERF_SEL_RB0_WPTR_WRAP_VF1            = 0x0000007b,
21816 IH_PERF_SEL_RB0_WPTR_WRAP_VF2            = 0x0000007c,
21817 IH_PERF_SEL_RB0_WPTR_WRAP_VF3            = 0x0000007d,
21818 IH_PERF_SEL_RB0_WPTR_WRAP_VF4            = 0x0000007e,
21819 IH_PERF_SEL_RB0_WPTR_WRAP_VF5            = 0x0000007f,
21820 IH_PERF_SEL_RB0_WPTR_WRAP_VF6            = 0x00000080,
21821 IH_PERF_SEL_RB0_WPTR_WRAP_VF7            = 0x00000081,
21822 IH_PERF_SEL_RB0_WPTR_WRAP_VF8            = 0x00000082,
21823 IH_PERF_SEL_RB0_WPTR_WRAP_VF9            = 0x00000083,
21824 IH_PERF_SEL_RB0_WPTR_WRAP_VF10           = 0x00000084,
21825 IH_PERF_SEL_RB0_WPTR_WRAP_VF11           = 0x00000085,
21826 IH_PERF_SEL_RB0_WPTR_WRAP_VF12           = 0x00000086,
21827 IH_PERF_SEL_RB0_WPTR_WRAP_VF13           = 0x00000087,
21828 IH_PERF_SEL_RB0_WPTR_WRAP_VF14           = 0x00000088,
21829 IH_PERF_SEL_RB0_WPTR_WRAP_VF15           = 0x00000089,
21830 IH_PERF_SEL_RB0_WPTR_WRAP_VF16           = 0x0000008a,
21831 IH_PERF_SEL_RB0_WPTR_WRAP_VF17           = 0x0000008b,
21832 IH_PERF_SEL_RB0_WPTR_WRAP_VF18           = 0x0000008c,
21833 IH_PERF_SEL_RB0_WPTR_WRAP_VF19           = 0x0000008d,
21834 IH_PERF_SEL_RB0_WPTR_WRAP_VF20           = 0x0000008e,
21835 IH_PERF_SEL_RB0_WPTR_WRAP_VF21           = 0x0000008f,
21836 IH_PERF_SEL_RB0_WPTR_WRAP_VF22           = 0x00000090,
21837 IH_PERF_SEL_RB0_WPTR_WRAP_VF23           = 0x00000091,
21838 IH_PERF_SEL_RB0_WPTR_WRAP_VF24           = 0x00000092,
21839 IH_PERF_SEL_RB0_WPTR_WRAP_VF25           = 0x00000093,
21840 IH_PERF_SEL_RB0_WPTR_WRAP_VF26           = 0x00000094,
21841 IH_PERF_SEL_RB0_WPTR_WRAP_VF27           = 0x00000095,
21842 IH_PERF_SEL_RB0_WPTR_WRAP_VF28           = 0x00000096,
21843 IH_PERF_SEL_RB0_WPTR_WRAP_VF29           = 0x00000097,
21844 IH_PERF_SEL_RB0_WPTR_WRAP_VF30           = 0x00000098,
21845 IH_PERF_SEL_RB0_RPTR_WRAP_VF0            = 0x00000099,
21846 IH_PERF_SEL_RB0_RPTR_WRAP_VF1            = 0x0000009a,
21847 IH_PERF_SEL_RB0_RPTR_WRAP_VF2            = 0x0000009b,
21848 IH_PERF_SEL_RB0_RPTR_WRAP_VF3            = 0x0000009c,
21849 IH_PERF_SEL_RB0_RPTR_WRAP_VF4            = 0x0000009d,
21850 IH_PERF_SEL_RB0_RPTR_WRAP_VF5            = 0x0000009e,
21851 IH_PERF_SEL_RB0_RPTR_WRAP_VF6            = 0x0000009f,
21852 IH_PERF_SEL_RB0_RPTR_WRAP_VF7            = 0x000000a0,
21853 IH_PERF_SEL_RB0_RPTR_WRAP_VF8            = 0x000000a1,
21854 IH_PERF_SEL_RB0_RPTR_WRAP_VF9            = 0x000000a2,
21855 IH_PERF_SEL_RB0_RPTR_WRAP_VF10           = 0x000000a3,
21856 IH_PERF_SEL_RB0_RPTR_WRAP_VF11           = 0x000000a4,
21857 IH_PERF_SEL_RB0_RPTR_WRAP_VF12           = 0x000000a5,
21858 IH_PERF_SEL_RB0_RPTR_WRAP_VF13           = 0x000000a6,
21859 IH_PERF_SEL_RB0_RPTR_WRAP_VF14           = 0x000000a7,
21860 IH_PERF_SEL_RB0_RPTR_WRAP_VF15           = 0x000000a8,
21861 IH_PERF_SEL_RB0_RPTR_WRAP_VF16           = 0x000000a9,
21862 IH_PERF_SEL_RB0_RPTR_WRAP_VF17           = 0x000000aa,
21863 IH_PERF_SEL_RB0_RPTR_WRAP_VF18           = 0x000000ab,
21864 IH_PERF_SEL_RB0_RPTR_WRAP_VF19           = 0x000000ac,
21865 IH_PERF_SEL_RB0_RPTR_WRAP_VF20           = 0x000000ad,
21866 IH_PERF_SEL_RB0_RPTR_WRAP_VF21           = 0x000000ae,
21867 IH_PERF_SEL_RB0_RPTR_WRAP_VF22           = 0x000000af,
21868 IH_PERF_SEL_RB0_RPTR_WRAP_VF23           = 0x000000b0,
21869 IH_PERF_SEL_RB0_RPTR_WRAP_VF24           = 0x000000b1,
21870 IH_PERF_SEL_RB0_RPTR_WRAP_VF25           = 0x000000b2,
21871 IH_PERF_SEL_RB0_RPTR_WRAP_VF26           = 0x000000b3,
21872 IH_PERF_SEL_RB0_RPTR_WRAP_VF27           = 0x000000b4,
21873 IH_PERF_SEL_RB0_RPTR_WRAP_VF28           = 0x000000b5,
21874 IH_PERF_SEL_RB0_RPTR_WRAP_VF29           = 0x000000b6,
21875 IH_PERF_SEL_RB0_RPTR_WRAP_VF30           = 0x000000b7,
21876 IH_PERF_SEL_BIF_LINE0_RISING_VF0         = 0x000000b8,
21877 IH_PERF_SEL_BIF_LINE0_RISING_VF1         = 0x000000b9,
21878 IH_PERF_SEL_BIF_LINE0_RISING_VF2         = 0x000000ba,
21879 IH_PERF_SEL_BIF_LINE0_RISING_VF3         = 0x000000bb,
21880 IH_PERF_SEL_BIF_LINE0_RISING_VF4         = 0x000000bc,
21881 IH_PERF_SEL_BIF_LINE0_RISING_VF5         = 0x000000bd,
21882 IH_PERF_SEL_BIF_LINE0_RISING_VF6         = 0x000000be,
21883 IH_PERF_SEL_BIF_LINE0_RISING_VF7         = 0x000000bf,
21884 IH_PERF_SEL_BIF_LINE0_RISING_VF8         = 0x000000c0,
21885 IH_PERF_SEL_BIF_LINE0_RISING_VF9         = 0x000000c1,
21886 IH_PERF_SEL_BIF_LINE0_RISING_VF10        = 0x000000c2,
21887 IH_PERF_SEL_BIF_LINE0_RISING_VF11        = 0x000000c3,
21888 IH_PERF_SEL_BIF_LINE0_RISING_VF12        = 0x000000c4,
21889 IH_PERF_SEL_BIF_LINE0_RISING_VF13        = 0x000000c5,
21890 IH_PERF_SEL_BIF_LINE0_RISING_VF14        = 0x000000c6,
21891 IH_PERF_SEL_BIF_LINE0_RISING_VF15        = 0x000000c7,
21892 IH_PERF_SEL_BIF_LINE0_RISING_VF16        = 0x000000c8,
21893 IH_PERF_SEL_BIF_LINE0_RISING_VF17        = 0x000000c9,
21894 IH_PERF_SEL_BIF_LINE0_RISING_VF18        = 0x000000ca,
21895 IH_PERF_SEL_BIF_LINE0_RISING_VF19        = 0x000000cb,
21896 IH_PERF_SEL_BIF_LINE0_RISING_VF20        = 0x000000cc,
21897 IH_PERF_SEL_BIF_LINE0_RISING_VF21        = 0x000000cd,
21898 IH_PERF_SEL_BIF_LINE0_RISING_VF22        = 0x000000ce,
21899 IH_PERF_SEL_BIF_LINE0_RISING_VF23        = 0x000000cf,
21900 IH_PERF_SEL_BIF_LINE0_RISING_VF24        = 0x000000d0,
21901 IH_PERF_SEL_BIF_LINE0_RISING_VF25        = 0x000000d1,
21902 IH_PERF_SEL_BIF_LINE0_RISING_VF26        = 0x000000d2,
21903 IH_PERF_SEL_BIF_LINE0_RISING_VF27        = 0x000000d3,
21904 IH_PERF_SEL_BIF_LINE0_RISING_VF28        = 0x000000d4,
21905 IH_PERF_SEL_BIF_LINE0_RISING_VF29        = 0x000000d5,
21906 IH_PERF_SEL_BIF_LINE0_RISING_VF30        = 0x000000d6,
21907 IH_PERF_SEL_BIF_LINE0_FALLING_VF0        = 0x000000d7,
21908 IH_PERF_SEL_BIF_LINE0_FALLING_VF1        = 0x000000d8,
21909 IH_PERF_SEL_BIF_LINE0_FALLING_VF2        = 0x000000d9,
21910 IH_PERF_SEL_BIF_LINE0_FALLING_VF3        = 0x000000da,
21911 IH_PERF_SEL_BIF_LINE0_FALLING_VF4        = 0x000000db,
21912 IH_PERF_SEL_BIF_LINE0_FALLING_VF5        = 0x000000dc,
21913 IH_PERF_SEL_BIF_LINE0_FALLING_VF6        = 0x000000dd,
21914 IH_PERF_SEL_BIF_LINE0_FALLING_VF7        = 0x000000de,
21915 IH_PERF_SEL_BIF_LINE0_FALLING_VF8        = 0x000000df,
21916 IH_PERF_SEL_BIF_LINE0_FALLING_VF9        = 0x000000e0,
21917 IH_PERF_SEL_BIF_LINE0_FALLING_VF10       = 0x000000e1,
21918 IH_PERF_SEL_BIF_LINE0_FALLING_VF11       = 0x000000e2,
21919 IH_PERF_SEL_BIF_LINE0_FALLING_VF12       = 0x000000e3,
21920 IH_PERF_SEL_BIF_LINE0_FALLING_VF13       = 0x000000e4,
21921 IH_PERF_SEL_BIF_LINE0_FALLING_VF14       = 0x000000e5,
21922 IH_PERF_SEL_BIF_LINE0_FALLING_VF15       = 0x000000e6,
21923 IH_PERF_SEL_BIF_LINE0_FALLING_VF16       = 0x000000e7,
21924 IH_PERF_SEL_BIF_LINE0_FALLING_VF17       = 0x000000e8,
21925 IH_PERF_SEL_BIF_LINE0_FALLING_VF18       = 0x000000e9,
21926 IH_PERF_SEL_BIF_LINE0_FALLING_VF19       = 0x000000ea,
21927 IH_PERF_SEL_BIF_LINE0_FALLING_VF20       = 0x000000eb,
21928 IH_PERF_SEL_BIF_LINE0_FALLING_VF21       = 0x000000ec,
21929 IH_PERF_SEL_BIF_LINE0_FALLING_VF22       = 0x000000ed,
21930 IH_PERF_SEL_BIF_LINE0_FALLING_VF23       = 0x000000ee,
21931 IH_PERF_SEL_BIF_LINE0_FALLING_VF24       = 0x000000ef,
21932 IH_PERF_SEL_BIF_LINE0_FALLING_VF25       = 0x000000f0,
21933 IH_PERF_SEL_BIF_LINE0_FALLING_VF26       = 0x000000f1,
21934 IH_PERF_SEL_BIF_LINE0_FALLING_VF27       = 0x000000f2,
21935 IH_PERF_SEL_BIF_LINE0_FALLING_VF28       = 0x000000f3,
21936 IH_PERF_SEL_BIF_LINE0_FALLING_VF29       = 0x000000f4,
21937 IH_PERF_SEL_BIF_LINE0_FALLING_VF30       = 0x000000f5,
21938 IH_PERF_SEL_CLIENT0_INT                  = 0x000000f6,
21939 IH_PERF_SEL_CLIENT1_INT                  = 0x000000f7,
21940 IH_PERF_SEL_CLIENT2_INT                  = 0x000000f8,
21941 IH_PERF_SEL_CLIENT3_INT                  = 0x000000f9,
21942 IH_PERF_SEL_CLIENT4_INT                  = 0x000000fa,
21943 IH_PERF_SEL_CLIENT5_INT                  = 0x000000fb,
21944 IH_PERF_SEL_CLIENT6_INT                  = 0x000000fc,
21945 IH_PERF_SEL_CLIENT7_INT                  = 0x000000fd,
21946 IH_PERF_SEL_CLIENT8_INT                  = 0x000000fe,
21947 IH_PERF_SEL_CLIENT9_INT                  = 0x000000ff,
21948 IH_PERF_SEL_CLIENT10_INT                 = 0x00000100,
21949 IH_PERF_SEL_CLIENT11_INT                 = 0x00000101,
21950 IH_PERF_SEL_CLIENT12_INT                 = 0x00000102,
21951 IH_PERF_SEL_CLIENT13_INT                 = 0x00000103,
21952 IH_PERF_SEL_CLIENT14_INT                 = 0x00000104,
21953 IH_PERF_SEL_CLIENT15_INT                 = 0x00000105,
21954 IH_PERF_SEL_CLIENT16_INT                 = 0x00000106,
21955 IH_PERF_SEL_CLIENT17_INT                 = 0x00000107,
21956 IH_PERF_SEL_CLIENT18_INT                 = 0x00000108,
21957 IH_PERF_SEL_CLIENT19_INT                 = 0x00000109,
21958 IH_PERF_SEL_CLIENT20_INT                 = 0x0000010a,
21959 IH_PERF_SEL_CLIENT21_INT                 = 0x0000010b,
21960 IH_PERF_SEL_CLIENT22_INT                 = 0x0000010c,
21961 IH_PERF_SEL_CLIENT23_INT                 = 0x0000010d,
21962 IH_PERF_SEL_CLIENT24_INT                 = 0x0000010e,
21963 IH_PERF_SEL_CLIENT25_INT                 = 0x0000010f,
21964 IH_PERF_SEL_CLIENT26_INT                 = 0x00000110,
21965 IH_PERF_SEL_CLIENT27_INT                 = 0x00000111,
21966 IH_PERF_SEL_CLIENT28_INT                 = 0x00000112,
21967 IH_PERF_SEL_CLIENT29_INT                 = 0x00000113,
21968 IH_PERF_SEL_CLIENT30_INT                 = 0x00000114,
21969 IH_PERF_SEL_CLIENT31_INT                 = 0x00000115,
21970 IH_PERF_SEL_RB1_FULL_VF0                 = 0x00000116,
21971 IH_PERF_SEL_RB1_FULL_VF1                 = 0x00000117,
21972 IH_PERF_SEL_RB1_FULL_VF2                 = 0x00000118,
21973 IH_PERF_SEL_RB1_FULL_VF3                 = 0x00000119,
21974 IH_PERF_SEL_RB1_FULL_VF4                 = 0x0000011a,
21975 IH_PERF_SEL_RB1_FULL_VF5                 = 0x0000011b,
21976 IH_PERF_SEL_RB1_FULL_VF6                 = 0x0000011c,
21977 IH_PERF_SEL_RB1_FULL_VF7                 = 0x0000011d,
21978 IH_PERF_SEL_RB1_FULL_VF8                 = 0x0000011e,
21979 IH_PERF_SEL_RB1_FULL_VF9                 = 0x0000011f,
21980 IH_PERF_SEL_RB1_FULL_VF10                = 0x00000120,
21981 IH_PERF_SEL_RB1_FULL_VF11                = 0x00000121,
21982 IH_PERF_SEL_RB1_FULL_VF12                = 0x00000122,
21983 IH_PERF_SEL_RB1_FULL_VF13                = 0x00000123,
21984 IH_PERF_SEL_RB1_FULL_VF14                = 0x00000124,
21985 IH_PERF_SEL_RB1_FULL_VF15                = 0x00000125,
21986 IH_PERF_SEL_RB1_FULL_VF16                = 0x00000126,
21987 IH_PERF_SEL_RB1_FULL_VF17                = 0x00000127,
21988 IH_PERF_SEL_RB1_FULL_VF18                = 0x00000128,
21989 IH_PERF_SEL_RB1_FULL_VF19                = 0x00000129,
21990 IH_PERF_SEL_RB1_FULL_VF20                = 0x0000012a,
21991 IH_PERF_SEL_RB1_FULL_VF21                = 0x0000012b,
21992 IH_PERF_SEL_RB1_FULL_VF22                = 0x0000012c,
21993 IH_PERF_SEL_RB1_FULL_VF23                = 0x0000012d,
21994 IH_PERF_SEL_RB1_FULL_VF24                = 0x0000012e,
21995 IH_PERF_SEL_RB1_FULL_VF25                = 0x0000012f,
21996 IH_PERF_SEL_RB1_FULL_VF26                = 0x00000130,
21997 IH_PERF_SEL_RB1_FULL_VF27                = 0x00000131,
21998 IH_PERF_SEL_RB1_FULL_VF28                = 0x00000132,
21999 IH_PERF_SEL_RB1_FULL_VF29                = 0x00000133,
22000 IH_PERF_SEL_RB1_FULL_VF30                = 0x00000134,
22001 IH_PERF_SEL_RB1_OVERFLOW_VF0             = 0x00000135,
22002 IH_PERF_SEL_RB1_OVERFLOW_VF1             = 0x00000136,
22003 IH_PERF_SEL_RB1_OVERFLOW_VF2             = 0x00000137,
22004 IH_PERF_SEL_RB1_OVERFLOW_VF3             = 0x00000138,
22005 IH_PERF_SEL_RB1_OVERFLOW_VF4             = 0x00000139,
22006 IH_PERF_SEL_RB1_OVERFLOW_VF5             = 0x0000013a,
22007 IH_PERF_SEL_RB1_OVERFLOW_VF6             = 0x0000013b,
22008 IH_PERF_SEL_RB1_OVERFLOW_VF7             = 0x0000013c,
22009 IH_PERF_SEL_RB1_OVERFLOW_VF8             = 0x0000013d,
22010 IH_PERF_SEL_RB1_OVERFLOW_VF9             = 0x0000013e,
22011 IH_PERF_SEL_RB1_OVERFLOW_VF10            = 0x0000013f,
22012 IH_PERF_SEL_RB1_OVERFLOW_VF11            = 0x00000140,
22013 IH_PERF_SEL_RB1_OVERFLOW_VF12            = 0x00000141,
22014 IH_PERF_SEL_RB1_OVERFLOW_VF13            = 0x00000142,
22015 IH_PERF_SEL_RB1_OVERFLOW_VF14            = 0x00000143,
22016 IH_PERF_SEL_RB1_OVERFLOW_VF15            = 0x00000144,
22017 IH_PERF_SEL_RB1_OVERFLOW_VF16            = 0x00000145,
22018 IH_PERF_SEL_RB1_OVERFLOW_VF17            = 0x00000146,
22019 IH_PERF_SEL_RB1_OVERFLOW_VF18            = 0x00000147,
22020 IH_PERF_SEL_RB1_OVERFLOW_VF19            = 0x00000148,
22021 IH_PERF_SEL_RB1_OVERFLOW_VF20            = 0x00000149,
22022 IH_PERF_SEL_RB1_OVERFLOW_VF21            = 0x0000014a,
22023 IH_PERF_SEL_RB1_OVERFLOW_VF22            = 0x0000014b,
22024 IH_PERF_SEL_RB1_OVERFLOW_VF23            = 0x0000014c,
22025 IH_PERF_SEL_RB1_OVERFLOW_VF24            = 0x0000014d,
22026 IH_PERF_SEL_RB1_OVERFLOW_VF25            = 0x0000014e,
22027 IH_PERF_SEL_RB1_OVERFLOW_VF26            = 0x0000014f,
22028 IH_PERF_SEL_RB1_OVERFLOW_VF27            = 0x00000150,
22029 IH_PERF_SEL_RB1_OVERFLOW_VF28            = 0x00000151,
22030 IH_PERF_SEL_RB1_OVERFLOW_VF29            = 0x00000152,
22031 IH_PERF_SEL_RB1_OVERFLOW_VF30            = 0x00000153,
22032 IH_PERF_SEL_RB1_WPTR_WRAP_VF0            = 0x00000154,
22033 IH_PERF_SEL_RB1_WPTR_WRAP_VF1            = 0x00000155,
22034 IH_PERF_SEL_RB1_WPTR_WRAP_VF2            = 0x00000156,
22035 IH_PERF_SEL_RB1_WPTR_WRAP_VF3            = 0x00000157,
22036 IH_PERF_SEL_RB1_WPTR_WRAP_VF4            = 0x00000158,
22037 IH_PERF_SEL_RB1_WPTR_WRAP_VF5            = 0x00000159,
22038 IH_PERF_SEL_RB1_WPTR_WRAP_VF6            = 0x0000015a,
22039 IH_PERF_SEL_RB1_WPTR_WRAP_VF7            = 0x0000015b,
22040 IH_PERF_SEL_RB1_WPTR_WRAP_VF8            = 0x0000015c,
22041 IH_PERF_SEL_RB1_WPTR_WRAP_VF9            = 0x0000015d,
22042 IH_PERF_SEL_RB1_WPTR_WRAP_VF10           = 0x0000015e,
22043 IH_PERF_SEL_RB1_WPTR_WRAP_VF11           = 0x0000015f,
22044 IH_PERF_SEL_RB1_WPTR_WRAP_VF12           = 0x00000160,
22045 IH_PERF_SEL_RB1_WPTR_WRAP_VF13           = 0x00000161,
22046 IH_PERF_SEL_RB1_WPTR_WRAP_VF14           = 0x00000162,
22047 IH_PERF_SEL_RB1_WPTR_WRAP_VF15           = 0x00000163,
22048 IH_PERF_SEL_RB1_WPTR_WRAP_VF16           = 0x00000164,
22049 IH_PERF_SEL_RB1_WPTR_WRAP_VF17           = 0x00000165,
22050 IH_PERF_SEL_RB1_WPTR_WRAP_VF18           = 0x00000166,
22051 IH_PERF_SEL_RB1_WPTR_WRAP_VF19           = 0x00000167,
22052 IH_PERF_SEL_RB1_WPTR_WRAP_VF20           = 0x00000168,
22053 IH_PERF_SEL_RB1_WPTR_WRAP_VF21           = 0x00000169,
22054 IH_PERF_SEL_RB1_WPTR_WRAP_VF22           = 0x0000016a,
22055 IH_PERF_SEL_RB1_WPTR_WRAP_VF23           = 0x0000016b,
22056 IH_PERF_SEL_RB1_WPTR_WRAP_VF24           = 0x0000016c,
22057 IH_PERF_SEL_RB1_WPTR_WRAP_VF25           = 0x0000016d,
22058 IH_PERF_SEL_RB1_WPTR_WRAP_VF26           = 0x0000016e,
22059 IH_PERF_SEL_RB1_WPTR_WRAP_VF27           = 0x0000016f,
22060 IH_PERF_SEL_RB1_WPTR_WRAP_VF28           = 0x00000170,
22061 IH_PERF_SEL_RB1_WPTR_WRAP_VF29           = 0x00000171,
22062 IH_PERF_SEL_RB1_WPTR_WRAP_VF30           = 0x00000172,
22063 IH_PERF_SEL_RB1_RPTR_WRAP_VF0            = 0x00000173,
22064 IH_PERF_SEL_RB1_RPTR_WRAP_VF1            = 0x00000174,
22065 IH_PERF_SEL_RB1_RPTR_WRAP_VF2            = 0x00000175,
22066 IH_PERF_SEL_RB1_RPTR_WRAP_VF3            = 0x00000176,
22067 IH_PERF_SEL_RB1_RPTR_WRAP_VF4            = 0x00000177,
22068 IH_PERF_SEL_RB1_RPTR_WRAP_VF5            = 0x00000178,
22069 IH_PERF_SEL_RB1_RPTR_WRAP_VF6            = 0x00000179,
22070 IH_PERF_SEL_RB1_RPTR_WRAP_VF7            = 0x0000017a,
22071 IH_PERF_SEL_RB1_RPTR_WRAP_VF8            = 0x0000017b,
22072 IH_PERF_SEL_RB1_RPTR_WRAP_VF9            = 0x0000017c,
22073 IH_PERF_SEL_RB1_RPTR_WRAP_VF10           = 0x0000017d,
22074 IH_PERF_SEL_RB1_RPTR_WRAP_VF11           = 0x0000017e,
22075 IH_PERF_SEL_RB1_RPTR_WRAP_VF12           = 0x0000017f,
22076 IH_PERF_SEL_RB1_RPTR_WRAP_VF13           = 0x00000180,
22077 IH_PERF_SEL_RB1_RPTR_WRAP_VF14           = 0x00000181,
22078 IH_PERF_SEL_RB1_RPTR_WRAP_VF15           = 0x00000182,
22079 IH_PERF_SEL_RB1_RPTR_WRAP_VF16           = 0x00000183,
22080 IH_PERF_SEL_RB1_RPTR_WRAP_VF17           = 0x00000184,
22081 IH_PERF_SEL_RB1_RPTR_WRAP_VF18           = 0x00000185,
22082 IH_PERF_SEL_RB1_RPTR_WRAP_VF19           = 0x00000186,
22083 IH_PERF_SEL_RB1_RPTR_WRAP_VF20           = 0x00000187,
22084 IH_PERF_SEL_RB1_RPTR_WRAP_VF21           = 0x00000188,
22085 IH_PERF_SEL_RB1_RPTR_WRAP_VF22           = 0x00000189,
22086 IH_PERF_SEL_RB1_RPTR_WRAP_VF23           = 0x0000018a,
22087 IH_PERF_SEL_RB1_RPTR_WRAP_VF24           = 0x0000018b,
22088 IH_PERF_SEL_RB1_RPTR_WRAP_VF25           = 0x0000018c,
22089 IH_PERF_SEL_RB1_RPTR_WRAP_VF26           = 0x0000018d,
22090 IH_PERF_SEL_RB1_RPTR_WRAP_VF27           = 0x0000018e,
22091 IH_PERF_SEL_RB1_RPTR_WRAP_VF28           = 0x0000018f,
22092 IH_PERF_SEL_RB1_RPTR_WRAP_VF29           = 0x00000190,
22093 IH_PERF_SEL_RB1_RPTR_WRAP_VF30           = 0x00000191,
22094 IH_PERF_SEL_RB2_FULL_VF0                 = 0x00000192,
22095 IH_PERF_SEL_RB2_FULL_VF1                 = 0x00000193,
22096 IH_PERF_SEL_RB2_FULL_VF2                 = 0x00000194,
22097 IH_PERF_SEL_RB2_FULL_VF3                 = 0x00000195,
22098 IH_PERF_SEL_RB2_FULL_VF4                 = 0x00000196,
22099 IH_PERF_SEL_RB2_FULL_VF5                 = 0x00000197,
22100 IH_PERF_SEL_RB2_FULL_VF6                 = 0x00000198,
22101 IH_PERF_SEL_RB2_FULL_VF7                 = 0x00000199,
22102 IH_PERF_SEL_RB2_FULL_VF8                 = 0x0000019a,
22103 IH_PERF_SEL_RB2_FULL_VF9                 = 0x0000019b,
22104 IH_PERF_SEL_RB2_FULL_VF10                = 0x0000019c,
22105 IH_PERF_SEL_RB2_FULL_VF11                = 0x0000019d,
22106 IH_PERF_SEL_RB2_FULL_VF12                = 0x0000019e,
22107 IH_PERF_SEL_RB2_FULL_VF13                = 0x0000019f,
22108 IH_PERF_SEL_RB2_FULL_VF14                = 0x000001a0,
22109 IH_PERF_SEL_RB2_FULL_VF15                = 0x000001a1,
22110 IH_PERF_SEL_RB2_FULL_VF16                = 0x000001a2,
22111 IH_PERF_SEL_RB2_FULL_VF17                = 0x000001a3,
22112 IH_PERF_SEL_RB2_FULL_VF18                = 0x000001a4,
22113 IH_PERF_SEL_RB2_FULL_VF19                = 0x000001a5,
22114 IH_PERF_SEL_RB2_FULL_VF20                = 0x000001a6,
22115 IH_PERF_SEL_RB2_FULL_VF21                = 0x000001a7,
22116 IH_PERF_SEL_RB2_FULL_VF22                = 0x000001a8,
22117 IH_PERF_SEL_RB2_FULL_VF23                = 0x000001a9,
22118 IH_PERF_SEL_RB2_FULL_VF24                = 0x000001aa,
22119 IH_PERF_SEL_RB2_FULL_VF25                = 0x000001ab,
22120 IH_PERF_SEL_RB2_FULL_VF26                = 0x000001ac,
22121 IH_PERF_SEL_RB2_FULL_VF27                = 0x000001ad,
22122 IH_PERF_SEL_RB2_FULL_VF28                = 0x000001ae,
22123 IH_PERF_SEL_RB2_FULL_VF29                = 0x000001af,
22124 IH_PERF_SEL_RB2_FULL_VF30                = 0x000001b0,
22125 IH_PERF_SEL_RB2_OVERFLOW_VF0             = 0x000001b1,
22126 IH_PERF_SEL_RB2_OVERFLOW_VF1             = 0x000001b2,
22127 IH_PERF_SEL_RB2_OVERFLOW_VF2             = 0x000001b3,
22128 IH_PERF_SEL_RB2_OVERFLOW_VF3             = 0x000001b4,
22129 IH_PERF_SEL_RB2_OVERFLOW_VF4             = 0x000001b5,
22130 IH_PERF_SEL_RB2_OVERFLOW_VF5             = 0x000001b6,
22131 IH_PERF_SEL_RB2_OVERFLOW_VF6             = 0x000001b7,
22132 IH_PERF_SEL_RB2_OVERFLOW_VF7             = 0x000001b8,
22133 IH_PERF_SEL_RB2_OVERFLOW_VF8             = 0x000001b9,
22134 IH_PERF_SEL_RB2_OVERFLOW_VF9             = 0x000001ba,
22135 IH_PERF_SEL_RB2_OVERFLOW_VF10            = 0x000001bb,
22136 IH_PERF_SEL_RB2_OVERFLOW_VF11            = 0x000001bc,
22137 IH_PERF_SEL_RB2_OVERFLOW_VF12            = 0x000001bd,
22138 IH_PERF_SEL_RB2_OVERFLOW_VF13            = 0x000001be,
22139 IH_PERF_SEL_RB2_OVERFLOW_VF14            = 0x000001bf,
22140 IH_PERF_SEL_RB2_OVERFLOW_VF15            = 0x000001c0,
22141 IH_PERF_SEL_RB2_OVERFLOW_VF16            = 0x000001c1,
22142 IH_PERF_SEL_RB2_OVERFLOW_VF17            = 0x000001c2,
22143 IH_PERF_SEL_RB2_OVERFLOW_VF18            = 0x000001c3,
22144 IH_PERF_SEL_RB2_OVERFLOW_VF19            = 0x000001c4,
22145 IH_PERF_SEL_RB2_OVERFLOW_VF20            = 0x000001c5,
22146 IH_PERF_SEL_RB2_OVERFLOW_VF21            = 0x000001c6,
22147 IH_PERF_SEL_RB2_OVERFLOW_VF22            = 0x000001c7,
22148 IH_PERF_SEL_RB2_OVERFLOW_VF23            = 0x000001c8,
22149 IH_PERF_SEL_RB2_OVERFLOW_VF24            = 0x000001c9,
22150 IH_PERF_SEL_RB2_OVERFLOW_VF25            = 0x000001ca,
22151 IH_PERF_SEL_RB2_OVERFLOW_VF26            = 0x000001cb,
22152 IH_PERF_SEL_RB2_OVERFLOW_VF27            = 0x000001cc,
22153 IH_PERF_SEL_RB2_OVERFLOW_VF28            = 0x000001cd,
22154 IH_PERF_SEL_RB2_OVERFLOW_VF29            = 0x000001ce,
22155 IH_PERF_SEL_RB2_OVERFLOW_VF30            = 0x000001cf,
22156 IH_PERF_SEL_RB2_WPTR_WRAP_VF0            = 0x000001d0,
22157 IH_PERF_SEL_RB2_WPTR_WRAP_VF1            = 0x000001d1,
22158 IH_PERF_SEL_RB2_WPTR_WRAP_VF2            = 0x000001d2,
22159 IH_PERF_SEL_RB2_WPTR_WRAP_VF3            = 0x000001d3,
22160 IH_PERF_SEL_RB2_WPTR_WRAP_VF4            = 0x000001d4,
22161 IH_PERF_SEL_RB2_WPTR_WRAP_VF5            = 0x000001d5,
22162 IH_PERF_SEL_RB2_WPTR_WRAP_VF6            = 0x000001d6,
22163 IH_PERF_SEL_RB2_WPTR_WRAP_VF7            = 0x000001d7,
22164 IH_PERF_SEL_RB2_WPTR_WRAP_VF8            = 0x000001d8,
22165 IH_PERF_SEL_RB2_WPTR_WRAP_VF9            = 0x000001d9,
22166 IH_PERF_SEL_RB2_WPTR_WRAP_VF10           = 0x000001da,
22167 IH_PERF_SEL_RB2_WPTR_WRAP_VF11           = 0x000001db,
22168 IH_PERF_SEL_RB2_WPTR_WRAP_VF12           = 0x000001dc,
22169 IH_PERF_SEL_RB2_WPTR_WRAP_VF13           = 0x000001dd,
22170 IH_PERF_SEL_RB2_WPTR_WRAP_VF14           = 0x000001de,
22171 IH_PERF_SEL_RB2_WPTR_WRAP_VF15           = 0x000001df,
22172 IH_PERF_SEL_RB2_WPTR_WRAP_VF16           = 0x000001e0,
22173 IH_PERF_SEL_RB2_WPTR_WRAP_VF17           = 0x000001e1,
22174 IH_PERF_SEL_RB2_WPTR_WRAP_VF18           = 0x000001e2,
22175 IH_PERF_SEL_RB2_WPTR_WRAP_VF19           = 0x000001e3,
22176 IH_PERF_SEL_RB2_WPTR_WRAP_VF20           = 0x000001e4,
22177 IH_PERF_SEL_RB2_WPTR_WRAP_VF21           = 0x000001e5,
22178 IH_PERF_SEL_RB2_WPTR_WRAP_VF22           = 0x000001e6,
22179 IH_PERF_SEL_RB2_WPTR_WRAP_VF23           = 0x000001e7,
22180 IH_PERF_SEL_RB2_WPTR_WRAP_VF24           = 0x000001e8,
22181 IH_PERF_SEL_RB2_WPTR_WRAP_VF25           = 0x000001e9,
22182 IH_PERF_SEL_RB2_WPTR_WRAP_VF26           = 0x000001ea,
22183 IH_PERF_SEL_RB2_WPTR_WRAP_VF27           = 0x000001eb,
22184 IH_PERF_SEL_RB2_WPTR_WRAP_VF28           = 0x000001ec,
22185 IH_PERF_SEL_RB2_WPTR_WRAP_VF29           = 0x000001ed,
22186 IH_PERF_SEL_RB2_WPTR_WRAP_VF30           = 0x000001ee,
22187 IH_PERF_SEL_RB2_RPTR_WRAP_VF0            = 0x000001ef,
22188 IH_PERF_SEL_RB2_RPTR_WRAP_VF1            = 0x000001f0,
22189 IH_PERF_SEL_RB2_RPTR_WRAP_VF2            = 0x000001f1,
22190 IH_PERF_SEL_RB2_RPTR_WRAP_VF3            = 0x000001f2,
22191 IH_PERF_SEL_RB2_RPTR_WRAP_VF4            = 0x000001f3,
22192 IH_PERF_SEL_RB2_RPTR_WRAP_VF5            = 0x000001f4,
22193 IH_PERF_SEL_RB2_RPTR_WRAP_VF6            = 0x000001f5,
22194 IH_PERF_SEL_RB2_RPTR_WRAP_VF7            = 0x000001f6,
22195 IH_PERF_SEL_RB2_RPTR_WRAP_VF8            = 0x000001f7,
22196 IH_PERF_SEL_RB2_RPTR_WRAP_VF9            = 0x000001f8,
22197 IH_PERF_SEL_RB2_RPTR_WRAP_VF10           = 0x000001f9,
22198 IH_PERF_SEL_RB2_RPTR_WRAP_VF11           = 0x000001fa,
22199 IH_PERF_SEL_RB2_RPTR_WRAP_VF12           = 0x000001fb,
22200 IH_PERF_SEL_RB2_RPTR_WRAP_VF13           = 0x000001fc,
22201 IH_PERF_SEL_RB2_RPTR_WRAP_VF14           = 0x000001fd,
22202 IH_PERF_SEL_RB2_RPTR_WRAP_VF15           = 0x000001fe,
22203 IH_PERF_SEL_RB2_RPTR_WRAP_VF16           = 0x000001ff,
22204 IH_PERF_SEL_RB2_RPTR_WRAP_VF17           = 0x00000200,
22205 IH_PERF_SEL_RB2_RPTR_WRAP_VF18           = 0x00000201,
22206 IH_PERF_SEL_RB2_RPTR_WRAP_VF19           = 0x00000202,
22207 IH_PERF_SEL_RB2_RPTR_WRAP_VF20           = 0x00000203,
22208 IH_PERF_SEL_RB2_RPTR_WRAP_VF21           = 0x00000204,
22209 IH_PERF_SEL_RB2_RPTR_WRAP_VF22           = 0x00000205,
22210 IH_PERF_SEL_RB2_RPTR_WRAP_VF23           = 0x00000206,
22211 IH_PERF_SEL_RB2_RPTR_WRAP_VF24           = 0x00000207,
22212 IH_PERF_SEL_RB2_RPTR_WRAP_VF25           = 0x00000208,
22213 IH_PERF_SEL_RB2_RPTR_WRAP_VF26           = 0x00000209,
22214 IH_PERF_SEL_RB2_RPTR_WRAP_VF27           = 0x0000020a,
22215 IH_PERF_SEL_RB2_RPTR_WRAP_VF28           = 0x0000020b,
22216 IH_PERF_SEL_RB2_RPTR_WRAP_VF29           = 0x0000020c,
22217 IH_PERF_SEL_RB2_RPTR_WRAP_VF30           = 0x0000020d,
22218 IH_PERF_SEL_RB0_FULL_DRAIN_DROP          = 0x0000020e,
22219 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0      = 0x0000020f,
22220 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1      = 0x00000210,
22221 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2      = 0x00000211,
22222 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3      = 0x00000212,
22223 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4      = 0x00000213,
22224 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5      = 0x00000214,
22225 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6      = 0x00000215,
22226 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7      = 0x00000216,
22227 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8      = 0x00000217,
22228 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9      = 0x00000218,
22229 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10     = 0x00000219,
22230 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11     = 0x0000021a,
22231 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12     = 0x0000021b,
22232 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13     = 0x0000021c,
22233 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14     = 0x0000021d,
22234 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15     = 0x0000021e,
22235 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16     = 0x0000021f,
22236 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17     = 0x00000220,
22237 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18     = 0x00000221,
22238 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19     = 0x00000222,
22239 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20     = 0x00000223,
22240 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21     = 0x00000224,
22241 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22     = 0x00000225,
22242 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23     = 0x00000226,
22243 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24     = 0x00000227,
22244 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25     = 0x00000228,
22245 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26     = 0x00000229,
22246 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27     = 0x0000022a,
22247 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28     = 0x0000022b,
22248 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29     = 0x0000022c,
22249 IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30     = 0x0000022d,
22250 IH_PERF_SEL_RB1_FULL_DRAIN_DROP          = 0x0000022e,
22251 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0      = 0x0000022f,
22252 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1      = 0x00000230,
22253 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2      = 0x00000231,
22254 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3      = 0x00000232,
22255 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4      = 0x00000233,
22256 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5      = 0x00000234,
22257 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6      = 0x00000235,
22258 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7      = 0x00000236,
22259 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8      = 0x00000237,
22260 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9      = 0x00000238,
22261 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10     = 0x00000239,
22262 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11     = 0x0000023a,
22263 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12     = 0x0000023b,
22264 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13     = 0x0000023c,
22265 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14     = 0x0000023d,
22266 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15     = 0x0000023e,
22267 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16     = 0x0000023f,
22268 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17     = 0x00000240,
22269 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18     = 0x00000241,
22270 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19     = 0x00000242,
22271 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20     = 0x00000243,
22272 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21     = 0x00000244,
22273 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22     = 0x00000245,
22274 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23     = 0x00000246,
22275 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24     = 0x00000247,
22276 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25     = 0x00000248,
22277 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26     = 0x00000249,
22278 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27     = 0x0000024a,
22279 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28     = 0x0000024b,
22280 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29     = 0x0000024c,
22281 IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30     = 0x0000024d,
22282 IH_PERF_SEL_RB2_FULL_DRAIN_DROP          = 0x0000024e,
22283 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0      = 0x0000024f,
22284 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1      = 0x00000250,
22285 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2      = 0x00000251,
22286 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3      = 0x00000252,
22287 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4      = 0x00000253,
22288 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5      = 0x00000254,
22289 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6      = 0x00000255,
22290 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7      = 0x00000256,
22291 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8      = 0x00000257,
22292 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9      = 0x00000258,
22293 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10     = 0x00000259,
22294 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11     = 0x0000025a,
22295 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12     = 0x0000025b,
22296 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13     = 0x0000025c,
22297 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14     = 0x0000025d,
22298 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15     = 0x0000025e,
22299 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16     = 0x0000025f,
22300 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17     = 0x00000260,
22301 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18     = 0x00000261,
22302 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19     = 0x00000262,
22303 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20     = 0x00000263,
22304 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21     = 0x00000264,
22305 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22     = 0x00000265,
22306 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23     = 0x00000266,
22307 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24     = 0x00000267,
22308 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25     = 0x00000268,
22309 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26     = 0x00000269,
22310 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27     = 0x0000026a,
22311 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28     = 0x0000026b,
22312 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29     = 0x0000026c,
22313 IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30     = 0x0000026d,
22314 IH_PERF_SEL_RB0_LOAD_RPTR                = 0x0000026e,
22315 IH_PERF_SEL_RB0_LOAD_RPTR_VF0            = 0x0000026f,
22316 IH_PERF_SEL_RB0_LOAD_RPTR_VF1            = 0x00000270,
22317 IH_PERF_SEL_RB0_LOAD_RPTR_VF2            = 0x00000271,
22318 IH_PERF_SEL_RB0_LOAD_RPTR_VF3            = 0x00000272,
22319 IH_PERF_SEL_RB0_LOAD_RPTR_VF4            = 0x00000273,
22320 IH_PERF_SEL_RB0_LOAD_RPTR_VF5            = 0x00000274,
22321 IH_PERF_SEL_RB0_LOAD_RPTR_VF6            = 0x00000275,
22322 IH_PERF_SEL_RB0_LOAD_RPTR_VF7            = 0x00000276,
22323 IH_PERF_SEL_RB0_LOAD_RPTR_VF8            = 0x00000277,
22324 IH_PERF_SEL_RB0_LOAD_RPTR_VF9            = 0x00000278,
22325 IH_PERF_SEL_RB0_LOAD_RPTR_VF10           = 0x00000279,
22326 IH_PERF_SEL_RB0_LOAD_RPTR_VF11           = 0x0000027a,
22327 IH_PERF_SEL_RB0_LOAD_RPTR_VF12           = 0x0000027b,
22328 IH_PERF_SEL_RB0_LOAD_RPTR_VF13           = 0x0000027c,
22329 IH_PERF_SEL_RB0_LOAD_RPTR_VF14           = 0x0000027d,
22330 IH_PERF_SEL_RB0_LOAD_RPTR_VF15           = 0x0000027e,
22331 IH_PERF_SEL_RB0_LOAD_RPTR_VF16           = 0x0000027f,
22332 IH_PERF_SEL_RB0_LOAD_RPTR_VF17           = 0x00000280,
22333 IH_PERF_SEL_RB0_LOAD_RPTR_VF18           = 0x00000281,
22334 IH_PERF_SEL_RB0_LOAD_RPTR_VF19           = 0x00000282,
22335 IH_PERF_SEL_RB0_LOAD_RPTR_VF20           = 0x00000283,
22336 IH_PERF_SEL_RB0_LOAD_RPTR_VF21           = 0x00000284,
22337 IH_PERF_SEL_RB0_LOAD_RPTR_VF22           = 0x00000285,
22338 IH_PERF_SEL_RB0_LOAD_RPTR_VF23           = 0x00000286,
22339 IH_PERF_SEL_RB0_LOAD_RPTR_VF24           = 0x00000287,
22340 IH_PERF_SEL_RB0_LOAD_RPTR_VF25           = 0x00000288,
22341 IH_PERF_SEL_RB0_LOAD_RPTR_VF26           = 0x00000289,
22342 IH_PERF_SEL_RB0_LOAD_RPTR_VF27           = 0x0000028a,
22343 IH_PERF_SEL_RB0_LOAD_RPTR_VF28           = 0x0000028b,
22344 IH_PERF_SEL_RB0_LOAD_RPTR_VF29           = 0x0000028c,
22345 IH_PERF_SEL_RB0_LOAD_RPTR_VF30           = 0x0000028d,
22346 IH_PERF_SEL_RB1_LOAD_RPTR                = 0x0000028e,
22347 IH_PERF_SEL_RB1_LOAD_RPTR_VF0            = 0x0000028f,
22348 IH_PERF_SEL_RB1_LOAD_RPTR_VF1            = 0x00000290,
22349 IH_PERF_SEL_RB1_LOAD_RPTR_VF2            = 0x00000291,
22350 IH_PERF_SEL_RB1_LOAD_RPTR_VF3            = 0x00000292,
22351 IH_PERF_SEL_RB1_LOAD_RPTR_VF4            = 0x00000293,
22352 IH_PERF_SEL_RB1_LOAD_RPTR_VF5            = 0x00000294,
22353 IH_PERF_SEL_RB1_LOAD_RPTR_VF6            = 0x00000295,
22354 IH_PERF_SEL_RB1_LOAD_RPTR_VF7            = 0x00000296,
22355 IH_PERF_SEL_RB1_LOAD_RPTR_VF8            = 0x00000297,
22356 IH_PERF_SEL_RB1_LOAD_RPTR_VF9            = 0x00000298,
22357 IH_PERF_SEL_RB1_LOAD_RPTR_VF10           = 0x00000299,
22358 IH_PERF_SEL_RB1_LOAD_RPTR_VF11           = 0x0000029a,
22359 IH_PERF_SEL_RB1_LOAD_RPTR_VF12           = 0x0000029b,
22360 IH_PERF_SEL_RB1_LOAD_RPTR_VF13           = 0x0000029c,
22361 IH_PERF_SEL_RB1_LOAD_RPTR_VF14           = 0x0000029d,
22362 IH_PERF_SEL_RB1_LOAD_RPTR_VF15           = 0x0000029e,
22363 IH_PERF_SEL_RB1_LOAD_RPTR_VF16           = 0x0000029f,
22364 IH_PERF_SEL_RB1_LOAD_RPTR_VF17           = 0x000002a0,
22365 IH_PERF_SEL_RB1_LOAD_RPTR_VF18           = 0x000002a1,
22366 IH_PERF_SEL_RB1_LOAD_RPTR_VF19           = 0x000002a2,
22367 IH_PERF_SEL_RB1_LOAD_RPTR_VF20           = 0x000002a3,
22368 IH_PERF_SEL_RB1_LOAD_RPTR_VF21           = 0x000002a4,
22369 IH_PERF_SEL_RB1_LOAD_RPTR_VF22           = 0x000002a5,
22370 IH_PERF_SEL_RB1_LOAD_RPTR_VF23           = 0x000002a6,
22371 IH_PERF_SEL_RB1_LOAD_RPTR_VF24           = 0x000002a7,
22372 IH_PERF_SEL_RB1_LOAD_RPTR_VF25           = 0x000002a8,
22373 IH_PERF_SEL_RB1_LOAD_RPTR_VF26           = 0x000002a9,
22374 IH_PERF_SEL_RB1_LOAD_RPTR_VF27           = 0x000002aa,
22375 IH_PERF_SEL_RB1_LOAD_RPTR_VF28           = 0x000002ab,
22376 IH_PERF_SEL_RB1_LOAD_RPTR_VF29           = 0x000002ac,
22377 IH_PERF_SEL_RB1_LOAD_RPTR_VF30           = 0x000002ad,
22378 IH_PERF_SEL_RB2_LOAD_RPTR                = 0x000002ae,
22379 IH_PERF_SEL_RB2_LOAD_RPTR_VF0            = 0x000002af,
22380 IH_PERF_SEL_RB2_LOAD_RPTR_VF1            = 0x000002b0,
22381 IH_PERF_SEL_RB2_LOAD_RPTR_VF2            = 0x000002b1,
22382 IH_PERF_SEL_RB2_LOAD_RPTR_VF3            = 0x000002b2,
22383 IH_PERF_SEL_RB2_LOAD_RPTR_VF4            = 0x000002b3,
22384 IH_PERF_SEL_RB2_LOAD_RPTR_VF5            = 0x000002b4,
22385 IH_PERF_SEL_RB2_LOAD_RPTR_VF6            = 0x000002b5,
22386 IH_PERF_SEL_RB2_LOAD_RPTR_VF7            = 0x000002b6,
22387 IH_PERF_SEL_RB2_LOAD_RPTR_VF8            = 0x000002b7,
22388 IH_PERF_SEL_RB2_LOAD_RPTR_VF9            = 0x000002b8,
22389 IH_PERF_SEL_RB2_LOAD_RPTR_VF10           = 0x000002b9,
22390 IH_PERF_SEL_RB2_LOAD_RPTR_VF11           = 0x000002ba,
22391 IH_PERF_SEL_RB2_LOAD_RPTR_VF12           = 0x000002bb,
22392 IH_PERF_SEL_RB2_LOAD_RPTR_VF13           = 0x000002bc,
22393 IH_PERF_SEL_RB2_LOAD_RPTR_VF14           = 0x000002bd,
22394 IH_PERF_SEL_RB2_LOAD_RPTR_VF15           = 0x000002be,
22395 IH_PERF_SEL_RB2_LOAD_RPTR_VF16           = 0x000002bf,
22396 IH_PERF_SEL_RB2_LOAD_RPTR_VF17           = 0x000002c0,
22397 IH_PERF_SEL_RB2_LOAD_RPTR_VF18           = 0x000002c1,
22398 IH_PERF_SEL_RB2_LOAD_RPTR_VF19           = 0x000002c2,
22399 IH_PERF_SEL_RB2_LOAD_RPTR_VF20           = 0x000002c3,
22400 IH_PERF_SEL_RB2_LOAD_RPTR_VF21           = 0x000002c4,
22401 IH_PERF_SEL_RB2_LOAD_RPTR_VF22           = 0x000002c5,
22402 IH_PERF_SEL_RB2_LOAD_RPTR_VF23           = 0x000002c6,
22403 IH_PERF_SEL_RB2_LOAD_RPTR_VF24           = 0x000002c7,
22404 IH_PERF_SEL_RB2_LOAD_RPTR_VF25           = 0x000002c8,
22405 IH_PERF_SEL_RB2_LOAD_RPTR_VF26           = 0x000002c9,
22406 IH_PERF_SEL_RB2_LOAD_RPTR_VF27           = 0x000002ca,
22407 IH_PERF_SEL_RB2_LOAD_RPTR_VF28           = 0x000002cb,
22408 IH_PERF_SEL_RB2_LOAD_RPTR_VF29           = 0x000002cc,
22409 IH_PERF_SEL_RB2_LOAD_RPTR_VF30           = 0x000002cd,
22410 } IH_PERF_SEL;
22411 
22412 /*
22413  * IH_CLIENT_TYPE enum
22414  */
22415 
22416 typedef enum IH_CLIENT_TYPE {
22417 IH_GFX_VMID_CLIENT                       = 0x00000000,
22418 IH_MM_VMID_CLIENT                        = 0x00000001,
22419 IH_MULTI_VMID_CLIENT                     = 0x00000002,
22420 IH_CLIENT_TYPE_RESERVED                  = 0x00000003,
22421 } IH_CLIENT_TYPE;
22422 
22423 /*
22424  * IH_RING_ID enum
22425  */
22426 
22427 typedef enum IH_RING_ID {
22428 IH_RING_ID_INTERRUPT                     = 0x00000000,
22429 IH_RING_ID_REQUEST                       = 0x00000001,
22430 IH_RING_ID_TRANSLATION                   = 0x00000002,
22431 IH_RING_ID_RESERVED                      = 0x00000003,
22432 } IH_RING_ID;
22433 
22434 /*
22435  * IH_VF_RB_SELECT enum
22436  */
22437 
22438 typedef enum IH_VF_RB_SELECT {
22439 IH_VF_RB_SELECT_CLIENT_FCN_ID            = 0x00000000,
22440 IH_VF_RB_SELECT_IH_FCN_ID                = 0x00000001,
22441 IH_VF_RB_SELECT_PF                       = 0x00000002,
22442 IH_VF_RB_SELECT_RESERVED                 = 0x00000003,
22443 } IH_VF_RB_SELECT;
22444 
22445 /*
22446  * IH_INTERFACE_TYPE enum
22447  */
22448 
22449 typedef enum IH_INTERFACE_TYPE {
22450 IH_LEGACY_INTERFACE                      = 0x00000000,
22451 IH_REGISTER_WRITE_INTERFACE              = 0x00000001,
22452 } IH_INTERFACE_TYPE;
22453 
22454 /*******************************************************
22455  * SEM Enums
22456  *******************************************************/
22457 
22458 /*
22459  * SEM_PERF_SEL enum
22460  */
22461 
22462 typedef enum SEM_PERF_SEL {
22463 SEM_PERF_SEL_CYCLE                       = 0x00000000,
22464 SEM_PERF_SEL_IDLE                        = 0x00000001,
22465 SEM_PERF_SEL_SDMA0_REQ_SIGNAL            = 0x00000002,
22466 SEM_PERF_SEL_SDMA1_REQ_SIGNAL            = 0x00000003,
22467 SEM_PERF_SEL_UVD_REQ_SIGNAL              = 0x00000004,
22468 SEM_PERF_SEL_VCE0_REQ_SIGNAL             = 0x00000005,
22469 SEM_PERF_SEL_ACP_REQ_SIGNAL              = 0x00000006,
22470 SEM_PERF_SEL_ISP_REQ_SIGNAL              = 0x00000007,
22471 SEM_PERF_SEL_VCE1_REQ_SIGNAL             = 0x00000008,
22472 SEM_PERF_SEL_VP8_REQ_SIGNAL              = 0x00000009,
22473 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL           = 0x0000000a,
22474 SEM_PERF_SEL_CPG_E1_REQ_SIGNAL           = 0x0000000b,
22475 SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL     = 0x0000000c,
22476 SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL     = 0x0000000d,
22477 SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL     = 0x0000000e,
22478 SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL     = 0x0000000f,
22479 SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL     = 0x00000010,
22480 SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL     = 0x00000011,
22481 SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL     = 0x00000012,
22482 SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL     = 0x00000013,
22483 SEM_PERF_SEL_SDMA0_REQ_WAIT              = 0x00000014,
22484 SEM_PERF_SEL_SDMA1_REQ_WAIT              = 0x00000015,
22485 SEM_PERF_SEL_UVD_REQ_WAIT                = 0x00000016,
22486 SEM_PERF_SEL_VCE0_REQ_WAIT               = 0x00000017,
22487 SEM_PERF_SEL_ACP_REQ_WAIT                = 0x00000018,
22488 SEM_PERF_SEL_ISP_REQ_WAIT                = 0x00000019,
22489 SEM_PERF_SEL_VCE1_REQ_WAIT               = 0x0000001a,
22490 SEM_PERF_SEL_VP8_REQ_WAIT                = 0x0000001b,
22491 SEM_PERF_SEL_CPG_E0_REQ_WAIT             = 0x0000001c,
22492 SEM_PERF_SEL_CPG_E1_REQ_WAIT             = 0x0000001d,
22493 SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT       = 0x0000001e,
22494 SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT       = 0x0000001f,
22495 SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT       = 0x00000020,
22496 SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT       = 0x00000021,
22497 SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT       = 0x00000022,
22498 SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT       = 0x00000023,
22499 SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT       = 0x00000024,
22500 SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT       = 0x00000025,
22501 SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT       = 0x00000026,
22502 SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT       = 0x00000027,
22503 SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT       = 0x00000028,
22504 SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT       = 0x00000029,
22505 SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT       = 0x0000002a,
22506 SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT       = 0x0000002b,
22507 SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT       = 0x0000002c,
22508 SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT       = 0x0000002d,
22509 SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT       = 0x0000002e,
22510 SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT       = 0x0000002f,
22511 SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT      = 0x00000030,
22512 SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT      = 0x00000031,
22513 SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT      = 0x00000032,
22514 SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT      = 0x00000033,
22515 SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT      = 0x00000034,
22516 SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT      = 0x00000035,
22517 SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT      = 0x00000036,
22518 SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT      = 0x00000037,
22519 SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT      = 0x00000038,
22520 SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT      = 0x00000039,
22521 SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT      = 0x0000003a,
22522 SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT      = 0x0000003b,
22523 SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT      = 0x0000003c,
22524 SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT      = 0x0000003d,
22525 SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT      = 0x0000003e,
22526 SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT      = 0x0000003f,
22527 SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT      = 0x00000040,
22528 SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT      = 0x00000041,
22529 SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT      = 0x00000042,
22530 SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT      = 0x00000043,
22531 SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT      = 0x00000044,
22532 SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT      = 0x00000045,
22533 SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT       = 0x00000046,
22534 SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT       = 0x00000047,
22535 SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT       = 0x00000048,
22536 SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT       = 0x00000049,
22537 SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT       = 0x0000004a,
22538 SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT       = 0x0000004b,
22539 SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT       = 0x0000004c,
22540 SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT       = 0x0000004d,
22541 SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT       = 0x0000004e,
22542 SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT       = 0x0000004f,
22543 SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT      = 0x00000050,
22544 SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT      = 0x00000051,
22545 SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT      = 0x00000052,
22546 SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT      = 0x00000053,
22547 SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT      = 0x00000054,
22548 SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT      = 0x00000055,
22549 SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT      = 0x00000056,
22550 SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT      = 0x00000057,
22551 SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT      = 0x00000058,
22552 SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT      = 0x00000059,
22553 SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT      = 0x0000005a,
22554 SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT      = 0x0000005b,
22555 SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT      = 0x0000005c,
22556 SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT      = 0x0000005d,
22557 SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT      = 0x0000005e,
22558 SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT      = 0x0000005f,
22559 SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT      = 0x00000060,
22560 SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT      = 0x00000061,
22561 SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT      = 0x00000062,
22562 SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT      = 0x00000063,
22563 SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT      = 0x00000064,
22564 SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT      = 0x00000065,
22565 SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT      = 0x00000066,
22566 SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT      = 0x00000067,
22567 SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT      = 0x00000068,
22568 SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT      = 0x00000069,
22569 SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT      = 0x0000006a,
22570 SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT      = 0x0000006b,
22571 SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT      = 0x0000006c,
22572 SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT      = 0x0000006d,
22573 SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT      = 0x0000006e,
22574 SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT      = 0x0000006f,
22575 SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT     = 0x00000070,
22576 SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT     = 0x00000071,
22577 SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT     = 0x00000072,
22578 SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT     = 0x00000073,
22579 SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT     = 0x00000074,
22580 SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT     = 0x00000075,
22581 SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT     = 0x00000076,
22582 SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT     = 0x00000077,
22583 SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT     = 0x00000078,
22584 SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT     = 0x00000079,
22585 SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT     = 0x0000007a,
22586 SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT     = 0x0000007b,
22587 SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT     = 0x0000007c,
22588 SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT     = 0x0000007d,
22589 SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT     = 0x0000007e,
22590 SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT     = 0x0000007f,
22591 SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT     = 0x00000080,
22592 SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT     = 0x00000081,
22593 SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT     = 0x00000082,
22594 SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT     = 0x00000083,
22595 SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT     = 0x00000084,
22596 SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT     = 0x00000085,
22597 SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT      = 0x00000086,
22598 SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT      = 0x00000087,
22599 SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT      = 0x00000088,
22600 SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT      = 0x00000089,
22601 SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT      = 0x0000008a,
22602 SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT      = 0x0000008b,
22603 SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT      = 0x0000008c,
22604 SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT      = 0x0000008d,
22605 SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT      = 0x0000008e,
22606 SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT      = 0x0000008f,
22607 SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT     = 0x00000090,
22608 SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT     = 0x00000091,
22609 SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT     = 0x00000092,
22610 SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT     = 0x00000093,
22611 SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT     = 0x00000094,
22612 SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT     = 0x00000095,
22613 SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT     = 0x00000096,
22614 SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT     = 0x00000097,
22615 SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT     = 0x00000098,
22616 SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT     = 0x00000099,
22617 SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT     = 0x0000009a,
22618 SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT     = 0x0000009b,
22619 SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT     = 0x0000009c,
22620 SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT     = 0x0000009d,
22621 SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT     = 0x0000009e,
22622 SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT     = 0x0000009f,
22623 SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT     = 0x000000a0,
22624 SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT     = 0x000000a1,
22625 SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT     = 0x000000a2,
22626 SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT     = 0x000000a3,
22627 SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT     = 0x000000a4,
22628 SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT     = 0x000000a5,
22629 SEM_PERF_SEL_MC_RD_REQ                   = 0x000000a6,
22630 SEM_PERF_SEL_MC_RD_RET                   = 0x000000a7,
22631 SEM_PERF_SEL_MC_WR_REQ                   = 0x000000a8,
22632 SEM_PERF_SEL_MC_WR_RET                   = 0x000000a9,
22633 SEM_PERF_SEL_ATC_REQ                     = 0x000000aa,
22634 SEM_PERF_SEL_ATC_RET                     = 0x000000ab,
22635 SEM_PERF_SEL_ATC_XNACK                   = 0x000000ac,
22636 SEM_PERF_SEL_ATC_INVALIDATION            = 0x000000ad,
22637 SEM_PERF_SEL_ATC_VM_INVALIDATION         = 0x000000ae,
22638 } SEM_PERF_SEL;
22639 
22640 /*******************************************************
22641  * SMUIO Enums
22642  *******************************************************/
22643 
22644 /*
22645  * ROM_SIGNATURE value
22646  */
22647 
22648 #define ROM_SIGNATURE                  0x0000aa55
22649 
22650 /*******************************************************
22651  * UVD_EFC Enums
22652  *******************************************************/
22653 
22654 /*
22655  * EFC_SURFACE_PIXEL_FORMAT enum
22656  */
22657 
22658 typedef enum EFC_SURFACE_PIXEL_FORMAT {
22659 EFC_ARGB1555                             = 0x00000001,
22660 EFC_RGBA5551                             = 0x00000002,
22661 EFC_RGB565                               = 0x00000003,
22662 EFC_BGR565                               = 0x00000004,
22663 EFC_ARGB4444                             = 0x00000005,
22664 EFC_RGBA4444                             = 0x00000006,
22665 EFC_ARGB8888                             = 0x00000008,
22666 EFC_RGBA8888                             = 0x00000009,
22667 EFC_ARGB2101010                          = 0x0000000a,
22668 EFC_RGBA1010102                          = 0x0000000b,
22669 EFC_AYCrCb8888                           = 0x0000000c,
22670 EFC_YCrCbA8888                           = 0x0000000d,
22671 EFC_ACrYCb8888                           = 0x0000000e,
22672 EFC_CrYCbA8888                           = 0x0000000f,
22673 EFC_ARGB16161616_10MSB                   = 0x00000010,
22674 EFC_RGBA16161616_10MSB                   = 0x00000011,
22675 EFC_ARGB16161616_10LSB                   = 0x00000012,
22676 EFC_RGBA16161616_10LSB                   = 0x00000013,
22677 EFC_ARGB16161616_12MSB                   = 0x00000014,
22678 EFC_RGBA16161616_12MSB                   = 0x00000015,
22679 EFC_ARGB16161616_12LSB                   = 0x00000016,
22680 EFC_RGBA16161616_12LSB                   = 0x00000017,
22681 EFC_ARGB16161616_FLOAT                   = 0x00000018,
22682 EFC_RGBA16161616_FLOAT                   = 0x00000019,
22683 EFC_ARGB16161616_UNORM                   = 0x0000001a,
22684 EFC_RGBA16161616_UNORM                   = 0x0000001b,
22685 EFC_ARGB16161616_SNORM                   = 0x0000001c,
22686 EFC_RGBA16161616_SNORM                   = 0x0000001d,
22687 EFC_AYCrCb16161616_10MSB                 = 0x00000020,
22688 EFC_AYCrCb16161616_10LSB                 = 0x00000021,
22689 EFC_YCrCbA16161616_10MSB                 = 0x00000022,
22690 EFC_YCrCbA16161616_10LSB                 = 0x00000023,
22691 EFC_ACrYCb16161616_10MSB                 = 0x00000024,
22692 EFC_ACrYCb16161616_10LSB                 = 0x00000025,
22693 EFC_CrYCbA16161616_10MSB                 = 0x00000026,
22694 EFC_CrYCbA16161616_10LSB                 = 0x00000027,
22695 EFC_AYCrCb16161616_12MSB                 = 0x00000028,
22696 EFC_AYCrCb16161616_12LSB                 = 0x00000029,
22697 EFC_YCrCbA16161616_12MSB                 = 0x0000002a,
22698 EFC_YCrCbA16161616_12LSB                 = 0x0000002b,
22699 EFC_ACrYCb16161616_12MSB                 = 0x0000002c,
22700 EFC_ACrYCb16161616_12LSB                 = 0x0000002d,
22701 EFC_CrYCbA16161616_12MSB                 = 0x0000002e,
22702 EFC_CrYCbA16161616_12LSB                 = 0x0000002f,
22703 EFC_Y8_CrCb88_420_PLANAR                 = 0x00000040,
22704 EFC_Y8_CbCr88_420_PLANAR                 = 0x00000041,
22705 EFC_Y10_CrCb1010_420_PLANAR              = 0x00000042,
22706 EFC_Y10_CbCr1010_420_PLANAR              = 0x00000043,
22707 EFC_Y12_CrCb1212_420_PLANAR              = 0x00000044,
22708 EFC_Y12_CbCr1212_420_PLANAR              = 0x00000045,
22709 EFC_YCrYCb8888_422_PACKED                = 0x00000048,
22710 EFC_YCbYCr8888_422_PACKED                = 0x00000049,
22711 EFC_CrYCbY8888_422_PACKED                = 0x0000004a,
22712 EFC_CbYCrY8888_422_PACKED                = 0x0000004b,
22713 EFC_YCrYCb10101010_422_PACKED            = 0x0000004c,
22714 EFC_YCbYCr10101010_422_PACKED            = 0x0000004d,
22715 EFC_CrYCbY10101010_422_PACKED            = 0x0000004e,
22716 EFC_CbYCrY10101010_422_PACKED            = 0x0000004f,
22717 EFC_YCrYCb12121212_422_PACKED            = 0x00000050,
22718 EFC_YCbYCr12121212_422_PACKED            = 0x00000051,
22719 EFC_CrYCbY12121212_422_PACKED            = 0x00000052,
22720 EFC_CbYCrY12121212_422_PACKED            = 0x00000053,
22721 EFC_RGB111110_FIX                        = 0x00000070,
22722 EFC_BGR101111_FIX                        = 0x00000071,
22723 EFC_ACrYCb2101010                        = 0x00000072,
22724 EFC_CrYCbA1010102                        = 0x00000073,
22725 EFC_RGB111110_FLOAT                      = 0x00000076,
22726 EFC_BGR101111_FLOAT                      = 0x00000077,
22727 EFC_MONO_8                               = 0x00000078,
22728 EFC_MONO_10MSB                           = 0x00000079,
22729 EFC_MONO_10LSB                           = 0x0000007a,
22730 EFC_MONO_12MSB                           = 0x0000007b,
22731 EFC_MONO_12LSB                           = 0x0000007c,
22732 EFC_MONO_16                              = 0x0000007d,
22733 } EFC_SURFACE_PIXEL_FORMAT;
22734 
22735 /*******************************************************
22736  * UVD Enums
22737  *******************************************************/
22738 
22739 /*
22740  * UVDFirmwareCommand enum
22741  */
22742 
22743 typedef enum UVDFirmwareCommand {
22744 UVDFC_FENCE                              = 0x00000000,
22745 UVDFC_TRAP                               = 0x00000001,
22746 UVDFC_DECODED_ADDR                       = 0x00000002,
22747 UVDFC_MBLOCK_ADDR                        = 0x00000003,
22748 UVDFC_ITBUF_ADDR                         = 0x00000004,
22749 UVDFC_DISPLAY_ADDR                       = 0x00000005,
22750 UVDFC_EOD                                = 0x00000006,
22751 UVDFC_DISPLAY_PITCH                      = 0x00000007,
22752 UVDFC_DISPLAY_TILING                     = 0x00000008,
22753 UVDFC_BITSTREAM_ADDR                     = 0x00000009,
22754 UVDFC_BITSTREAM_SIZE                     = 0x0000000a,
22755 } UVDFirmwareCommand;
22756 
22757 /*******************************************************
22758  * I2C_4_ Enums
22759  *******************************************************/
22760 
22761 /*
22762  * REVISION_ID value
22763  */
22764 
22765 #define IP_USB_PD_REVISION_ID          0x00000000
22766 
22767 #endif /*_navi10_ENUM_HEADER*/
22768 
22769