xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/vega10_enum.h (revision e4a580baf2598beeaae98d953ac7635b8700b80c) 
1 /*	$NetBSD: vega10_enum.h,v 1.3 2021/12/19 10:59:02 riastradh Exp $	*/
2 
3 /*
4  * Copyright (C) 2017  Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included
14  * in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #if !defined (_vega10_ENUM_HEADER)
24 #define _vega10_ENUM_HEADER
25 
26 #ifndef _DRIVER_BUILD
27 #ifndef GL_ZERO
28 #define GL__ZERO                      BLEND_ZERO
29 #define GL__ONE                       BLEND_ONE
30 #define GL__SRC_COLOR                 BLEND_SRC_COLOR
31 #define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
32 #define GL__DST_COLOR                 BLEND_DST_COLOR
33 #define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
34 #define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
35 #define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
36 #define GL__DST_ALPHA                 BLEND_DST_ALPHA
37 #define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
38 #define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
39 #define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
40 #define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
41 #define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
42 #define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
43 #endif
44 #endif
45 
46 /*******************************************************
47  * GDS DATA_TYPE Enums
48  *******************************************************/
49 
50 #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
51 #define ENUMS_GDS_PERFCOUNT_SELECT_H
52 typedef enum GDS_PERFCOUNT_SELECT {
53  GDS_PERF_SEL_DS_ADDR_CONFL = 0,
54  GDS_PERF_SEL_DS_BANK_CONFL = 1,
55  GDS_PERF_SEL_WBUF_FLUSH = 2,
56  GDS_PERF_SEL_WR_COMP = 3,
57  GDS_PERF_SEL_WBUF_WR = 4,
58  GDS_PERF_SEL_RBUF_HIT = 5,
59  GDS_PERF_SEL_RBUF_MISS = 6,
60  GDS_PERF_SEL_SE0_SH0_NORET = 7,
61  GDS_PERF_SEL_SE0_SH0_RET = 8,
62  GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
63  GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
64  GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
65  GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
66  GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
67  GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
68  GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
69  GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
70  GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
71  GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
72  GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
73  GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
74  GDS_PERF_SEL_SE0_SH1_NORET = 21,
75  GDS_PERF_SEL_SE0_SH1_RET = 22,
76  GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
77  GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
78  GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
79  GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
80  GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
81  GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
82  GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
83  GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
84  GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
85  GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
86  GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
87  GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
88  GDS_PERF_SEL_SE1_SH0_NORET = 35,
89  GDS_PERF_SEL_SE1_SH0_RET = 36,
90  GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
91  GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
92  GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
93  GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
94  GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
95  GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
96  GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
97  GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
98  GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
99  GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
100  GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
101  GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
102  GDS_PERF_SEL_SE1_SH1_NORET = 49,
103  GDS_PERF_SEL_SE1_SH1_RET = 50,
104  GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
105  GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
106  GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
107  GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
108  GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
109  GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
110  GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
111  GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
112  GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
113  GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
114  GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
115  GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
116  GDS_PERF_SEL_SE2_SH0_NORET = 63,
117  GDS_PERF_SEL_SE2_SH0_RET = 64,
118  GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
119  GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
120  GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
121  GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
122  GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
123  GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
124  GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
125  GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
126  GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
127  GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
128  GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
129  GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
130  GDS_PERF_SEL_SE2_SH1_NORET = 77,
131  GDS_PERF_SEL_SE2_SH1_RET = 78,
132  GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
133  GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
134  GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
135  GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
136  GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
137  GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
138  GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
139  GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
140  GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
141  GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
142  GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
143  GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
144  GDS_PERF_SEL_SE3_SH0_NORET = 91,
145  GDS_PERF_SEL_SE3_SH0_RET = 92,
146  GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
147  GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
148  GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
149  GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
150  GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
151  GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
152  GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
153  GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
154  GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
155  GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
156  GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
157  GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
158  GDS_PERF_SEL_SE3_SH1_NORET = 105,
159  GDS_PERF_SEL_SE3_SH1_RET = 106,
160  GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
161  GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
162  GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
163  GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
164  GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
165  GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
166  GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
167  GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
168  GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
169  GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
170  GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
171  GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
172  GDS_PERF_SEL_GWS_RELEASED = 119,
173  GDS_PERF_SEL_GWS_BYPASS = 120,
174 } GDS_PERFCOUNT_SELECT;
175 #endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
176 
177 /*******************************************************
178  * Chip Enums
179  *******************************************************/
180 
181 /*
182  * MEM_PWR_FORCE_CTRL enum
183  */
184 
185 typedef enum MEM_PWR_FORCE_CTRL {
186 NO_FORCE_REQUEST                         = 0x00000000,
187 FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
188 FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
189 FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
190 } MEM_PWR_FORCE_CTRL;
191 
192 /*
193  * MEM_PWR_FORCE_CTRL2 enum
194  */
195 
196 typedef enum MEM_PWR_FORCE_CTRL2 {
197 NO_FORCE_REQ                             = 0x00000000,
198 FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
199 } MEM_PWR_FORCE_CTRL2;
200 
201 /*
202  * MEM_PWR_DIS_CTRL enum
203  */
204 
205 typedef enum MEM_PWR_DIS_CTRL {
206 ENABLE_MEM_PWR_CTRL                      = 0x00000000,
207 DISABLE_MEM_PWR_CTRL                     = 0x00000001,
208 } MEM_PWR_DIS_CTRL;
209 
210 /*
211  * MEM_PWR_SEL_CTRL enum
212  */
213 
214 typedef enum MEM_PWR_SEL_CTRL {
215 DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
216 DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
217 DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
218 } MEM_PWR_SEL_CTRL;
219 
220 /*
221  * MEM_PWR_SEL_CTRL2 enum
222  */
223 
224 typedef enum MEM_PWR_SEL_CTRL2 {
225 DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
226 DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
227 } MEM_PWR_SEL_CTRL2;
228 
229 /*
230  * RowSize enum
231  */
232 
233 typedef enum RowSize {
234 ADDR_CONFIG_1KB_ROW                      = 0x00000000,
235 ADDR_CONFIG_2KB_ROW                      = 0x00000001,
236 ADDR_CONFIG_4KB_ROW                      = 0x00000002,
237 } RowSize;
238 
239 /*
240  * SurfaceEndian enum
241  */
242 
243 typedef enum SurfaceEndian {
244 ENDIAN_NONE                              = 0x00000000,
245 ENDIAN_8IN16                             = 0x00000001,
246 ENDIAN_8IN32                             = 0x00000002,
247 ENDIAN_8IN64                             = 0x00000003,
248 } SurfaceEndian;
249 
250 /*
251  * ArrayMode enum
252  */
253 
254 typedef enum ArrayMode {
255 ARRAY_LINEAR_GENERAL                     = 0x00000000,
256 ARRAY_LINEAR_ALIGNED                     = 0x00000001,
257 ARRAY_1D_TILED_THIN1                     = 0x00000002,
258 ARRAY_1D_TILED_THICK                     = 0x00000003,
259 ARRAY_2D_TILED_THIN1                     = 0x00000004,
260 ARRAY_PRT_TILED_THIN1                    = 0x00000005,
261 ARRAY_PRT_2D_TILED_THIN1                 = 0x00000006,
262 ARRAY_2D_TILED_THICK                     = 0x00000007,
263 ARRAY_2D_TILED_XTHICK                    = 0x00000008,
264 ARRAY_PRT_TILED_THICK                    = 0x00000009,
265 ARRAY_PRT_2D_TILED_THICK                 = 0x0000000a,
266 ARRAY_PRT_3D_TILED_THIN1                 = 0x0000000b,
267 ARRAY_3D_TILED_THIN1                     = 0x0000000c,
268 ARRAY_3D_TILED_THICK                     = 0x0000000d,
269 ARRAY_3D_TILED_XTHICK                    = 0x0000000e,
270 ARRAY_PRT_3D_TILED_THICK                 = 0x0000000f,
271 } ArrayMode;
272 
273 /*
274  * NumPipes enum
275  */
276 
277 typedef enum NumPipes {
278 ADDR_CONFIG_1_PIPE                       = 0x00000000,
279 ADDR_CONFIG_2_PIPE                       = 0x00000001,
280 ADDR_CONFIG_4_PIPE                       = 0x00000002,
281 ADDR_CONFIG_8_PIPE                       = 0x00000003,
282 ADDR_CONFIG_16_PIPE                      = 0x00000004,
283 ADDR_CONFIG_32_PIPE                      = 0x00000005,
284 } NumPipes;
285 
286 /*
287  * NumBanksConfig enum
288  */
289 
290 typedef enum NumBanksConfig {
291 ADDR_CONFIG_1_BANK                       = 0x00000000,
292 ADDR_CONFIG_2_BANK                       = 0x00000001,
293 ADDR_CONFIG_4_BANK                       = 0x00000002,
294 ADDR_CONFIG_8_BANK                       = 0x00000003,
295 ADDR_CONFIG_16_BANK                      = 0x00000004,
296 } NumBanksConfig;
297 
298 /*
299  * PipeInterleaveSize enum
300  */
301 
302 typedef enum PipeInterleaveSize {
303 ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
304 ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
305 ADDR_CONFIG_PIPE_INTERLEAVE_1KB          = 0x00000002,
306 ADDR_CONFIG_PIPE_INTERLEAVE_2KB          = 0x00000003,
307 } PipeInterleaveSize;
308 
309 /*
310  * BankInterleaveSize enum
311  */
312 
313 typedef enum BankInterleaveSize {
314 ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
315 ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
316 ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
317 ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
318 } BankInterleaveSize;
319 
320 /*
321  * NumShaderEngines enum
322  */
323 
324 typedef enum NumShaderEngines {
325 ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
326 ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
327 ADDR_CONFIG_4_SHADER_ENGINE              = 0x00000002,
328 ADDR_CONFIG_8_SHADER_ENGINE              = 0x00000003,
329 } NumShaderEngines;
330 
331 /*
332  * NumRbPerShaderEngine enum
333  */
334 
335 typedef enum NumRbPerShaderEngine {
336 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE       = 0x00000000,
337 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE       = 0x00000001,
338 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE       = 0x00000002,
339 } NumRbPerShaderEngine;
340 
341 /*
342  * NumGPUs enum
343  */
344 
345 typedef enum NumGPUs {
346 ADDR_CONFIG_1_GPU                        = 0x00000000,
347 ADDR_CONFIG_2_GPU                        = 0x00000001,
348 ADDR_CONFIG_4_GPU                        = 0x00000002,
349 ADDR_CONFIG_8_GPU                        = 0x00000003,
350 } NumGPUs;
351 
352 /*
353  * NumMaxCompressedFragments enum
354  */
355 
356 typedef enum NumMaxCompressedFragments {
357 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS   = 0x00000000,
358 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS   = 0x00000001,
359 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS   = 0x00000002,
360 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS   = 0x00000003,
361 } NumMaxCompressedFragments;
362 
363 /*
364  * ShaderEngineTileSize enum
365  */
366 
367 typedef enum ShaderEngineTileSize {
368 ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
369 ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
370 } ShaderEngineTileSize;
371 
372 /*
373  * MultiGPUTileSize enum
374  */
375 
376 typedef enum MultiGPUTileSize {
377 ADDR_CONFIG_GPU_TILE_16                  = 0x00000000,
378 ADDR_CONFIG_GPU_TILE_32                  = 0x00000001,
379 ADDR_CONFIG_GPU_TILE_64                  = 0x00000002,
380 ADDR_CONFIG_GPU_TILE_128                 = 0x00000003,
381 } MultiGPUTileSize;
382 
383 /*
384  * NumLowerPipes enum
385  */
386 
387 typedef enum NumLowerPipes {
388 ADDR_CONFIG_1_LOWER_PIPES                = 0x00000000,
389 ADDR_CONFIG_2_LOWER_PIPES                = 0x00000001,
390 } NumLowerPipes;
391 
392 /*
393  * ColorTransform enum
394  */
395 
396 typedef enum ColorTransform {
397 DCC_CT_AUTO                              = 0x00000000,
398 DCC_CT_NONE                              = 0x00000001,
399 ABGR_TO_A_BG_G_RB                        = 0x00000002,
400 BGRA_TO_BG_G_RB_A                        = 0x00000003,
401 } ColorTransform;
402 
403 /*
404  * CompareRef enum
405  */
406 
407 typedef enum CompareRef {
408 REF_NEVER                                = 0x00000000,
409 REF_LESS                                 = 0x00000001,
410 REF_EQUAL                                = 0x00000002,
411 REF_LEQUAL                               = 0x00000003,
412 REF_GREATER                              = 0x00000004,
413 REF_NOTEQUAL                             = 0x00000005,
414 REF_GEQUAL                               = 0x00000006,
415 REF_ALWAYS                               = 0x00000007,
416 } CompareRef;
417 
418 /*
419  * ReadSize enum
420  */
421 
422 typedef enum ReadSize {
423 READ_256_BITS                            = 0x00000000,
424 READ_512_BITS                            = 0x00000001,
425 } ReadSize;
426 
427 /*
428  * DepthFormat enum
429  */
430 
431 typedef enum DepthFormat {
432 DEPTH_INVALID                            = 0x00000000,
433 DEPTH_16                                 = 0x00000001,
434 DEPTH_X8_24                              = 0x00000002,
435 DEPTH_8_24                               = 0x00000003,
436 DEPTH_X8_24_FLOAT                        = 0x00000004,
437 DEPTH_8_24_FLOAT                         = 0x00000005,
438 DEPTH_32_FLOAT                           = 0x00000006,
439 DEPTH_X24_8_32_FLOAT                     = 0x00000007,
440 } DepthFormat;
441 
442 /*
443  * ZFormat enum
444  */
445 
446 typedef enum ZFormat {
447 Z_INVALID                                = 0x00000000,
448 Z_16                                     = 0x00000001,
449 Z_24                                     = 0x00000002,
450 Z_32_FLOAT                               = 0x00000003,
451 } ZFormat;
452 
453 /*
454  * StencilFormat enum
455  */
456 
457 typedef enum StencilFormat {
458 STENCIL_INVALID                          = 0x00000000,
459 STENCIL_8                                = 0x00000001,
460 } StencilFormat;
461 
462 /*
463  * CmaskMode enum
464  */
465 
466 typedef enum CmaskMode {
467 CMASK_CLEAR_NONE                         = 0x00000000,
468 CMASK_CLEAR_ONE                          = 0x00000001,
469 CMASK_CLEAR_ALL                          = 0x00000002,
470 CMASK_ANY_EXPANDED                       = 0x00000003,
471 CMASK_ALPHA0_FRAG1                       = 0x00000004,
472 CMASK_ALPHA0_FRAG2                       = 0x00000005,
473 CMASK_ALPHA0_FRAG4                       = 0x00000006,
474 CMASK_ALPHA0_FRAGS                       = 0x00000007,
475 CMASK_ALPHA1_FRAG1                       = 0x00000008,
476 CMASK_ALPHA1_FRAG2                       = 0x00000009,
477 CMASK_ALPHA1_FRAG4                       = 0x0000000a,
478 CMASK_ALPHA1_FRAGS                       = 0x0000000b,
479 CMASK_ALPHAX_FRAG1                       = 0x0000000c,
480 CMASK_ALPHAX_FRAG2                       = 0x0000000d,
481 CMASK_ALPHAX_FRAG4                       = 0x0000000e,
482 CMASK_ALPHAX_FRAGS                       = 0x0000000f,
483 } CmaskMode;
484 
485 /*
486  * QuadExportFormat enum
487  */
488 
489 typedef enum QuadExportFormat {
490 EXPORT_UNUSED                            = 0x00000000,
491 EXPORT_32_R                              = 0x00000001,
492 EXPORT_32_GR                             = 0x00000002,
493 EXPORT_32_AR                             = 0x00000003,
494 EXPORT_FP16_ABGR                         = 0x00000004,
495 EXPORT_UNSIGNED16_ABGR                   = 0x00000005,
496 EXPORT_SIGNED16_ABGR                     = 0x00000006,
497 EXPORT_32_ABGR                           = 0x00000007,
498 EXPORT_32BPP_8PIX                        = 0x00000008,
499 EXPORT_16_16_UNSIGNED_8PIX               = 0x00000009,
500 EXPORT_16_16_SIGNED_8PIX                 = 0x0000000a,
501 EXPORT_16_16_FLOAT_8PIX                  = 0x0000000b,
502 } QuadExportFormat;
503 
504 /*
505  * QuadExportFormatOld enum
506  */
507 
508 typedef enum QuadExportFormatOld {
509 EXPORT_4P_32BPC_ABGR                     = 0x00000000,
510 EXPORT_4P_16BPC_ABGR                     = 0x00000001,
511 EXPORT_4P_32BPC_GR                       = 0x00000002,
512 EXPORT_4P_32BPC_AR                       = 0x00000003,
513 EXPORT_2P_32BPC_ABGR                     = 0x00000004,
514 EXPORT_8P_32BPC_R                        = 0x00000005,
515 } QuadExportFormatOld;
516 
517 /*
518  * ColorFormat enum
519  */
520 
521 typedef enum ColorFormat {
522 COLOR_INVALID                            = 0x00000000,
523 COLOR_8                                  = 0x00000001,
524 COLOR_16                                 = 0x00000002,
525 COLOR_8_8                                = 0x00000003,
526 COLOR_32                                 = 0x00000004,
527 COLOR_16_16                              = 0x00000005,
528 COLOR_10_11_11                           = 0x00000006,
529 COLOR_11_11_10                           = 0x00000007,
530 COLOR_10_10_10_2                         = 0x00000008,
531 COLOR_2_10_10_10                         = 0x00000009,
532 COLOR_8_8_8_8                            = 0x0000000a,
533 COLOR_32_32                              = 0x0000000b,
534 COLOR_16_16_16_16                        = 0x0000000c,
535 COLOR_RESERVED_13                        = 0x0000000d,
536 COLOR_32_32_32_32                        = 0x0000000e,
537 COLOR_RESERVED_15                        = 0x0000000f,
538 COLOR_5_6_5                              = 0x00000010,
539 COLOR_1_5_5_5                            = 0x00000011,
540 COLOR_5_5_5_1                            = 0x00000012,
541 COLOR_4_4_4_4                            = 0x00000013,
542 COLOR_8_24                               = 0x00000014,
543 COLOR_24_8                               = 0x00000015,
544 COLOR_X24_8_32_FLOAT                     = 0x00000016,
545 COLOR_RESERVED_23                        = 0x00000017,
546 COLOR_RESERVED_24                        = 0x00000018,
547 COLOR_RESERVED_25                        = 0x00000019,
548 COLOR_RESERVED_26                        = 0x0000001a,
549 COLOR_RESERVED_27                        = 0x0000001b,
550 COLOR_RESERVED_28                        = 0x0000001c,
551 COLOR_RESERVED_29                        = 0x0000001d,
552 COLOR_RESERVED_30                        = 0x0000001e,
553 COLOR_2_10_10_10_6E4                     = 0x0000001f,
554 } ColorFormat;
555 
556 /*
557  * SurfaceFormat enum
558  */
559 
560 typedef enum SurfaceFormat {
561 FMT_INVALID                              = 0x00000000,
562 FMT_8                                    = 0x00000001,
563 FMT_16                                   = 0x00000002,
564 FMT_8_8                                  = 0x00000003,
565 FMT_32                                   = 0x00000004,
566 FMT_16_16                                = 0x00000005,
567 FMT_10_11_11                             = 0x00000006,
568 FMT_11_11_10                             = 0x00000007,
569 FMT_10_10_10_2                           = 0x00000008,
570 FMT_2_10_10_10                           = 0x00000009,
571 FMT_8_8_8_8                              = 0x0000000a,
572 FMT_32_32                                = 0x0000000b,
573 FMT_16_16_16_16                          = 0x0000000c,
574 FMT_32_32_32                             = 0x0000000d,
575 FMT_32_32_32_32                          = 0x0000000e,
576 FMT_RESERVED_4                           = 0x0000000f,
577 FMT_5_6_5                                = 0x00000010,
578 FMT_1_5_5_5                              = 0x00000011,
579 FMT_5_5_5_1                              = 0x00000012,
580 FMT_4_4_4_4                              = 0x00000013,
581 FMT_8_24                                 = 0x00000014,
582 FMT_24_8                                 = 0x00000015,
583 FMT_X24_8_32_FLOAT                       = 0x00000016,
584 FMT_RESERVED_33                          = 0x00000017,
585 FMT_11_11_10_FLOAT                       = 0x00000018,
586 FMT_16_FLOAT                             = 0x00000019,
587 FMT_32_FLOAT                             = 0x0000001a,
588 FMT_16_16_FLOAT                          = 0x0000001b,
589 FMT_8_24_FLOAT                           = 0x0000001c,
590 FMT_24_8_FLOAT                           = 0x0000001d,
591 FMT_32_32_FLOAT                          = 0x0000001e,
592 FMT_10_11_11_FLOAT                       = 0x0000001f,
593 FMT_16_16_16_16_FLOAT                    = 0x00000020,
594 FMT_3_3_2                                = 0x00000021,
595 FMT_6_5_5                                = 0x00000022,
596 FMT_32_32_32_32_FLOAT                    = 0x00000023,
597 FMT_RESERVED_36                          = 0x00000024,
598 FMT_1                                    = 0x00000025,
599 FMT_1_REVERSED                           = 0x00000026,
600 FMT_GB_GR                                = 0x00000027,
601 FMT_BG_RG                                = 0x00000028,
602 FMT_32_AS_8                              = 0x00000029,
603 FMT_32_AS_8_8                            = 0x0000002a,
604 FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
605 FMT_8_8_8                                = 0x0000002c,
606 FMT_16_16_16                             = 0x0000002d,
607 FMT_16_16_16_FLOAT                       = 0x0000002e,
608 FMT_4_4                                  = 0x0000002f,
609 FMT_32_32_32_FLOAT                       = 0x00000030,
610 FMT_BC1                                  = 0x00000031,
611 FMT_BC2                                  = 0x00000032,
612 FMT_BC3                                  = 0x00000033,
613 FMT_BC4                                  = 0x00000034,
614 FMT_BC5                                  = 0x00000035,
615 FMT_BC6                                  = 0x00000036,
616 FMT_BC7                                  = 0x00000037,
617 FMT_32_AS_32_32_32_32                    = 0x00000038,
618 FMT_APC3                                 = 0x00000039,
619 FMT_APC4                                 = 0x0000003a,
620 FMT_APC5                                 = 0x0000003b,
621 FMT_APC6                                 = 0x0000003c,
622 FMT_APC7                                 = 0x0000003d,
623 FMT_CTX1                                 = 0x0000003e,
624 FMT_RESERVED_63                          = 0x0000003f,
625 } SurfaceFormat;
626 
627 /*
628  * BUF_DATA_FORMAT enum
629  */
630 
631 typedef enum BUF_DATA_FORMAT {
632 BUF_DATA_FORMAT_INVALID                  = 0x00000000,
633 BUF_DATA_FORMAT_8                        = 0x00000001,
634 BUF_DATA_FORMAT_16                       = 0x00000002,
635 BUF_DATA_FORMAT_8_8                      = 0x00000003,
636 BUF_DATA_FORMAT_32                       = 0x00000004,
637 BUF_DATA_FORMAT_16_16                    = 0x00000005,
638 BUF_DATA_FORMAT_10_11_11                 = 0x00000006,
639 BUF_DATA_FORMAT_11_11_10                 = 0x00000007,
640 BUF_DATA_FORMAT_10_10_10_2               = 0x00000008,
641 BUF_DATA_FORMAT_2_10_10_10               = 0x00000009,
642 BUF_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
643 BUF_DATA_FORMAT_32_32                    = 0x0000000b,
644 BUF_DATA_FORMAT_16_16_16_16              = 0x0000000c,
645 BUF_DATA_FORMAT_32_32_32                 = 0x0000000d,
646 BUF_DATA_FORMAT_32_32_32_32              = 0x0000000e,
647 BUF_DATA_FORMAT_RESERVED_15              = 0x0000000f,
648 } BUF_DATA_FORMAT;
649 
650 /*
651  * IMG_DATA_FORMAT enum
652  */
653 
654 typedef enum IMG_DATA_FORMAT {
655 IMG_DATA_FORMAT_INVALID                  = 0x00000000,
656 IMG_DATA_FORMAT_8                        = 0x00000001,
657 IMG_DATA_FORMAT_16                       = 0x00000002,
658 IMG_DATA_FORMAT_8_8                      = 0x00000003,
659 IMG_DATA_FORMAT_32                       = 0x00000004,
660 IMG_DATA_FORMAT_16_16                    = 0x00000005,
661 IMG_DATA_FORMAT_10_11_11                 = 0x00000006,
662 IMG_DATA_FORMAT_11_11_10                 = 0x00000007,
663 IMG_DATA_FORMAT_10_10_10_2               = 0x00000008,
664 IMG_DATA_FORMAT_2_10_10_10               = 0x00000009,
665 IMG_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
666 IMG_DATA_FORMAT_32_32                    = 0x0000000b,
667 IMG_DATA_FORMAT_16_16_16_16              = 0x0000000c,
668 IMG_DATA_FORMAT_32_32_32                 = 0x0000000d,
669 IMG_DATA_FORMAT_32_32_32_32              = 0x0000000e,
670 IMG_DATA_FORMAT_RESERVED_15              = 0x0000000f,
671 IMG_DATA_FORMAT_5_6_5                    = 0x00000010,
672 IMG_DATA_FORMAT_1_5_5_5                  = 0x00000011,
673 IMG_DATA_FORMAT_5_5_5_1                  = 0x00000012,
674 IMG_DATA_FORMAT_4_4_4_4                  = 0x00000013,
675 IMG_DATA_FORMAT_8_24                     = 0x00000014,
676 IMG_DATA_FORMAT_24_8                     = 0x00000015,
677 IMG_DATA_FORMAT_X24_8_32                 = 0x00000016,
678 IMG_DATA_FORMAT_8_AS_8_8_8_8             = 0x00000017,
679 IMG_DATA_FORMAT_ETC2_RGB                 = 0x00000018,
680 IMG_DATA_FORMAT_ETC2_RGBA                = 0x00000019,
681 IMG_DATA_FORMAT_ETC2_R                   = 0x0000001a,
682 IMG_DATA_FORMAT_ETC2_RG                  = 0x0000001b,
683 IMG_DATA_FORMAT_ETC2_RGBA1               = 0x0000001c,
684 IMG_DATA_FORMAT_RESERVED_29              = 0x0000001d,
685 IMG_DATA_FORMAT_RESERVED_30              = 0x0000001e,
686 IMG_DATA_FORMAT_6E4                      = 0x0000001f,
687 IMG_DATA_FORMAT_GB_GR                    = 0x00000020,
688 IMG_DATA_FORMAT_BG_RG                    = 0x00000021,
689 IMG_DATA_FORMAT_5_9_9_9                  = 0x00000022,
690 IMG_DATA_FORMAT_BC1                      = 0x00000023,
691 IMG_DATA_FORMAT_BC2                      = 0x00000024,
692 IMG_DATA_FORMAT_BC3                      = 0x00000025,
693 IMG_DATA_FORMAT_BC4                      = 0x00000026,
694 IMG_DATA_FORMAT_BC5                      = 0x00000027,
695 IMG_DATA_FORMAT_BC6                      = 0x00000028,
696 IMG_DATA_FORMAT_BC7                      = 0x00000029,
697 IMG_DATA_FORMAT_16_AS_32_32              = 0x0000002a,
698 IMG_DATA_FORMAT_16_AS_16_16_16_16        = 0x0000002b,
699 IMG_DATA_FORMAT_16_AS_32_32_32_32        = 0x0000002c,
700 IMG_DATA_FORMAT_FMASK                    = 0x0000002d,
701 IMG_DATA_FORMAT_ASTC_2D_LDR              = 0x0000002e,
702 IMG_DATA_FORMAT_ASTC_2D_HDR              = 0x0000002f,
703 IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB         = 0x00000030,
704 IMG_DATA_FORMAT_ASTC_3D_LDR              = 0x00000031,
705 IMG_DATA_FORMAT_ASTC_3D_HDR              = 0x00000032,
706 IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB         = 0x00000033,
707 IMG_DATA_FORMAT_N_IN_16                  = 0x00000034,
708 IMG_DATA_FORMAT_N_IN_16_16               = 0x00000035,
709 IMG_DATA_FORMAT_N_IN_16_16_16_16         = 0x00000036,
710 IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16   = 0x00000037,
711 IMG_DATA_FORMAT_RESERVED_56              = 0x00000038,
712 IMG_DATA_FORMAT_4_4                      = 0x00000039,
713 IMG_DATA_FORMAT_6_5_5                    = 0x0000003a,
714 IMG_DATA_FORMAT_RESERVED_59              = 0x0000003b,
715 IMG_DATA_FORMAT_RESERVED_60              = 0x0000003c,
716 IMG_DATA_FORMAT_8_AS_32                  = 0x0000003d,
717 IMG_DATA_FORMAT_8_AS_32_32               = 0x0000003e,
718 IMG_DATA_FORMAT_32_AS_32_32_32_32        = 0x0000003f,
719 } IMG_DATA_FORMAT;
720 
721 /*
722  * BUF_NUM_FORMAT enum
723  */
724 
725 typedef enum BUF_NUM_FORMAT {
726 BUF_NUM_FORMAT_UNORM                     = 0x00000000,
727 BUF_NUM_FORMAT_SNORM                     = 0x00000001,
728 BUF_NUM_FORMAT_USCALED                   = 0x00000002,
729 BUF_NUM_FORMAT_SSCALED                   = 0x00000003,
730 BUF_NUM_FORMAT_UINT                      = 0x00000004,
731 BUF_NUM_FORMAT_SINT                      = 0x00000005,
732 BUF_NUM_FORMAT_UNORM_UINT                = 0x00000006,
733 BUF_NUM_FORMAT_FLOAT                     = 0x00000007,
734 } BUF_NUM_FORMAT;
735 
736 /*
737  * IMG_NUM_FORMAT enum
738  */
739 
740 typedef enum IMG_NUM_FORMAT {
741 IMG_NUM_FORMAT_UNORM                     = 0x00000000,
742 IMG_NUM_FORMAT_SNORM                     = 0x00000001,
743 IMG_NUM_FORMAT_USCALED                   = 0x00000002,
744 IMG_NUM_FORMAT_SSCALED                   = 0x00000003,
745 IMG_NUM_FORMAT_UINT                      = 0x00000004,
746 IMG_NUM_FORMAT_SINT                      = 0x00000005,
747 IMG_NUM_FORMAT_UNORM_UINT                = 0x00000006,
748 IMG_NUM_FORMAT_FLOAT                     = 0x00000007,
749 IMG_NUM_FORMAT_RESERVED_8                = 0x00000008,
750 IMG_NUM_FORMAT_SRGB                      = 0x00000009,
751 IMG_NUM_FORMAT_RESERVED_10               = 0x0000000a,
752 IMG_NUM_FORMAT_RESERVED_11               = 0x0000000b,
753 IMG_NUM_FORMAT_RESERVED_12               = 0x0000000c,
754 IMG_NUM_FORMAT_RESERVED_13               = 0x0000000d,
755 IMG_NUM_FORMAT_RESERVED_14               = 0x0000000e,
756 IMG_NUM_FORMAT_RESERVED_15               = 0x0000000f,
757 } IMG_NUM_FORMAT;
758 
759 /*
760  * IMG_NUM_FORMAT_FMASK enum
761  */
762 
763 typedef enum IMG_NUM_FORMAT_FMASK {
764 IMG_NUM_FORMAT_FMASK_8_2_1               = 0x00000000,
765 IMG_NUM_FORMAT_FMASK_8_4_1               = 0x00000001,
766 IMG_NUM_FORMAT_FMASK_8_8_1               = 0x00000002,
767 IMG_NUM_FORMAT_FMASK_8_2_2               = 0x00000003,
768 IMG_NUM_FORMAT_FMASK_8_4_2               = 0x00000004,
769 IMG_NUM_FORMAT_FMASK_8_4_4               = 0x00000005,
770 IMG_NUM_FORMAT_FMASK_16_16_1             = 0x00000006,
771 IMG_NUM_FORMAT_FMASK_16_8_2              = 0x00000007,
772 IMG_NUM_FORMAT_FMASK_32_16_2             = 0x00000008,
773 IMG_NUM_FORMAT_FMASK_32_8_4              = 0x00000009,
774 IMG_NUM_FORMAT_FMASK_32_8_8              = 0x0000000a,
775 IMG_NUM_FORMAT_FMASK_64_16_4             = 0x0000000b,
776 IMG_NUM_FORMAT_FMASK_64_16_8             = 0x0000000c,
777 IMG_NUM_FORMAT_FMASK_RESERVED_13         = 0x0000000d,
778 IMG_NUM_FORMAT_FMASK_RESERVED_14         = 0x0000000e,
779 IMG_NUM_FORMAT_FMASK_RESERVED_15         = 0x0000000f,
780 } IMG_NUM_FORMAT_FMASK;
781 
782 /*
783  * IMG_NUM_FORMAT_N_IN_16 enum
784  */
785 
786 typedef enum IMG_NUM_FORMAT_N_IN_16 {
787 IMG_NUM_FORMAT_N_IN_16_RESERVED_0        = 0x00000000,
788 IMG_NUM_FORMAT_N_IN_16_UNORM_10          = 0x00000001,
789 IMG_NUM_FORMAT_N_IN_16_UNORM_9           = 0x00000002,
790 IMG_NUM_FORMAT_N_IN_16_RESERVED_3        = 0x00000003,
791 IMG_NUM_FORMAT_N_IN_16_UINT_10           = 0x00000004,
792 IMG_NUM_FORMAT_N_IN_16_UINT_9            = 0x00000005,
793 IMG_NUM_FORMAT_N_IN_16_RESERVED_6        = 0x00000006,
794 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10     = 0x00000007,
795 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9      = 0x00000008,
796 IMG_NUM_FORMAT_N_IN_16_RESERVED_9        = 0x00000009,
797 IMG_NUM_FORMAT_N_IN_16_RESERVED_10       = 0x0000000a,
798 IMG_NUM_FORMAT_N_IN_16_RESERVED_11       = 0x0000000b,
799 IMG_NUM_FORMAT_N_IN_16_RESERVED_12       = 0x0000000c,
800 IMG_NUM_FORMAT_N_IN_16_RESERVED_13       = 0x0000000d,
801 IMG_NUM_FORMAT_N_IN_16_RESERVED_14       = 0x0000000e,
802 IMG_NUM_FORMAT_N_IN_16_RESERVED_15       = 0x0000000f,
803 } IMG_NUM_FORMAT_N_IN_16;
804 
805 /*
806  * IMG_NUM_FORMAT_ASTC_2D enum
807  */
808 
809 typedef enum IMG_NUM_FORMAT_ASTC_2D {
810 IMG_NUM_FORMAT_ASTC_2D_4x4               = 0x00000000,
811 IMG_NUM_FORMAT_ASTC_2D_5x4               = 0x00000001,
812 IMG_NUM_FORMAT_ASTC_2D_5x5               = 0x00000002,
813 IMG_NUM_FORMAT_ASTC_2D_6x5               = 0x00000003,
814 IMG_NUM_FORMAT_ASTC_2D_6x6               = 0x00000004,
815 IMG_NUM_FORMAT_ASTC_2D_8x5               = 0x00000005,
816 IMG_NUM_FORMAT_ASTC_2D_8x6               = 0x00000006,
817 IMG_NUM_FORMAT_ASTC_2D_8x8               = 0x00000007,
818 IMG_NUM_FORMAT_ASTC_2D_10x5              = 0x00000008,
819 IMG_NUM_FORMAT_ASTC_2D_10x6              = 0x00000009,
820 IMG_NUM_FORMAT_ASTC_2D_10x8              = 0x0000000a,
821 IMG_NUM_FORMAT_ASTC_2D_10x10             = 0x0000000b,
822 IMG_NUM_FORMAT_ASTC_2D_12x10             = 0x0000000c,
823 IMG_NUM_FORMAT_ASTC_2D_12x12             = 0x0000000d,
824 IMG_NUM_FORMAT_ASTC_2D_RESERVED_14       = 0x0000000e,
825 IMG_NUM_FORMAT_ASTC_2D_RESERVED_15       = 0x0000000f,
826 } IMG_NUM_FORMAT_ASTC_2D;
827 
828 /*
829  * IMG_NUM_FORMAT_ASTC_3D enum
830  */
831 
832 typedef enum IMG_NUM_FORMAT_ASTC_3D {
833 IMG_NUM_FORMAT_ASTC_3D_3x3x3             = 0x00000000,
834 IMG_NUM_FORMAT_ASTC_3D_4x3x3             = 0x00000001,
835 IMG_NUM_FORMAT_ASTC_3D_4x4x3             = 0x00000002,
836 IMG_NUM_FORMAT_ASTC_3D_4x4x4             = 0x00000003,
837 IMG_NUM_FORMAT_ASTC_3D_5x4x4             = 0x00000004,
838 IMG_NUM_FORMAT_ASTC_3D_5x5x4             = 0x00000005,
839 IMG_NUM_FORMAT_ASTC_3D_5x5x5             = 0x00000006,
840 IMG_NUM_FORMAT_ASTC_3D_6x5x5             = 0x00000007,
841 IMG_NUM_FORMAT_ASTC_3D_6x6x5             = 0x00000008,
842 IMG_NUM_FORMAT_ASTC_3D_6x6x6             = 0x00000009,
843 IMG_NUM_FORMAT_ASTC_3D_RESERVED_10       = 0x0000000a,
844 IMG_NUM_FORMAT_ASTC_3D_RESERVED_11       = 0x0000000b,
845 IMG_NUM_FORMAT_ASTC_3D_RESERVED_12       = 0x0000000c,
846 IMG_NUM_FORMAT_ASTC_3D_RESERVED_13       = 0x0000000d,
847 IMG_NUM_FORMAT_ASTC_3D_RESERVED_14       = 0x0000000e,
848 IMG_NUM_FORMAT_ASTC_3D_RESERVED_15       = 0x0000000f,
849 } IMG_NUM_FORMAT_ASTC_3D;
850 
851 /*
852  * TileType enum
853  */
854 
855 typedef enum TileType {
856 ARRAY_COLOR_TILE                         = 0x00000000,
857 ARRAY_DEPTH_TILE                         = 0x00000001,
858 } TileType;
859 
860 /*
861  * NonDispTilingOrder enum
862  */
863 
864 typedef enum NonDispTilingOrder {
865 ADDR_SURF_MICRO_TILING_DISPLAY           = 0x00000000,
866 ADDR_SURF_MICRO_TILING_NON_DISPLAY       = 0x00000001,
867 } NonDispTilingOrder;
868 
869 /*
870  * MicroTileMode enum
871  */
872 
873 typedef enum MicroTileMode {
874 ADDR_SURF_DISPLAY_MICRO_TILING           = 0x00000000,
875 ADDR_SURF_THIN_MICRO_TILING              = 0x00000001,
876 ADDR_SURF_DEPTH_MICRO_TILING             = 0x00000002,
877 ADDR_SURF_ROTATED_MICRO_TILING           = 0x00000003,
878 ADDR_SURF_THICK_MICRO_TILING             = 0x00000004,
879 } MicroTileMode;
880 
881 /*
882  * TileSplit enum
883  */
884 
885 typedef enum TileSplit {
886 ADDR_SURF_TILE_SPLIT_64B                 = 0x00000000,
887 ADDR_SURF_TILE_SPLIT_128B                = 0x00000001,
888 ADDR_SURF_TILE_SPLIT_256B                = 0x00000002,
889 ADDR_SURF_TILE_SPLIT_512B                = 0x00000003,
890 ADDR_SURF_TILE_SPLIT_1KB                 = 0x00000004,
891 ADDR_SURF_TILE_SPLIT_2KB                 = 0x00000005,
892 ADDR_SURF_TILE_SPLIT_4KB                 = 0x00000006,
893 } TileSplit;
894 
895 /*
896  * SampleSplit enum
897  */
898 
899 typedef enum SampleSplit {
900 ADDR_SURF_SAMPLE_SPLIT_1                 = 0x00000000,
901 ADDR_SURF_SAMPLE_SPLIT_2                 = 0x00000001,
902 ADDR_SURF_SAMPLE_SPLIT_4                 = 0x00000002,
903 ADDR_SURF_SAMPLE_SPLIT_8                 = 0x00000003,
904 } SampleSplit;
905 
906 /*
907  * PipeConfig enum
908  */
909 
910 typedef enum PipeConfig {
911 ADDR_SURF_P2                             = 0x00000000,
912 ADDR_SURF_P2_RESERVED0                   = 0x00000001,
913 ADDR_SURF_P2_RESERVED1                   = 0x00000002,
914 ADDR_SURF_P2_RESERVED2                   = 0x00000003,
915 ADDR_SURF_P4_8x16                        = 0x00000004,
916 ADDR_SURF_P4_16x16                       = 0x00000005,
917 ADDR_SURF_P4_16x32                       = 0x00000006,
918 ADDR_SURF_P4_32x32                       = 0x00000007,
919 ADDR_SURF_P8_16x16_8x16                  = 0x00000008,
920 ADDR_SURF_P8_16x32_8x16                  = 0x00000009,
921 ADDR_SURF_P8_32x32_8x16                  = 0x0000000a,
922 ADDR_SURF_P8_16x32_16x16                 = 0x0000000b,
923 ADDR_SURF_P8_32x32_16x16                 = 0x0000000c,
924 ADDR_SURF_P8_32x32_16x32                 = 0x0000000d,
925 ADDR_SURF_P8_32x64_32x32                 = 0x0000000e,
926 ADDR_SURF_P8_RESERVED0                   = 0x0000000f,
927 ADDR_SURF_P16_32x32_8x16                 = 0x00000010,
928 ADDR_SURF_P16_32x32_16x16                = 0x00000011,
929 } PipeConfig;
930 
931 /*
932  * SeEnable enum
933  */
934 
935 typedef enum SeEnable {
936 ADDR_CONFIG_DISABLE_SE                   = 0x00000000,
937 ADDR_CONFIG_ENABLE_SE                    = 0x00000001,
938 } SeEnable;
939 
940 /*
941  * NumBanks enum
942  */
943 
944 typedef enum NumBanks {
945 ADDR_SURF_2_BANK                         = 0x00000000,
946 ADDR_SURF_4_BANK                         = 0x00000001,
947 ADDR_SURF_8_BANK                         = 0x00000002,
948 ADDR_SURF_16_BANK                        = 0x00000003,
949 } NumBanks;
950 
951 /*
952  * BankWidth enum
953  */
954 
955 typedef enum BankWidth {
956 ADDR_SURF_BANK_WIDTH_1                   = 0x00000000,
957 ADDR_SURF_BANK_WIDTH_2                   = 0x00000001,
958 ADDR_SURF_BANK_WIDTH_4                   = 0x00000002,
959 ADDR_SURF_BANK_WIDTH_8                   = 0x00000003,
960 } BankWidth;
961 
962 /*
963  * BankHeight enum
964  */
965 
966 typedef enum BankHeight {
967 ADDR_SURF_BANK_HEIGHT_1                  = 0x00000000,
968 ADDR_SURF_BANK_HEIGHT_2                  = 0x00000001,
969 ADDR_SURF_BANK_HEIGHT_4                  = 0x00000002,
970 ADDR_SURF_BANK_HEIGHT_8                  = 0x00000003,
971 } BankHeight;
972 
973 /*
974  * BankWidthHeight enum
975  */
976 
977 typedef enum BankWidthHeight {
978 ADDR_SURF_BANK_WH_1                      = 0x00000000,
979 ADDR_SURF_BANK_WH_2                      = 0x00000001,
980 ADDR_SURF_BANK_WH_4                      = 0x00000002,
981 ADDR_SURF_BANK_WH_8                      = 0x00000003,
982 } BankWidthHeight;
983 
984 /*
985  * MacroTileAspect enum
986  */
987 
988 typedef enum MacroTileAspect {
989 ADDR_SURF_MACRO_ASPECT_1                 = 0x00000000,
990 ADDR_SURF_MACRO_ASPECT_2                 = 0x00000001,
991 ADDR_SURF_MACRO_ASPECT_4                 = 0x00000002,
992 ADDR_SURF_MACRO_ASPECT_8                 = 0x00000003,
993 } MacroTileAspect;
994 
995 /*
996  * GATCL1RequestType enum
997  */
998 
999 typedef enum GATCL1RequestType {
1000 GATCL1_TYPE_NORMAL                       = 0x00000000,
1001 GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
1002 GATCL1_TYPE_BYPASS                       = 0x00000002,
1003 } GATCL1RequestType;
1004 
1005 /*
1006  * UTCL1RequestType enum
1007  */
1008 
1009 typedef enum UTCL1RequestType {
1010 UTCL1_TYPE_NORMAL                        = 0x00000000,
1011 UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
1012 UTCL1_TYPE_BYPASS                        = 0x00000002,
1013 } UTCL1RequestType;
1014 
1015 /*
1016  * UTCL1FaultType enum
1017  */
1018 
1019 typedef enum UTCL1FaultType {
1020 UTCL1_XNACK_SUCCESS                      = 0x00000000,
1021 UTCL1_XNACK_RETRY                        = 0x00000001,
1022 UTCL1_XNACK_PRT                          = 0x00000002,
1023 UTCL1_XNACK_NO_RETRY                     = 0x00000003,
1024 } UTCL1FaultType;
1025 
1026 /*
1027  * TCC_CACHE_POLICIES enum
1028  */
1029 
1030 typedef enum TCC_CACHE_POLICIES {
1031 TCC_CACHE_POLICY_LRU                     = 0x00000000,
1032 TCC_CACHE_POLICY_STREAM                  = 0x00000001,
1033 } TCC_CACHE_POLICIES;
1034 
1035 /*
1036  * MTYPE enum
1037  */
1038 
1039 typedef enum MTYPE {
1040 MTYPE_NC                                 = 0x00000000,
1041 MTYPE_WC                                 = 0x00000001,
1042 MTYPE_RW                                 = 0x00000001,
1043 MTYPE_CC                                 = 0x00000002,
1044 MTYPE_UC                                 = 0x00000003,
1045 } MTYPE;
1046 
1047 /*
1048  * RMI_CID enum
1049  */
1050 
1051 typedef enum RMI_CID {
1052 RMI_CID_CC                               = 0x00000000,
1053 RMI_CID_FC                               = 0x00000001,
1054 RMI_CID_CM                               = 0x00000002,
1055 RMI_CID_DC                               = 0x00000003,
1056 RMI_CID_Z                                = 0x00000004,
1057 RMI_CID_S                                = 0x00000005,
1058 RMI_CID_TILE                             = 0x00000006,
1059 RMI_CID_ZPCPSD                           = 0x00000007,
1060 } RMI_CID;
1061 
1062 /*
1063  * PERFMON_COUNTER_MODE enum
1064  */
1065 
1066 typedef enum PERFMON_COUNTER_MODE {
1067 PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
1068 PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
1069 PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
1070 PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
1071 PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
1072 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT  = 0x00000005,
1073 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT  = 0x00000006,
1074 PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
1075 PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
1076 PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
1077 PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
1078 } PERFMON_COUNTER_MODE;
1079 
1080 /*
1081  * PERFMON_SPM_MODE enum
1082  */
1083 
1084 typedef enum PERFMON_SPM_MODE {
1085 PERFMON_SPM_MODE_OFF                     = 0x00000000,
1086 PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
1087 PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
1088 PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
1089 PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
1090 PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
1091 PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
1092 PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
1093 PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
1094 PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
1095 PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
1096 } PERFMON_SPM_MODE;
1097 
1098 /*
1099  * SurfaceTiling enum
1100  */
1101 
1102 typedef enum SurfaceTiling {
1103 ARRAY_LINEAR                             = 0x00000000,
1104 ARRAY_TILED                              = 0x00000001,
1105 } SurfaceTiling;
1106 
1107 /*
1108  * SurfaceArray enum
1109  */
1110 
1111 typedef enum SurfaceArray {
1112 ARRAY_1D                                 = 0x00000000,
1113 ARRAY_2D                                 = 0x00000001,
1114 ARRAY_3D                                 = 0x00000002,
1115 ARRAY_3D_SLICE                           = 0x00000003,
1116 } SurfaceArray;
1117 
1118 /*
1119  * ColorArray enum
1120  */
1121 
1122 typedef enum ColorArray {
1123 ARRAY_2D_ALT_COLOR                       = 0x00000000,
1124 ARRAY_2D_COLOR                           = 0x00000001,
1125 ARRAY_3D_SLICE_COLOR                     = 0x00000003,
1126 } ColorArray;
1127 
1128 /*
1129  * DepthArray enum
1130  */
1131 
1132 typedef enum DepthArray {
1133 ARRAY_2D_ALT_DEPTH                       = 0x00000000,
1134 ARRAY_2D_DEPTH                           = 0x00000001,
1135 } DepthArray;
1136 
1137 /*
1138  * ENUM_NUM_SIMD_PER_CU enum
1139  */
1140 
1141 typedef enum ENUM_NUM_SIMD_PER_CU {
1142 NUM_SIMD_PER_CU                          = 0x00000004,
1143 } ENUM_NUM_SIMD_PER_CU;
1144 
1145 /*
1146  * DSM_ENABLE_ERROR_INJECT enum
1147  */
1148 
1149 typedef enum DSM_ENABLE_ERROR_INJECT {
1150 DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,
1151 DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,
1152 DSM_ENABLE_ERROR_INJECT_DOUBLE           = 0x00000002,
1153 DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED   = 0x00000003,
1154 } DSM_ENABLE_ERROR_INJECT;
1155 
1156 /*
1157  * DSM_SELECT_INJECT_DELAY enum
1158  */
1159 
1160 typedef enum DSM_SELECT_INJECT_DELAY {
1161 DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,
1162 DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,
1163 } DSM_SELECT_INJECT_DELAY;
1164 
1165 /*
1166  * SWIZZLE_TYPE_ENUM enum
1167  */
1168 
1169 typedef enum SWIZZLE_TYPE_ENUM {
1170 SW_Z                                     = 0x00000000,
1171 SW_S                                     = 0x00000001,
1172 SW_D                                     = 0x00000002,
1173 SW_R                                     = 0x00000003,
1174 SW_L                                     = 0x00000004,
1175 } SWIZZLE_TYPE_ENUM;
1176 
1177 /*
1178  * TC_MICRO_TILE_MODE enum
1179  */
1180 
1181 typedef enum TC_MICRO_TILE_MODE {
1182 MICRO_TILE_MODE_LINEAR                   = 0x00000000,
1183 MICRO_TILE_MODE_ROTATED                  = 0x00000001,
1184 MICRO_TILE_MODE_STD_2D                   = 0x00000002,
1185 MICRO_TILE_MODE_STD_3D                   = 0x00000003,
1186 MICRO_TILE_MODE_DISPLAY_2D               = 0x00000004,
1187 MICRO_TILE_MODE_DISPLAY_3D               = 0x00000005,
1188 MICRO_TILE_MODE_Z_2D                     = 0x00000006,
1189 MICRO_TILE_MODE_Z_3D                     = 0x00000007,
1190 } TC_MICRO_TILE_MODE;
1191 
1192 /*
1193  * SWIZZLE_MODE_ENUM enum
1194  */
1195 
1196 typedef enum SWIZZLE_MODE_ENUM {
1197 SW_LINEAR                                = 0x00000000,
1198 SW_256B_S                                = 0x00000001,
1199 SW_256B_D                                = 0x00000002,
1200 SW_256B_R                                = 0x00000003,
1201 SW_4KB_Z                                 = 0x00000004,
1202 SW_4KB_S                                 = 0x00000005,
1203 SW_4KB_D                                 = 0x00000006,
1204 SW_4KB_R                                 = 0x00000007,
1205 SW_64KB_Z                                = 0x00000008,
1206 SW_64KB_S                                = 0x00000009,
1207 SW_64KB_D                                = 0x0000000a,
1208 SW_64KB_R                                = 0x0000000b,
1209 SW_VAR_Z                                 = 0x0000000c,
1210 SW_VAR_S                                 = 0x0000000d,
1211 SW_VAR_D                                 = 0x0000000e,
1212 SW_VAR_R                                 = 0x0000000f,
1213 SW_RESERVED_16                           = 0x00000010,
1214 SW_RESERVED_17                           = 0x00000011,
1215 SW_RESERVED_18                           = 0x00000012,
1216 SW_RESERVED_19                           = 0x00000013,
1217 SW_4KB_Z_X                               = 0x00000014,
1218 SW_4KB_S_X                               = 0x00000015,
1219 SW_4KB_D_X                               = 0x00000016,
1220 SW_4KB_R_X                               = 0x00000017,
1221 SW_64KB_Z_X                              = 0x00000018,
1222 SW_64KB_S_X                              = 0x00000019,
1223 SW_64KB_D_X                              = 0x0000001a,
1224 SW_64KB_R_X                              = 0x0000001b,
1225 SW_VAR_Z_X                               = 0x0000001c,
1226 SW_VAR_S_X                               = 0x0000001d,
1227 SW_VAR_D_X                               = 0x0000001e,
1228 SW_VAR_R_X                               = 0x0000001f,
1229 SW_RESERVED_12                           = 0x00000020,
1230 SW_RESERVED_13                           = 0x00000021,
1231 SW_RESERVED_14                           = 0x00000022,
1232 SW_RESERVED_15                           = 0x00000023,
1233 } SWIZZLE_MODE_ENUM;
1234 
1235 /*
1236  * PipeTiling enum
1237  */
1238 
1239 typedef enum PipeTiling {
1240 CONFIG_1_PIPE                            = 0x00000000,
1241 CONFIG_2_PIPE                            = 0x00000001,
1242 CONFIG_4_PIPE                            = 0x00000002,
1243 CONFIG_8_PIPE                            = 0x00000003,
1244 } PipeTiling;
1245 
1246 /*
1247  * BankTiling enum
1248  */
1249 
1250 typedef enum BankTiling {
1251 CONFIG_4_BANK                            = 0x00000000,
1252 CONFIG_8_BANK                            = 0x00000001,
1253 } BankTiling;
1254 
1255 /*
1256  * GroupInterleave enum
1257  */
1258 
1259 typedef enum GroupInterleave {
1260 CONFIG_256B_GROUP                        = 0x00000000,
1261 CONFIG_512B_GROUP                        = 0x00000001,
1262 } GroupInterleave;
1263 
1264 /*
1265  * RowTiling enum
1266  */
1267 
1268 typedef enum RowTiling {
1269 CONFIG_1KB_ROW                           = 0x00000000,
1270 CONFIG_2KB_ROW                           = 0x00000001,
1271 CONFIG_4KB_ROW                           = 0x00000002,
1272 CONFIG_8KB_ROW                           = 0x00000003,
1273 CONFIG_1KB_ROW_OPT                       = 0x00000004,
1274 CONFIG_2KB_ROW_OPT                       = 0x00000005,
1275 CONFIG_4KB_ROW_OPT                       = 0x00000006,
1276 CONFIG_8KB_ROW_OPT                       = 0x00000007,
1277 } RowTiling;
1278 
1279 /*
1280  * BankSwapBytes enum
1281  */
1282 
1283 typedef enum BankSwapBytes {
1284 CONFIG_128B_SWAPS                        = 0x00000000,
1285 CONFIG_256B_SWAPS                        = 0x00000001,
1286 CONFIG_512B_SWAPS                        = 0x00000002,
1287 CONFIG_1KB_SWAPS                         = 0x00000003,
1288 } BankSwapBytes;
1289 
1290 /*
1291  * SampleSplitBytes enum
1292  */
1293 
1294 typedef enum SampleSplitBytes {
1295 CONFIG_1KB_SPLIT                         = 0x00000000,
1296 CONFIG_2KB_SPLIT                         = 0x00000001,
1297 CONFIG_4KB_SPLIT                         = 0x00000002,
1298 CONFIG_8KB_SPLIT                         = 0x00000003,
1299 } SampleSplitBytes;
1300 
1301 /*******************************************************
1302  * AZSTREAM Enums
1303  *******************************************************/
1304 
1305 /*
1306  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
1307  */
1308 
1309 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1310 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET  = 0x00000000,
1311 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET  = 0x00000001,
1312 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
1313 
1314 /*
1315  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
1316  */
1317 
1318 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1319 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET  = 0x00000000,
1320 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET  = 0x00000001,
1321 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
1322 
1323 /*
1324  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
1325  */
1326 
1327 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1328 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET  = 0x00000000,
1329 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET  = 0x00000001,
1330 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
1331 
1332 /*
1333  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
1334  */
1335 
1336 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1337 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY  = 0x00000000,
1338 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY  = 0x00000001,
1339 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
1340 
1341 /*
1342  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
1343  */
1344 
1345 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1346 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED  = 0x00000000,
1347 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED  = 0x00000001,
1348 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
1349 
1350 /*
1351  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
1352  */
1353 
1354 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1355 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED  = 0x00000000,
1356 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED  = 0x00000001,
1357 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
1358 
1359 /*
1360  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
1361  */
1362 
1363 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1364 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED  = 0x00000000,
1365 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED  = 0x00000001,
1366 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
1367 
1368 /*
1369  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
1370  */
1371 
1372 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1373 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN  = 0x00000000,
1374 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN  = 0x00000001,
1375 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
1376 
1377 /*
1378  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
1379  */
1380 
1381 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1382 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET  = 0x00000000,
1383 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET  = 0x00000001,
1384 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
1385 
1386 /*
1387  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
1388  */
1389 
1390 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1391 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
1392 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
1393 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
1394 
1395 /*
1396  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
1397  */
1398 
1399 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1400 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
1401 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
1402 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
1403 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
1404 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
1405 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
1406 
1407 /*
1408  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
1409  */
1410 
1411 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1412 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
1413 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
1414 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
1415 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
1416 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
1417 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
1418 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
1419 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
1420 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
1421 
1422 /*
1423  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
1424  */
1425 
1426 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1427 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
1428 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
1429 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
1430 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
1431 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
1432 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
1433 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
1434 
1435 /*
1436  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
1437  */
1438 
1439 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1440 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
1441 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
1442 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
1443 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
1444 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
1445 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
1446 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
1447 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
1448 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED  = 0x00000008,
1449 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED  = 0x00000009,
1450 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED  = 0x0000000a,
1451 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED  = 0x0000000b,
1452 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED  = 0x0000000c,
1453 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED  = 0x0000000d,
1454 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED  = 0x0000000e,
1455 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED  = 0x0000000f,
1456 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
1457 
1458 /*******************************************************
1459  * BLNDV Enums
1460  *******************************************************/
1461 
1462 /*
1463  * BLNDV_CONTROL_BLND_MODE enum
1464  */
1465 
1466 typedef enum BLNDV_CONTROL_BLND_MODE {
1467 BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
1468 BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY  = 0x00000001,
1469 BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
1470 BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
1471 } BLNDV_CONTROL_BLND_MODE;
1472 
1473 /*
1474  * BLNDV_CONTROL_BLND_STEREO_TYPE enum
1475  */
1476 
1477 typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1478 BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
1479 BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
1480 BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
1481 BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED    = 0x00000003,
1482 } BLNDV_CONTROL_BLND_STEREO_TYPE;
1483 
1484 /*
1485  * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
1486  */
1487 
1488 typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1489 BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW   = 0x00000000,
1490 BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH  = 0x00000001,
1491 } BLNDV_CONTROL_BLND_STEREO_POLARITY;
1492 
1493 /*
1494  * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
1495  */
1496 
1497 typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1498 BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE  = 0x00000000,
1499 BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE   = 0x00000001,
1500 } BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
1501 
1502 /*
1503  * BLNDV_CONTROL_BLND_ALPHA_MODE enum
1504  */
1505 
1506 typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1507 BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
1508 BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
1509 BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
1510 BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED     = 0x00000003,
1511 } BLNDV_CONTROL_BLND_ALPHA_MODE;
1512 
1513 /*
1514  * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
1515  */
1516 
1517 typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1518 BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE  = 0x00000000,
1519 BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE  = 0x00000001,
1520 } BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
1521 
1522 /*
1523  * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
1524  */
1525 
1526 typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1527 BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
1528 BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE  = 0x00000001,
1529 } BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
1530 
1531 /*
1532  * BLNDV_SM_CONTROL2_SM_MODE enum
1533  */
1534 
1535 typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1536 BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE   = 0x00000000,
1537 BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
1538 BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
1539 BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
1540 } BLNDV_SM_CONTROL2_SM_MODE;
1541 
1542 /*
1543  * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
1544  */
1545 
1546 typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1547 BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
1548 BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
1549 } BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
1550 
1551 /*
1552  * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
1553  */
1554 
1555 typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1556 BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
1557 BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
1558 } BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
1559 
1560 /*
1561  * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
1562  */
1563 
1564 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1565 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
1566 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
1567 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
1568 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
1569 } BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
1570 
1571 /*
1572  * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
1573  */
1574 
1575 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1576 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
1577 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
1578 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
1579 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
1580 } BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
1581 
1582 /*
1583  * BLNDV_CONTROL2_PTI_ENABLE enum
1584  */
1585 
1586 typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1587 BLNDV_CONTROL2_PTI_ENABLE_FALSE          = 0x00000000,
1588 BLNDV_CONTROL2_PTI_ENABLE_TRUE           = 0x00000001,
1589 } BLNDV_CONTROL2_PTI_ENABLE;
1590 
1591 /*
1592  * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
1593  */
1594 
1595 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1596 BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
1597 BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
1598 } BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
1599 
1600 /*
1601  * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
1602  */
1603 
1604 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1605 BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
1606 BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
1607 } BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
1608 
1609 /*
1610  * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
1611  */
1612 
1613 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1614 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
1615 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
1616 } BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
1617 
1618 /*
1619  * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
1620  */
1621 
1622 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1623 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
1624 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
1625 } BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
1626 
1627 /*
1628  * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
1629  */
1630 
1631 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1632 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
1633 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
1634 } BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
1635 
1636 /*
1637  * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
1638  */
1639 
1640 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1641 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
1642 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
1643 } BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
1644 
1645 /*
1646  * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
1647  */
1648 
1649 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1650 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
1651 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
1652 } BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
1653 
1654 /*
1655  * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
1656  */
1657 
1658 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1659 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
1660 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
1661 } BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
1662 
1663 /*
1664  * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
1665  */
1666 
1667 typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1668 BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
1669 BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
1670 } BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
1671 
1672 /*
1673  * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
1674  */
1675 
1676 typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1677 BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
1678 BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
1679 } BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
1680 
1681 /*
1682  * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
1683  */
1684 
1685 typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1686 BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
1687 BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
1688 } BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
1689 
1690 /*
1691  * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
1692  */
1693 
1694 typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1695 BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW      = 0x00000000,
1696 BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH     = 0x00000001,
1697 } BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
1698 
1699 /*
1700  * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
1701  */
1702 
1703 typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1704 BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
1705 BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
1706 } BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
1707 
1708 /*******************************************************
1709  * LBV Enums
1710  *******************************************************/
1711 
1712 /*
1713  * LBV_PIXEL_DEPTH enum
1714  */
1715 
1716 typedef enum LBV_PIXEL_DEPTH {
1717 PIXEL_DEPTH_30BPP                        = 0x00000000,
1718 PIXEL_DEPTH_24BPP                        = 0x00000001,
1719 PIXEL_DEPTH_18BPP                        = 0x00000002,
1720 PIXEL_DEPTH_38BPP                        = 0x00000003,
1721 } LBV_PIXEL_DEPTH;
1722 
1723 /*
1724  * LBV_PIXEL_EXPAN_MODE enum
1725  */
1726 
1727 typedef enum LBV_PIXEL_EXPAN_MODE {
1728 PIXEL_EXPAN_MODE_ZERO_EXP                = 0x00000000,
1729 PIXEL_EXPAN_MODE_DYN_EXP                 = 0x00000001,
1730 } LBV_PIXEL_EXPAN_MODE;
1731 
1732 /*
1733  * LBV_INTERLEAVE_EN enum
1734  */
1735 
1736 typedef enum LBV_INTERLEAVE_EN {
1737 INTERLEAVE_DIS                           = 0x00000000,
1738 INTERLEAVE_EN                            = 0x00000001,
1739 } LBV_INTERLEAVE_EN;
1740 
1741 /*
1742  * LBV_PIXEL_REDUCE_MODE enum
1743  */
1744 
1745 typedef enum LBV_PIXEL_REDUCE_MODE {
1746 PIXEL_REDUCE_MODE_TRUNCATION             = 0x00000000,
1747 PIXEL_REDUCE_MODE_ROUNDING               = 0x00000001,
1748 } LBV_PIXEL_REDUCE_MODE;
1749 
1750 /*
1751  * LBV_DYNAMIC_PIXEL_DEPTH enum
1752  */
1753 
1754 typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1755 DYNAMIC_PIXEL_DEPTH_36BPP                = 0x00000000,
1756 DYNAMIC_PIXEL_DEPTH_30BPP                = 0x00000001,
1757 } LBV_DYNAMIC_PIXEL_DEPTH;
1758 
1759 /*
1760  * LBV_DITHER_EN enum
1761  */
1762 
1763 typedef enum LBV_DITHER_EN {
1764 DITHER_DIS                               = 0x00000000,
1765 DITHER_EN                                = 0x00000001,
1766 } LBV_DITHER_EN;
1767 
1768 /*
1769  * LBV_DOWNSCALE_PREFETCH_EN enum
1770  */
1771 
1772 typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1773 DOWNSCALE_PREFETCH_DIS                   = 0x00000000,
1774 DOWNSCALE_PREFETCH_EN                    = 0x00000001,
1775 } LBV_DOWNSCALE_PREFETCH_EN;
1776 
1777 /*
1778  * LBV_MEMORY_CONFIG enum
1779  */
1780 
1781 typedef enum LBV_MEMORY_CONFIG {
1782 MEMORY_CONFIG_0                          = 0x00000000,
1783 MEMORY_CONFIG_1                          = 0x00000001,
1784 MEMORY_CONFIG_2                          = 0x00000002,
1785 MEMORY_CONFIG_3                          = 0x00000003,
1786 } LBV_MEMORY_CONFIG;
1787 
1788 /*
1789  * LBV_SYNC_RESET_SEL2 enum
1790  */
1791 
1792 typedef enum LBV_SYNC_RESET_SEL2 {
1793 SYNC_RESET_SEL2_VBLANK                   = 0x00000000,
1794 SYNC_RESET_SEL2_VSYNC                    = 0x00000001,
1795 } LBV_SYNC_RESET_SEL2;
1796 
1797 /*
1798  * LBV_SYNC_DURATION enum
1799  */
1800 
1801 typedef enum LBV_SYNC_DURATION {
1802 SYNC_DURATION_16                         = 0x00000000,
1803 SYNC_DURATION_32                         = 0x00000001,
1804 SYNC_DURATION_64                         = 0x00000002,
1805 SYNC_DURATION_128                        = 0x00000003,
1806 } LBV_SYNC_DURATION;
1807 
1808 /*******************************************************
1809  * CRTC Enums
1810  *******************************************************/
1811 
1812 /*
1813  * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
1814  */
1815 
1816 typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1817 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
1818 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP    = 0x00000001,
1819 } CRTC_CONTROL_CRTC_START_POINT_CNTL;
1820 
1821 /*
1822  * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
1823  */
1824 
1825 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1826 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
1827 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP   = 0x00000001,
1828 } CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
1829 
1830 /*
1831  * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
1832  */
1833 
1834 typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1835 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE  = 0x00000000,
1836 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT  = 0x00000001,
1837 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED  = 0x00000002,
1838 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST  = 0x00000003,
1839 } CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
1840 
1841 /*
1842  * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
1843  */
1844 
1845 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1846 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE  = 0x00000000,
1847 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE  = 0x00000001,
1848 } CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
1849 
1850 /*
1851  * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
1852  */
1853 
1854 typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1855 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE  = 0x00000000,
1856 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE  = 0x00000001,
1857 } CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
1858 
1859 /*
1860  * CRTC_CONTROL_CRTC_SOF_PULL_EN enum
1861  */
1862 
1863 typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1864 CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE      = 0x00000000,
1865 CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE       = 0x00000001,
1866 } CRTC_CONTROL_CRTC_SOF_PULL_EN;
1867 
1868 /*
1869  * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
1870  */
1871 
1872 typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1873 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE  = 0x00000000,
1874 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE  = 0x00000001,
1875 } CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
1876 
1877 /*
1878  * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
1879  */
1880 
1881 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1882 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x00000000,
1883 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE  = 0x00000001,
1884 } CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
1885 
1886 /*
1887  * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
1888  */
1889 
1890 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1891 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x00000000,
1892 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE  = 0x00000001,
1893 } CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
1894 
1895 /*
1896  * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
1897  */
1898 
1899 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1900 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE  = 0x00000000,
1901 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE  = 0x00000001,
1902 } CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
1903 
1904 /*
1905  * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
1906  */
1907 
1908 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1909 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
1910 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE  = 0x00000001,
1911 } CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
1912 
1913 /*
1914  * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
1915  */
1916 
1917 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1918 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
1919 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE  = 0x00000001,
1920 } CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
1921 
1922 /*
1923  * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
1924  */
1925 
1926 typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1927 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
1928 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE  = 0x00000001,
1929 } CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
1930 
1931 /*
1932  * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
1933  */
1934 
1935 typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1936 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
1937 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE  = 0x00000001,
1938 } CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
1939 
1940 /*
1941  * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
1942  */
1943 
1944 typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1945 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE  = 0x00000000,
1946 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE  = 0x00000001,
1947 } CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
1948 
1949 /*
1950  * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
1951  */
1952 
1953 typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1954 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE  = 0x00000000,
1955 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE  = 0x00000001,
1956 } CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
1957 
1958 /*
1959  * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
1960  */
1961 
1962 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1963 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER  = 0x00000001,
1964 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER  = 0x00000002,
1965 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF  = 0x00000005,
1966 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE  = 0x00000006,
1967 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x00000007,
1968 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x00000008,
1969 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x00000009,
1970 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0x0000000a,
1971 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1  = 0x0000000b,
1972 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2  = 0x0000000c,
1973 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD  = 0x0000000d,
1974 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC  = 0x0000000e,
1975 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0  = 0x00000010,
1976 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1  = 0x00000011,
1977 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2  = 0x00000012,
1978 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON  = 0x00000013,
1979 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA  = 0x00000014,
1980 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB  = 0x00000015,
1981 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW  = 0x00000016,
1982 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW  = 0x00000017,
1983 } CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
1984 
1985 /*
1986  * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
1987  */
1988 
1989 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1990 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE  = 0x00000001,
1991 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA  = 0x00000002,
1992 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB  = 0x00000003,
1993 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA  = 0x00000004,
1994 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB  = 0x00000005,
1995 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO  = 0x00000006,
1996 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC  = 0x00000007,
1997 } CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
1998 
1999 /*
2000  * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
2001  */
2002 
2003 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
2004 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
2005 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
2006 } CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
2007 
2008 /*
2009  * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
2010  */
2011 
2012 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2013 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE   = 0x00000000,
2014 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE    = 0x00000001,
2015 } CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
2016 
2017 /*
2018  * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
2019  */
2020 
2021 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2022 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER  = 0x00000001,
2023 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER  = 0x00000002,
2024 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF  = 0x00000005,
2025 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE  = 0x00000006,
2026 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x00000007,
2027 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x00000008,
2028 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x00000009,
2029 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0x0000000a,
2030 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1  = 0x0000000b,
2031 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2  = 0x0000000c,
2032 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD  = 0x0000000d,
2033 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC  = 0x0000000e,
2034 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0  = 0x00000010,
2035 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1  = 0x00000011,
2036 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2  = 0x00000012,
2037 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON  = 0x00000013,
2038 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA  = 0x00000014,
2039 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB  = 0x00000015,
2040 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW  = 0x00000016,
2041 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW  = 0x00000017,
2042 } CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
2043 
2044 /*
2045  * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
2046  */
2047 
2048 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2049 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE  = 0x00000001,
2050 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA  = 0x00000002,
2051 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB  = 0x00000003,
2052 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA  = 0x00000004,
2053 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB  = 0x00000005,
2054 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO  = 0x00000006,
2055 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC  = 0x00000007,
2056 } CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
2057 
2058 /*
2059  * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
2060  */
2061 
2062 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2063 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
2064 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
2065 } CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
2066 
2067 /*
2068  * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
2069  */
2070 
2071 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2072 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE   = 0x00000000,
2073 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE    = 0x00000001,
2074 } CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
2075 
2076 /*
2077  * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
2078  */
2079 
2080 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2081 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE  = 0x00000000,
2082 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT  = 0x00000001,
2083 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT  = 0x00000002,
2084 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED  = 0x00000003,
2085 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
2086 
2087 /*
2088  * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
2089  */
2090 
2091 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2092 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE  = 0x00000000,
2093 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE  = 0x00000001,
2094 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
2095 
2096 /*
2097  * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
2098  */
2099 
2100 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2101 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE  = 0x00000000,
2102 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE  = 0x00000001,
2103 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
2104 
2105 /*
2106  * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
2107  */
2108 
2109 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2110 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
2111 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE  = 0x00000001,
2112 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
2113 
2114 /*
2115  * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
2116  */
2117 
2118 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2119 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0  = 0x00000000,
2120 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF  = 0x00000001,
2121 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE  = 0x00000002,
2122 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1  = 0x00000003,
2123 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2  = 0x00000004,
2124 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA  = 0x00000005,
2125 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK  = 0x00000006,
2126 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA  = 0x00000007,
2127 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK  = 0x00000008,
2128 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK  = 0x00000009,
2129 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL  = 0x0000000a,
2130 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1  = 0x0000000b,
2131 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB  = 0x0000000c,
2132 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA  = 0x0000000d,
2133 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD  = 0x0000000e,
2134 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC  = 0x0000000f,
2135 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
2136 
2137 /*
2138  * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
2139  */
2140 
2141 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2142 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE  = 0x00000000,
2143 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE  = 0x00000001,
2144 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
2145 
2146 /*
2147  * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
2148  */
2149 
2150 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2151 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE  = 0x00000000,
2152 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE  = 0x00000001,
2153 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
2154 
2155 /*
2156  * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
2157  */
2158 
2159 typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2160 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO  = 0x00000000,
2161 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT  = 0x00000001,
2162 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT  = 0x00000002,
2163 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED  = 0x00000003,
2164 } CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
2165 
2166 /*
2167  * CRTC_CONTROL_CRTC_MASTER_EN enum
2168  */
2169 
2170 typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2171 CRTC_CONTROL_CRTC_MASTER_EN_FALSE        = 0x00000000,
2172 CRTC_CONTROL_CRTC_MASTER_EN_TRUE         = 0x00000001,
2173 } CRTC_CONTROL_CRTC_MASTER_EN;
2174 
2175 /*
2176  * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
2177  */
2178 
2179 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2180 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE  = 0x00000000,
2181 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE  = 0x00000001,
2182 } CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
2183 
2184 /*
2185  * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
2186  */
2187 
2188 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2189 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE  = 0x00000000,
2190 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE  = 0x00000001,
2191 } CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
2192 
2193 /*
2194  * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
2195  */
2196 
2197 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2198 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE  = 0x00000000,
2199 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE  = 0x00000001,
2200 } CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
2201 
2202 /*
2203  * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
2204  */
2205 
2206 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2207 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT  = 0x00000000,
2208 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD  = 0x00000001,
2209 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN  = 0x00000002,
2210 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2  = 0x00000003,
2211 } CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
2212 
2213 /*
2214  * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
2215  */
2216 
2217 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2218 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE  = 0x00000000,
2219 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE  = 0x00000001,
2220 } CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
2221 
2222 /*
2223  * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
2224  */
2225 
2226 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2227 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE  = 0x00000000,
2228 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE  = 0x00000001,
2229 } CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
2230 
2231 /*
2232  * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
2233  */
2234 
2235 typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2236 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x00000000,
2237 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE  = 0x00000001,
2238 } CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
2239 
2240 /*
2241  * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
2242  */
2243 
2244 typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2245 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
2246 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE  = 0x00000001,
2247 } CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
2248 
2249 /*
2250  * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
2251  */
2252 
2253 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2254 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
2255 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE  = 0x00000001,
2256 } CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
2257 
2258 /*
2259  * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
2260  */
2261 
2262 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2263 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE  = 0x00000000,
2264 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA  = 0x00000001,
2265 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB  = 0x00000002,
2266 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED  = 0x00000003,
2267 } CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
2268 
2269 /*
2270  * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
2271  */
2272 
2273 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2274 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE  = 0x00000000,
2275 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE  = 0x00000001,
2276 } CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
2277 
2278 /*
2279  * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
2280  */
2281 
2282 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2283 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE  = 0x00000000,
2284 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE  = 0x00000001,
2285 } CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
2286 
2287 /*
2288  * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
2289  */
2290 
2291 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2292 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE  = 0x00000000,
2293 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE  = 0x00000001,
2294 } CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
2295 
2296 /*
2297  * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
2298  */
2299 
2300 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2301 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE  = 0x00000000,
2302 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE  = 0x00000001,
2303 } CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
2304 
2305 /*
2306  * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
2307  */
2308 
2309 typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2310 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
2311 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE  = 0x00000001,
2312 } CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
2313 
2314 /*
2315  * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
2316  */
2317 
2318 typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2319 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE  = 0x00000000,
2320 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA  = 0x00000001,
2321 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB  = 0x00000002,
2322 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED  = 0x00000003,
2323 } CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
2324 
2325 /*
2326  * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
2327  */
2328 
2329 typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2330 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
2331 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE  = 0x00000001,
2332 } CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
2333 
2334 /*
2335  * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
2336  */
2337 
2338 typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2339 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
2340 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE  = 0x00000001,
2341 } CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
2342 
2343 /*
2344  * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
2345  */
2346 
2347 typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2348 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE  = 0x00000000,
2349 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE  = 0x00000001,
2350 } CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
2351 
2352 /*
2353  * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
2354  */
2355 
2356 typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2357 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE  = 0x00000000,
2358 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE  = 0x00000001,
2359 } CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
2360 
2361 /*
2362  * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
2363  */
2364 
2365 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2366 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE  = 0x00000000,
2367 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE  = 0x00000001,
2368 } CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
2369 
2370 /*
2371  * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
2372  */
2373 
2374 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2375 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE  = 0x00000000,
2376 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE  = 0x00000001,
2377 } CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
2378 
2379 /*
2380  * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
2381  */
2382 
2383 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2384 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE  = 0x00000000,
2385 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE  = 0x00000001,
2386 } CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
2387 
2388 /*
2389  * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
2390  */
2391 
2392 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2393 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE  = 0x00000000,
2394 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE  = 0x00000001,
2395 } CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
2396 
2397 /*
2398  * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
2399  */
2400 
2401 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2402 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE  = 0x00000000,
2403 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE  = 0x00000001,
2404 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
2405 
2406 /*
2407  * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
2408  */
2409 
2410 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2411 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE  = 0x00000000,
2412 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE  = 0x00000001,
2413 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
2414 
2415 /*
2416  * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
2417  */
2418 
2419 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2420 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE  = 0x00000000,
2421 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE  = 0x00000001,
2422 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
2423 
2424 /*
2425  * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
2426  */
2427 
2428 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2429 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE  = 0x00000000,
2430 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE  = 0x00000001,
2431 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
2432 
2433 /*
2434  * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
2435  */
2436 
2437 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2438 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x00000000,
2439 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE  = 0x00000001,
2440 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
2441 
2442 /*
2443  * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
2444  */
2445 
2446 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2447 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE  = 0x00000000,
2448 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x00000001,
2449 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
2450 
2451 /*
2452  * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
2453  */
2454 
2455 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2456 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x00000000,
2457 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE  = 0x00000001,
2458 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
2459 
2460 /*
2461  * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
2462  */
2463 
2464 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2465 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE  = 0x00000000,
2466 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x00000001,
2467 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
2468 
2469 /*
2470  * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
2471  */
2472 
2473 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2474 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE  = 0x00000000,
2475 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE  = 0x00000001,
2476 } CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
2477 
2478 /*
2479  * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
2480  */
2481 
2482 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2483 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE  = 0x00000000,
2484 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE  = 0x00000001,
2485 } CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
2486 
2487 /*
2488  * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
2489  */
2490 
2491 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2492 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE  = 0x00000000,
2493 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE  = 0x00000001,
2494 } CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
2495 
2496 /*
2497  * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
2498  */
2499 
2500 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2501 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE  = 0x00000000,
2502 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE  = 0x00000001,
2503 } CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
2504 
2505 /*
2506  * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
2507  */
2508 
2509 typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2510 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE  = 0x00000000,
2511 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE   = 0x00000001,
2512 } CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
2513 
2514 /*
2515  * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
2516  */
2517 
2518 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2519 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE  = 0x00000000,
2520 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE  = 0x00000001,
2521 } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
2522 
2523 /*
2524  * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
2525  */
2526 
2527 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2528 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE  = 0x00000000,
2529 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE  = 0x00000001,
2530 } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
2531 
2532 /*
2533  * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
2534  */
2535 
2536 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2537 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0  = 0x00000000,
2538 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1  = 0x00000001,
2539 } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
2540 
2541 /*
2542  * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
2543  */
2544 
2545 typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2546 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE  = 0x00000000,
2547 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE  = 0x00000001,
2548 } CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
2549 
2550 /*
2551  * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
2552  */
2553 
2554 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2555 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE  = 0x00000000,
2556 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE  = 0x00000001,
2557 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
2558 
2559 /*
2560  * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
2561  */
2562 
2563 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2564 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB  = 0x00000000,
2565 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601  = 0x00000001,
2566 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709  = 0x00000002,
2567 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS  = 0x00000003,
2568 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS  = 0x00000004,
2569 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB  = 0x00000005,
2570 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB  = 0x00000006,
2571 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS  = 0x00000007,
2572 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
2573 
2574 /*
2575  * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
2576  */
2577 
2578 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2579 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE  = 0x00000000,
2580 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE  = 0x00000001,
2581 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
2582 
2583 /*
2584  * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
2585  */
2586 
2587 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2588 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC  = 0x00000000,
2589 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC  = 0x00000001,
2590 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC  = 0x00000002,
2591 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED  = 0x00000003,
2592 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
2593 
2594 /*
2595  * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
2596  */
2597 
2598 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2599 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
2600 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
2601 } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
2602 
2603 /*
2604  * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
2605  */
2606 
2607 typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2608 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
2609 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
2610 } MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
2611 
2612 /*
2613  * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
2614  */
2615 
2616 typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2617 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE  = 0x00000000,
2618 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE  = 0x00000001,
2619 } MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
2620 
2621 /*
2622  * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
2623  */
2624 
2625 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2626 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN  = 0x00000000,
2627 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA  = 0x00000001,
2628 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA  = 0x00000002,
2629 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE  = 0x00000003,
2630 } MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
2631 
2632 /*
2633  * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
2634  */
2635 
2636 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2637 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH  = 0x00000000,
2638 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN  = 0x00000001,
2639 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD  = 0x00000002,
2640 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED  = 0x00000003,
2641 } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
2642 
2643 /*
2644  * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
2645  */
2646 
2647 typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2648 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE  = 0x00000000,
2649 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG  = 0x00000001,
2650 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL  = 0x00000002,
2651 } CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
2652 
2653 /*
2654  * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
2655  */
2656 
2657 typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2658 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
2659 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE  = 0x00000001,
2660 } CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
2661 
2662 /*
2663  * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
2664  */
2665 
2666 typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2667 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
2668 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE  = 0x00000001,
2669 } CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
2670 
2671 /*
2672  * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
2673  */
2674 
2675 typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2676 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
2677 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE  = 0x00000001,
2678 } CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
2679 
2680 /*
2681  * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
2682  */
2683 
2684 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2685 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE  = 0x00000000,
2686 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE  = 0x00000001,
2687 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
2688 
2689 /*
2690  * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
2691  */
2692 
2693 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2694 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
2695 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE  = 0x00000001,
2696 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
2697 
2698 /*
2699  * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
2700  */
2701 
2702 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2703 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
2704 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE  = 0x00000001,
2705 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
2706 
2707 /*
2708  * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
2709  */
2710 
2711 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2712 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE  = 0x00000000,
2713 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE  = 0x00000001,
2714 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
2715 
2716 /*
2717  * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
2718  */
2719 
2720 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2721 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
2722 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE  = 0x00000001,
2723 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
2724 
2725 /*
2726  * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
2727  */
2728 
2729 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2730 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
2731 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE  = 0x00000001,
2732 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
2733 
2734 /*
2735  * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
2736  */
2737 
2738 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2739 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE  = 0x00000000,
2740 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE  = 0x00000001,
2741 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
2742 
2743 /*
2744  * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
2745  */
2746 
2747 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2748 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
2749 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE  = 0x00000001,
2750 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
2751 
2752 /*
2753  * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
2754  */
2755 
2756 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2757 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
2758 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE  = 0x00000001,
2759 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
2760 
2761 /*
2762  * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
2763  */
2764 
2765 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2766 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE  = 0x00000000,
2767 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE  = 0x00000001,
2768 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
2769 
2770 /*
2771  * CRTC_CRC_CNTL_CRTC_CRC_EN enum
2772  */
2773 
2774 typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2775 CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE          = 0x00000000,
2776 CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE           = 0x00000001,
2777 } CRTC_CRC_CNTL_CRTC_CRC_EN;
2778 
2779 /*
2780  * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
2781  */
2782 
2783 typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2784 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE     = 0x00000000,
2785 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE      = 0x00000001,
2786 } CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
2787 
2788 /*
2789  * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
2790  */
2791 
2792 typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2793 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT  = 0x00000000,
2794 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT  = 0x00000001,
2795 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES  = 0x00000002,
2796 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS  = 0x00000003,
2797 } CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
2798 
2799 /*
2800  * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
2801  */
2802 
2803 typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2804 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP  = 0x00000000,
2805 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM  = 0x00000001,
2806 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
2807 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD  = 0x00000003,
2808 } CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
2809 
2810 /*
2811  * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
2812  */
2813 
2814 typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2815 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
2816 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE  = 0x00000001,
2817 } CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
2818 
2819 /*
2820  * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
2821  */
2822 
2823 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2824 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB  = 0x00000000,
2825 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B  = 0x00000001,
2826 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB  = 0x00000002,
2827 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B  = 0x00000003,
2828 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB  = 0x00000004,
2829 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B  = 0x00000005,
2830 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB  = 0x00000006,
2831 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B  = 0x00000007,
2832 } CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
2833 
2834 /*
2835  * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
2836  */
2837 
2838 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2839 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB  = 0x00000000,
2840 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B  = 0x00000001,
2841 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB  = 0x00000002,
2842 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B  = 0x00000003,
2843 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB  = 0x00000004,
2844 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B  = 0x00000005,
2845 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB  = 0x00000006,
2846 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B  = 0x00000007,
2847 } CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
2848 
2849 /*
2850  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
2851  */
2852 
2853 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2854 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE  = 0x00000000,
2855 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT  = 0x00000001,
2856 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS  = 0x00000002,
2857 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED  = 0x00000003,
2858 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
2859 
2860 /*
2861  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
2862  */
2863 
2864 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2865 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE  = 0x00000000,
2866 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE  = 0x00000001,
2867 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
2868 
2869 /*
2870  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
2871  */
2872 
2873 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2874 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE  = 0x00000000,
2875 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE  = 0x00000001,
2876 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
2877 
2878 /*
2879  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
2880  */
2881 
2882 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2883 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel  = 0x00000000,
2884 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel  = 0x00000001,
2885 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel  = 0x00000002,
2886 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel  = 0x00000003,
2887 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
2888 
2889 /*
2890  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
2891  */
2892 
2893 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2894 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE  = 0x00000000,
2895 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE  = 0x00000001,
2896 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
2897 
2898 /*
2899  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
2900  */
2901 
2902 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2903 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
2904 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE  = 0x00000001,
2905 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
2906 
2907 /*
2908  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
2909  */
2910 
2911 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2912 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE  = 0x00000000,
2913 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE  = 0x00000001,
2914 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
2915 
2916 /*
2917  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
2918  */
2919 
2920 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2921 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE  = 0x00000000,
2922 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE  = 0x00000001,
2923 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
2924 
2925 /*
2926  * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
2927  */
2928 
2929 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2930 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE  = 0x00000000,
2931 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE  = 0x00000001,
2932 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
2933 
2934 /*
2935  * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
2936  */
2937 
2938 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2939 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE  = 0x00000000,
2940 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE  = 0x00000001,
2941 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
2942 
2943 /*
2944  * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
2945  */
2946 
2947 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2948 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
2949 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE  = 0x00000001,
2950 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
2951 
2952 /*
2953  * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
2954  */
2955 
2956 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2957 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE  = 0x00000000,
2958 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE  = 0x00000001,
2959 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
2960 
2961 /*
2962  * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
2963  */
2964 
2965 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2966 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME  = 0x00000000,
2967 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME  = 0x00000001,
2968 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME  = 0x00000002,
2969 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME  = 0x00000003,
2970 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME  = 0x00000004,
2971 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME  = 0x00000005,
2972 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME  = 0x00000006,
2973 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME  = 0x00000007,
2974 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
2975 
2976 /*
2977  * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
2978  */
2979 
2980 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2981 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE  = 0x00000000,
2982 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE  = 0x00000001,
2983 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
2984 
2985 /*
2986  * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
2987  */
2988 
2989 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2990 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
2991 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE  = 0x00000001,
2992 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
2993 
2994 /*
2995  * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
2996  */
2997 
2998 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
2999 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE  = 0x00000000,
3000 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE  = 0x00000001,
3001 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
3002 
3003 /*
3004  * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
3005  */
3006 
3007 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3008 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE  = 0x00000000,
3009 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE  = 0x00000001,
3010 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
3011 
3012 /*
3013  * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
3014  */
3015 
3016 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3017 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
3018 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE  = 0x00000001,
3019 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
3020 
3021 /*
3022  * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
3023  */
3024 
3025 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3026 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE  = 0x00000000,
3027 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE  = 0x00000001,
3028 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
3029 
3030 /*
3031  * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
3032  */
3033 
3034 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3035 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE  = 0x00000000,
3036 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE  = 0x00000001,
3037 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
3038 
3039 /*
3040  * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
3041  */
3042 
3043 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3044 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
3045 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE  = 0x00000001,
3046 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
3047 
3048 /*
3049  * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
3050  */
3051 
3052 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3053 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE  = 0x00000000,
3054 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE  = 0x00000001,
3055 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
3056 
3057 /*
3058  * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
3059  */
3060 
3061 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3062 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE  = 0x00000000,
3063 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE  = 0x00000001,
3064 } CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
3065 
3066 /*
3067  * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
3068  */
3069 
3070 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3071 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF  = 0x00000000,
3072 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON  = 0x00000001,
3073 } CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
3074 
3075 /*
3076  * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
3077  */
3078 
3079 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3080 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE  = 0x00000000,
3081 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE  = 0x00000001,
3082 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
3083 
3084 /*
3085  * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
3086  */
3087 
3088 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3089 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE  = 0x00000000,
3090 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE  = 0x00000001,
3091 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
3092 
3093 /*
3094  * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
3095  */
3096 
3097 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3098 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH  = 0x00000000,
3099 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE  = 0x00000001,
3100 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE  = 0x00000002,
3101 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED  = 0x00000003,
3102 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
3103 
3104 /*
3105  * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
3106  */
3107 
3108 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3109 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE  = 0x00000000,
3110 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE  = 0x00000001,
3111 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
3112 
3113 /*
3114  * CRTC_V_SYNC_A_POL enum
3115  */
3116 
3117 typedef enum CRTC_V_SYNC_A_POL {
3118 CRTC_V_SYNC_A_POL_HIGH                   = 0x00000000,
3119 CRTC_V_SYNC_A_POL_LOW                    = 0x00000001,
3120 } CRTC_V_SYNC_A_POL;
3121 
3122 /*
3123  * CRTC_H_SYNC_A_POL enum
3124  */
3125 
3126 typedef enum CRTC_H_SYNC_A_POL {
3127 CRTC_H_SYNC_A_POL_HIGH                   = 0x00000000,
3128 CRTC_H_SYNC_A_POL_LOW                    = 0x00000001,
3129 } CRTC_H_SYNC_A_POL;
3130 
3131 /*
3132  * CRTC_HORZ_REPETITION_COUNT enum
3133  */
3134 
3135 typedef enum CRTC_HORZ_REPETITION_COUNT {
3136 CRTC_HORZ_REPETITION_COUNT_0             = 0x00000000,
3137 CRTC_HORZ_REPETITION_COUNT_1             = 0x00000001,
3138 CRTC_HORZ_REPETITION_COUNT_2             = 0x00000002,
3139 CRTC_HORZ_REPETITION_COUNT_3             = 0x00000003,
3140 CRTC_HORZ_REPETITION_COUNT_4             = 0x00000004,
3141 CRTC_HORZ_REPETITION_COUNT_5             = 0x00000005,
3142 CRTC_HORZ_REPETITION_COUNT_6             = 0x00000006,
3143 CRTC_HORZ_REPETITION_COUNT_7             = 0x00000007,
3144 CRTC_HORZ_REPETITION_COUNT_8             = 0x00000008,
3145 CRTC_HORZ_REPETITION_COUNT_9             = 0x00000009,
3146 CRTC_HORZ_REPETITION_COUNT_10            = 0x0000000a,
3147 CRTC_HORZ_REPETITION_COUNT_11            = 0x0000000b,
3148 CRTC_HORZ_REPETITION_COUNT_12            = 0x0000000c,
3149 CRTC_HORZ_REPETITION_COUNT_13            = 0x0000000d,
3150 CRTC_HORZ_REPETITION_COUNT_14            = 0x0000000e,
3151 CRTC_HORZ_REPETITION_COUNT_15            = 0x0000000f,
3152 } CRTC_HORZ_REPETITION_COUNT;
3153 
3154 /*
3155  * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
3156  */
3157 
3158 typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3159 CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE  = 0x00000000,
3160 CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL  = 0x00000001,
3161 CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF   = 0x00000002,
3162 CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF  = 0x00000003,
3163 } CRTC_DRR_MODE_DBUF_UPDATE_MODE;
3164 
3165 /*******************************************************
3166  * FMT Enums
3167  *******************************************************/
3168 
3169 /*
3170  * FMT_CONTROL_PIXEL_ENCODING enum
3171  */
3172 
3173 typedef enum FMT_CONTROL_PIXEL_ENCODING {
3174 FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444  = 0x00000000,
3175 FMT_CONTROL_PIXEL_ENCODING_YCBCR422      = 0x00000001,
3176 FMT_CONTROL_PIXEL_ENCODING_YCBCR420      = 0x00000002,
3177 FMT_CONTROL_PIXEL_ENCODING_RESERVED      = 0x00000003,
3178 } FMT_CONTROL_PIXEL_ENCODING;
3179 
3180 /*
3181  * FMT_CONTROL_SUBSAMPLING_MODE enum
3182  */
3183 
3184 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3185 FMT_CONTROL_SUBSAMPLING_MODE_DROP        = 0x00000000,
3186 FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE     = 0x00000001,
3187 FMT_CONTROL_SUBSAMPLING_MOME_3_TAP       = 0x00000002,
3188 FMT_CONTROL_SUBSAMPLING_MOME_RESERVED    = 0x00000003,
3189 } FMT_CONTROL_SUBSAMPLING_MODE;
3190 
3191 /*
3192  * FMT_CONTROL_SUBSAMPLING_ORDER enum
3193  */
3194 
3195 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3196 FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR  = 0x00000000,
3197 FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB  = 0x00000001,
3198 } FMT_CONTROL_SUBSAMPLING_ORDER;
3199 
3200 /*
3201  * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3202  */
3203 
3204 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3205 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE  = 0x00000000,
3206 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE  = 0x00000001,
3207 } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3208 
3209 /*
3210  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3211  */
3212 
3213 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3214 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION  = 0x00000000,
3215 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING  = 0x00000001,
3216 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3217 
3218 /*
3219  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3220  */
3221 
3222 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3223 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP  = 0x00000000,
3224 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP  = 0x00000001,
3225 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP  = 0x00000002,
3226 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3227 
3228 /*
3229  * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3230  */
3231 
3232 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3233 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP  = 0x00000000,
3234 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP  = 0x00000001,
3235 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP  = 0x00000002,
3236 } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3237 
3238 /*
3239  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3240  */
3241 
3242 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3243 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP  = 0x00000000,
3244 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP  = 0x00000001,
3245 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP  = 0x00000002,
3246 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3247 
3248 /*
3249  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3250  */
3251 
3252 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3253 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2  = 0x00000000,
3254 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4  = 0x00000001,
3255 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3256 
3257 /*
3258  * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3259  */
3260 
3261 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3262 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei       = 0x00000000,
3263 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi       = 0x00000001,
3264 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi       = 0x00000002,
3265 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED  = 0x00000003,
3266 } FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3267 
3268 /*
3269  * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3270  */
3271 
3272 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3273 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A        = 0x00000000,
3274 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B        = 0x00000001,
3275 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C        = 0x00000002,
3276 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D        = 0x00000003,
3277 } FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3278 
3279 /*
3280  * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3281  */
3282 
3283 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3284 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E        = 0x00000000,
3285 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F        = 0x00000001,
3286 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G        = 0x00000002,
3287 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED  = 0x00000003,
3288 } FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3289 
3290 /*
3291  * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
3292  */
3293 
3294 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3295 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN  = 0x00000000,
3296 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN  = 0x00000001,
3297 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3298 
3299 /*
3300  * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3301  */
3302 
3303 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3304 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR  = 0x00000000,
3305 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB  = 0x00000001,
3306 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3307 
3308 /*
3309  * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3310  */
3311 
3312 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3313 FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC         = 0x00000000,
3314 FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC         = 0x00000001,
3315 FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC        = 0x00000002,
3316 FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC        = 0x00000003,
3317 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1    = 0x00000004,
3318 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2    = 0x00000005,
3319 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3    = 0x00000006,
3320 FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE  = 0x00000007,
3321 } FMT_CLAMP_CNTL_COLOR_FORMAT;
3322 
3323 /*
3324  * FMT_CRC_CNTL_CONT_EN enum
3325  */
3326 
3327 typedef enum FMT_CRC_CNTL_CONT_EN {
3328 FMT_CRC_CNTL_CONT_EN_ONE_SHOT            = 0x00000000,
3329 FMT_CRC_CNTL_CONT_EN_CONT                = 0x00000001,
3330 } FMT_CRC_CNTL_CONT_EN;
3331 
3332 /*
3333  * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
3334  */
3335 
3336 typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3337 FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE  = 0x00000000,
3338 FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE    = 0x00000001,
3339 } FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3340 
3341 /*
3342  * FMT_CRC_CNTL_ONLY_BLANKB enum
3343  */
3344 
3345 typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3346 FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD    = 0x00000000,
3347 FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK       = 0x00000001,
3348 } FMT_CRC_CNTL_ONLY_BLANKB;
3349 
3350 /*
3351  * FMT_CRC_CNTL_PSR_MODE_ENABLE enum
3352  */
3353 
3354 typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3355 FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL      = 0x00000000,
3356 FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC  = 0x00000001,
3357 } FMT_CRC_CNTL_PSR_MODE_ENABLE;
3358 
3359 /*
3360  * FMT_CRC_CNTL_INTERLACE_MODE enum
3361  */
3362 
3363 typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3364 FMT_CRC_CNTL_INTERLACE_MODE_TOP          = 0x00000000,
3365 FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM       = 0x00000001,
3366 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
3367 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH    = 0x00000003,
3368 } FMT_CRC_CNTL_INTERLACE_MODE;
3369 
3370 /*
3371  * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
3372  */
3373 
3374 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3375 FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL     = 0x00000000,
3376 FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN  = 0x00000001,
3377 } FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3378 
3379 /*
3380  * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
3381  */
3382 
3383 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3384 FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN    = 0x00000000,
3385 FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD     = 0x00000001,
3386 } FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3387 
3388 /*
3389  * FMT_DEBUG_CNTL_COLOR_SELECT enum
3390  */
3391 
3392 typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3393 FMT_DEBUG_CNTL_COLOR_SELECT_BLUE         = 0x00000000,
3394 FMT_DEBUG_CNTL_COLOR_SELECT_GREEN        = 0x00000001,
3395 FMT_DEBUG_CNTL_COLOR_SELECT_RED1         = 0x00000002,
3396 FMT_DEBUG_CNTL_COLOR_SELECT_RED2         = 0x00000003,
3397 } FMT_DEBUG_CNTL_COLOR_SELECT;
3398 
3399 /*
3400  * FMT_SPATIAL_DITHER_MODE enum
3401  */
3402 
3403 typedef enum FMT_SPATIAL_DITHER_MODE {
3404 FMT_SPATIAL_DITHER_MODE_0                = 0x00000000,
3405 FMT_SPATIAL_DITHER_MODE_1                = 0x00000001,
3406 FMT_SPATIAL_DITHER_MODE_2                = 0x00000002,
3407 FMT_SPATIAL_DITHER_MODE_3                = 0x00000003,
3408 } FMT_SPATIAL_DITHER_MODE;
3409 
3410 /*
3411  * FMT_STEREOSYNC_OVR_POL enum
3412  */
3413 
3414 typedef enum FMT_STEREOSYNC_OVR_POL {
3415 FMT_STEREOSYNC_OVR_POL_INVERTED          = 0x00000000,
3416 FMT_STEREOSYNC_OVR_POL_NOT_INVERTED      = 0x00000001,
3417 } FMT_STEREOSYNC_OVR_POL;
3418 
3419 /*
3420  * FMT_DYNAMIC_EXP_MODE enum
3421  */
3422 
3423 typedef enum FMT_DYNAMIC_EXP_MODE {
3424 FMT_DYNAMIC_EXP_MODE_10to12              = 0x00000000,
3425 FMT_DYNAMIC_EXP_MODE_8to12               = 0x00000001,
3426 } FMT_DYNAMIC_EXP_MODE;
3427 
3428 /*******************************************************
3429  * HPD Enums
3430  *******************************************************/
3431 
3432 /*
3433  * HPD_INT_CONTROL_ACK enum
3434  */
3435 
3436 typedef enum HPD_INT_CONTROL_ACK {
3437 HPD_INT_CONTROL_ACK_0                    = 0x00000000,
3438 HPD_INT_CONTROL_ACK_1                    = 0x00000001,
3439 } HPD_INT_CONTROL_ACK;
3440 
3441 /*
3442  * HPD_INT_CONTROL_POLARITY enum
3443  */
3444 
3445 typedef enum HPD_INT_CONTROL_POLARITY {
3446 HPD_INT_CONTROL_GEN_INT_ON_DISCON        = 0x00000000,
3447 HPD_INT_CONTROL_GEN_INT_ON_CON           = 0x00000001,
3448 } HPD_INT_CONTROL_POLARITY;
3449 
3450 /*
3451  * HPD_INT_CONTROL_RX_INT_ACK enum
3452  */
3453 
3454 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3455 HPD_INT_CONTROL_RX_INT_ACK_0             = 0x00000000,
3456 HPD_INT_CONTROL_RX_INT_ACK_1             = 0x00000001,
3457 } HPD_INT_CONTROL_RX_INT_ACK;
3458 
3459 /*******************************************************
3460  * LB Enums
3461  *******************************************************/
3462 
3463 /*
3464  * LB_DATA_FORMAT_PIXEL_DEPTH enum
3465  */
3466 
3467 typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3468 LB_DATA_FORMAT_PIXEL_DEPTH_30BPP         = 0x00000000,
3469 LB_DATA_FORMAT_PIXEL_DEPTH_24BPP         = 0x00000001,
3470 LB_DATA_FORMAT_PIXEL_DEPTH_18BPP         = 0x00000002,
3471 LB_DATA_FORMAT_PIXEL_DEPTH_36BPP         = 0x00000003,
3472 } LB_DATA_FORMAT_PIXEL_DEPTH;
3473 
3474 /*
3475  * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
3476  */
3477 
3478 typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3479 LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
3480 LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
3481 } LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3482 
3483 /*
3484  * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
3485  */
3486 
3487 typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3488 LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
3489 LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
3490 } LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3491 
3492 /*
3493  * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
3494  */
3495 
3496 typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3497 LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
3498 LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
3499 } LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3500 
3501 /*
3502  * LB_DATA_FORMAT_INTERLEAVE_EN enum
3503  */
3504 
3505 typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3506 LB_DATA_FORMAT_INTERLEAVE_DISABLE        = 0x00000000,
3507 LB_DATA_FORMAT_INTERLEAVE_ENABLE         = 0x00000001,
3508 } LB_DATA_FORMAT_INTERLEAVE_EN;
3509 
3510 /*
3511  * LB_DATA_FORMAT_REQUEST_MODE enum
3512  */
3513 
3514 typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3515 LB_DATA_FORMAT_REQUEST_MODE_NORMAL       = 0x00000000,
3516 LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE  = 0x00000001,
3517 } LB_DATA_FORMAT_REQUEST_MODE;
3518 
3519 /*
3520  * LB_DATA_FORMAT_ALPHA_EN enum
3521  */
3522 
3523 typedef enum LB_DATA_FORMAT_ALPHA_EN {
3524 LB_DATA_FORMAT_ALPHA_DISABLE             = 0x00000000,
3525 LB_DATA_FORMAT_ALPHA_ENABLE              = 0x00000001,
3526 } LB_DATA_FORMAT_ALPHA_EN;
3527 
3528 /*
3529  * LB_VLINE_START_END_VLINE_INV enum
3530  */
3531 
3532 typedef enum LB_VLINE_START_END_VLINE_INV {
3533 LB_VLINE_START_END_VLINE_NORMAL          = 0x00000000,
3534 LB_VLINE_START_END_VLINE_INVERSE         = 0x00000001,
3535 } LB_VLINE_START_END_VLINE_INV;
3536 
3537 /*
3538  * LB_VLINE2_START_END_VLINE2_INV enum
3539  */
3540 
3541 typedef enum LB_VLINE2_START_END_VLINE2_INV {
3542 LB_VLINE2_START_END_VLINE2_NORMAL        = 0x00000000,
3543 LB_VLINE2_START_END_VLINE2_INVERSE       = 0x00000001,
3544 } LB_VLINE2_START_END_VLINE2_INV;
3545 
3546 /*
3547  * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
3548  */
3549 
3550 typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3551 LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
3552 LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
3553 } LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3554 
3555 /*
3556  * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
3557  */
3558 
3559 typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3560 LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
3561 LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
3562 } LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3563 
3564 /*
3565  * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
3566  */
3567 
3568 typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3569 LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
3570 LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
3571 } LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3572 
3573 /*
3574  * LB_VLINE_STATUS_VLINE_ACK enum
3575  */
3576 
3577 typedef enum LB_VLINE_STATUS_VLINE_ACK {
3578 LB_VLINE_STATUS_VLINE_NORMAL             = 0x00000000,
3579 LB_VLINE_STATUS_VLINE_CLEAR              = 0x00000001,
3580 } LB_VLINE_STATUS_VLINE_ACK;
3581 
3582 /*
3583  * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
3584  */
3585 
3586 typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3587 LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3588 LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3589 } LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3590 
3591 /*
3592  * LB_VLINE2_STATUS_VLINE2_ACK enum
3593  */
3594 
3595 typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3596 LB_VLINE2_STATUS_VLINE2_NORMAL           = 0x00000000,
3597 LB_VLINE2_STATUS_VLINE2_CLEAR            = 0x00000001,
3598 } LB_VLINE2_STATUS_VLINE2_ACK;
3599 
3600 /*
3601  * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
3602  */
3603 
3604 typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3605 LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3606 LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3607 } LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3608 
3609 /*
3610  * LB_VBLANK_STATUS_VBLANK_ACK enum
3611  */
3612 
3613 typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3614 LB_VBLANK_STATUS_VBLANK_NORMAL           = 0x00000000,
3615 LB_VBLANK_STATUS_VBLANK_CLEAR            = 0x00000001,
3616 } LB_VBLANK_STATUS_VBLANK_ACK;
3617 
3618 /*
3619  * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
3620  */
3621 
3622 typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3623 LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3624 LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3625 } LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3626 
3627 /*
3628  * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
3629  */
3630 
3631 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3632 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE  = 0x00000000,
3633 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK  = 0x00000001,
3634 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET  = 0x00000002,
3635 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET  = 0x00000003,
3636 } LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3637 
3638 /*
3639  * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
3640  */
3641 
3642 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3643 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK  = 0x00000000,
3644 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC  = 0x00000001,
3645 } LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3646 
3647 /*
3648  * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
3649  */
3650 
3651 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3652 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
3653 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
3654 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
3655 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
3656 } LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3657 
3658 /*
3659  * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
3660  */
3661 
3662 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3663 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
3664 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
3665 } LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3666 
3667 /*
3668  * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
3669  */
3670 
3671 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3672 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
3673 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
3674 } LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3675 
3676 /*
3677  * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
3678  */
3679 
3680 typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3681 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL  = 0x00000000,
3682 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET   = 0x00000001,
3683 } LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3684 
3685 /*
3686  * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
3687  */
3688 
3689 typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3690 LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL   = 0x00000000,
3691 LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET    = 0x00000001,
3692 } LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3693 
3694 /*
3695  * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
3696  */
3697 
3698 typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3699 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP  = 0x00000002,
3700 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP  = 0x00000003,
3701 } LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3702 
3703 /*
3704  * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
3705  */
3706 
3707 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3708 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
3709 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE  = 0x00000001,
3710 } LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3711 
3712 /*
3713  * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
3714  */
3715 
3716 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3717 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
3718 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
3719 } LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3720 
3721 /*
3722  * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
3723  */
3724 
3725 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3726 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT  = 0x00000000,
3727 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG  = 0x00000001,
3728 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE  = 0x00000002,
3729 } LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3730 
3731 /*
3732  * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
3733  */
3734 
3735 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3736 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE  = 0x00000000,
3737 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN  = 0x00000001,
3738 } LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3739 
3740 /*
3741  * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
3742  */
3743 
3744 typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3745 ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER  = 0x00000001,
3746 ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE  = 0x00000002,
3747 } LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3748 
3749 /*
3750  * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
3751  */
3752 
3753 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3754 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
3755 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
3756 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3757 
3758 /*
3759  * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
3760  */
3761 
3762 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3763 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
3764 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE  = 0x00000001,
3765 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3766 
3767 /*
3768  * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
3769  */
3770 
3771 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3772 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
3773 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO  = 0x00000001,
3774 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3775 
3776 /*
3777  * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
3778  */
3779 
3780 typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3781 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
3782 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
3783 } LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3784 
3785 /*******************************************************
3786  * DIG Enums
3787  *******************************************************/
3788 
3789 /*
3790  * HDMI_KEEPOUT_MODE enum
3791  */
3792 
3793 typedef enum HDMI_KEEPOUT_MODE {
3794 HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC        = 0x00000000,
3795 HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC      = 0x00000001,
3796 } HDMI_KEEPOUT_MODE;
3797 
3798 /*
3799  * HDMI_DATA_SCRAMBLE_EN enum
3800  */
3801 
3802 typedef enum HDMI_DATA_SCRAMBLE_EN {
3803 HDMI_DATA_SCRAMBLE_DISABLE               = 0x00000000,
3804 HDMI_DATA_SCRAMBLE_ENABLE                = 0x00000001,
3805 } HDMI_DATA_SCRAMBLE_EN;
3806 
3807 /*
3808  * HDMI_CLOCK_CHANNEL_RATE enum
3809  */
3810 
3811 typedef enum HDMI_CLOCK_CHANNEL_RATE {
3812 HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE  = 0x00000000,
3813 HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE  = 0x00000001,
3814 } HDMI_CLOCK_CHANNEL_RATE;
3815 
3816 /*
3817  * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
3818  */
3819 
3820 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3821 HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE     = 0x00000000,
3822 HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE    = 0x00000001,
3823 } HDMI_NO_EXTRA_NULL_PACKET_FILLED;
3824 
3825 /*
3826  * HDMI_PACKET_GEN_VERSION enum
3827  */
3828 
3829 typedef enum HDMI_PACKET_GEN_VERSION {
3830 HDMI_PACKET_GEN_VERSION_OLD              = 0x00000000,
3831 HDMI_PACKET_GEN_VERSION_NEW              = 0x00000001,
3832 } HDMI_PACKET_GEN_VERSION;
3833 
3834 /*
3835  * HDMI_ERROR_ACK enum
3836  */
3837 
3838 typedef enum HDMI_ERROR_ACK {
3839 HDMI_ERROR_ACK_INT                       = 0x00000000,
3840 HDMI_ERROR_NOT_ACK                       = 0x00000001,
3841 } HDMI_ERROR_ACK;
3842 
3843 /*
3844  * HDMI_ERROR_MASK enum
3845  */
3846 
3847 typedef enum HDMI_ERROR_MASK {
3848 HDMI_ERROR_MASK_INT                      = 0x00000000,
3849 HDMI_ERROR_NOT_MASK                      = 0x00000001,
3850 } HDMI_ERROR_MASK;
3851 
3852 /*
3853  * HDMI_DEEP_COLOR_DEPTH enum
3854  */
3855 
3856 typedef enum HDMI_DEEP_COLOR_DEPTH {
3857 HDMI_DEEP_COLOR_DEPTH_24BPP              = 0x00000000,
3858 HDMI_DEEP_COLOR_DEPTH_30BPP              = 0x00000001,
3859 HDMI_DEEP_COLOR_DEPTH_36BPP              = 0x00000002,
3860 HDMI_DEEP_COLOR_DEPTH_RESERVED           = 0x00000003,
3861 } HDMI_DEEP_COLOR_DEPTH;
3862 
3863 /*
3864  * HDMI_AUDIO_DELAY_EN enum
3865  */
3866 
3867 typedef enum HDMI_AUDIO_DELAY_EN {
3868 HDMI_AUDIO_DELAY_DISABLE                 = 0x00000000,
3869 HDMI_AUDIO_DELAY_58CLK                   = 0x00000001,
3870 HDMI_AUDIO_DELAY_56CLK                   = 0x00000002,
3871 HDMI_AUDIO_DELAY_RESERVED                = 0x00000003,
3872 } HDMI_AUDIO_DELAY_EN;
3873 
3874 /*
3875  * HDMI_AUDIO_SEND_MAX_PACKETS enum
3876  */
3877 
3878 typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3879 HDMI_NOT_SEND_MAX_AUDIO_PACKETS          = 0x00000000,
3880 HDMI_SEND_MAX_AUDIO_PACKETS              = 0x00000001,
3881 } HDMI_AUDIO_SEND_MAX_PACKETS;
3882 
3883 /*
3884  * HDMI_ACR_SEND enum
3885  */
3886 
3887 typedef enum HDMI_ACR_SEND {
3888 HDMI_ACR_NOT_SEND                        = 0x00000000,
3889 HDMI_ACR_PKT_SEND                        = 0x00000001,
3890 } HDMI_ACR_SEND;
3891 
3892 /*
3893  * HDMI_ACR_CONT enum
3894  */
3895 
3896 typedef enum HDMI_ACR_CONT {
3897 HDMI_ACR_CONT_DISABLE                    = 0x00000000,
3898 HDMI_ACR_CONT_ENABLE                     = 0x00000001,
3899 } HDMI_ACR_CONT;
3900 
3901 /*
3902  * HDMI_ACR_SELECT enum
3903  */
3904 
3905 typedef enum HDMI_ACR_SELECT {
3906 HDMI_ACR_SELECT_HW                       = 0x00000000,
3907 HDMI_ACR_SELECT_32K                      = 0x00000001,
3908 HDMI_ACR_SELECT_44K                      = 0x00000002,
3909 HDMI_ACR_SELECT_48K                      = 0x00000003,
3910 } HDMI_ACR_SELECT;
3911 
3912 /*
3913  * HDMI_ACR_SOURCE enum
3914  */
3915 
3916 typedef enum HDMI_ACR_SOURCE {
3917 HDMI_ACR_SOURCE_HW                       = 0x00000000,
3918 HDMI_ACR_SOURCE_SW                       = 0x00000001,
3919 } HDMI_ACR_SOURCE;
3920 
3921 /*
3922  * HDMI_ACR_N_MULTIPLE enum
3923  */
3924 
3925 typedef enum HDMI_ACR_N_MULTIPLE {
3926 HDMI_ACR_0_MULTIPLE_RESERVED             = 0x00000000,
3927 HDMI_ACR_1_MULTIPLE                      = 0x00000001,
3928 HDMI_ACR_2_MULTIPLE                      = 0x00000002,
3929 HDMI_ACR_3_MULTIPLE_RESERVED             = 0x00000003,
3930 HDMI_ACR_4_MULTIPLE                      = 0x00000004,
3931 HDMI_ACR_5_MULTIPLE_RESERVED             = 0x00000005,
3932 HDMI_ACR_6_MULTIPLE_RESERVED             = 0x00000006,
3933 HDMI_ACR_7_MULTIPLE_RESERVED             = 0x00000007,
3934 } HDMI_ACR_N_MULTIPLE;
3935 
3936 /*
3937  * HDMI_ACR_AUDIO_PRIORITY enum
3938  */
3939 
3940 typedef enum HDMI_ACR_AUDIO_PRIORITY {
3941 HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE  = 0x00000000,
3942 HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT  = 0x00000001,
3943 } HDMI_ACR_AUDIO_PRIORITY;
3944 
3945 /*
3946  * HDMI_NULL_SEND enum
3947  */
3948 
3949 typedef enum HDMI_NULL_SEND {
3950 HDMI_NULL_NOT_SEND                       = 0x00000000,
3951 HDMI_NULL_PKT_SEND                       = 0x00000001,
3952 } HDMI_NULL_SEND;
3953 
3954 /*
3955  * HDMI_GC_SEND enum
3956  */
3957 
3958 typedef enum HDMI_GC_SEND {
3959 HDMI_GC_NOT_SEND                         = 0x00000000,
3960 HDMI_GC_PKT_SEND                         = 0x00000001,
3961 } HDMI_GC_SEND;
3962 
3963 /*
3964  * HDMI_GC_CONT enum
3965  */
3966 
3967 typedef enum HDMI_GC_CONT {
3968 HDMI_GC_CONT_DISABLE                     = 0x00000000,
3969 HDMI_GC_CONT_ENABLE                      = 0x00000001,
3970 } HDMI_GC_CONT;
3971 
3972 /*
3973  * HDMI_ISRC_SEND enum
3974  */
3975 
3976 typedef enum HDMI_ISRC_SEND {
3977 HDMI_ISRC_NOT_SEND                       = 0x00000000,
3978 HDMI_ISRC_PKT_SEND                       = 0x00000001,
3979 } HDMI_ISRC_SEND;
3980 
3981 /*
3982  * HDMI_ISRC_CONT enum
3983  */
3984 
3985 typedef enum HDMI_ISRC_CONT {
3986 HDMI_ISRC_CONT_DISABLE                   = 0x00000000,
3987 HDMI_ISRC_CONT_ENABLE                    = 0x00000001,
3988 } HDMI_ISRC_CONT;
3989 
3990 /*
3991  * HDMI_AVI_INFO_SEND enum
3992  */
3993 
3994 typedef enum HDMI_AVI_INFO_SEND {
3995 HDMI_AVI_INFO_NOT_SEND                   = 0x00000000,
3996 HDMI_AVI_INFO_PKT_SEND                   = 0x00000001,
3997 } HDMI_AVI_INFO_SEND;
3998 
3999 /*
4000  * HDMI_AVI_INFO_CONT enum
4001  */
4002 
4003 typedef enum HDMI_AVI_INFO_CONT {
4004 HDMI_AVI_INFO_CONT_DISABLE               = 0x00000000,
4005 HDMI_AVI_INFO_CONT_ENABLE                = 0x00000001,
4006 } HDMI_AVI_INFO_CONT;
4007 
4008 /*
4009  * HDMI_AUDIO_INFO_SEND enum
4010  */
4011 
4012 typedef enum HDMI_AUDIO_INFO_SEND {
4013 HDMI_AUDIO_INFO_NOT_SEND                 = 0x00000000,
4014 HDMI_AUDIO_INFO_PKT_SEND                 = 0x00000001,
4015 } HDMI_AUDIO_INFO_SEND;
4016 
4017 /*
4018  * HDMI_AUDIO_INFO_CONT enum
4019  */
4020 
4021 typedef enum HDMI_AUDIO_INFO_CONT {
4022 HDMI_AUDIO_INFO_CONT_DISABLE             = 0x00000000,
4023 HDMI_AUDIO_INFO_CONT_ENABLE              = 0x00000001,
4024 } HDMI_AUDIO_INFO_CONT;
4025 
4026 /*
4027  * HDMI_MPEG_INFO_SEND enum
4028  */
4029 
4030 typedef enum HDMI_MPEG_INFO_SEND {
4031 HDMI_MPEG_INFO_NOT_SEND                  = 0x00000000,
4032 HDMI_MPEG_INFO_PKT_SEND                  = 0x00000001,
4033 } HDMI_MPEG_INFO_SEND;
4034 
4035 /*
4036  * HDMI_MPEG_INFO_CONT enum
4037  */
4038 
4039 typedef enum HDMI_MPEG_INFO_CONT {
4040 HDMI_MPEG_INFO_CONT_DISABLE              = 0x00000000,
4041 HDMI_MPEG_INFO_CONT_ENABLE               = 0x00000001,
4042 } HDMI_MPEG_INFO_CONT;
4043 
4044 /*
4045  * HDMI_GENERIC0_SEND enum
4046  */
4047 
4048 typedef enum HDMI_GENERIC0_SEND {
4049 HDMI_GENERIC0_NOT_SEND                   = 0x00000000,
4050 HDMI_GENERIC0_PKT_SEND                   = 0x00000001,
4051 } HDMI_GENERIC0_SEND;
4052 
4053 /*
4054  * HDMI_GENERIC0_CONT enum
4055  */
4056 
4057 typedef enum HDMI_GENERIC0_CONT {
4058 HDMI_GENERIC0_CONT_DISABLE               = 0x00000000,
4059 HDMI_GENERIC0_CONT_ENABLE                = 0x00000001,
4060 } HDMI_GENERIC0_CONT;
4061 
4062 /*
4063  * HDMI_GENERIC1_SEND enum
4064  */
4065 
4066 typedef enum HDMI_GENERIC1_SEND {
4067 HDMI_GENERIC1_NOT_SEND                   = 0x00000000,
4068 HDMI_GENERIC1_PKT_SEND                   = 0x00000001,
4069 } HDMI_GENERIC1_SEND;
4070 
4071 /*
4072  * HDMI_GENERIC1_CONT enum
4073  */
4074 
4075 typedef enum HDMI_GENERIC1_CONT {
4076 HDMI_GENERIC1_CONT_DISABLE               = 0x00000000,
4077 HDMI_GENERIC1_CONT_ENABLE                = 0x00000001,
4078 } HDMI_GENERIC1_CONT;
4079 
4080 /*
4081  * HDMI_GC_AVMUTE_CONT enum
4082  */
4083 
4084 typedef enum HDMI_GC_AVMUTE_CONT {
4085 HDMI_GC_AVMUTE_CONT_DISABLE              = 0x00000000,
4086 HDMI_GC_AVMUTE_CONT_ENABLE               = 0x00000001,
4087 } HDMI_GC_AVMUTE_CONT;
4088 
4089 /*
4090  * HDMI_PACKING_PHASE_OVERRIDE enum
4091  */
4092 
4093 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4094 HDMI_PACKING_PHASE_SET_BY_HW             = 0x00000000,
4095 HDMI_PACKING_PHASE_SET_BY_SW             = 0x00000001,
4096 } HDMI_PACKING_PHASE_OVERRIDE;
4097 
4098 /*
4099  * HDMI_GENERIC2_SEND enum
4100  */
4101 
4102 typedef enum HDMI_GENERIC2_SEND {
4103 HDMI_GENERIC2_NOT_SEND                   = 0x00000000,
4104 HDMI_GENERIC2_PKT_SEND                   = 0x00000001,
4105 } HDMI_GENERIC2_SEND;
4106 
4107 /*
4108  * HDMI_GENERIC2_CONT enum
4109  */
4110 
4111 typedef enum HDMI_GENERIC2_CONT {
4112 HDMI_GENERIC2_CONT_DISABLE               = 0x00000000,
4113 HDMI_GENERIC2_CONT_ENABLE                = 0x00000001,
4114 } HDMI_GENERIC2_CONT;
4115 
4116 /*
4117  * HDMI_GENERIC3_SEND enum
4118  */
4119 
4120 typedef enum HDMI_GENERIC3_SEND {
4121 HDMI_GENERIC3_NOT_SEND                   = 0x00000000,
4122 HDMI_GENERIC3_PKT_SEND                   = 0x00000001,
4123 } HDMI_GENERIC3_SEND;
4124 
4125 /*
4126  * HDMI_GENERIC3_CONT enum
4127  */
4128 
4129 typedef enum HDMI_GENERIC3_CONT {
4130 HDMI_GENERIC3_CONT_DISABLE               = 0x00000000,
4131 HDMI_GENERIC3_CONT_ENABLE                = 0x00000001,
4132 } HDMI_GENERIC3_CONT;
4133 
4134 /*
4135  * TMDS_PIXEL_ENCODING enum
4136  */
4137 
4138 typedef enum TMDS_PIXEL_ENCODING {
4139 TMDS_PIXEL_ENCODING_444_OR_420           = 0x00000000,
4140 TMDS_PIXEL_ENCODING_422                  = 0x00000001,
4141 } TMDS_PIXEL_ENCODING;
4142 
4143 /*
4144  * TMDS_COLOR_FORMAT enum
4145  */
4146 
4147 typedef enum TMDS_COLOR_FORMAT {
4148 TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP  = 0x00000000,
4149 TMDS_COLOR_FORMAT_TWIN30BPP_LSB          = 0x00000001,
4150 TMDS_COLOR_FORMAT_DUAL30BPP              = 0x00000002,
4151 TMDS_COLOR_FORMAT_RESERVED               = 0x00000003,
4152 } TMDS_COLOR_FORMAT;
4153 
4154 /*
4155  * TMDS_STEREOSYNC_CTL_SEL_REG enum
4156  */
4157 
4158 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4159 TMDS_STEREOSYNC_CTL0                     = 0x00000000,
4160 TMDS_STEREOSYNC_CTL1                     = 0x00000001,
4161 TMDS_STEREOSYNC_CTL2                     = 0x00000002,
4162 TMDS_STEREOSYNC_CTL3                     = 0x00000003,
4163 } TMDS_STEREOSYNC_CTL_SEL_REG;
4164 
4165 /*
4166  * TMDS_CTL0_DATA_SEL enum
4167  */
4168 
4169 typedef enum TMDS_CTL0_DATA_SEL {
4170 TMDS_CTL0_DATA_SEL0_RESERVED             = 0x00000000,
4171 TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4172 TMDS_CTL0_DATA_SEL2_VSYNC                = 0x00000002,
4173 TMDS_CTL0_DATA_SEL3_RESERVED             = 0x00000003,
4174 TMDS_CTL0_DATA_SEL4_HSYNC                = 0x00000004,
4175 TMDS_CTL0_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4176 TMDS_CTL0_DATA_SEL8_RANDOM_DATA          = 0x00000006,
4177 TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA    = 0x00000007,
4178 } TMDS_CTL0_DATA_SEL;
4179 
4180 /*
4181  * TMDS_CTL0_DATA_INVERT enum
4182  */
4183 
4184 typedef enum TMDS_CTL0_DATA_INVERT {
4185 TMDS_CTL0_DATA_NORMAL                    = 0x00000000,
4186 TMDS_CTL0_DATA_INVERT_EN                 = 0x00000001,
4187 } TMDS_CTL0_DATA_INVERT;
4188 
4189 /*
4190  * TMDS_CTL0_DATA_MODULATION enum
4191  */
4192 
4193 typedef enum TMDS_CTL0_DATA_MODULATION {
4194 TMDS_CTL0_DATA_MODULATION_DISABLE        = 0x00000000,
4195 TMDS_CTL0_DATA_MODULATION_BIT0           = 0x00000001,
4196 TMDS_CTL0_DATA_MODULATION_BIT1           = 0x00000002,
4197 TMDS_CTL0_DATA_MODULATION_BIT2           = 0x00000003,
4198 } TMDS_CTL0_DATA_MODULATION;
4199 
4200 /*
4201  * TMDS_CTL0_PATTERN_OUT_EN enum
4202  */
4203 
4204 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4205 TMDS_CTL0_PATTERN_OUT_DISABLE            = 0x00000000,
4206 TMDS_CTL0_PATTERN_OUT_ENABLE             = 0x00000001,
4207 } TMDS_CTL0_PATTERN_OUT_EN;
4208 
4209 /*
4210  * TMDS_CTL1_DATA_SEL enum
4211  */
4212 
4213 typedef enum TMDS_CTL1_DATA_SEL {
4214 TMDS_CTL1_DATA_SEL0_RESERVED             = 0x00000000,
4215 TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4216 TMDS_CTL1_DATA_SEL2_VSYNC                = 0x00000002,
4217 TMDS_CTL1_DATA_SEL3_RESERVED             = 0x00000003,
4218 TMDS_CTL1_DATA_SEL4_HSYNC                = 0x00000004,
4219 TMDS_CTL1_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4220 TMDS_CTL1_DATA_SEL8_BLANK_TIME           = 0x00000006,
4221 TMDS_CTL1_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4222 } TMDS_CTL1_DATA_SEL;
4223 
4224 /*
4225  * TMDS_CTL1_DATA_INVERT enum
4226  */
4227 
4228 typedef enum TMDS_CTL1_DATA_INVERT {
4229 TMDS_CTL1_DATA_NORMAL                    = 0x00000000,
4230 TMDS_CTL1_DATA_INVERT_EN                 = 0x00000001,
4231 } TMDS_CTL1_DATA_INVERT;
4232 
4233 /*
4234  * TMDS_CTL1_DATA_MODULATION enum
4235  */
4236 
4237 typedef enum TMDS_CTL1_DATA_MODULATION {
4238 TMDS_CTL1_DATA_MODULATION_DISABLE        = 0x00000000,
4239 TMDS_CTL1_DATA_MODULATION_BIT0           = 0x00000001,
4240 TMDS_CTL1_DATA_MODULATION_BIT1           = 0x00000002,
4241 TMDS_CTL1_DATA_MODULATION_BIT2           = 0x00000003,
4242 } TMDS_CTL1_DATA_MODULATION;
4243 
4244 /*
4245  * TMDS_CTL1_PATTERN_OUT_EN enum
4246  */
4247 
4248 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4249 TMDS_CTL1_PATTERN_OUT_DISABLE            = 0x00000000,
4250 TMDS_CTL1_PATTERN_OUT_ENABLE             = 0x00000001,
4251 } TMDS_CTL1_PATTERN_OUT_EN;
4252 
4253 /*
4254  * TMDS_CTL2_DATA_SEL enum
4255  */
4256 
4257 typedef enum TMDS_CTL2_DATA_SEL {
4258 TMDS_CTL2_DATA_SEL0_RESERVED             = 0x00000000,
4259 TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4260 TMDS_CTL2_DATA_SEL2_VSYNC                = 0x00000002,
4261 TMDS_CTL2_DATA_SEL3_RESERVED             = 0x00000003,
4262 TMDS_CTL2_DATA_SEL4_HSYNC                = 0x00000004,
4263 TMDS_CTL2_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4264 TMDS_CTL2_DATA_SEL8_BLANK_TIME           = 0x00000006,
4265 TMDS_CTL2_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4266 } TMDS_CTL2_DATA_SEL;
4267 
4268 /*
4269  * TMDS_CTL2_DATA_INVERT enum
4270  */
4271 
4272 typedef enum TMDS_CTL2_DATA_INVERT {
4273 TMDS_CTL2_DATA_NORMAL                    = 0x00000000,
4274 TMDS_CTL2_DATA_INVERT_EN                 = 0x00000001,
4275 } TMDS_CTL2_DATA_INVERT;
4276 
4277 /*
4278  * TMDS_CTL2_DATA_MODULATION enum
4279  */
4280 
4281 typedef enum TMDS_CTL2_DATA_MODULATION {
4282 TMDS_CTL2_DATA_MODULATION_DISABLE        = 0x00000000,
4283 TMDS_CTL2_DATA_MODULATION_BIT0           = 0x00000001,
4284 TMDS_CTL2_DATA_MODULATION_BIT1           = 0x00000002,
4285 TMDS_CTL2_DATA_MODULATION_BIT2           = 0x00000003,
4286 } TMDS_CTL2_DATA_MODULATION;
4287 
4288 /*
4289  * TMDS_CTL2_PATTERN_OUT_EN enum
4290  */
4291 
4292 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4293 TMDS_CTL2_PATTERN_OUT_DISABLE            = 0x00000000,
4294 TMDS_CTL2_PATTERN_OUT_ENABLE             = 0x00000001,
4295 } TMDS_CTL2_PATTERN_OUT_EN;
4296 
4297 /*
4298  * TMDS_CTL3_DATA_INVERT enum
4299  */
4300 
4301 typedef enum TMDS_CTL3_DATA_INVERT {
4302 TMDS_CTL3_DATA_NORMAL                    = 0x00000000,
4303 TMDS_CTL3_DATA_INVERT_EN                 = 0x00000001,
4304 } TMDS_CTL3_DATA_INVERT;
4305 
4306 /*
4307  * TMDS_CTL3_DATA_MODULATION enum
4308  */
4309 
4310 typedef enum TMDS_CTL3_DATA_MODULATION {
4311 TMDS_CTL3_DATA_MODULATION_DISABLE        = 0x00000000,
4312 TMDS_CTL3_DATA_MODULATION_BIT0           = 0x00000001,
4313 TMDS_CTL3_DATA_MODULATION_BIT1           = 0x00000002,
4314 TMDS_CTL3_DATA_MODULATION_BIT2           = 0x00000003,
4315 } TMDS_CTL3_DATA_MODULATION;
4316 
4317 /*
4318  * TMDS_CTL3_PATTERN_OUT_EN enum
4319  */
4320 
4321 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4322 TMDS_CTL3_PATTERN_OUT_DISABLE            = 0x00000000,
4323 TMDS_CTL3_PATTERN_OUT_ENABLE             = 0x00000001,
4324 } TMDS_CTL3_PATTERN_OUT_EN;
4325 
4326 /*
4327  * TMDS_CTL3_DATA_SEL enum
4328  */
4329 
4330 typedef enum TMDS_CTL3_DATA_SEL {
4331 TMDS_CTL3_DATA_SEL0_RESERVED             = 0x00000000,
4332 TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4333 TMDS_CTL3_DATA_SEL2_VSYNC                = 0x00000002,
4334 TMDS_CTL3_DATA_SEL3_RESERVED             = 0x00000003,
4335 TMDS_CTL3_DATA_SEL4_HSYNC                = 0x00000004,
4336 TMDS_CTL3_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4337 TMDS_CTL3_DATA_SEL8_BLANK_TIME           = 0x00000006,
4338 TMDS_CTL3_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4339 } TMDS_CTL3_DATA_SEL;
4340 
4341 /*
4342  * DIG_FE_CNTL_SOURCE_SELECT enum
4343  */
4344 
4345 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4346 DIG_FE_SOURCE_FROM_FMT0                  = 0x00000000,
4347 DIG_FE_SOURCE_FROM_FMT1                  = 0x00000001,
4348 DIG_FE_SOURCE_FROM_FMT2                  = 0x00000002,
4349 DIG_FE_SOURCE_FROM_FMT3                  = 0x00000003,
4350 DIG_FE_SOURCE_FROM_FMT4                  = 0x00000004,
4351 DIG_FE_SOURCE_FROM_FMT5                  = 0x00000005,
4352 } DIG_FE_CNTL_SOURCE_SELECT;
4353 
4354 /*
4355  * DIG_FE_CNTL_STEREOSYNC_SELECT enum
4356  */
4357 
4358 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4359 DIG_FE_STEREOSYNC_FROM_FMT0              = 0x00000000,
4360 DIG_FE_STEREOSYNC_FROM_FMT1              = 0x00000001,
4361 DIG_FE_STEREOSYNC_FROM_FMT2              = 0x00000002,
4362 DIG_FE_STEREOSYNC_FROM_FMT3              = 0x00000003,
4363 DIG_FE_STEREOSYNC_FROM_FMT4              = 0x00000004,
4364 DIG_FE_STEREOSYNC_FROM_FMT5              = 0x00000005,
4365 } DIG_FE_CNTL_STEREOSYNC_SELECT;
4366 
4367 /*
4368  * DIG_FIFO_READ_CLOCK_SRC enum
4369  */
4370 
4371 typedef enum DIG_FIFO_READ_CLOCK_SRC {
4372 DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG        = 0x00000000,
4373 DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE  = 0x00000001,
4374 } DIG_FIFO_READ_CLOCK_SRC;
4375 
4376 /*
4377  * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
4378  */
4379 
4380 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4381 DIG_OUTPUT_CRC_ON_LINK0                  = 0x00000000,
4382 DIG_OUTPUT_CRC_ON_LINK1                  = 0x00000001,
4383 } DIG_OUTPUT_CRC_CNTL_LINK_SEL;
4384 
4385 /*
4386  * DIG_OUTPUT_CRC_DATA_SEL enum
4387  */
4388 
4389 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4390 DIG_OUTPUT_CRC_FOR_FULLFRAME             = 0x00000000,
4391 DIG_OUTPUT_CRC_FOR_ACTIVEONLY            = 0x00000001,
4392 DIG_OUTPUT_CRC_FOR_VBI                   = 0x00000002,
4393 DIG_OUTPUT_CRC_FOR_AUDIO                 = 0x00000003,
4394 } DIG_OUTPUT_CRC_DATA_SEL;
4395 
4396 /*
4397  * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
4398  */
4399 
4400 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4401 DIG_IN_NORMAL_OPERATION                  = 0x00000000,
4402 DIG_IN_DEBUG_MODE                        = 0x00000001,
4403 } DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
4404 
4405 /*
4406  * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
4407  */
4408 
4409 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4410 DIG_10BIT_TEST_PATTERN                   = 0x00000000,
4411 DIG_ALTERNATING_TEST_PATTERN             = 0x00000001,
4412 } DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
4413 
4414 /*
4415  * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
4416  */
4417 
4418 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4419 DIG_TEST_PATTERN_NORMAL                  = 0x00000000,
4420 DIG_TEST_PATTERN_RANDOM                  = 0x00000001,
4421 } DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
4422 
4423 /*
4424  * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
4425  */
4426 
4427 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4428 DIG_RANDOM_PATTERN_ENABLED               = 0x00000000,
4429 DIG_RANDOM_PATTERN_RESETED               = 0x00000001,
4430 } DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
4431 
4432 /*
4433  * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
4434  */
4435 
4436 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4437 DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE   = 0x00000000,
4438 DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG  = 0x00000001,
4439 } DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
4440 
4441 /*
4442  * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
4443  */
4444 
4445 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4446 DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS  = 0x00000000,
4447 DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH  = 0x00000001,
4448 } DIG_RANDOM_PATTERN_SEED_RAN_PAT;
4449 
4450 /*
4451  * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
4452  */
4453 
4454 typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4455 DIG_FIFO_USE_OVERWRITE_LEVEL             = 0x00000000,
4456 DIG_FIFO_USE_CAL_AVERAGE_LEVEL           = 0x00000001,
4457 } DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
4458 
4459 /*
4460  * DIG_FIFO_ERROR_ACK enum
4461  */
4462 
4463 typedef enum DIG_FIFO_ERROR_ACK {
4464 DIG_FIFO_ERROR_ACK_INT                   = 0x00000000,
4465 DIG_FIFO_ERROR_NOT_ACK                   = 0x00000001,
4466 } DIG_FIFO_ERROR_ACK;
4467 
4468 /*
4469  * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
4470  */
4471 
4472 typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4473 DIG_FIFO_NOT_FORCE_RECAL_AVERAGE         = 0x00000000,
4474 DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL       = 0x00000001,
4475 } DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
4476 
4477 /*
4478  * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
4479  */
4480 
4481 typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4482 DIG_FIFO_NOT_FORCE_RECOMP_MINMAX         = 0x00000000,
4483 DIG_FIFO_FORCE_RECOMP_MINMAX             = 0x00000001,
4484 } DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
4485 
4486 /*
4487  * AFMT_INTERRUPT_STATUS_CHG_MASK enum
4488  */
4489 
4490 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4491 AFMT_INTERRUPT_DISABLE                   = 0x00000000,
4492 AFMT_INTERRUPT_ENABLE                    = 0x00000001,
4493 } AFMT_INTERRUPT_STATUS_CHG_MASK;
4494 
4495 /*
4496  * HDMI_GC_AVMUTE enum
4497  */
4498 
4499 typedef enum HDMI_GC_AVMUTE {
4500 HDMI_GC_AVMUTE_SET                       = 0x00000000,
4501 HDMI_GC_AVMUTE_UNSET                     = 0x00000001,
4502 } HDMI_GC_AVMUTE;
4503 
4504 /*
4505  * HDMI_DEFAULT_PAHSE enum
4506  */
4507 
4508 typedef enum HDMI_DEFAULT_PAHSE {
4509 HDMI_DEFAULT_PHASE_IS_0                  = 0x00000000,
4510 HDMI_DEFAULT_PHASE_IS_1                  = 0x00000001,
4511 } HDMI_DEFAULT_PAHSE;
4512 
4513 /*
4514  * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
4515  */
4516 
4517 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4518 AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS  = 0x00000000,
4519 AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER       = 0x00000001,
4520 } AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
4521 
4522 /*
4523  * AUDIO_LAYOUT_SELECT enum
4524  */
4525 
4526 typedef enum AUDIO_LAYOUT_SELECT {
4527 AUDIO_LAYOUT_0                           = 0x00000000,
4528 AUDIO_LAYOUT_1                           = 0x00000001,
4529 } AUDIO_LAYOUT_SELECT;
4530 
4531 /*
4532  * AFMT_AUDIO_CRC_CONTROL_CONT enum
4533  */
4534 
4535 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4536 AFMT_AUDIO_CRC_ONESHOT                   = 0x00000000,
4537 AFMT_AUDIO_CRC_AUTO_RESTART              = 0x00000001,
4538 } AFMT_AUDIO_CRC_CONTROL_CONT;
4539 
4540 /*
4541  * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
4542  */
4543 
4544 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4545 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT    = 0x00000000,
4546 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT   = 0x00000001,
4547 } AFMT_AUDIO_CRC_CONTROL_SOURCE;
4548 
4549 /*
4550  * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
4551  */
4552 
4553 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4554 AFMT_AUDIO_CRC_CH0_SIG                   = 0x00000000,
4555 AFMT_AUDIO_CRC_CH1_SIG                   = 0x00000001,
4556 AFMT_AUDIO_CRC_CH2_SIG                   = 0x00000002,
4557 AFMT_AUDIO_CRC_CH3_SIG                   = 0x00000003,
4558 AFMT_AUDIO_CRC_CH4_SIG                   = 0x00000004,
4559 AFMT_AUDIO_CRC_CH5_SIG                   = 0x00000005,
4560 AFMT_AUDIO_CRC_CH6_SIG                   = 0x00000006,
4561 AFMT_AUDIO_CRC_CH7_SIG                   = 0x00000007,
4562 AFMT_AUDIO_CRC_RESERVED_8                = 0x00000008,
4563 AFMT_AUDIO_CRC_RESERVED_9                = 0x00000009,
4564 AFMT_AUDIO_CRC_RESERVED_10               = 0x0000000a,
4565 AFMT_AUDIO_CRC_RESERVED_11               = 0x0000000b,
4566 AFMT_AUDIO_CRC_RESERVED_12               = 0x0000000c,
4567 AFMT_AUDIO_CRC_RESERVED_13               = 0x0000000d,
4568 AFMT_AUDIO_CRC_RESERVED_14               = 0x0000000e,
4569 AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT        = 0x0000000f,
4570 } AFMT_AUDIO_CRC_CONTROL_CH_SEL;
4571 
4572 /*
4573  * AFMT_RAMP_CONTROL0_SIGN enum
4574  */
4575 
4576 typedef enum AFMT_RAMP_CONTROL0_SIGN {
4577 AFMT_RAMP_SIGNED                         = 0x00000000,
4578 AFMT_RAMP_UNSIGNED                       = 0x00000001,
4579 } AFMT_RAMP_CONTROL0_SIGN;
4580 
4581 /*
4582  * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
4583  */
4584 
4585 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
4586 AFMT_AUDIO_PACKET_SENT_DISABLED          = 0x00000000,
4587 AFMT_AUDIO_PACKET_SENT_ENABLED           = 0x00000001,
4588 } AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
4589 
4590 /*
4591  * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
4592  */
4593 
4594 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
4595 AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED  = 0x00000000,
4596 AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED  = 0x00000001,
4597 } AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
4598 
4599 /*
4600  * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
4601  */
4602 
4603 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
4604 AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK  = 0x00000000,
4605 AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS  = 0x00000001,
4606 } AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
4607 
4608 /*
4609  * AFMT_AUDIO_SRC_CONTROL_SELECT enum
4610  */
4611 
4612 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
4613 AFMT_AUDIO_SRC_FROM_AZ_STREAM0           = 0x00000000,
4614 AFMT_AUDIO_SRC_FROM_AZ_STREAM1           = 0x00000001,
4615 AFMT_AUDIO_SRC_FROM_AZ_STREAM2           = 0x00000002,
4616 AFMT_AUDIO_SRC_FROM_AZ_STREAM3           = 0x00000003,
4617 AFMT_AUDIO_SRC_FROM_AZ_STREAM4           = 0x00000004,
4618 AFMT_AUDIO_SRC_FROM_AZ_STREAM5           = 0x00000005,
4619 AFMT_AUDIO_SRC_RESERVED                  = 0x00000006,
4620 } AFMT_AUDIO_SRC_CONTROL_SELECT;
4621 
4622 /*
4623  * DIG_BE_CNTL_MODE enum
4624  */
4625 
4626 typedef enum DIG_BE_CNTL_MODE {
4627 DIG_BE_DP_SST_MODE                       = 0x00000000,
4628 DIG_BE_RESERVED1                         = 0x00000001,
4629 DIG_BE_TMDS_DVI_MODE                     = 0x00000002,
4630 DIG_BE_TMDS_HDMI_MODE                    = 0x00000003,
4631 DIG_BE_SDVO_RESERVED                     = 0x00000004,
4632 DIG_BE_DP_MST_MODE                       = 0x00000005,
4633 DIG_BE_RESERVED2                         = 0x00000006,
4634 DIG_BE_RESERVED3                         = 0x00000007,
4635 } DIG_BE_CNTL_MODE;
4636 
4637 /*
4638  * DIG_BE_CNTL_HPD_SELECT enum
4639  */
4640 
4641 typedef enum DIG_BE_CNTL_HPD_SELECT {
4642 DIG_BE_CNTL_HPD1                         = 0x00000000,
4643 DIG_BE_CNTL_HPD2                         = 0x00000001,
4644 DIG_BE_CNTL_HPD3                         = 0x00000002,
4645 DIG_BE_CNTL_HPD4                         = 0x00000003,
4646 DIG_BE_CNTL_HPD5                         = 0x00000004,
4647 DIG_BE_CNTL_HPD6                         = 0x00000005,
4648 } DIG_BE_CNTL_HPD_SELECT;
4649 
4650 /*
4651  * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
4652  */
4653 
4654 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
4655 LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS     = 0x00000000,
4656 LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH   = 0x00000001,
4657 } LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
4658 
4659 /*
4660  * TMDS_SYNC_PHASE enum
4661  */
4662 
4663 typedef enum TMDS_SYNC_PHASE {
4664 TMDS_NOT_SYNC_PHASE_ON_FRAME_START       = 0x00000000,
4665 TMDS_SYNC_PHASE_ON_FRAME_START           = 0x00000001,
4666 } TMDS_SYNC_PHASE;
4667 
4668 /*
4669  * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
4670  */
4671 
4672 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
4673 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS  = 0x00000000,
4674 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL  = 0x00000001,
4675 } TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
4676 
4677 /*
4678  * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
4679  */
4680 
4681 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
4682 TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE   = 0x00000000,
4683 TMDS_TRANSMITTER_HPD_MASK_OVERRIDE       = 0x00000001,
4684 } TMDS_TRANSMITTER_ENABLE_HPD_MASK;
4685 
4686 /*
4687  * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
4688  */
4689 
4690 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
4691 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
4692 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE  = 0x00000001,
4693 } TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
4694 
4695 /*
4696  * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
4697  */
4698 
4699 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
4700 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
4701 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE  = 0x00000001,
4702 } TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
4703 
4704 /*
4705  * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
4706  */
4707 
4708 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
4709 TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE  = 0x00000000,
4710 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON  = 0x00000001,
4711 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x00000002,
4712 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE  = 0x00000003,
4713 } TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
4714 
4715 /*
4716  * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
4717  */
4718 
4719 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
4720 TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK   = 0x00000000,
4721 TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK     = 0x00000001,
4722 } TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
4723 
4724 /*
4725  * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
4726  */
4727 
4728 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
4729 TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK   = 0x00000000,
4730 TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK     = 0x00000001,
4731 } TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
4732 
4733 /*
4734  * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
4735  */
4736 
4737 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
4738 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE   = 0x00000000,
4739 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE    = 0x00000001,
4740 } TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
4741 
4742 /*
4743  * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
4744  */
4745 
4746 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
4747 TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD      = 0x00000000,
4748 TMDS_TRANSMITTER_PLL_RST_ON_HPD          = 0x00000001,
4749 } TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
4750 
4751 /*
4752  * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
4753  */
4754 
4755 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
4756 TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK   = 0x00000000,
4757 TMDS_TRANSMITTER_TMCLK_FROM_PADS         = 0x00000001,
4758 } TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
4759 
4760 /*
4761  * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
4762  */
4763 
4764 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
4765 TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK   = 0x00000000,
4766 TMDS_TRANSMITTER_TDCLK_FROM_PADS         = 0x00000001,
4767 } TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
4768 
4769 /*
4770  * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
4771  */
4772 
4773 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
4774 TMDS_TRANSMITTER_PLLSEL_BY_HW            = 0x00000000,
4775 TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW  = 0x00000001,
4776 } TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
4777 
4778 /*
4779  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
4780  */
4781 
4782 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
4783 TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT    = 0x00000000,
4784 TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT  = 0x00000001,
4785 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
4786 
4787 /*
4788  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
4789  */
4790 
4791 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
4792 TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT    = 0x00000000,
4793 TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT  = 0x00000001,
4794 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
4795 
4796 /*
4797  * TMDS_REG_TEST_OUTPUTA_CNTLA enum
4798  */
4799 
4800 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
4801 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0      = 0x00000000,
4802 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1      = 0x00000001,
4803 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2      = 0x00000002,
4804 TMDS_REG_TEST_OUTPUTA_CNTLA_NA           = 0x00000003,
4805 } TMDS_REG_TEST_OUTPUTA_CNTLA;
4806 
4807 /*
4808  * TMDS_REG_TEST_OUTPUTB_CNTLB enum
4809  */
4810 
4811 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
4812 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0      = 0x00000000,
4813 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1      = 0x00000001,
4814 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2      = 0x00000002,
4815 TMDS_REG_TEST_OUTPUTB_CNTLB_NA           = 0x00000003,
4816 } TMDS_REG_TEST_OUTPUTB_CNTLB;
4817 
4818 /*******************************************************
4819  * DCP Enums
4820  *******************************************************/
4821 
4822 /*
4823  * DCP_GRPH_ENABLE enum
4824  */
4825 
4826 typedef enum DCP_GRPH_ENABLE {
4827 DCP_GRPH_ENABLE_FALSE                    = 0x00000000,
4828 DCP_GRPH_ENABLE_TRUE                     = 0x00000001,
4829 } DCP_GRPH_ENABLE;
4830 
4831 /*
4832  * DCP_GRPH_KEYER_ALPHA_SEL enum
4833  */
4834 
4835 typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
4836 DCP_GRPH_KEYER_ALPHA_SEL_FALSE           = 0x00000000,
4837 DCP_GRPH_KEYER_ALPHA_SEL_TRUE            = 0x00000001,
4838 } DCP_GRPH_KEYER_ALPHA_SEL;
4839 
4840 /*
4841  * DCP_GRPH_DEPTH enum
4842  */
4843 
4844 typedef enum DCP_GRPH_DEPTH {
4845 DCP_GRPH_DEPTH_8BPP                      = 0x00000000,
4846 DCP_GRPH_DEPTH_16BPP                     = 0x00000001,
4847 DCP_GRPH_DEPTH_32BPP                     = 0x00000002,
4848 DCP_GRPH_DEPTH_64BPP                     = 0x00000003,
4849 } DCP_GRPH_DEPTH;
4850 
4851 /*
4852  * DCP_GRPH_NUM_BANKS enum
4853  */
4854 
4855 typedef enum DCP_GRPH_NUM_BANKS {
4856 DCP_GRPH_NUM_BANKS_1BANK                 = 0x00000000,
4857 DCP_GRPH_NUM_BANKS_2BANK                 = 0x00000001,
4858 DCP_GRPH_NUM_BANKS_4BANK                 = 0x00000002,
4859 DCP_GRPH_NUM_BANKS_8BANK                 = 0x00000003,
4860 DCP_GRPH_NUM_BANKS_16BANK                = 0x00000004,
4861 } DCP_GRPH_NUM_BANKS;
4862 
4863 /*
4864  * DCP_GRPH_NUM_PIPES enum
4865  */
4866 
4867 typedef enum DCP_GRPH_NUM_PIPES {
4868 DCP_GRPH_NUM_PIPES_1PIPE                 = 0x00000000,
4869 DCP_GRPH_NUM_PIPES_2PIPE                 = 0x00000001,
4870 DCP_GRPH_NUM_PIPES_4PIPE                 = 0x00000002,
4871 DCP_GRPH_NUM_PIPES_8PIPE                 = 0x00000003,
4872 } DCP_GRPH_NUM_PIPES;
4873 
4874 /*
4875  * DCP_GRPH_FORMAT enum
4876  */
4877 
4878 typedef enum DCP_GRPH_FORMAT {
4879 DCP_GRPH_FORMAT_8BPP                     = 0x00000000,
4880 DCP_GRPH_FORMAT_16BPP                    = 0x00000001,
4881 DCP_GRPH_FORMAT_32BPP                    = 0x00000002,
4882 DCP_GRPH_FORMAT_64BPP                    = 0x00000003,
4883 } DCP_GRPH_FORMAT;
4884 
4885 /*
4886  * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
4887  */
4888 
4889 typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4890 DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE  = 0x00000000,
4891 DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE  = 0x00000001,
4892 } DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
4893 
4894 /*
4895  * DCP_GRPH_SW_MODE enum
4896  */
4897 
4898 typedef enum DCP_GRPH_SW_MODE {
4899 DCP_GRPH_SW_MODE_0                       = 0x00000000,
4900 DCP_GRPH_SW_MODE_2                       = 0x00000002,
4901 DCP_GRPH_SW_MODE_3                       = 0x00000003,
4902 DCP_GRPH_SW_MODE_22                      = 0x00000016,
4903 DCP_GRPH_SW_MODE_23                      = 0x00000017,
4904 DCP_GRPH_SW_MODE_26                      = 0x0000001a,
4905 DCP_GRPH_SW_MODE_27                      = 0x0000001b,
4906 DCP_GRPH_SW_MODE_30                      = 0x0000001e,
4907 DCP_GRPH_SW_MODE_31                      = 0x0000001f,
4908 } DCP_GRPH_SW_MODE;
4909 
4910 /*
4911  * DCP_GRPH_COLOR_EXPANSION_MODE enum
4912  */
4913 
4914 typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
4915 DCP_GRPH_COLOR_EXPANSION_MODE_DEXP       = 0x00000000,
4916 DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP       = 0x00000001,
4917 } DCP_GRPH_COLOR_EXPANSION_MODE;
4918 
4919 /*
4920  * DCP_GRPH_LUT_10BIT_BYPASS_EN enum
4921  */
4922 
4923 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
4924 DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE       = 0x00000000,
4925 DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE        = 0x00000001,
4926 } DCP_GRPH_LUT_10BIT_BYPASS_EN;
4927 
4928 /*
4929  * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum
4930  */
4931 
4932 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
4933 DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE  = 0x00000000,
4934 DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE  = 0x00000001,
4935 } DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
4936 
4937 /*
4938  * DCP_GRPH_ENDIAN_SWAP enum
4939  */
4940 
4941 typedef enum DCP_GRPH_ENDIAN_SWAP {
4942 DCP_GRPH_ENDIAN_SWAP_NONE                = 0x00000000,
4943 DCP_GRPH_ENDIAN_SWAP_8IN16               = 0x00000001,
4944 DCP_GRPH_ENDIAN_SWAP_8IN32               = 0x00000002,
4945 DCP_GRPH_ENDIAN_SWAP_8IN64               = 0x00000003,
4946 } DCP_GRPH_ENDIAN_SWAP;
4947 
4948 /*
4949  * DCP_GRPH_RED_CROSSBAR enum
4950  */
4951 
4952 typedef enum DCP_GRPH_RED_CROSSBAR {
4953 DCP_GRPH_RED_CROSSBAR_FROM_R             = 0x00000000,
4954 DCP_GRPH_RED_CROSSBAR_FROM_G             = 0x00000001,
4955 DCP_GRPH_RED_CROSSBAR_FROM_B             = 0x00000002,
4956 DCP_GRPH_RED_CROSSBAR_FROM_A             = 0x00000003,
4957 } DCP_GRPH_RED_CROSSBAR;
4958 
4959 /*
4960  * DCP_GRPH_GREEN_CROSSBAR enum
4961  */
4962 
4963 typedef enum DCP_GRPH_GREEN_CROSSBAR {
4964 DCP_GRPH_GREEN_CROSSBAR_FROM_G           = 0x00000000,
4965 DCP_GRPH_GREEN_CROSSBAR_FROM_B           = 0x00000001,
4966 DCP_GRPH_GREEN_CROSSBAR_FROM_A           = 0x00000002,
4967 DCP_GRPH_GREEN_CROSSBAR_FROM_R           = 0x00000003,
4968 } DCP_GRPH_GREEN_CROSSBAR;
4969 
4970 /*
4971  * DCP_GRPH_BLUE_CROSSBAR enum
4972  */
4973 
4974 typedef enum DCP_GRPH_BLUE_CROSSBAR {
4975 DCP_GRPH_BLUE_CROSSBAR_FROM_B            = 0x00000000,
4976 DCP_GRPH_BLUE_CROSSBAR_FROM_A            = 0x00000001,
4977 DCP_GRPH_BLUE_CROSSBAR_FROM_R            = 0x00000002,
4978 DCP_GRPH_BLUE_CROSSBAR_FROM_G            = 0x00000003,
4979 } DCP_GRPH_BLUE_CROSSBAR;
4980 
4981 /*
4982  * DCP_GRPH_ALPHA_CROSSBAR enum
4983  */
4984 
4985 typedef enum DCP_GRPH_ALPHA_CROSSBAR {
4986 DCP_GRPH_ALPHA_CROSSBAR_FROM_A           = 0x00000000,
4987 DCP_GRPH_ALPHA_CROSSBAR_FROM_R           = 0x00000001,
4988 DCP_GRPH_ALPHA_CROSSBAR_FROM_G           = 0x00000002,
4989 DCP_GRPH_ALPHA_CROSSBAR_FROM_B           = 0x00000003,
4990 } DCP_GRPH_ALPHA_CROSSBAR;
4991 
4992 /*
4993  * DCP_GRPH_PRIMARY_DFQ_ENABLE enum
4994  */
4995 
4996 typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
4997 DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE        = 0x00000000,
4998 DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE         = 0x00000001,
4999 } DCP_GRPH_PRIMARY_DFQ_ENABLE;
5000 
5001 /*
5002  * DCP_GRPH_SECONDARY_DFQ_ENABLE enum
5003  */
5004 
5005 typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
5006 DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE      = 0x00000000,
5007 DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE       = 0x00000001,
5008 } DCP_GRPH_SECONDARY_DFQ_ENABLE;
5009 
5010 /*
5011  * DCP_GRPH_INPUT_GAMMA_MODE enum
5012  */
5013 
5014 typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
5015 DCP_GRPH_INPUT_GAMMA_MODE_LUT            = 0x00000000,
5016 DCP_GRPH_INPUT_GAMMA_MODE_BYPASS         = 0x00000001,
5017 } DCP_GRPH_INPUT_GAMMA_MODE;
5018 
5019 /*
5020  * DCP_GRPH_MODE_UPDATE_PENDING enum
5021  */
5022 
5023 typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
5024 DCP_GRPH_MODE_UPDATE_PENDING_FALSE       = 0x00000000,
5025 DCP_GRPH_MODE_UPDATE_PENDING_TRUE        = 0x00000001,
5026 } DCP_GRPH_MODE_UPDATE_PENDING;
5027 
5028 /*
5029  * DCP_GRPH_MODE_UPDATE_TAKEN enum
5030  */
5031 
5032 typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
5033 DCP_GRPH_MODE_UPDATE_TAKEN_FALSE         = 0x00000000,
5034 DCP_GRPH_MODE_UPDATE_TAKEN_TRUE          = 0x00000001,
5035 } DCP_GRPH_MODE_UPDATE_TAKEN;
5036 
5037 /*
5038  * DCP_GRPH_SURFACE_UPDATE_PENDING enum
5039  */
5040 
5041 typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
5042 DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE    = 0x00000000,
5043 DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE     = 0x00000001,
5044 } DCP_GRPH_SURFACE_UPDATE_PENDING;
5045 
5046 /*
5047  * DCP_GRPH_SURFACE_UPDATE_TAKEN enum
5048  */
5049 
5050 typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
5051 DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE      = 0x00000000,
5052 DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE       = 0x00000001,
5053 } DCP_GRPH_SURFACE_UPDATE_TAKEN;
5054 
5055 /*
5056  * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum
5057  */
5058 
5059 typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
5060 DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000,
5061 DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001,
5062 } DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
5063 
5064 /*
5065  * DCP_GRPH_UPDATE_LOCK enum
5066  */
5067 
5068 typedef enum DCP_GRPH_UPDATE_LOCK {
5069 DCP_GRPH_UPDATE_LOCK_FALSE               = 0x00000000,
5070 DCP_GRPH_UPDATE_LOCK_TRUE                = 0x00000001,
5071 } DCP_GRPH_UPDATE_LOCK;
5072 
5073 /*
5074  * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
5075  */
5076 
5077 typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
5078 DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE  = 0x00000000,
5079 DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE  = 0x00000001,
5080 } DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
5081 
5082 /*
5083  * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
5084  */
5085 
5086 typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
5087 DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5088 DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5089 } DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
5090 
5091 /*
5092  * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
5093  */
5094 
5095 typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
5096 DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5097 DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5098 } DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
5099 
5100 /*
5101  * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum
5102  */
5103 
5104 typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
5105 DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE  = 0x00000000,
5106 DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE  = 0x00000001,
5107 } DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
5108 
5109 /*
5110  * DCP_GRPH_XDMA_SUPER_AA_EN enum
5111  */
5112 
5113 typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
5114 DCP_GRPH_XDMA_SUPER_AA_EN_FALSE          = 0x00000000,
5115 DCP_GRPH_XDMA_SUPER_AA_EN_TRUE           = 0x00000001,
5116 } DCP_GRPH_XDMA_SUPER_AA_EN;
5117 
5118 /*
5119  * DCP_GRPH_DFQ_RESET enum
5120  */
5121 
5122 typedef enum DCP_GRPH_DFQ_RESET {
5123 DCP_GRPH_DFQ_RESET_FALSE                 = 0x00000000,
5124 DCP_GRPH_DFQ_RESET_TRUE                  = 0x00000001,
5125 } DCP_GRPH_DFQ_RESET;
5126 
5127 /*
5128  * DCP_GRPH_DFQ_SIZE enum
5129  */
5130 
5131 typedef enum DCP_GRPH_DFQ_SIZE {
5132 DCP_GRPH_DFQ_SIZE_DEEP1                  = 0x00000000,
5133 DCP_GRPH_DFQ_SIZE_DEEP2                  = 0x00000001,
5134 DCP_GRPH_DFQ_SIZE_DEEP3                  = 0x00000002,
5135 DCP_GRPH_DFQ_SIZE_DEEP4                  = 0x00000003,
5136 DCP_GRPH_DFQ_SIZE_DEEP5                  = 0x00000004,
5137 DCP_GRPH_DFQ_SIZE_DEEP6                  = 0x00000005,
5138 DCP_GRPH_DFQ_SIZE_DEEP7                  = 0x00000006,
5139 DCP_GRPH_DFQ_SIZE_DEEP8                  = 0x00000007,
5140 } DCP_GRPH_DFQ_SIZE;
5141 
5142 /*
5143  * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum
5144  */
5145 
5146 typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
5147 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1          = 0x00000000,
5148 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2          = 0x00000001,
5149 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3          = 0x00000002,
5150 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4          = 0x00000003,
5151 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5          = 0x00000004,
5152 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6          = 0x00000005,
5153 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7          = 0x00000006,
5154 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8          = 0x00000007,
5155 } DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
5156 
5157 /*
5158  * DCP_GRPH_DFQ_RESET_ACK enum
5159  */
5160 
5161 typedef enum DCP_GRPH_DFQ_RESET_ACK {
5162 DCP_GRPH_DFQ_RESET_ACK_FALSE             = 0x00000000,
5163 DCP_GRPH_DFQ_RESET_ACK_TRUE              = 0x00000001,
5164 } DCP_GRPH_DFQ_RESET_ACK;
5165 
5166 /*
5167  * DCP_GRPH_PFLIP_INT_CLEAR enum
5168  */
5169 
5170 typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
5171 DCP_GRPH_PFLIP_INT_CLEAR_FALSE           = 0x00000000,
5172 DCP_GRPH_PFLIP_INT_CLEAR_TRUE            = 0x00000001,
5173 } DCP_GRPH_PFLIP_INT_CLEAR;
5174 
5175 /*
5176  * DCP_GRPH_PFLIP_INT_MASK enum
5177  */
5178 
5179 typedef enum DCP_GRPH_PFLIP_INT_MASK {
5180 DCP_GRPH_PFLIP_INT_MASK_FALSE            = 0x00000000,
5181 DCP_GRPH_PFLIP_INT_MASK_TRUE             = 0x00000001,
5182 } DCP_GRPH_PFLIP_INT_MASK;
5183 
5184 /*
5185  * DCP_GRPH_PFLIP_INT_TYPE enum
5186  */
5187 
5188 typedef enum DCP_GRPH_PFLIP_INT_TYPE {
5189 DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL     = 0x00000000,
5190 DCP_GRPH_PFLIP_INT_TYPE_PULSE            = 0x00000001,
5191 } DCP_GRPH_PFLIP_INT_TYPE;
5192 
5193 /*
5194  * DCP_GRPH_PRESCALE_SELECT enum
5195  */
5196 
5197 typedef enum DCP_GRPH_PRESCALE_SELECT {
5198 DCP_GRPH_PRESCALE_SELECT_FIXED           = 0x00000000,
5199 DCP_GRPH_PRESCALE_SELECT_FLOATING        = 0x00000001,
5200 } DCP_GRPH_PRESCALE_SELECT;
5201 
5202 /*
5203  * DCP_GRPH_PRESCALE_R_SIGN enum
5204  */
5205 
5206 typedef enum DCP_GRPH_PRESCALE_R_SIGN {
5207 DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED        = 0x00000000,
5208 DCP_GRPH_PRESCALE_R_SIGN_SIGNED          = 0x00000001,
5209 } DCP_GRPH_PRESCALE_R_SIGN;
5210 
5211 /*
5212  * DCP_GRPH_PRESCALE_G_SIGN enum
5213  */
5214 
5215 typedef enum DCP_GRPH_PRESCALE_G_SIGN {
5216 DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED        = 0x00000000,
5217 DCP_GRPH_PRESCALE_G_SIGN_SIGNED          = 0x00000001,
5218 } DCP_GRPH_PRESCALE_G_SIGN;
5219 
5220 /*
5221  * DCP_GRPH_PRESCALE_B_SIGN enum
5222  */
5223 
5224 typedef enum DCP_GRPH_PRESCALE_B_SIGN {
5225 DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED        = 0x00000000,
5226 DCP_GRPH_PRESCALE_B_SIGN_SIGNED          = 0x00000001,
5227 } DCP_GRPH_PRESCALE_B_SIGN;
5228 
5229 /*
5230  * DCP_GRPH_PRESCALE_BYPASS enum
5231  */
5232 
5233 typedef enum DCP_GRPH_PRESCALE_BYPASS {
5234 DCP_GRPH_PRESCALE_BYPASS_FALSE           = 0x00000000,
5235 DCP_GRPH_PRESCALE_BYPASS_TRUE            = 0x00000001,
5236 } DCP_GRPH_PRESCALE_BYPASS;
5237 
5238 /*
5239  * DCP_INPUT_CSC_GRPH_MODE enum
5240  */
5241 
5242 typedef enum DCP_INPUT_CSC_GRPH_MODE {
5243 DCP_INPUT_CSC_GRPH_MODE_BYPASS           = 0x00000000,
5244 DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF   = 0x00000001,
5245 DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF      = 0x00000002,
5246 DCP_INPUT_CSC_GRPH_MODE_RESERVED         = 0x00000003,
5247 } DCP_INPUT_CSC_GRPH_MODE;
5248 
5249 /*
5250  * DCP_OUTPUT_CSC_GRPH_MODE enum
5251  */
5252 
5253 typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
5254 DCP_OUTPUT_CSC_GRPH_MODE_BYPASS          = 0x00000000,
5255 DCP_OUTPUT_CSC_GRPH_MODE_RGB             = 0x00000001,
5256 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601        = 0x00000002,
5257 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709        = 0x00000003,
5258 DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF  = 0x00000004,
5259 DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF     = 0x00000005,
5260 DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0       = 0x00000006,
5261 DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1       = 0x00000007,
5262 } DCP_OUTPUT_CSC_GRPH_MODE;
5263 
5264 /*
5265  * DCP_DENORM_MODE enum
5266  */
5267 
5268 typedef enum DCP_DENORM_MODE {
5269 DCP_DENORM_MODE_UNITY                    = 0x00000000,
5270 DCP_DENORM_MODE_6BIT                     = 0x00000001,
5271 DCP_DENORM_MODE_8BIT                     = 0x00000002,
5272 DCP_DENORM_MODE_10BIT                    = 0x00000003,
5273 DCP_DENORM_MODE_11BIT                    = 0x00000004,
5274 DCP_DENORM_MODE_12BIT                    = 0x00000005,
5275 DCP_DENORM_MODE_RESERVED0                = 0x00000006,
5276 DCP_DENORM_MODE_RESERVED1                = 0x00000007,
5277 } DCP_DENORM_MODE;
5278 
5279 /*
5280  * DCP_DENORM_14BIT_OUT enum
5281  */
5282 
5283 typedef enum DCP_DENORM_14BIT_OUT {
5284 DCP_DENORM_14BIT_OUT_FALSE               = 0x00000000,
5285 DCP_DENORM_14BIT_OUT_TRUE                = 0x00000001,
5286 } DCP_DENORM_14BIT_OUT;
5287 
5288 /*
5289  * DCP_OUT_ROUND_TRUNC_MODE enum
5290  */
5291 
5292 typedef enum DCP_OUT_ROUND_TRUNC_MODE {
5293 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12     = 0x00000000,
5294 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11     = 0x00000001,
5295 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10     = 0x00000002,
5296 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9      = 0x00000003,
5297 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8      = 0x00000004,
5298 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED  = 0x00000005,
5299 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14     = 0x00000006,
5300 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13     = 0x00000007,
5301 DCP_OUT_ROUND_TRUNC_MODE_ROUND_12        = 0x00000008,
5302 DCP_OUT_ROUND_TRUNC_MODE_ROUND_11        = 0x00000009,
5303 DCP_OUT_ROUND_TRUNC_MODE_ROUND_10        = 0x0000000a,
5304 DCP_OUT_ROUND_TRUNC_MODE_ROUND_9         = 0x0000000b,
5305 DCP_OUT_ROUND_TRUNC_MODE_ROUND_8         = 0x0000000c,
5306 DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED  = 0x0000000d,
5307 DCP_OUT_ROUND_TRUNC_MODE_ROUND_14        = 0x0000000e,
5308 DCP_OUT_ROUND_TRUNC_MODE_ROUND_13        = 0x0000000f,
5309 } DCP_OUT_ROUND_TRUNC_MODE;
5310 
5311 /*
5312  * DCP_KEY_MODE enum
5313  */
5314 
5315 typedef enum DCP_KEY_MODE {
5316 DCP_KEY_MODE_ALPHA0                      = 0x00000000,
5317 DCP_KEY_MODE_ALPHA1                      = 0x00000001,
5318 DCP_KEY_MODE_IN_RANGE_ALPHA1             = 0x00000002,
5319 DCP_KEY_MODE_IN_RANGE_ALPHA0             = 0x00000003,
5320 } DCP_KEY_MODE;
5321 
5322 /*
5323  * DCP_GRPH_DEGAMMA_MODE enum
5324  */
5325 
5326 typedef enum DCP_GRPH_DEGAMMA_MODE {
5327 DCP_GRPH_DEGAMMA_MODE_BYPASS             = 0x00000000,
5328 DCP_GRPH_DEGAMMA_MODE_ROMA               = 0x00000001,
5329 DCP_GRPH_DEGAMMA_MODE_ROMB               = 0x00000002,
5330 DCP_GRPH_DEGAMMA_MODE_RESERVED           = 0x00000003,
5331 } DCP_GRPH_DEGAMMA_MODE;
5332 
5333 /*
5334  * DCP_CURSOR_DEGAMMA_MODE enum
5335  */
5336 
5337 typedef enum DCP_CURSOR_DEGAMMA_MODE {
5338 DCP_CURSOR_DEGAMMA_MODE_BYPASS           = 0x00000000,
5339 DCP_CURSOR_DEGAMMA_MODE_ROMA             = 0x00000001,
5340 DCP_CURSOR_DEGAMMA_MODE_ROMB             = 0x00000002,
5341 DCP_CURSOR_DEGAMMA_MODE_RESERVED         = 0x00000003,
5342 } DCP_CURSOR_DEGAMMA_MODE;
5343 
5344 /*
5345  * DCP_GRPH_GAMUT_REMAP_MODE enum
5346  */
5347 
5348 typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
5349 DCP_GRPH_GAMUT_REMAP_MODE_BYPASS         = 0x00000000,
5350 DCP_GRPH_GAMUT_REMAP_MODE_ROMA           = 0x00000001,
5351 DCP_GRPH_GAMUT_REMAP_MODE_ROMB           = 0x00000002,
5352 DCP_GRPH_GAMUT_REMAP_MODE_RESERVED       = 0x00000003,
5353 } DCP_GRPH_GAMUT_REMAP_MODE;
5354 
5355 /*
5356  * DCP_SPATIAL_DITHER_EN enum
5357  */
5358 
5359 typedef enum DCP_SPATIAL_DITHER_EN {
5360 DCP_SPATIAL_DITHER_EN_FALSE              = 0x00000000,
5361 DCP_SPATIAL_DITHER_EN_TRUE               = 0x00000001,
5362 } DCP_SPATIAL_DITHER_EN;
5363 
5364 /*
5365  * DCP_SPATIAL_DITHER_MODE enum
5366  */
5367 
5368 typedef enum DCP_SPATIAL_DITHER_MODE {
5369 DCP_SPATIAL_DITHER_MODE_BYPASS           = 0x00000000,
5370 DCP_SPATIAL_DITHER_MODE_ROMA             = 0x00000001,
5371 DCP_SPATIAL_DITHER_MODE_ROMB             = 0x00000002,
5372 DCP_SPATIAL_DITHER_MODE_RESERVED         = 0x00000003,
5373 } DCP_SPATIAL_DITHER_MODE;
5374 
5375 /*
5376  * DCP_SPATIAL_DITHER_DEPTH enum
5377  */
5378 
5379 typedef enum DCP_SPATIAL_DITHER_DEPTH {
5380 DCP_SPATIAL_DITHER_DEPTH_30BPP           = 0x00000000,
5381 DCP_SPATIAL_DITHER_DEPTH_24BPP           = 0x00000001,
5382 DCP_SPATIAL_DITHER_DEPTH_36BPP           = 0x00000002,
5383 DCP_SPATIAL_DITHER_DEPTH_UNDEFINED       = 0x00000003,
5384 } DCP_SPATIAL_DITHER_DEPTH;
5385 
5386 /*
5387  * DCP_FRAME_RANDOM_ENABLE enum
5388  */
5389 
5390 typedef enum DCP_FRAME_RANDOM_ENABLE {
5391 DCP_FRAME_RANDOM_ENABLE_FALSE            = 0x00000000,
5392 DCP_FRAME_RANDOM_ENABLE_TRUE             = 0x00000001,
5393 } DCP_FRAME_RANDOM_ENABLE;
5394 
5395 /*
5396  * DCP_RGB_RANDOM_ENABLE enum
5397  */
5398 
5399 typedef enum DCP_RGB_RANDOM_ENABLE {
5400 DCP_RGB_RANDOM_ENABLE_FALSE              = 0x00000000,
5401 DCP_RGB_RANDOM_ENABLE_TRUE               = 0x00000001,
5402 } DCP_RGB_RANDOM_ENABLE;
5403 
5404 /*
5405  * DCP_HIGHPASS_RANDOM_ENABLE enum
5406  */
5407 
5408 typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
5409 DCP_HIGHPASS_RANDOM_ENABLE_FALSE         = 0x00000000,
5410 DCP_HIGHPASS_RANDOM_ENABLE_TRUE          = 0x00000001,
5411 } DCP_HIGHPASS_RANDOM_ENABLE;
5412 
5413 /*
5414  * DCP_CURSOR_EN enum
5415  */
5416 
5417 typedef enum DCP_CURSOR_EN {
5418 DCP_CURSOR_EN_FALSE                      = 0x00000000,
5419 DCP_CURSOR_EN_TRUE                       = 0x00000001,
5420 } DCP_CURSOR_EN;
5421 
5422 /*
5423  * DCP_CUR_INV_TRANS_CLAMP enum
5424  */
5425 
5426 typedef enum DCP_CUR_INV_TRANS_CLAMP {
5427 DCP_CUR_INV_TRANS_CLAMP_FALSE            = 0x00000000,
5428 DCP_CUR_INV_TRANS_CLAMP_TRUE             = 0x00000001,
5429 } DCP_CUR_INV_TRANS_CLAMP;
5430 
5431 /*
5432  * DCP_CURSOR_MODE enum
5433  */
5434 
5435 typedef enum DCP_CURSOR_MODE {
5436 DCP_CURSOR_MODE_MONO_2BPP                = 0x00000000,
5437 DCP_CURSOR_MODE_24BPP_1BIT               = 0x00000001,
5438 DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI      = 0x00000002,
5439 DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI    = 0x00000003,
5440 } DCP_CURSOR_MODE;
5441 
5442 /*
5443  * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum
5444  */
5445 
5446 typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
5447 DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE  = 0x00000000,
5448 DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO  = 0x00000001,
5449 } DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM;
5450 
5451 /*
5452  * DCP_CURSOR_2X_MAGNIFY enum
5453  */
5454 
5455 typedef enum DCP_CURSOR_2X_MAGNIFY {
5456 DCP_CURSOR_2X_MAGNIFY_FALSE              = 0x00000000,
5457 DCP_CURSOR_2X_MAGNIFY_TRUE               = 0x00000001,
5458 } DCP_CURSOR_2X_MAGNIFY;
5459 
5460 /*
5461  * DCP_CURSOR_FORCE_MC_ON enum
5462  */
5463 
5464 typedef enum DCP_CURSOR_FORCE_MC_ON {
5465 DCP_CURSOR_FORCE_MC_ON_FALSE             = 0x00000000,
5466 DCP_CURSOR_FORCE_MC_ON_TRUE              = 0x00000001,
5467 } DCP_CURSOR_FORCE_MC_ON;
5468 
5469 /*
5470  * DCP_CURSOR_URGENT_CONTROL enum
5471  */
5472 
5473 typedef enum DCP_CURSOR_URGENT_CONTROL {
5474 DCP_CURSOR_URGENT_CONTROL_MODE_0         = 0x00000000,
5475 DCP_CURSOR_URGENT_CONTROL_MODE_1         = 0x00000001,
5476 DCP_CURSOR_URGENT_CONTROL_MODE_2         = 0x00000002,
5477 DCP_CURSOR_URGENT_CONTROL_MODE_3         = 0x00000003,
5478 DCP_CURSOR_URGENT_CONTROL_MODE_4         = 0x00000004,
5479 } DCP_CURSOR_URGENT_CONTROL;
5480 
5481 /*
5482  * DCP_CURSOR_UPDATE_PENDING enum
5483  */
5484 
5485 typedef enum DCP_CURSOR_UPDATE_PENDING {
5486 DCP_CURSOR_UPDATE_PENDING_FALSE          = 0x00000000,
5487 DCP_CURSOR_UPDATE_PENDING_TRUE           = 0x00000001,
5488 } DCP_CURSOR_UPDATE_PENDING;
5489 
5490 /*
5491  * DCP_CURSOR_UPDATE_TAKEN enum
5492  */
5493 
5494 typedef enum DCP_CURSOR_UPDATE_TAKEN {
5495 DCP_CURSOR_UPDATE_TAKEN_FALSE            = 0x00000000,
5496 DCP_CURSOR_UPDATE_TAKEN_TRUE             = 0x00000001,
5497 } DCP_CURSOR_UPDATE_TAKEN;
5498 
5499 /*
5500  * DCP_CURSOR_UPDATE_LOCK enum
5501  */
5502 
5503 typedef enum DCP_CURSOR_UPDATE_LOCK {
5504 DCP_CURSOR_UPDATE_LOCK_FALSE             = 0x00000000,
5505 DCP_CURSOR_UPDATE_LOCK_TRUE              = 0x00000001,
5506 } DCP_CURSOR_UPDATE_LOCK;
5507 
5508 /*
5509  * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum
5510  */
5511 
5512 typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
5513 DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5514 DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5515 } DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
5516 
5517 /*
5518  * DCP_CURSOR_UPDATE_STEREO_MODE enum
5519  */
5520 
5521 typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
5522 DCP_CURSOR_UPDATE_STEREO_MODE_BOTH       = 0x00000000,
5523 DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY  = 0x00000001,
5524 DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED  = 0x00000002,
5525 DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY  = 0x00000003,
5526 } DCP_CURSOR_UPDATE_STEREO_MODE;
5527 
5528 /*
5529  * DCP_CUR2_INV_TRANS_CLAMP enum
5530  */
5531 
5532 typedef enum DCP_CUR2_INV_TRANS_CLAMP {
5533 DCP_CUR2_INV_TRANS_CLAMP_FALSE           = 0x00000000,
5534 DCP_CUR2_INV_TRANS_CLAMP_TRUE            = 0x00000001,
5535 } DCP_CUR2_INV_TRANS_CLAMP;
5536 
5537 /*
5538  * DCP_CUR_REQUEST_FILTER_DIS enum
5539  */
5540 
5541 typedef enum DCP_CUR_REQUEST_FILTER_DIS {
5542 DCP_CUR_REQUEST_FILTER_DIS_FALSE         = 0x00000000,
5543 DCP_CUR_REQUEST_FILTER_DIS_TRUE          = 0x00000001,
5544 } DCP_CUR_REQUEST_FILTER_DIS;
5545 
5546 /*
5547  * DCP_CURSOR_STEREO_EN enum
5548  */
5549 
5550 typedef enum DCP_CURSOR_STEREO_EN {
5551 DCP_CURSOR_STEREO_EN_FALSE               = 0x00000000,
5552 DCP_CURSOR_STEREO_EN_TRUE                = 0x00000001,
5553 } DCP_CURSOR_STEREO_EN;
5554 
5555 /*
5556  * DCP_CURSOR_STEREO_OFFSET_YNX enum
5557  */
5558 
5559 typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
5560 DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION  = 0x00000000,
5561 DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION  = 0x00000001,
5562 } DCP_CURSOR_STEREO_OFFSET_YNX;
5563 
5564 /*
5565  * DCP_DC_LUT_RW_MODE enum
5566  */
5567 
5568 typedef enum DCP_DC_LUT_RW_MODE {
5569 DCP_DC_LUT_RW_MODE_256_ENTRY             = 0x00000000,
5570 DCP_DC_LUT_RW_MODE_PWL                   = 0x00000001,
5571 } DCP_DC_LUT_RW_MODE;
5572 
5573 /*
5574  * DCP_DC_LUT_VGA_ACCESS_ENABLE enum
5575  */
5576 
5577 typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
5578 DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE       = 0x00000000,
5579 DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE        = 0x00000001,
5580 } DCP_DC_LUT_VGA_ACCESS_ENABLE;
5581 
5582 /*
5583  * DCP_DC_LUT_AUTOFILL enum
5584  */
5585 
5586 typedef enum DCP_DC_LUT_AUTOFILL {
5587 DCP_DC_LUT_AUTOFILL_FALSE                = 0x00000000,
5588 DCP_DC_LUT_AUTOFILL_TRUE                 = 0x00000001,
5589 } DCP_DC_LUT_AUTOFILL;
5590 
5591 /*
5592  * DCP_DC_LUT_AUTOFILL_DONE enum
5593  */
5594 
5595 typedef enum DCP_DC_LUT_AUTOFILL_DONE {
5596 DCP_DC_LUT_AUTOFILL_DONE_FALSE           = 0x00000000,
5597 DCP_DC_LUT_AUTOFILL_DONE_TRUE            = 0x00000001,
5598 } DCP_DC_LUT_AUTOFILL_DONE;
5599 
5600 /*
5601  * DCP_DC_LUT_INC_B enum
5602  */
5603 
5604 typedef enum DCP_DC_LUT_INC_B {
5605 DCP_DC_LUT_INC_B_NA                      = 0x00000000,
5606 DCP_DC_LUT_INC_B_2                       = 0x00000001,
5607 DCP_DC_LUT_INC_B_4                       = 0x00000002,
5608 DCP_DC_LUT_INC_B_8                       = 0x00000003,
5609 DCP_DC_LUT_INC_B_16                      = 0x00000004,
5610 DCP_DC_LUT_INC_B_32                      = 0x00000005,
5611 DCP_DC_LUT_INC_B_64                      = 0x00000006,
5612 DCP_DC_LUT_INC_B_128                     = 0x00000007,
5613 DCP_DC_LUT_INC_B_256                     = 0x00000008,
5614 DCP_DC_LUT_INC_B_512                     = 0x00000009,
5615 } DCP_DC_LUT_INC_B;
5616 
5617 /*
5618  * DCP_DC_LUT_DATA_B_SIGNED_EN enum
5619  */
5620 
5621 typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
5622 DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE        = 0x00000000,
5623 DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE         = 0x00000001,
5624 } DCP_DC_LUT_DATA_B_SIGNED_EN;
5625 
5626 /*
5627  * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum
5628  */
5629 
5630 typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
5631 DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE   = 0x00000000,
5632 DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE    = 0x00000001,
5633 } DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
5634 
5635 /*
5636  * DCP_DC_LUT_DATA_B_FORMAT enum
5637  */
5638 
5639 typedef enum DCP_DC_LUT_DATA_B_FORMAT {
5640 DCP_DC_LUT_DATA_B_FORMAT_U0P10           = 0x00000000,
5641 DCP_DC_LUT_DATA_B_FORMAT_S1P10           = 0x00000001,
5642 DCP_DC_LUT_DATA_B_FORMAT_U1P11           = 0x00000002,
5643 DCP_DC_LUT_DATA_B_FORMAT_U0P12           = 0x00000003,
5644 } DCP_DC_LUT_DATA_B_FORMAT;
5645 
5646 /*
5647  * DCP_DC_LUT_INC_G enum
5648  */
5649 
5650 typedef enum DCP_DC_LUT_INC_G {
5651 DCP_DC_LUT_INC_G_NA                      = 0x00000000,
5652 DCP_DC_LUT_INC_G_2                       = 0x00000001,
5653 DCP_DC_LUT_INC_G_4                       = 0x00000002,
5654 DCP_DC_LUT_INC_G_8                       = 0x00000003,
5655 DCP_DC_LUT_INC_G_16                      = 0x00000004,
5656 DCP_DC_LUT_INC_G_32                      = 0x00000005,
5657 DCP_DC_LUT_INC_G_64                      = 0x00000006,
5658 DCP_DC_LUT_INC_G_128                     = 0x00000007,
5659 DCP_DC_LUT_INC_G_256                     = 0x00000008,
5660 DCP_DC_LUT_INC_G_512                     = 0x00000009,
5661 } DCP_DC_LUT_INC_G;
5662 
5663 /*
5664  * DCP_DC_LUT_DATA_G_SIGNED_EN enum
5665  */
5666 
5667 typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
5668 DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE        = 0x00000000,
5669 DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE         = 0x00000001,
5670 } DCP_DC_LUT_DATA_G_SIGNED_EN;
5671 
5672 /*
5673  * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum
5674  */
5675 
5676 typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
5677 DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE   = 0x00000000,
5678 DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE    = 0x00000001,
5679 } DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
5680 
5681 /*
5682  * DCP_DC_LUT_DATA_G_FORMAT enum
5683  */
5684 
5685 typedef enum DCP_DC_LUT_DATA_G_FORMAT {
5686 DCP_DC_LUT_DATA_G_FORMAT_U0P10           = 0x00000000,
5687 DCP_DC_LUT_DATA_G_FORMAT_S1P10           = 0x00000001,
5688 DCP_DC_LUT_DATA_G_FORMAT_U1P11           = 0x00000002,
5689 DCP_DC_LUT_DATA_G_FORMAT_U0P12           = 0x00000003,
5690 } DCP_DC_LUT_DATA_G_FORMAT;
5691 
5692 /*
5693  * DCP_DC_LUT_INC_R enum
5694  */
5695 
5696 typedef enum DCP_DC_LUT_INC_R {
5697 DCP_DC_LUT_INC_R_NA                      = 0x00000000,
5698 DCP_DC_LUT_INC_R_2                       = 0x00000001,
5699 DCP_DC_LUT_INC_R_4                       = 0x00000002,
5700 DCP_DC_LUT_INC_R_8                       = 0x00000003,
5701 DCP_DC_LUT_INC_R_16                      = 0x00000004,
5702 DCP_DC_LUT_INC_R_32                      = 0x00000005,
5703 DCP_DC_LUT_INC_R_64                      = 0x00000006,
5704 DCP_DC_LUT_INC_R_128                     = 0x00000007,
5705 DCP_DC_LUT_INC_R_256                     = 0x00000008,
5706 DCP_DC_LUT_INC_R_512                     = 0x00000009,
5707 } DCP_DC_LUT_INC_R;
5708 
5709 /*
5710  * DCP_DC_LUT_DATA_R_SIGNED_EN enum
5711  */
5712 
5713 typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
5714 DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE        = 0x00000000,
5715 DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE         = 0x00000001,
5716 } DCP_DC_LUT_DATA_R_SIGNED_EN;
5717 
5718 /*
5719  * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum
5720  */
5721 
5722 typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
5723 DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE   = 0x00000000,
5724 DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE    = 0x00000001,
5725 } DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
5726 
5727 /*
5728  * DCP_DC_LUT_DATA_R_FORMAT enum
5729  */
5730 
5731 typedef enum DCP_DC_LUT_DATA_R_FORMAT {
5732 DCP_DC_LUT_DATA_R_FORMAT_U0P10           = 0x00000000,
5733 DCP_DC_LUT_DATA_R_FORMAT_S1P10           = 0x00000001,
5734 DCP_DC_LUT_DATA_R_FORMAT_U1P11           = 0x00000002,
5735 DCP_DC_LUT_DATA_R_FORMAT_U0P12           = 0x00000003,
5736 } DCP_DC_LUT_DATA_R_FORMAT;
5737 
5738 /*
5739  * DCP_CRC_ENABLE enum
5740  */
5741 
5742 typedef enum DCP_CRC_ENABLE {
5743 DCP_CRC_ENABLE_FALSE                     = 0x00000000,
5744 DCP_CRC_ENABLE_TRUE                      = 0x00000001,
5745 } DCP_CRC_ENABLE;
5746 
5747 /*
5748  * DCP_CRC_SOURCE_SEL enum
5749  */
5750 
5751 typedef enum DCP_CRC_SOURCE_SEL {
5752 DCP_CRC_SOURCE_SEL_OUTPUT_PIX            = 0x00000000,
5753 DCP_CRC_SOURCE_SEL_INPUT_L32             = 0x00000001,
5754 DCP_CRC_SOURCE_SEL_INPUT_H32             = 0x00000002,
5755 DCP_CRC_SOURCE_SEL_OUTPUT_CNTL           = 0x00000004,
5756 } DCP_CRC_SOURCE_SEL;
5757 
5758 /*
5759  * DCP_CRC_LINE_SEL enum
5760  */
5761 
5762 typedef enum DCP_CRC_LINE_SEL {
5763 DCP_CRC_LINE_SEL_RESERVED                = 0x00000000,
5764 DCP_CRC_LINE_SEL_EVEN                    = 0x00000001,
5765 DCP_CRC_LINE_SEL_ODD                     = 0x00000002,
5766 DCP_CRC_LINE_SEL_BOTH                    = 0x00000003,
5767 } DCP_CRC_LINE_SEL;
5768 
5769 /*
5770  * DCP_GRPH_FLIP_RATE enum
5771  */
5772 
5773 typedef enum DCP_GRPH_FLIP_RATE {
5774 DCP_GRPH_FLIP_RATE_1FRAME                = 0x00000000,
5775 DCP_GRPH_FLIP_RATE_2FRAME                = 0x00000001,
5776 DCP_GRPH_FLIP_RATE_3FRAME                = 0x00000002,
5777 DCP_GRPH_FLIP_RATE_4FRAME                = 0x00000003,
5778 DCP_GRPH_FLIP_RATE_5FRAME                = 0x00000004,
5779 DCP_GRPH_FLIP_RATE_6FRAME                = 0x00000005,
5780 DCP_GRPH_FLIP_RATE_7FRAME                = 0x00000006,
5781 DCP_GRPH_FLIP_RATE_8FRAME                = 0x00000007,
5782 } DCP_GRPH_FLIP_RATE;
5783 
5784 /*
5785  * DCP_GRPH_FLIP_RATE_ENABLE enum
5786  */
5787 
5788 typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
5789 DCP_GRPH_FLIP_RATE_ENABLE_FALSE          = 0x00000000,
5790 DCP_GRPH_FLIP_RATE_ENABLE_TRUE           = 0x00000001,
5791 } DCP_GRPH_FLIP_RATE_ENABLE;
5792 
5793 /*
5794  * DCP_GSL0_EN enum
5795  */
5796 
5797 typedef enum DCP_GSL0_EN {
5798 DCP_GSL0_EN_FALSE                        = 0x00000000,
5799 DCP_GSL0_EN_TRUE                         = 0x00000001,
5800 } DCP_GSL0_EN;
5801 
5802 /*
5803  * DCP_GSL1_EN enum
5804  */
5805 
5806 typedef enum DCP_GSL1_EN {
5807 DCP_GSL1_EN_FALSE                        = 0x00000000,
5808 DCP_GSL1_EN_TRUE                         = 0x00000001,
5809 } DCP_GSL1_EN;
5810 
5811 /*
5812  * DCP_GSL2_EN enum
5813  */
5814 
5815 typedef enum DCP_GSL2_EN {
5816 DCP_GSL2_EN_FALSE                        = 0x00000000,
5817 DCP_GSL2_EN_TRUE                         = 0x00000001,
5818 } DCP_GSL2_EN;
5819 
5820 /*
5821  * DCP_GSL_MASTER_EN enum
5822  */
5823 
5824 typedef enum DCP_GSL_MASTER_EN {
5825 DCP_GSL_MASTER_EN_FALSE                  = 0x00000000,
5826 DCP_GSL_MASTER_EN_TRUE                   = 0x00000001,
5827 } DCP_GSL_MASTER_EN;
5828 
5829 /*
5830  * DCP_GSL_XDMA_GROUP enum
5831  */
5832 
5833 typedef enum DCP_GSL_XDMA_GROUP {
5834 DCP_GSL_XDMA_GROUP_VSYNC                 = 0x00000000,
5835 DCP_GSL_XDMA_GROUP_HSYNC0                = 0x00000001,
5836 DCP_GSL_XDMA_GROUP_HSYNC1                = 0x00000002,
5837 DCP_GSL_XDMA_GROUP_HSYNC2                = 0x00000003,
5838 } DCP_GSL_XDMA_GROUP;
5839 
5840 /*
5841  * DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum
5842  */
5843 
5844 typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
5845 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE    = 0x00000000,
5846 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE     = 0x00000001,
5847 } DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
5848 
5849 /*
5850  * DCP_GSL_SYNC_SOURCE enum
5851  */
5852 
5853 typedef enum DCP_GSL_SYNC_SOURCE {
5854 DCP_GSL_SYNC_SOURCE_FLIP                 = 0x00000000,
5855 DCP_GSL_SYNC_SOURCE_PHASE0               = 0x00000001,
5856 DCP_GSL_SYNC_SOURCE_RESET                = 0x00000002,
5857 DCP_GSL_SYNC_SOURCE_PHASE1               = 0x00000003,
5858 } DCP_GSL_SYNC_SOURCE;
5859 
5860 /*
5861  * DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum
5862  */
5863 
5864 typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
5865 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS  = 0x00000000,
5866 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN  = 0x00000001,
5867 } DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC;
5868 
5869 /*
5870  * DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum
5871  */
5872 
5873 typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
5874 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE  = 0x00000000,
5875 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE  = 0x00000001,
5876 } DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
5877 
5878 /*
5879  * DCP_TEST_DEBUG_WRITE_EN enum
5880  */
5881 
5882 typedef enum DCP_TEST_DEBUG_WRITE_EN {
5883 DCP_TEST_DEBUG_WRITE_EN_FALSE            = 0x00000000,
5884 DCP_TEST_DEBUG_WRITE_EN_TRUE             = 0x00000001,
5885 } DCP_TEST_DEBUG_WRITE_EN;
5886 
5887 /*
5888  * DCP_GRPH_STEREOSYNC_FLIP_EN enum
5889  */
5890 
5891 typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
5892 DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE        = 0x00000000,
5893 DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE         = 0x00000001,
5894 } DCP_GRPH_STEREOSYNC_FLIP_EN;
5895 
5896 /*
5897  * DCP_GRPH_STEREOSYNC_FLIP_MODE enum
5898  */
5899 
5900 typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
5901 DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP       = 0x00000000,
5902 DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0     = 0x00000001,
5903 DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET      = 0x00000002,
5904 DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1     = 0x00000003,
5905 } DCP_GRPH_STEREOSYNC_FLIP_MODE;
5906 
5907 /*
5908  * DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum
5909  */
5910 
5911 typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
5912 DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE  = 0x00000000,
5913 DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE  = 0x00000001,
5914 } DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
5915 
5916 /*
5917  * DCP_GRPH_ROTATION_ANGLE enum
5918  */
5919 
5920 typedef enum DCP_GRPH_ROTATION_ANGLE {
5921 DCP_GRPH_ROTATION_ANGLE_0                = 0x00000000,
5922 DCP_GRPH_ROTATION_ANGLE_90               = 0x00000001,
5923 DCP_GRPH_ROTATION_ANGLE_180              = 0x00000002,
5924 DCP_GRPH_ROTATION_ANGLE_270              = 0x00000003,
5925 } DCP_GRPH_ROTATION_ANGLE;
5926 
5927 /*
5928  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum
5929  */
5930 
5931 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
5932 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE  = 0x00000000,
5933 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE  = 0x00000001,
5934 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
5935 
5936 /*
5937  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum
5938  */
5939 
5940 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
5941 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM  = 0x00000000,
5942 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE  = 0x00000001,
5943 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
5944 
5945 /*
5946  * DCP_GRPH_REGAMMA_MODE enum
5947  */
5948 
5949 typedef enum DCP_GRPH_REGAMMA_MODE {
5950 DCP_GRPH_REGAMMA_MODE_BYPASS             = 0x00000000,
5951 DCP_GRPH_REGAMMA_MODE_SRGB               = 0x00000001,
5952 DCP_GRPH_REGAMMA_MODE_XVYCC              = 0x00000002,
5953 DCP_GRPH_REGAMMA_MODE_PROGA              = 0x00000003,
5954 DCP_GRPH_REGAMMA_MODE_PROGB              = 0x00000004,
5955 } DCP_GRPH_REGAMMA_MODE;
5956 
5957 /*
5958  * DCP_ALPHA_ROUND_TRUNC_MODE enum
5959  */
5960 
5961 typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
5962 DCP_ALPHA_ROUND_TRUNC_MODE_ROUND         = 0x00000000,
5963 DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC         = 0x00000001,
5964 } DCP_ALPHA_ROUND_TRUNC_MODE;
5965 
5966 /*
5967  * DCP_CURSOR_ALPHA_BLND_ENA enum
5968  */
5969 
5970 typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
5971 DCP_CURSOR_ALPHA_BLND_ENA_FALSE          = 0x00000000,
5972 DCP_CURSOR_ALPHA_BLND_ENA_TRUE           = 0x00000001,
5973 } DCP_CURSOR_ALPHA_BLND_ENA;
5974 
5975 /*
5976  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum
5977  */
5978 
5979 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
5980 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE  = 0x00000000,
5981 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE  = 0x00000001,
5982 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
5983 
5984 /*
5985  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum
5986  */
5987 
5988 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
5989 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x00000000,
5990 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE  = 0x00000001,
5991 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
5992 
5993 /*
5994  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum
5995  */
5996 
5997 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
5998 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE  = 0x00000000,
5999 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE  = 0x00000001,
6000 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
6001 
6002 /*
6003  * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum
6004  */
6005 
6006 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
6007 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6008 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE  = 0x00000001,
6009 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
6010 
6011 /*
6012  * DCP_GRPH_SURFACE_COUNTER_EN enum
6013  */
6014 
6015 typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
6016 DCP_GRPH_SURFACE_COUNTER_EN_DISABLE      = 0x00000000,
6017 DCP_GRPH_SURFACE_COUNTER_EN_ENABLE       = 0x00000001,
6018 } DCP_GRPH_SURFACE_COUNTER_EN;
6019 
6020 /*
6021  * DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum
6022  */
6023 
6024 typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
6025 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0  = 0x00000000,
6026 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1  = 0x00000001,
6027 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2  = 0x00000002,
6028 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3  = 0x00000003,
6029 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4  = 0x00000004,
6030 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5  = 0x00000005,
6031 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6  = 0x00000006,
6032 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7  = 0x00000007,
6033 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8  = 0x00000008,
6034 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9  = 0x00000009,
6035 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10  = 0x0000000a,
6036 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11  = 0x0000000b,
6037 } DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
6038 
6039 /*
6040  * DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum
6041  */
6042 
6043 typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
6044 DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO  = 0x00000000,
6045 DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES  = 0x00000001,
6046 } DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
6047 
6048 /*
6049  * DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum
6050  */
6051 
6052 typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
6053 DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE    = 0x00000000,
6054 DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE     = 0x00000001,
6055 } DCP_GRPH_XDMA_FLIP_TYPE_CLEAR;
6056 
6057 /*
6058  * DCP_GRPH_XDMA_DRR_MODE_ENABLE enum
6059  */
6060 
6061 typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
6062 DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE    = 0x00000000,
6063 DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE     = 0x00000001,
6064 } DCP_GRPH_XDMA_DRR_MODE_ENABLE;
6065 
6066 /*
6067  * DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum
6068  */
6069 
6070 typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
6071 DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE   = 0x00000000,
6072 DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE    = 0x00000001,
6073 } DCP_GRPH_XDMA_MULTIFLIP_ENABLE;
6074 
6075 /*
6076  * DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum
6077  */
6078 
6079 typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
6080 DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE    = 0x00000000,
6081 DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE     = 0x00000001,
6082 } DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK;
6083 
6084 /*
6085  * DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum
6086  */
6087 
6088 typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
6089 DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE     = 0x00000000,
6090 DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE      = 0x00000001,
6091 } DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK;
6092 
6093 /*******************************************************
6094  * DC_PERFMON Enums
6095  *******************************************************/
6096 
6097 /*
6098  * PERFCOUNTER_CVALUE_SEL enum
6099  */
6100 
6101 typedef enum PERFCOUNTER_CVALUE_SEL {
6102 PERFCOUNTER_CVALUE_SEL_47_0              = 0x00000000,
6103 PERFCOUNTER_CVALUE_SEL_15_0              = 0x00000001,
6104 PERFCOUNTER_CVALUE_SEL_31_16             = 0x00000002,
6105 PERFCOUNTER_CVALUE_SEL_47_32             = 0x00000003,
6106 PERFCOUNTER_CVALUE_SEL_11_0              = 0x00000004,
6107 PERFCOUNTER_CVALUE_SEL_23_12             = 0x00000005,
6108 PERFCOUNTER_CVALUE_SEL_35_24             = 0x00000006,
6109 PERFCOUNTER_CVALUE_SEL_47_36             = 0x00000007,
6110 } PERFCOUNTER_CVALUE_SEL;
6111 
6112 /*
6113  * PERFCOUNTER_INC_MODE enum
6114  */
6115 
6116 typedef enum PERFCOUNTER_INC_MODE {
6117 PERFCOUNTER_INC_MODE_MULTI_BIT           = 0x00000000,
6118 PERFCOUNTER_INC_MODE_BOTH_EDGE           = 0x00000001,
6119 PERFCOUNTER_INC_MODE_LSB                 = 0x00000002,
6120 PERFCOUNTER_INC_MODE_POS_EDGE            = 0x00000003,
6121 PERFCOUNTER_INC_MODE_NEG_EDGE            = 0x00000004,
6122 } PERFCOUNTER_INC_MODE;
6123 
6124 /*
6125  * PERFCOUNTER_HW_CNTL_SEL enum
6126  */
6127 
6128 typedef enum PERFCOUNTER_HW_CNTL_SEL {
6129 PERFCOUNTER_HW_CNTL_SEL_RUNEN            = 0x00000000,
6130 PERFCOUNTER_HW_CNTL_SEL_CNTOFF           = 0x00000001,
6131 } PERFCOUNTER_HW_CNTL_SEL;
6132 
6133 /*
6134  * PERFCOUNTER_RUNEN_MODE enum
6135  */
6136 
6137 typedef enum PERFCOUNTER_RUNEN_MODE {
6138 PERFCOUNTER_RUNEN_MODE_LEVEL             = 0x00000000,
6139 PERFCOUNTER_RUNEN_MODE_EDGE              = 0x00000001,
6140 } PERFCOUNTER_RUNEN_MODE;
6141 
6142 /*
6143  * PERFCOUNTER_CNTOFF_START_DIS enum
6144  */
6145 
6146 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
6147 PERFCOUNTER_CNTOFF_START_ENABLE          = 0x00000000,
6148 PERFCOUNTER_CNTOFF_START_DISABLE         = 0x00000001,
6149 } PERFCOUNTER_CNTOFF_START_DIS;
6150 
6151 /*
6152  * PERFCOUNTER_RESTART_EN enum
6153  */
6154 
6155 typedef enum PERFCOUNTER_RESTART_EN {
6156 PERFCOUNTER_RESTART_DISABLE              = 0x00000000,
6157 PERFCOUNTER_RESTART_ENABLE               = 0x00000001,
6158 } PERFCOUNTER_RESTART_EN;
6159 
6160 /*
6161  * PERFCOUNTER_INT_EN enum
6162  */
6163 
6164 typedef enum PERFCOUNTER_INT_EN {
6165 PERFCOUNTER_INT_DISABLE                  = 0x00000000,
6166 PERFCOUNTER_INT_ENABLE                   = 0x00000001,
6167 } PERFCOUNTER_INT_EN;
6168 
6169 /*
6170  * PERFCOUNTER_OFF_MASK enum
6171  */
6172 
6173 typedef enum PERFCOUNTER_OFF_MASK {
6174 PERFCOUNTER_OFF_MASK_DISABLE             = 0x00000000,
6175 PERFCOUNTER_OFF_MASK_ENABLE              = 0x00000001,
6176 } PERFCOUNTER_OFF_MASK;
6177 
6178 /*
6179  * PERFCOUNTER_ACTIVE enum
6180  */
6181 
6182 typedef enum PERFCOUNTER_ACTIVE {
6183 PERFCOUNTER_IS_IDLE                      = 0x00000000,
6184 PERFCOUNTER_IS_ACTIVE                    = 0x00000001,
6185 } PERFCOUNTER_ACTIVE;
6186 
6187 /*
6188  * PERFCOUNTER_INT_TYPE enum
6189  */
6190 
6191 typedef enum PERFCOUNTER_INT_TYPE {
6192 PERFCOUNTER_INT_TYPE_LEVEL               = 0x00000000,
6193 PERFCOUNTER_INT_TYPE_PULSE               = 0x00000001,
6194 } PERFCOUNTER_INT_TYPE;
6195 
6196 /*
6197  * PERFCOUNTER_COUNTED_VALUE_TYPE enum
6198  */
6199 
6200 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
6201 PERFCOUNTER_COUNTED_VALUE_TYPE_ACC       = 0x00000000,
6202 PERFCOUNTER_COUNTED_VALUE_TYPE_MAX       = 0x00000001,
6203 PERFCOUNTER_COUNTED_VALUE_TYPE_MIN       = 0x00000002,
6204 } PERFCOUNTER_COUNTED_VALUE_TYPE;
6205 
6206 /*
6207  * PERFCOUNTER_CNTL_SEL enum
6208  */
6209 
6210 typedef enum PERFCOUNTER_CNTL_SEL {
6211 PERFCOUNTER_CNTL_SEL_0                   = 0x00000000,
6212 PERFCOUNTER_CNTL_SEL_1                   = 0x00000001,
6213 PERFCOUNTER_CNTL_SEL_2                   = 0x00000002,
6214 PERFCOUNTER_CNTL_SEL_3                   = 0x00000003,
6215 PERFCOUNTER_CNTL_SEL_4                   = 0x00000004,
6216 PERFCOUNTER_CNTL_SEL_5                   = 0x00000005,
6217 PERFCOUNTER_CNTL_SEL_6                   = 0x00000006,
6218 PERFCOUNTER_CNTL_SEL_7                   = 0x00000007,
6219 } PERFCOUNTER_CNTL_SEL;
6220 
6221 /*
6222  * PERFCOUNTER_CNT0_STATE enum
6223  */
6224 
6225 typedef enum PERFCOUNTER_CNT0_STATE {
6226 PERFCOUNTER_CNT0_STATE_RESET             = 0x00000000,
6227 PERFCOUNTER_CNT0_STATE_START             = 0x00000001,
6228 PERFCOUNTER_CNT0_STATE_FREEZE            = 0x00000002,
6229 PERFCOUNTER_CNT0_STATE_HW                = 0x00000003,
6230 } PERFCOUNTER_CNT0_STATE;
6231 
6232 /*
6233  * PERFCOUNTER_STATE_SEL0 enum
6234  */
6235 
6236 typedef enum PERFCOUNTER_STATE_SEL0 {
6237 PERFCOUNTER_STATE_SEL0_GLOBAL            = 0x00000000,
6238 PERFCOUNTER_STATE_SEL0_LOCAL             = 0x00000001,
6239 } PERFCOUNTER_STATE_SEL0;
6240 
6241 /*
6242  * PERFCOUNTER_CNT1_STATE enum
6243  */
6244 
6245 typedef enum PERFCOUNTER_CNT1_STATE {
6246 PERFCOUNTER_CNT1_STATE_RESET             = 0x00000000,
6247 PERFCOUNTER_CNT1_STATE_START             = 0x00000001,
6248 PERFCOUNTER_CNT1_STATE_FREEZE            = 0x00000002,
6249 PERFCOUNTER_CNT1_STATE_HW                = 0x00000003,
6250 } PERFCOUNTER_CNT1_STATE;
6251 
6252 /*
6253  * PERFCOUNTER_STATE_SEL1 enum
6254  */
6255 
6256 typedef enum PERFCOUNTER_STATE_SEL1 {
6257 PERFCOUNTER_STATE_SEL1_GLOBAL            = 0x00000000,
6258 PERFCOUNTER_STATE_SEL1_LOCAL             = 0x00000001,
6259 } PERFCOUNTER_STATE_SEL1;
6260 
6261 /*
6262  * PERFCOUNTER_CNT2_STATE enum
6263  */
6264 
6265 typedef enum PERFCOUNTER_CNT2_STATE {
6266 PERFCOUNTER_CNT2_STATE_RESET             = 0x00000000,
6267 PERFCOUNTER_CNT2_STATE_START             = 0x00000001,
6268 PERFCOUNTER_CNT2_STATE_FREEZE            = 0x00000002,
6269 PERFCOUNTER_CNT2_STATE_HW                = 0x00000003,
6270 } PERFCOUNTER_CNT2_STATE;
6271 
6272 /*
6273  * PERFCOUNTER_STATE_SEL2 enum
6274  */
6275 
6276 typedef enum PERFCOUNTER_STATE_SEL2 {
6277 PERFCOUNTER_STATE_SEL2_GLOBAL            = 0x00000000,
6278 PERFCOUNTER_STATE_SEL2_LOCAL             = 0x00000001,
6279 } PERFCOUNTER_STATE_SEL2;
6280 
6281 /*
6282  * PERFCOUNTER_CNT3_STATE enum
6283  */
6284 
6285 typedef enum PERFCOUNTER_CNT3_STATE {
6286 PERFCOUNTER_CNT3_STATE_RESET             = 0x00000000,
6287 PERFCOUNTER_CNT3_STATE_START             = 0x00000001,
6288 PERFCOUNTER_CNT3_STATE_FREEZE            = 0x00000002,
6289 PERFCOUNTER_CNT3_STATE_HW                = 0x00000003,
6290 } PERFCOUNTER_CNT3_STATE;
6291 
6292 /*
6293  * PERFCOUNTER_STATE_SEL3 enum
6294  */
6295 
6296 typedef enum PERFCOUNTER_STATE_SEL3 {
6297 PERFCOUNTER_STATE_SEL3_GLOBAL            = 0x00000000,
6298 PERFCOUNTER_STATE_SEL3_LOCAL             = 0x00000001,
6299 } PERFCOUNTER_STATE_SEL3;
6300 
6301 /*
6302  * PERFCOUNTER_CNT4_STATE enum
6303  */
6304 
6305 typedef enum PERFCOUNTER_CNT4_STATE {
6306 PERFCOUNTER_CNT4_STATE_RESET             = 0x00000000,
6307 PERFCOUNTER_CNT4_STATE_START             = 0x00000001,
6308 PERFCOUNTER_CNT4_STATE_FREEZE            = 0x00000002,
6309 PERFCOUNTER_CNT4_STATE_HW                = 0x00000003,
6310 } PERFCOUNTER_CNT4_STATE;
6311 
6312 /*
6313  * PERFCOUNTER_STATE_SEL4 enum
6314  */
6315 
6316 typedef enum PERFCOUNTER_STATE_SEL4 {
6317 PERFCOUNTER_STATE_SEL4_GLOBAL            = 0x00000000,
6318 PERFCOUNTER_STATE_SEL4_LOCAL             = 0x00000001,
6319 } PERFCOUNTER_STATE_SEL4;
6320 
6321 /*
6322  * PERFCOUNTER_CNT5_STATE enum
6323  */
6324 
6325 typedef enum PERFCOUNTER_CNT5_STATE {
6326 PERFCOUNTER_CNT5_STATE_RESET             = 0x00000000,
6327 PERFCOUNTER_CNT5_STATE_START             = 0x00000001,
6328 PERFCOUNTER_CNT5_STATE_FREEZE            = 0x00000002,
6329 PERFCOUNTER_CNT5_STATE_HW                = 0x00000003,
6330 } PERFCOUNTER_CNT5_STATE;
6331 
6332 /*
6333  * PERFCOUNTER_STATE_SEL5 enum
6334  */
6335 
6336 typedef enum PERFCOUNTER_STATE_SEL5 {
6337 PERFCOUNTER_STATE_SEL5_GLOBAL            = 0x00000000,
6338 PERFCOUNTER_STATE_SEL5_LOCAL             = 0x00000001,
6339 } PERFCOUNTER_STATE_SEL5;
6340 
6341 /*
6342  * PERFCOUNTER_CNT6_STATE enum
6343  */
6344 
6345 typedef enum PERFCOUNTER_CNT6_STATE {
6346 PERFCOUNTER_CNT6_STATE_RESET             = 0x00000000,
6347 PERFCOUNTER_CNT6_STATE_START             = 0x00000001,
6348 PERFCOUNTER_CNT6_STATE_FREEZE            = 0x00000002,
6349 PERFCOUNTER_CNT6_STATE_HW                = 0x00000003,
6350 } PERFCOUNTER_CNT6_STATE;
6351 
6352 /*
6353  * PERFCOUNTER_STATE_SEL6 enum
6354  */
6355 
6356 typedef enum PERFCOUNTER_STATE_SEL6 {
6357 PERFCOUNTER_STATE_SEL6_GLOBAL            = 0x00000000,
6358 PERFCOUNTER_STATE_SEL6_LOCAL             = 0x00000001,
6359 } PERFCOUNTER_STATE_SEL6;
6360 
6361 /*
6362  * PERFCOUNTER_CNT7_STATE enum
6363  */
6364 
6365 typedef enum PERFCOUNTER_CNT7_STATE {
6366 PERFCOUNTER_CNT7_STATE_RESET             = 0x00000000,
6367 PERFCOUNTER_CNT7_STATE_START             = 0x00000001,
6368 PERFCOUNTER_CNT7_STATE_FREEZE            = 0x00000002,
6369 PERFCOUNTER_CNT7_STATE_HW                = 0x00000003,
6370 } PERFCOUNTER_CNT7_STATE;
6371 
6372 /*
6373  * PERFCOUNTER_STATE_SEL7 enum
6374  */
6375 
6376 typedef enum PERFCOUNTER_STATE_SEL7 {
6377 PERFCOUNTER_STATE_SEL7_GLOBAL            = 0x00000000,
6378 PERFCOUNTER_STATE_SEL7_LOCAL             = 0x00000001,
6379 } PERFCOUNTER_STATE_SEL7;
6380 
6381 /*
6382  * PERFMON_STATE enum
6383  */
6384 
6385 typedef enum PERFMON_STATE {
6386 PERFMON_STATE_RESET                      = 0x00000000,
6387 PERFMON_STATE_START                      = 0x00000001,
6388 PERFMON_STATE_FREEZE                     = 0x00000002,
6389 PERFMON_STATE_HW                         = 0x00000003,
6390 } PERFMON_STATE;
6391 
6392 /*
6393  * PERFMON_CNTOFF_AND_OR enum
6394  */
6395 
6396 typedef enum PERFMON_CNTOFF_AND_OR {
6397 PERFMON_CNTOFF_OR                        = 0x00000000,
6398 PERFMON_CNTOFF_AND                       = 0x00000001,
6399 } PERFMON_CNTOFF_AND_OR;
6400 
6401 /*
6402  * PERFMON_CNTOFF_INT_EN enum
6403  */
6404 
6405 typedef enum PERFMON_CNTOFF_INT_EN {
6406 PERFMON_CNTOFF_INT_DISABLE               = 0x00000000,
6407 PERFMON_CNTOFF_INT_ENABLE                = 0x00000001,
6408 } PERFMON_CNTOFF_INT_EN;
6409 
6410 /*
6411  * PERFMON_CNTOFF_INT_TYPE enum
6412  */
6413 
6414 typedef enum PERFMON_CNTOFF_INT_TYPE {
6415 PERFMON_CNTOFF_INT_TYPE_LEVEL            = 0x00000000,
6416 PERFMON_CNTOFF_INT_TYPE_PULSE            = 0x00000001,
6417 } PERFMON_CNTOFF_INT_TYPE;
6418 
6419 /*******************************************************
6420  * SCL Enums
6421  *******************************************************/
6422 
6423 /*
6424  * SCL_C_RAM_TAP_PAIR_IDX enum
6425  */
6426 
6427 typedef enum SCL_C_RAM_TAP_PAIR_IDX {
6428 SCL_C_RAM_TAP_PAIR_ID0                   = 0x00000000,
6429 SCL_C_RAM_TAP_PAIR_ID1                   = 0x00000001,
6430 SCL_C_RAM_TAP_PAIR_ID2                   = 0x00000002,
6431 SCL_C_RAM_TAP_PAIR_ID3                   = 0x00000003,
6432 SCL_C_RAM_TAP_PAIR_ID4                   = 0x00000004,
6433 } SCL_C_RAM_TAP_PAIR_IDX;
6434 
6435 /*
6436  * SCL_C_RAM_PHASE enum
6437  */
6438 
6439 typedef enum SCL_C_RAM_PHASE {
6440 SCL_C_RAM_PHASE_0                        = 0x00000000,
6441 SCL_C_RAM_PHASE_1                        = 0x00000001,
6442 SCL_C_RAM_PHASE_2                        = 0x00000002,
6443 SCL_C_RAM_PHASE_3                        = 0x00000003,
6444 SCL_C_RAM_PHASE_4                        = 0x00000004,
6445 SCL_C_RAM_PHASE_5                        = 0x00000005,
6446 SCL_C_RAM_PHASE_6                        = 0x00000006,
6447 SCL_C_RAM_PHASE_7                        = 0x00000007,
6448 SCL_C_RAM_PHASE_8                        = 0x00000008,
6449 } SCL_C_RAM_PHASE;
6450 
6451 /*
6452  * SCL_C_RAM_FILTER_TYPE enum
6453  */
6454 
6455 typedef enum SCL_C_RAM_FILTER_TYPE {
6456 SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT  = 0x00000000,
6457 SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT    = 0x00000001,
6458 SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT  = 0x00000002,
6459 SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT    = 0x00000003,
6460 } SCL_C_RAM_FILTER_TYPE;
6461 
6462 /*
6463  * SCL_MODE_SEL enum
6464  */
6465 
6466 typedef enum SCL_MODE_SEL {
6467 SCL_MODE_RGB_BYPASS                      = 0x00000000,
6468 SCL_MODE_RGB_SCALING                     = 0x00000001,
6469 SCL_MODE_YCBCR_SCALING                   = 0x00000002,
6470 SCL_MODE_YCBCR_BYPASS                    = 0x00000003,
6471 } SCL_MODE_SEL;
6472 
6473 /*
6474  * SCL_PSCL_EN enum
6475  */
6476 
6477 typedef enum SCL_PSCL_EN {
6478 SCL_PSCL_DISABLE                         = 0x00000000,
6479 SCL_PSCL_ENANBLE                         = 0x00000001,
6480 } SCL_PSCL_EN;
6481 
6482 /*
6483  * SCL_V_NUM_OF_TAPS enum
6484  */
6485 
6486 typedef enum SCL_V_NUM_OF_TAPS {
6487 SCL_V_NUM_OF_TAPS_1                      = 0x00000000,
6488 SCL_V_NUM_OF_TAPS_2                      = 0x00000001,
6489 SCL_V_NUM_OF_TAPS_3                      = 0x00000002,
6490 SCL_V_NUM_OF_TAPS_4                      = 0x00000003,
6491 SCL_V_NUM_OF_TAPS_5                      = 0x00000004,
6492 SCL_V_NUM_OF_TAPS_6                      = 0x00000005,
6493 } SCL_V_NUM_OF_TAPS;
6494 
6495 /*
6496  * SCL_H_NUM_OF_TAPS enum
6497  */
6498 
6499 typedef enum SCL_H_NUM_OF_TAPS {
6500 SCL_H_NUM_OF_TAPS_1                      = 0x00000000,
6501 SCL_H_NUM_OF_TAPS_2                      = 0x00000001,
6502 SCL_H_NUM_OF_TAPS_4                      = 0x00000003,
6503 SCL_H_NUM_OF_TAPS_6                      = 0x00000005,
6504 SCL_H_NUM_OF_TAPS_8                      = 0x00000007,
6505 SCL_H_NUM_OF_TAPS_10                     = 0x00000009,
6506 } SCL_H_NUM_OF_TAPS;
6507 
6508 /*
6509  * SCL_BOUNDARY_MODE enum
6510  */
6511 
6512 typedef enum SCL_BOUNDARY_MODE {
6513 SCL_BOUNDARY_MODE_BLACK                  = 0x00000000,
6514 SCL_BOUNDARY_MODE_EDGE                   = 0x00000001,
6515 } SCL_BOUNDARY_MODE;
6516 
6517 /*
6518  * SCL_EARLY_EOL_MOD enum
6519  */
6520 
6521 typedef enum SCL_EARLY_EOL_MOD {
6522 SCL_EARLY_EOL_MODE_CRTC                  = 0x00000000,
6523 SCL_EARLY_EOL_MODE_INTERNAL              = 0x00000001,
6524 } SCL_EARLY_EOL_MOD;
6525 
6526 /*
6527  * SCL_BYPASS_MODE enum
6528  */
6529 
6530 typedef enum SCL_BYPASS_MODE {
6531 SCL_BYPASS_MODE_MC_MR                    = 0x00000000,
6532 SCL_BYPASS_MODE_AC_NR                    = 0x00000001,
6533 SCL_BYPASS_MODE_AC_AR                    = 0x00000002,
6534 SCL_BYPASS_MODE_RESERVED                 = 0x00000003,
6535 } SCL_BYPASS_MODE;
6536 
6537 /*
6538  * SCL_V_MANUAL_REPLICATE_FACTOR enum
6539  */
6540 
6541 typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
6542 SCL_V_MANUAL_REPLICATE_FACTOR_1          = 0x00000000,
6543 SCL_V_MANUAL_REPLICATE_FACTOR_2          = 0x00000001,
6544 SCL_V_MANUAL_REPLICATE_FACTOR_3          = 0x00000002,
6545 SCL_V_MANUAL_REPLICATE_FACTOR_4          = 0x00000003,
6546 SCL_V_MANUAL_REPLICATE_FACTOR_5          = 0x00000004,
6547 SCL_V_MANUAL_REPLICATE_FACTOR_6          = 0x00000005,
6548 SCL_V_MANUAL_REPLICATE_FACTOR_7          = 0x00000006,
6549 SCL_V_MANUAL_REPLICATE_FACTOR_8          = 0x00000007,
6550 SCL_V_MANUAL_REPLICATE_FACTOR_9          = 0x00000008,
6551 SCL_V_MANUAL_REPLICATE_FACTOR_10         = 0x00000009,
6552 SCL_V_MANUAL_REPLICATE_FACTOR_11         = 0x0000000a,
6553 SCL_V_MANUAL_REPLICATE_FACTOR_12         = 0x0000000b,
6554 SCL_V_MANUAL_REPLICATE_FACTOR_13         = 0x0000000c,
6555 SCL_V_MANUAL_REPLICATE_FACTOR_14         = 0x0000000d,
6556 SCL_V_MANUAL_REPLICATE_FACTOR_15         = 0x0000000e,
6557 SCL_V_MANUAL_REPLICATE_FACTOR_16         = 0x0000000f,
6558 } SCL_V_MANUAL_REPLICATE_FACTOR;
6559 
6560 /*
6561  * SCL_H_MANUAL_REPLICATE_FACTOR enum
6562  */
6563 
6564 typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
6565 SCL_H_MANUAL_REPLICATE_FACTOR_1          = 0x00000000,
6566 SCL_H_MANUAL_REPLICATE_FACTOR_2          = 0x00000001,
6567 SCL_H_MANUAL_REPLICATE_FACTOR_3          = 0x00000002,
6568 SCL_H_MANUAL_REPLICATE_FACTOR_4          = 0x00000003,
6569 SCL_H_MANUAL_REPLICATE_FACTOR_5          = 0x00000004,
6570 SCL_H_MANUAL_REPLICATE_FACTOR_6          = 0x00000005,
6571 SCL_H_MANUAL_REPLICATE_FACTOR_7          = 0x00000006,
6572 SCL_H_MANUAL_REPLICATE_FACTOR_8          = 0x00000007,
6573 SCL_H_MANUAL_REPLICATE_FACTOR_9          = 0x00000008,
6574 SCL_H_MANUAL_REPLICATE_FACTOR_10         = 0x00000009,
6575 SCL_H_MANUAL_REPLICATE_FACTOR_11         = 0x0000000a,
6576 SCL_H_MANUAL_REPLICATE_FACTOR_12         = 0x0000000b,
6577 SCL_H_MANUAL_REPLICATE_FACTOR_13         = 0x0000000c,
6578 SCL_H_MANUAL_REPLICATE_FACTOR_14         = 0x0000000d,
6579 SCL_H_MANUAL_REPLICATE_FACTOR_15         = 0x0000000e,
6580 SCL_H_MANUAL_REPLICATE_FACTOR_16         = 0x0000000f,
6581 } SCL_H_MANUAL_REPLICATE_FACTOR;
6582 
6583 /*
6584  * SCL_V_CALC_AUTO_RATIO_EN enum
6585  */
6586 
6587 typedef enum SCL_V_CALC_AUTO_RATIO_EN {
6588 SCL_V_CALC_AUTO_RATIO_DISABLE            = 0x00000000,
6589 SCL_V_CALC_AUTO_RATIO_ENABLE             = 0x00000001,
6590 } SCL_V_CALC_AUTO_RATIO_EN;
6591 
6592 /*
6593  * SCL_H_CALC_AUTO_RATIO_EN enum
6594  */
6595 
6596 typedef enum SCL_H_CALC_AUTO_RATIO_EN {
6597 SCL_H_CALC_AUTO_RATIO_DISABLE            = 0x00000000,
6598 SCL_H_CALC_AUTO_RATIO_ENABLE             = 0x00000001,
6599 } SCL_H_CALC_AUTO_RATIO_EN;
6600 
6601 /*
6602  * SCL_H_FILTER_PICK_NEAREST enum
6603  */
6604 
6605 typedef enum SCL_H_FILTER_PICK_NEAREST {
6606 SCL_H_FILTER_PICK_NEAREST_DISABLE        = 0x00000000,
6607 SCL_H_FILTER_PICK_NEAREST_ENABLE         = 0x00000001,
6608 } SCL_H_FILTER_PICK_NEAREST;
6609 
6610 /*
6611  * SCL_H_2TAP_HARDCODE_COEF_EN enum
6612  */
6613 
6614 typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
6615 SCL_H_2TAP_HARDCODE_COEF_DISABLE         = 0x00000000,
6616 SCL_H_2TAP_HARDCODE_COEF_ENABLE          = 0x00000001,
6617 } SCL_H_2TAP_HARDCODE_COEF_EN;
6618 
6619 /*
6620  * SCL_V_FILTER_PICK_NEAREST enum
6621  */
6622 
6623 typedef enum SCL_V_FILTER_PICK_NEAREST {
6624 SCL_V_FILTER_PICK_NEAREST_DISABLE        = 0x00000000,
6625 SCL_V_FILTER_PICK_NEAREST_ENABLE         = 0x00000001,
6626 } SCL_V_FILTER_PICK_NEAREST;
6627 
6628 /*
6629  * SCL_V_2TAP_HARDCODE_COEF_EN enum
6630  */
6631 
6632 typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
6633 SCL_V_2TAP_HARDCODE_COEF_DISABLE         = 0x00000000,
6634 SCL_V_2TAP_HARDCODE_COEF_ENABLE          = 0x00000001,
6635 } SCL_V_2TAP_HARDCODE_COEF_EN;
6636 
6637 /*
6638  * SCL_UPDATE_TAKEN enum
6639  */
6640 
6641 typedef enum SCL_UPDATE_TAKEN {
6642 SCL_UPDATE_TAKEN_NO                      = 0x00000000,
6643 SCL_UPDATE_TAKEN_YES                     = 0x00000001,
6644 } SCL_UPDATE_TAKEN;
6645 
6646 /*
6647  * SCL_UPDATE_LOCK enum
6648  */
6649 
6650 typedef enum SCL_UPDATE_LOCK {
6651 SCL_UPDATE_UNLOCKED                      = 0x00000000,
6652 SCL_UPDATE_LOCKED                        = 0x00000001,
6653 } SCL_UPDATE_LOCK;
6654 
6655 /*
6656  * SCL_COEF_UPDATE_COMPLETE enum
6657  */
6658 
6659 typedef enum SCL_COEF_UPDATE_COMPLETE {
6660 SCL_COEF_UPDATE_NOT_COMPLETED            = 0x00000000,
6661 SCL_COEF_UPDATE_COMPLETED                = 0x00000001,
6662 } SCL_COEF_UPDATE_COMPLETE;
6663 
6664 /*
6665  * SCL_HF_SHARP_SCALE_FACTOR enum
6666  */
6667 
6668 typedef enum SCL_HF_SHARP_SCALE_FACTOR {
6669 SCL_HF_SHARP_SCALE_FACTOR_0              = 0x00000000,
6670 SCL_HF_SHARP_SCALE_FACTOR_1              = 0x00000001,
6671 SCL_HF_SHARP_SCALE_FACTOR_2              = 0x00000002,
6672 SCL_HF_SHARP_SCALE_FACTOR_3              = 0x00000003,
6673 SCL_HF_SHARP_SCALE_FACTOR_4              = 0x00000004,
6674 SCL_HF_SHARP_SCALE_FACTOR_5              = 0x00000005,
6675 SCL_HF_SHARP_SCALE_FACTOR_6              = 0x00000006,
6676 SCL_HF_SHARP_SCALE_FACTOR_7              = 0x00000007,
6677 } SCL_HF_SHARP_SCALE_FACTOR;
6678 
6679 /*
6680  * SCL_HF_SHARP_EN enum
6681  */
6682 
6683 typedef enum SCL_HF_SHARP_EN {
6684 SCL_HF_SHARP_DISABLE                     = 0x00000000,
6685 SCL_HF_SHARP_ENABLE                      = 0x00000001,
6686 } SCL_HF_SHARP_EN;
6687 
6688 /*
6689  * SCL_VF_SHARP_SCALE_FACTOR enum
6690  */
6691 
6692 typedef enum SCL_VF_SHARP_SCALE_FACTOR {
6693 SCL_VF_SHARP_SCALE_FACTOR_0              = 0x00000000,
6694 SCL_VF_SHARP_SCALE_FACTOR_1              = 0x00000001,
6695 SCL_VF_SHARP_SCALE_FACTOR_2              = 0x00000002,
6696 SCL_VF_SHARP_SCALE_FACTOR_3              = 0x00000003,
6697 SCL_VF_SHARP_SCALE_FACTOR_4              = 0x00000004,
6698 SCL_VF_SHARP_SCALE_FACTOR_5              = 0x00000005,
6699 SCL_VF_SHARP_SCALE_FACTOR_6              = 0x00000006,
6700 SCL_VF_SHARP_SCALE_FACTOR_7              = 0x00000007,
6701 } SCL_VF_SHARP_SCALE_FACTOR;
6702 
6703 /*
6704  * SCL_VF_SHARP_EN enum
6705  */
6706 
6707 typedef enum SCL_VF_SHARP_EN {
6708 SCL_VF_SHARP_DISABLE                     = 0x00000000,
6709 SCL_VF_SHARP_ENABLE                      = 0x00000001,
6710 } SCL_VF_SHARP_EN;
6711 
6712 /*
6713  * SCL_ALU_DISABLE enum
6714  */
6715 
6716 typedef enum SCL_ALU_DISABLE {
6717 SCL_ALU_ENABLED                          = 0x00000000,
6718 SCL_ALU_DISABLED                         = 0x00000001,
6719 } SCL_ALU_DISABLE;
6720 
6721 /*
6722  * SCL_HOST_CONFLICT_MASK enum
6723  */
6724 
6725 typedef enum SCL_HOST_CONFLICT_MASK {
6726 SCL_HOST_CONFLICT_DISABLE_INTERRUPT      = 0x00000000,
6727 SCL_HOST_CONFLICT_ENABLE_INTERRUPT       = 0x00000001,
6728 } SCL_HOST_CONFLICT_MASK;
6729 
6730 /*
6731  * SCL_SCL_MODE_CHANGE_MASK enum
6732  */
6733 
6734 typedef enum SCL_SCL_MODE_CHANGE_MASK {
6735 SCL_MODE_CHANGE_DISABLE_INTERRUPT        = 0x00000000,
6736 SCL_MODE_CHANGE_ENABLE_INTERRUPT         = 0x00000001,
6737 } SCL_SCL_MODE_CHANGE_MASK;
6738 
6739 /*******************************************************
6740  * SCLV Enums
6741  *******************************************************/
6742 
6743 /*
6744  * SCLV_MODE_SEL enum
6745  */
6746 
6747 typedef enum SCLV_MODE_SEL {
6748 SCLV_MODE_RGB_BYPASS                     = 0x00000000,
6749 SCLV_MODE_RGB_SCALING                    = 0x00000001,
6750 SCLV_MODE_YCBCR_SCALING                  = 0x00000002,
6751 SCLV_MODE_YCBCR_BYPASS                   = 0x00000003,
6752 } SCLV_MODE_SEL;
6753 
6754 /*
6755  * SCLV_INTERLACE_SOURCE enum
6756  */
6757 
6758 typedef enum SCLV_INTERLACE_SOURCE {
6759 INTERLACE_SOURCE_PROGRESSIVE             = 0x00000000,
6760 INTERLACE_SOURCE_INTERLEAVE              = 0x00000001,
6761 INTERLACE_SOURCE_STACK                   = 0x00000002,
6762 } SCLV_INTERLACE_SOURCE;
6763 
6764 /*
6765  * SCLV_UPDATE_LOCK enum
6766  */
6767 
6768 typedef enum SCLV_UPDATE_LOCK {
6769 UPDATE_UNLOCKED                          = 0x00000000,
6770 UPDATE_LOCKED                            = 0x00000001,
6771 } SCLV_UPDATE_LOCK;
6772 
6773 /*
6774  * SCLV_COEF_UPDATE_COMPLETE enum
6775  */
6776 
6777 typedef enum SCLV_COEF_UPDATE_COMPLETE {
6778 COEF_UPDATE_NOT_COMPLETE                 = 0x00000000,
6779 COEF_UPDATE_COMPLETE                     = 0x00000001,
6780 } SCLV_COEF_UPDATE_COMPLETE;
6781 
6782 /*******************************************************
6783  * DPRX_SD Enums
6784  *******************************************************/
6785 
6786 /*
6787  * DPRX_SD_PIXEL_ENCODING enum
6788  */
6789 
6790 typedef enum DPRX_SD_PIXEL_ENCODING {
6791 PIXEL_FORMAT_RGB_444                     = 0x00000000,
6792 PIXEL_FORMAT_YCBCR_444                   = 0x00000001,
6793 PIXEL_FORMAT_YCBCR_422                   = 0x00000002,
6794 PIXEL_FORMAT_Y_ONLY                      = 0x00000003,
6795 } DPRX_SD_PIXEL_ENCODING;
6796 
6797 /*
6798  * DPRX_SD_COMPONENT_DEPTH enum
6799  */
6800 
6801 typedef enum DPRX_SD_COMPONENT_DEPTH {
6802 COMPONENT_DEPTH_6BPC                     = 0x00000000,
6803 COMPONENT_DEPTH_8BPC                     = 0x00000001,
6804 COMPONENT_DEPTH_10BPC                    = 0x00000002,
6805 COMPONENT_DEPTH_12BPC                    = 0x00000003,
6806 COMPONENT_DEPTH_16BPC                    = 0x00000004,
6807 } DPRX_SD_COMPONENT_DEPTH;
6808 
6809 /*******************************************************
6810  * AZF0STREAM Enums
6811  *******************************************************/
6812 
6813 /*
6814  * AZ_LATENCY_COUNTER_CONTROL enum
6815  */
6816 
6817 typedef enum AZ_LATENCY_COUNTER_CONTROL {
6818 AZ_LATENCY_COUNTER_NO_RESET              = 0x00000000,
6819 AZ_LATENCY_COUNTER_RESET_DONE            = 0x00000001,
6820 } AZ_LATENCY_COUNTER_CONTROL;
6821 
6822 /*******************************************************
6823  * BLND Enums
6824  *******************************************************/
6825 
6826 /*
6827  * BLND_CONTROL_BLND_MODE enum
6828  */
6829 
6830 typedef enum BLND_CONTROL_BLND_MODE {
6831 BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
6832 BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY   = 0x00000001,
6833 BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
6834 BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
6835 } BLND_CONTROL_BLND_MODE;
6836 
6837 /*
6838  * BLND_CONTROL_BLND_STEREO_TYPE enum
6839  */
6840 
6841 typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
6842 BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
6843 BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
6844 BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
6845 BLND_CONTROL_BLND_STEREO_TYPE_UNUSED     = 0x00000003,
6846 } BLND_CONTROL_BLND_STEREO_TYPE;
6847 
6848 /*
6849  * BLND_CONTROL_BLND_STEREO_POLARITY enum
6850  */
6851 
6852 typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
6853 BLND_CONTROL_BLND_STEREO_POLARITY_LOW    = 0x00000000,
6854 BLND_CONTROL_BLND_STEREO_POLARITY_HIGH   = 0x00000001,
6855 } BLND_CONTROL_BLND_STEREO_POLARITY;
6856 
6857 /*
6858  * BLND_CONTROL_BLND_FEEDTHROUGH_EN enum
6859  */
6860 
6861 typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
6862 BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE   = 0x00000000,
6863 BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE    = 0x00000001,
6864 } BLND_CONTROL_BLND_FEEDTHROUGH_EN;
6865 
6866 /*
6867  * BLND_CONTROL_BLND_ALPHA_MODE enum
6868  */
6869 
6870 typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
6871 BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
6872 BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
6873 BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
6874 BLND_CONTROL_BLND_ALPHA_MODE_UNUSED      = 0x00000003,
6875 } BLND_CONTROL_BLND_ALPHA_MODE;
6876 
6877 /*
6878  * BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
6879  */
6880 
6881 typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
6882 BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE  = 0x00000000,
6883 BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE  = 0x00000001,
6884 } BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
6885 
6886 /*
6887  * BLND_CONTROL_BLND_MULTIPLIED_MODE enum
6888  */
6889 
6890 typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
6891 BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE  = 0x00000000,
6892 BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE   = 0x00000001,
6893 } BLND_CONTROL_BLND_MULTIPLIED_MODE;
6894 
6895 /*
6896  * BLND_SM_CONTROL2_SM_MODE enum
6897  */
6898 
6899 typedef enum BLND_SM_CONTROL2_SM_MODE {
6900 BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE    = 0x00000000,
6901 BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
6902 BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
6903 BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
6904 } BLND_SM_CONTROL2_SM_MODE;
6905 
6906 /*
6907  * BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum
6908  */
6909 
6910 typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
6911 BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
6912 BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
6913 } BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
6914 
6915 /*
6916  * BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum
6917  */
6918 
6919 typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
6920 BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
6921 BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
6922 } BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
6923 
6924 /*
6925  * BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
6926  */
6927 
6928 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6929 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
6930 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
6931 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
6932 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
6933 } BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
6934 
6935 /*
6936  * BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
6937  */
6938 
6939 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6940 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
6941 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
6942 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
6943 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
6944 } BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
6945 
6946 /*
6947  * BLND_CONTROL2_PTI_ENABLE enum
6948  */
6949 
6950 typedef enum BLND_CONTROL2_PTI_ENABLE {
6951 BLND_CONTROL2_PTI_ENABLE_FALSE           = 0x00000000,
6952 BLND_CONTROL2_PTI_ENABLE_TRUE            = 0x00000001,
6953 } BLND_CONTROL2_PTI_ENABLE;
6954 
6955 /*
6956  * BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
6957  */
6958 
6959 typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6960 BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
6961 BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
6962 } BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
6963 
6964 /*
6965  * BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
6966  */
6967 
6968 typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6969 BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
6970 BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
6971 } BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
6972 
6973 /*
6974  * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
6975  */
6976 
6977 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6978 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6979 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
6980 } BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
6981 
6982 /*
6983  * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
6984  */
6985 
6986 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6987 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
6988 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
6989 } BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
6990 
6991 /*
6992  * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
6993  */
6994 
6995 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6996 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
6997 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
6998 } BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
6999 
7000 /*
7001  * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
7002  */
7003 
7004 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
7005 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
7006 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
7007 } BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
7008 
7009 /*
7010  * BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
7011  */
7012 
7013 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
7014 BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
7015 BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
7016 } BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
7017 
7018 /*
7019  * BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
7020  */
7021 
7022 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
7023 BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
7024 BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
7025 } BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
7026 
7027 /*
7028  * BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
7029  */
7030 
7031 typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
7032 BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
7033 BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
7034 } BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
7035 
7036 /*
7037  * BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
7038  */
7039 
7040 typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
7041 BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
7042 BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
7043 } BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
7044 
7045 /*
7046  * BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
7047  */
7048 
7049 typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
7050 BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
7051 BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
7052 } BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
7053 
7054 /*
7055  * BLND_DEBUG_BLND_CNV_MUX_SELECT enum
7056  */
7057 
7058 typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
7059 BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW       = 0x00000000,
7060 BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH      = 0x00000001,
7061 } BLND_DEBUG_BLND_CNV_MUX_SELECT;
7062 
7063 /*
7064  * BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
7065  */
7066 
7067 typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
7068 BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
7069 BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
7070 } BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
7071 
7072 /*******************************************************
7073  * AZF0ENDPOINT Enums
7074  *******************************************************/
7075 
7076 /*
7077  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7078  */
7079 
7080 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7081 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7082 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7083 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7084 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7085 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7086 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7087 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7088 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7089 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
7090 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7091 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7092 
7093 /*
7094  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7095  */
7096 
7097 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7098 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7099 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7100 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7101 
7102 /*
7103  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7104  */
7105 
7106 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7107 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7108 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7109 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7110 
7111 /*
7112  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7113  */
7114 
7115 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7116 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7117 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7118 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7119 
7120 /*
7121  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7122  */
7123 
7124 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7125 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7126 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7127 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7128 
7129 /*
7130  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7131  */
7132 
7133 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7134 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7135 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7136 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7137 
7138 /*
7139  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7140  */
7141 
7142 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7143 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7144 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7145 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7146 
7147 /*
7148  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7149  */
7150 
7151 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7152 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7153 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7154 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7155 
7156 /*
7157  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7158  */
7159 
7160 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7161 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
7162 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE  = 0x00000001,
7163 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7164 
7165 /*
7166  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7167  */
7168 
7169 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7170 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7171 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7172 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7173 
7174 /*
7175  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7176  */
7177 
7178 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7179 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7180 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7181 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7182 
7183 /*
7184  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7185  */
7186 
7187 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7188 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7189 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7190 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7191 
7192 /*
7193  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7194  */
7195 
7196 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7197 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
7198 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
7199 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7200 
7201 /*
7202  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7203  */
7204 
7205 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7206 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7207 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7208 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7209 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7210 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7211 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7212 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7213 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7214 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
7215 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7216 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7217 
7218 /*
7219  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7220  */
7221 
7222 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7223 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7224 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7225 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7226 
7227 /*
7228  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7229  */
7230 
7231 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7232 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7233 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7234 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7235 
7236 /*
7237  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7238  */
7239 
7240 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7241 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7242 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7243 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7244 
7245 /*
7246  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7247  */
7248 
7249 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7250 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7251 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7252 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7253 
7254 /*
7255  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7256  */
7257 
7258 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7259 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7260 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7261 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7262 
7263 /*
7264  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7265  */
7266 
7267 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7268 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7269 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7270 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7271 
7272 /*
7273  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7274  */
7275 
7276 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7277 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7278 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7279 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7280 
7281 /*
7282  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7283  */
7284 
7285 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7286 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7287 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7288 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7289 
7290 /*
7291  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7292  */
7293 
7294 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7295 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7296 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7297 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7298 
7299 /*
7300  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7301  */
7302 
7303 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7304 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT  = 0x00000000,
7305 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7306 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7307 
7308 /*
7309  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7310  */
7311 
7312 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7313 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN  = 0x00000000,
7314 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN  = 0x00000001,
7315 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7316 
7317 /*
7318  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7319  */
7320 
7321 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7322 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED  = 0x00000000,
7323 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
7324 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7325 
7326 /*
7327  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7328  */
7329 
7330 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7331 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
7332 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
7333 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7334 
7335 /*
7336  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7337  */
7338 
7339 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7340 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
7341 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
7342 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7343 
7344 /*
7345  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7346  */
7347 
7348 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7349 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
7350 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
7351 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7352 
7353 /*
7354  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7355  */
7356 
7357 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7358 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY  = 0x00000000,
7359 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY  = 0x00000001,
7360 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7361 
7362 /*
7363  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7364  */
7365 
7366 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7367 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
7368 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
7369 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7370 
7371 /*
7372  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7373  */
7374 
7375 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7376 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
7377 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
7378 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7379 
7380 /*
7381  * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
7382  */
7383 
7384 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
7385 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
7386 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
7387 } AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
7388 
7389 /*
7390  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7391  */
7392 
7393 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7394 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY  = 0x00000000,
7395 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY  = 0x00000001,
7396 } AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7397 
7398 /*******************************************************
7399  * AZF0INPUTENDPOINT Enums
7400  *******************************************************/
7401 
7402 /*
7403  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7404  */
7405 
7406 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7407 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7408 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7409 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7410 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7411 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7412 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7413 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7414 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7415 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
7416 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7417 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7418 
7419 /*
7420  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7421  */
7422 
7423 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7424 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7425 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7426 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7427 
7428 /*
7429  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7430  */
7431 
7432 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7433 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7434 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7435 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7436 
7437 /*
7438  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7439  */
7440 
7441 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7442 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG  = 0x00000000,
7443 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL  = 0x00000001,
7444 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7445 
7446 /*
7447  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7448  */
7449 
7450 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7451 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7452 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7453 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7454 
7455 /*
7456  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7457  */
7458 
7459 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7460 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7461 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7462 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7463 
7464 /*
7465  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7466  */
7467 
7468 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7469 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7470 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7471 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7472 
7473 /*
7474  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7475  */
7476 
7477 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7478 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING  = 0x00000000,
7479 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7480 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7481 
7482 /*
7483  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7484  */
7485 
7486 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7487 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
7488 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE  = 0x00000001,
7489 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7490 
7491 /*
7492  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7493  */
7494 
7495 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7496 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7497 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER  = 0x00000001,
7498 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7499 
7500 /*
7501  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7502  */
7503 
7504 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7505 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7506 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7507 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7508 
7509 /*
7510  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7511  */
7512 
7513 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7514 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7515 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7516 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7517 
7518 /*
7519  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7520  */
7521 
7522 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7523 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
7524 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
7525 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7526 
7527 /*
7528  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7529  */
7530 
7531 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7532 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7533 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7534 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7535 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7536 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7537 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7538 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7539 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7540 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
7541 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7542 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7543 
7544 /*
7545  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7546  */
7547 
7548 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7549 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP  = 0x00000000,
7550 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP  = 0x00000001,
7551 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7552 
7553 /*
7554  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7555  */
7556 
7557 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7558 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7559 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7560 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7561 
7562 /*
7563  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7564  */
7565 
7566 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7567 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7568 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7569 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7570 
7571 /*
7572  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7573  */
7574 
7575 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7576 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7577 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7578 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7579 
7580 /*
7581  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7582  */
7583 
7584 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7585 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7586 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7587 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7588 
7589 /*
7590  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7591  */
7592 
7593 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7594 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES  = 0x00000000,
7595 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES  = 0x00000001,
7596 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7597 
7598 /*
7599  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7600  */
7601 
7602 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7603 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7604 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7605 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7606 
7607 /*
7608  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7609  */
7610 
7611 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7612 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7613 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7614 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7615 
7616 /*
7617  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7618  */
7619 
7620 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7621 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7622 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7623 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7624 
7625 /*
7626  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7627  */
7628 
7629 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7630 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7631 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7632 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7633 
7634 /*
7635  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
7636  */
7637 
7638 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
7639 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED  = 0x00000000,
7640 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED  = 0x00000001,
7641 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
7642 
7643 /*
7644  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7645  */
7646 
7647 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7648 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN  = 0x00000000,
7649 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN  = 0x00000001,
7650 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7651 
7652 /*
7653  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
7654  */
7655 
7656 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
7657 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED  = 0x00000000,
7658 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED  = 0x00000001,
7659 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
7660 
7661 /*
7662  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7663  */
7664 
7665 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7666 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED  = 0x00000000,
7667 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
7668 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7669 
7670 /*
7671  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7672  */
7673 
7674 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7675 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
7676 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
7677 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7678 
7679 /*
7680  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7681  */
7682 
7683 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7684 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
7685 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
7686 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7687 
7688 /*
7689  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7690  */
7691 
7692 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7693 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
7694 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
7695 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7696 
7697 /*
7698  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7699  */
7700 
7701 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7702 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000000,
7703 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000001,
7704 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7705 
7706 /*
7707  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7708  */
7709 
7710 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7711 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
7712 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
7713 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7714 
7715 /*
7716  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7717  */
7718 
7719 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7720 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
7721 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
7722 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7723 
7724 /*
7725  * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7726  */
7727 
7728 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7729 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY  = 0x00000000,
7730 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY  = 0x00000001,
7731 } AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7732 
7733 /*******************************************************
7734  * UNP Enums
7735  *******************************************************/
7736 
7737 /*
7738  * UNP_GRPH_EN enum
7739  */
7740 
7741 typedef enum UNP_GRPH_EN {
7742 UNP_GRPH_DISABLED                        = 0x00000000,
7743 UNP_GRPH_ENABLED                         = 0x00000001,
7744 } UNP_GRPH_EN;
7745 
7746 /*
7747  * UNP_GRPH_DEPTH enum
7748  */
7749 
7750 typedef enum UNP_GRPH_DEPTH {
7751 UNP_GRPH_8BPP                            = 0x00000000,
7752 UNP_GRPH_16BPP                           = 0x00000001,
7753 UNP_GRPH_32BPP                           = 0x00000002,
7754 } UNP_GRPH_DEPTH;
7755 
7756 /*
7757  * UNP_GRPH_NUM_BANKS enum
7758  */
7759 
7760 typedef enum UNP_GRPH_NUM_BANKS {
7761 UNP_GRPH_ADDR_SURF_2_BANK                = 0x00000000,
7762 UNP_GRPH_ADDR_SURF_4_BANK                = 0x00000001,
7763 UNP_GRPH_ADDR_SURF_8_BANK                = 0x00000002,
7764 UNP_GRPH_ADDR_SURF_16_BANK               = 0x00000003,
7765 } UNP_GRPH_NUM_BANKS;
7766 
7767 /*
7768  * UNP_GRPH_BANK_WIDTH enum
7769  */
7770 
7771 typedef enum UNP_GRPH_BANK_WIDTH {
7772 UNP_GRPH_ADDR_SURF_BANK_WIDTH_1          = 0x00000000,
7773 UNP_GRPH_ADDR_SURF_BANK_WIDTH_2          = 0x00000001,
7774 UNP_GRPH_ADDR_SURF_BANK_WIDTH_4          = 0x00000002,
7775 UNP_GRPH_ADDR_SURF_BANK_WIDTH_8          = 0x00000003,
7776 } UNP_GRPH_BANK_WIDTH;
7777 
7778 /*
7779  * UNP_GRPH_BANK_HEIGHT enum
7780  */
7781 
7782 typedef enum UNP_GRPH_BANK_HEIGHT {
7783 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1         = 0x00000000,
7784 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2         = 0x00000001,
7785 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4         = 0x00000002,
7786 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8         = 0x00000003,
7787 } UNP_GRPH_BANK_HEIGHT;
7788 
7789 /*
7790  * UNP_GRPH_TILE_SPLIT enum
7791  */
7792 
7793 typedef enum UNP_GRPH_TILE_SPLIT {
7794 UNP_ADDR_SURF_TILE_SPLIT_64B             = 0x00000000,
7795 UNP_ADDR_SURF_TILE_SPLIT_128B            = 0x00000001,
7796 UNP_ADDR_SURF_TILE_SPLIT_256B            = 0x00000002,
7797 UNP_ADDR_SURF_TILE_SPLIT_512B            = 0x00000003,
7798 UNP_ADDR_SURF_TILE_SPLIT_1KB             = 0x00000004,
7799 UNP_ADDR_SURF_TILE_SPLIT_2KB             = 0x00000005,
7800 UNP_ADDR_SURF_TILE_SPLIT_4KB             = 0x00000006,
7801 } UNP_GRPH_TILE_SPLIT;
7802 
7803 /*
7804  * UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
7805  */
7806 
7807 typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
7808 UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0     = 0x00000000,
7809 UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1     = 0x00000001,
7810 } UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
7811 
7812 /*
7813  * UNP_GRPH_MACRO_TILE_ASPECT enum
7814  */
7815 
7816 typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
7817 UNP_ADDR_SURF_MACRO_ASPECT_1             = 0x00000000,
7818 UNP_ADDR_SURF_MACRO_ASPECT_2             = 0x00000001,
7819 UNP_ADDR_SURF_MACRO_ASPECT_4             = 0x00000002,
7820 UNP_ADDR_SURF_MACRO_ASPECT_8             = 0x00000003,
7821 } UNP_GRPH_MACRO_TILE_ASPECT;
7822 
7823 /*
7824  * UNP_GRPH_COLOR_EXPANSION_MODE enum
7825  */
7826 
7827 typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
7828 UNP_GRPH_DYNAMIC_EXPANSION               = 0x00000000,
7829 UNP_GRPH_ZERO_EXPANSION                  = 0x00000001,
7830 } UNP_GRPH_COLOR_EXPANSION_MODE;
7831 
7832 /*
7833  * UNP_VIDEO_FORMAT enum
7834  */
7835 
7836 typedef enum UNP_VIDEO_FORMAT {
7837 UNP_VIDEO_FORMAT0                        = 0x00000000,
7838 UNP_VIDEO_FORMAT1                        = 0x00000001,
7839 UNP_VIDEO_FORMAT_YUV420_YCbCr            = 0x00000002,
7840 UNP_VIDEO_FORMAT_YUV420_YCrCb            = 0x00000003,
7841 UNP_VIDEO_FORMAT_YUV422_YCb              = 0x00000004,
7842 UNP_VIDEO_FORMAT_YUV422_YCr              = 0x00000005,
7843 UNP_VIDEO_FORMAT_YUV422_CbY              = 0x00000006,
7844 UNP_VIDEO_FORMAT_YUV422_CrY              = 0x00000007,
7845 } UNP_VIDEO_FORMAT;
7846 
7847 /*
7848  * UNP_GRPH_ENDIAN_SWAP enum
7849  */
7850 
7851 typedef enum UNP_GRPH_ENDIAN_SWAP {
7852 UNP_GRPH_ENDIAN_SWAP_NONE                = 0x00000000,
7853 UNP_GRPH_ENDIAN_SWAP_8IN16               = 0x00000001,
7854 UNP_GRPH_ENDIAN_SWAP_8IN32               = 0x00000002,
7855 UNP_GRPH_ENDIAN_SWAP_8IN43               = 0x00000003,
7856 } UNP_GRPH_ENDIAN_SWAP;
7857 
7858 /*
7859  * UNP_GRPH_RED_CROSSBAR enum
7860  */
7861 
7862 typedef enum UNP_GRPH_RED_CROSSBAR {
7863 UNP_GRPH_RED_CROSSBAR_R_Cr               = 0x00000000,
7864 UNP_GRPH_RED_CROSSBAR_G_Y                = 0x00000001,
7865 UNP_GRPH_RED_CROSSBAR_B_Cb               = 0x00000002,
7866 UNP_GRPH_RED_CROSSBAR_A                  = 0x00000003,
7867 } UNP_GRPH_RED_CROSSBAR;
7868 
7869 /*
7870  * UNP_GRPH_GREEN_CROSSBAR enum
7871  */
7872 
7873 typedef enum UNP_GRPH_GREEN_CROSSBAR {
7874 UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y     = 0x00000000,
7875 UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C   = 0x00000001,
7876 UNP_UNP_GRPH_GREEN_CROSSBAR_A            = 0x00000002,
7877 UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr         = 0x00000003,
7878 } UNP_GRPH_GREEN_CROSSBAR;
7879 
7880 /*
7881  * UNP_GRPH_BLUE_CROSSBAR enum
7882  */
7883 
7884 typedef enum UNP_GRPH_BLUE_CROSSBAR {
7885 UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C        = 0x00000000,
7886 UNP_GRPH_BLUE_CROSSBAR_A                 = 0x00000001,
7887 UNP_GRPH_BLUE_CROSSBAR_R_Cr              = 0x00000002,
7888 UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y          = 0x00000003,
7889 } UNP_GRPH_BLUE_CROSSBAR;
7890 
7891 /*
7892  * UNP_GRPH_MODE_UPDATE_LOCKG enum
7893  */
7894 
7895 typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
7896 UNP_GRPH_UPDATE_LOCK_0                   = 0x00000000,
7897 UNP_GRPH_UPDATE_LOCK_1                   = 0x00000001,
7898 } UNP_GRPH_MODE_UPDATE_LOCKG;
7899 
7900 /*
7901  * UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
7902  */
7903 
7904 typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
7905 UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0    = 0x00000000,
7906 UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1    = 0x00000001,
7907 } UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
7908 
7909 /*
7910  * UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
7911  */
7912 
7913 typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
7914 UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0  = 0x00000000,
7915 UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1  = 0x00000001,
7916 } UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
7917 
7918 /*
7919  * UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
7920  */
7921 
7922 typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
7923 UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0  = 0x00000000,
7924 UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1  = 0x00000001,
7925 } UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
7926 
7927 /*
7928  * UNP_GRPH_STEREOSYNC_FLIP_EN enum
7929  */
7930 
7931 typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
7932 UNP_GRPH_STEREOSYNC_FLIP_DISABLE         = 0x00000000,
7933 UNP_GRPH_STEREOSYNC_FLIP_ENABLE          = 0x00000001,
7934 } UNP_GRPH_STEREOSYNC_FLIP_EN;
7935 
7936 /*
7937  * UNP_GRPH_STEREOSYNC_FLIP_MODE enum
7938  */
7939 
7940 typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
7941 UNP_GRPH_STEREOSYNC_FLIP_MODE_0          = 0x00000000,
7942 UNP_GRPH_STEREOSYNC_FLIP_MODE_1          = 0x00000001,
7943 UNP_GRPH_STEREOSYNC_FLIP_MODE_2          = 0x00000002,
7944 UNP_GRPH_STEREOSYNC_FLIP_MODE_3          = 0x00000003,
7945 } UNP_GRPH_STEREOSYNC_FLIP_MODE;
7946 
7947 /*
7948  * UNP_GRPH_STACK_INTERLACE_FLIP_EN enum
7949  */
7950 
7951 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
7952 UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE    = 0x00000000,
7953 UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE     = 0x00000001,
7954 } UNP_GRPH_STACK_INTERLACE_FLIP_EN;
7955 
7956 /*
7957  * UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum
7958  */
7959 
7960 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
7961 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0     = 0x00000000,
7962 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1     = 0x00000001,
7963 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2     = 0x00000002,
7964 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3     = 0x00000003,
7965 } UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
7966 
7967 /*
7968  * UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum
7969  */
7970 
7971 typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
7972 UNP_GRPH_STEREOSYNC_SELECT_EN            = 0x00000000,
7973 UNP_GRPH_STEREOSYNC_SELECT_DIS           = 0x00000001,
7974 } UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
7975 
7976 /*
7977  * UNP_CRC_SOURCE_SEL enum
7978  */
7979 
7980 typedef enum UNP_CRC_SOURCE_SEL {
7981 UNP_CRC_SOURCE_SEL_NP_TO_LBV             = 0x00000000,
7982 UNP_CRC_SOURCE_SEL_LOWER32               = 0x00000001,
7983 UNP_CRC_SOURCE_SEL_RESERVED              = 0x00000002,
7984 UNP_CRC_SOURCE_SEL_LOWER16               = 0x00000003,
7985 UNP_CRC_SOURCE_SEL_UNP_TO_LBV            = 0x00000004,
7986 } UNP_CRC_SOURCE_SEL;
7987 
7988 /*
7989  * UNP_CRC_LINE_SEL enum
7990  */
7991 
7992 typedef enum UNP_CRC_LINE_SEL {
7993 UNP_CRC_LINE_SEL_RESERVED                = 0x00000000,
7994 UNP_CRC_LINE_SEL_EVEN_ONLY               = 0x00000001,
7995 UNP_CRC_LINE_SEL_ODD_ONLY                = 0x00000002,
7996 UNP_CRC_LINE_SEL_ODD_EVEN                = 0x00000003,
7997 } UNP_CRC_LINE_SEL;
7998 
7999 /*
8000  * UNP_ROTATION_ANGLE enum
8001  */
8002 
8003 typedef enum UNP_ROTATION_ANGLE {
8004 UNP_ROTATION_ANGLE_0                     = 0x00000000,
8005 UNP_ROTATION_ANGLE_90                    = 0x00000001,
8006 UNP_ROTATION_ANGLE_180                   = 0x00000002,
8007 UNP_ROTATION_ANGLE_270                   = 0x00000003,
8008 UNP_ROTATION_ANGLE_0m                    = 0x00000004,
8009 UNP_ROTATION_ANGLE_90m                   = 0x00000005,
8010 UNP_ROTATION_ANGLE_180m                  = 0x00000006,
8011 UNP_ROTATION_ANGLE_270m                  = 0x00000007,
8012 } UNP_ROTATION_ANGLE;
8013 
8014 /*
8015  * UNP_PIXEL_DROP enum
8016  */
8017 
8018 typedef enum UNP_PIXEL_DROP {
8019 UNP_PIXEL_NO_DROP                        = 0x00000000,
8020 UNP_PIXEL_DROPPING                       = 0x00000001,
8021 } UNP_PIXEL_DROP;
8022 
8023 /*
8024  * UNP_BUFFER_MODE enum
8025  */
8026 
8027 typedef enum UNP_BUFFER_MODE {
8028 UNP_BUFFER_MODE_LUMA                     = 0x00000000,
8029 UNP_BUFFER_MODE_LUMA_CHROMA              = 0x00000001,
8030 } UNP_BUFFER_MODE;
8031 
8032 /*******************************************************
8033  * DP Enums
8034  *******************************************************/
8035 
8036 /*
8037  * DP_LINK_TRAINING_COMPLETE enum
8038  */
8039 
8040 typedef enum DP_LINK_TRAINING_COMPLETE {
8041 DP_LINK_TRAINING_NOT_COMPLETE            = 0x00000000,
8042 DP_LINK_TRAINING_ALREADY_COMPLETE        = 0x00000001,
8043 } DP_LINK_TRAINING_COMPLETE;
8044 
8045 /*
8046  * DP_EMBEDDED_PANEL_MODE enum
8047  */
8048 
8049 typedef enum DP_EMBEDDED_PANEL_MODE {
8050 DP_EXTERNAL_PANEL                        = 0x00000000,
8051 DP_EMBEDDED_PANEL                        = 0x00000001,
8052 } DP_EMBEDDED_PANEL_MODE;
8053 
8054 /*
8055  * DP_PIXEL_ENCODING enum
8056  */
8057 
8058 typedef enum DP_PIXEL_ENCODING {
8059 DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
8060 DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
8061 DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
8062 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
8063 DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
8064 DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
8065 DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
8066 } DP_PIXEL_ENCODING;
8067 
8068 /*
8069  * DP_DYN_RANGE enum
8070  */
8071 
8072 typedef enum DP_DYN_RANGE {
8073 DP_DYN_VESA_RANGE                        = 0x00000000,
8074 DP_DYN_CEA_RANGE                         = 0x00000001,
8075 } DP_DYN_RANGE;
8076 
8077 /*
8078  * DP_YCBCR_RANGE enum
8079  */
8080 
8081 typedef enum DP_YCBCR_RANGE {
8082 DP_YCBCR_RANGE_BT601_5                   = 0x00000000,
8083 DP_YCBCR_RANGE_BT709_5                   = 0x00000001,
8084 } DP_YCBCR_RANGE;
8085 
8086 /*
8087  * DP_COMPONENT_DEPTH enum
8088  */
8089 
8090 typedef enum DP_COMPONENT_DEPTH {
8091 DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
8092 DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
8093 DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
8094 DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
8095 DP_COMPONENT_DEPTH_16BPC_RESERVED        = 0x00000004,
8096 DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
8097 } DP_COMPONENT_DEPTH;
8098 
8099 /*
8100  * DP_MSA_MISC0_OVERRIDE_ENABLE enum
8101  */
8102 
8103 typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
8104 MSA_MISC0_OVERRIDE_DISABLE               = 0x00000000,
8105 MSA_MISC0_OVERRIDE_ENABLE                = 0x00000001,
8106 } DP_MSA_MISC0_OVERRIDE_ENABLE;
8107 
8108 /*
8109  * DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum
8110  */
8111 
8112 typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
8113 MSA_MISC1_BIT7_OVERRIDE_DISABLE          = 0x00000000,
8114 MSA_MISC1_BIT7_OVERRIDE_ENABLE           = 0x00000001,
8115 } DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
8116 
8117 /*
8118  * DP_UDI_LANES enum
8119  */
8120 
8121 typedef enum DP_UDI_LANES {
8122 DP_UDI_1_LANE                            = 0x00000000,
8123 DP_UDI_2_LANES                           = 0x00000001,
8124 DP_UDI_LANES_RESERVED                    = 0x00000002,
8125 DP_UDI_4_LANES                           = 0x00000003,
8126 } DP_UDI_LANES;
8127 
8128 /*
8129  * DP_VID_STREAM_DIS_DEFER enum
8130  */
8131 
8132 typedef enum DP_VID_STREAM_DIS_DEFER {
8133 DP_VID_STREAM_DIS_NO_DEFER               = 0x00000000,
8134 DP_VID_STREAM_DIS_DEFER_TO_HBLANK        = 0x00000001,
8135 DP_VID_STREAM_DIS_DEFER_TO_VBLANK        = 0x00000002,
8136 } DP_VID_STREAM_DIS_DEFER;
8137 
8138 /*
8139  * DP_STEER_OVERFLOW_ACK enum
8140  */
8141 
8142 typedef enum DP_STEER_OVERFLOW_ACK {
8143 DP_STEER_OVERFLOW_ACK_NO_EFFECT          = 0x00000000,
8144 DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT      = 0x00000001,
8145 } DP_STEER_OVERFLOW_ACK;
8146 
8147 /*
8148  * DP_STEER_OVERFLOW_MASK enum
8149  */
8150 
8151 typedef enum DP_STEER_OVERFLOW_MASK {
8152 DP_STEER_OVERFLOW_MASKED                 = 0x00000000,
8153 DP_STEER_OVERFLOW_UNMASK                 = 0x00000001,
8154 } DP_STEER_OVERFLOW_MASK;
8155 
8156 /*
8157  * DP_TU_OVERFLOW_ACK enum
8158  */
8159 
8160 typedef enum DP_TU_OVERFLOW_ACK {
8161 DP_TU_OVERFLOW_ACK_NO_EFFECT             = 0x00000000,
8162 DP_TU_OVERFLOW_ACK_CLR_INTERRUPT         = 0x00000001,
8163 } DP_TU_OVERFLOW_ACK;
8164 
8165 /*
8166  * DPHY_ALT_SCRAMBLER_RESET_EN enum
8167  */
8168 
8169 typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
8170 DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE   = 0x00000000,
8171 DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION  = 0x00000001,
8172 } DPHY_ALT_SCRAMBLER_RESET_EN;
8173 
8174 /*
8175  * DPHY_ALT_SCRAMBLER_RESET_SEL enum
8176  */
8177 
8178 typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
8179 DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE  = 0x00000000,
8180 DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE  = 0x00000001,
8181 } DPHY_ALT_SCRAMBLER_RESET_SEL;
8182 
8183 /*
8184  * DP_VID_TIMING_MODE enum
8185  */
8186 
8187 typedef enum DP_VID_TIMING_MODE {
8188 DP_VID_TIMING_MODE_ASYNC                 = 0x00000000,
8189 DP_VID_TIMING_MODE_SYNC                  = 0x00000001,
8190 } DP_VID_TIMING_MODE;
8191 
8192 /*
8193  * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
8194  */
8195 
8196 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
8197 DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE  = 0x00000000,
8198 DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START  = 0x00000001,
8199 } DP_VID_M_N_DOUBLE_BUFFER_MODE;
8200 
8201 /*
8202  * DP_VID_M_N_GEN_EN enum
8203  */
8204 
8205 typedef enum DP_VID_M_N_GEN_EN {
8206 DP_VID_M_N_PROGRAMMED_VIA_REG            = 0x00000000,
8207 DP_VID_M_N_CALC_AUTO                     = 0x00000001,
8208 } DP_VID_M_N_GEN_EN;
8209 
8210 /*
8211  * DP_VID_M_DOUBLE_VALUE_EN enum
8212  */
8213 
8214 typedef enum DP_VID_M_DOUBLE_VALUE_EN {
8215 DP_VID_M_INPUT_PIXEL_RATE                = 0x00000000,
8216 DP_VID_M_DOUBLE_INPUT_PIXEL_RATE         = 0x00000001,
8217 } DP_VID_M_DOUBLE_VALUE_EN;
8218 
8219 /*
8220  * DP_VID_ENHANCED_FRAME_MODE enum
8221  */
8222 
8223 typedef enum DP_VID_ENHANCED_FRAME_MODE {
8224 VID_NORMAL_FRAME_MODE                    = 0x00000000,
8225 VID_ENHANCED_MODE                        = 0x00000001,
8226 } DP_VID_ENHANCED_FRAME_MODE;
8227 
8228 /*
8229  * DP_VID_MSA_TOP_FIELD_MODE enum
8230  */
8231 
8232 typedef enum DP_VID_MSA_TOP_FIELD_MODE {
8233 DP_TOP_FIELD_ONLY                        = 0x00000000,
8234 DP_TOP_PLUS_BOTTOM_FIELD                 = 0x00000001,
8235 } DP_VID_MSA_TOP_FIELD_MODE;
8236 
8237 /*
8238  * DP_VID_VBID_FIELD_POL enum
8239  */
8240 
8241 typedef enum DP_VID_VBID_FIELD_POL {
8242 DP_VID_VBID_FIELD_POL_NORMAL             = 0x00000000,
8243 DP_VID_VBID_FIELD_POL_INV                = 0x00000001,
8244 } DP_VID_VBID_FIELD_POL;
8245 
8246 /*
8247  * DP_VID_STREAM_DISABLE_ACK enum
8248  */
8249 
8250 typedef enum DP_VID_STREAM_DISABLE_ACK {
8251 ID_STREAM_DISABLE_NO_ACK                 = 0x00000000,
8252 ID_STREAM_DISABLE_ACKED                  = 0x00000001,
8253 } DP_VID_STREAM_DISABLE_ACK;
8254 
8255 /*
8256  * DP_VID_STREAM_DISABLE_MASK enum
8257  */
8258 
8259 typedef enum DP_VID_STREAM_DISABLE_MASK {
8260 VID_STREAM_DISABLE_MASKED                = 0x00000000,
8261 VID_STREAM_DISABLE_UNMASK                = 0x00000001,
8262 } DP_VID_STREAM_DISABLE_MASK;
8263 
8264 /*
8265  * DPHY_ATEST_SEL_LANE0 enum
8266  */
8267 
8268 typedef enum DPHY_ATEST_SEL_LANE0 {
8269 DPHY_ATEST_LANE0_PRBS_PATTERN            = 0x00000000,
8270 DPHY_ATEST_LANE0_REG_PATTERN             = 0x00000001,
8271 } DPHY_ATEST_SEL_LANE0;
8272 
8273 /*
8274  * DPHY_ATEST_SEL_LANE1 enum
8275  */
8276 
8277 typedef enum DPHY_ATEST_SEL_LANE1 {
8278 DPHY_ATEST_LANE1_PRBS_PATTERN            = 0x00000000,
8279 DPHY_ATEST_LANE1_REG_PATTERN             = 0x00000001,
8280 } DPHY_ATEST_SEL_LANE1;
8281 
8282 /*
8283  * DPHY_ATEST_SEL_LANE2 enum
8284  */
8285 
8286 typedef enum DPHY_ATEST_SEL_LANE2 {
8287 DPHY_ATEST_LANE2_PRBS_PATTERN            = 0x00000000,
8288 DPHY_ATEST_LANE2_REG_PATTERN             = 0x00000001,
8289 } DPHY_ATEST_SEL_LANE2;
8290 
8291 /*
8292  * DPHY_ATEST_SEL_LANE3 enum
8293  */
8294 
8295 typedef enum DPHY_ATEST_SEL_LANE3 {
8296 DPHY_ATEST_LANE3_PRBS_PATTERN            = 0x00000000,
8297 DPHY_ATEST_LANE3_REG_PATTERN             = 0x00000001,
8298 } DPHY_ATEST_SEL_LANE3;
8299 
8300 /*
8301  * DPHY_SCRAMBLER_SEL enum
8302  */
8303 
8304 typedef enum DPHY_SCRAMBLER_SEL {
8305 DPHY_SCRAMBLER_SEL_LANE_DATA             = 0x00000000,
8306 DPHY_SCRAMBLER_SEL_DBG_DATA              = 0x00000001,
8307 } DPHY_SCRAMBLER_SEL;
8308 
8309 /*
8310  * DPHY_BYPASS enum
8311  */
8312 
8313 typedef enum DPHY_BYPASS {
8314 DPHY_8B10B_OUTPUT                        = 0x00000000,
8315 DPHY_DBG_OUTPUT                          = 0x00000001,
8316 } DPHY_BYPASS;
8317 
8318 /*
8319  * DPHY_SKEW_BYPASS enum
8320  */
8321 
8322 typedef enum DPHY_SKEW_BYPASS {
8323 DPHY_WITH_SKEW                           = 0x00000000,
8324 DPHY_NO_SKEW                             = 0x00000001,
8325 } DPHY_SKEW_BYPASS;
8326 
8327 /*
8328  * DPHY_TRAINING_PATTERN_SEL enum
8329  */
8330 
8331 typedef enum DPHY_TRAINING_PATTERN_SEL {
8332 DPHY_TRAINING_PATTERN_1                  = 0x00000000,
8333 DPHY_TRAINING_PATTERN_2                  = 0x00000001,
8334 DPHY_TRAINING_PATTERN_3                  = 0x00000002,
8335 DPHY_TRAINING_PATTERN_4                  = 0x00000003,
8336 } DPHY_TRAINING_PATTERN_SEL;
8337 
8338 /*
8339  * DPHY_8B10B_RESET enum
8340  */
8341 
8342 typedef enum DPHY_8B10B_RESET {
8343 DPHY_8B10B_NOT_RESET                     = 0x00000000,
8344 DPHY_8B10B_RESETET                       = 0x00000001,
8345 } DPHY_8B10B_RESET;
8346 
8347 /*
8348  * DP_DPHY_8B10B_EXT_DISP enum
8349  */
8350 
8351 typedef enum DP_DPHY_8B10B_EXT_DISP {
8352 DP_DPHY_8B10B_EXT_DISP_ZERO              = 0x00000000,
8353 DP_DPHY_8B10B_EXT_DISP_ONE               = 0x00000001,
8354 } DP_DPHY_8B10B_EXT_DISP;
8355 
8356 /*
8357  * DPHY_8B10B_CUR_DISP enum
8358  */
8359 
8360 typedef enum DPHY_8B10B_CUR_DISP {
8361 DPHY_8B10B_CUR_DISP_ZERO                 = 0x00000000,
8362 DPHY_8B10B_CUR_DISP_ONE                  = 0x00000001,
8363 } DPHY_8B10B_CUR_DISP;
8364 
8365 /*
8366  * DPHY_PRBS_EN enum
8367  */
8368 
8369 typedef enum DPHY_PRBS_EN {
8370 DPHY_PRBS_DISABLE                        = 0x00000000,
8371 DPHY_PRBS_ENABLE                         = 0x00000001,
8372 } DPHY_PRBS_EN;
8373 
8374 /*
8375  * DPHY_PRBS_SEL enum
8376  */
8377 
8378 typedef enum DPHY_PRBS_SEL {
8379 DPHY_PRBS7_SELECTED                      = 0x00000000,
8380 DPHY_PRBS23_SELECTED                     = 0x00000001,
8381 DPHY_PRBS11_SELECTED                     = 0x00000002,
8382 } DPHY_PRBS_SEL;
8383 
8384 /*
8385  * DPHY_SCRAMBLER_DIS enum
8386  */
8387 
8388 typedef enum DPHY_SCRAMBLER_DIS {
8389 DPHY_SCR_ENABLED                         = 0x00000000,
8390 DPHY_SCR_DISABLED                        = 0x00000001,
8391 } DPHY_SCRAMBLER_DIS;
8392 
8393 /*
8394  * DPHY_SCRAMBLER_ADVANCE enum
8395  */
8396 
8397 typedef enum DPHY_SCRAMBLER_ADVANCE {
8398 DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY  = 0x00000000,
8399 DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL  = 0x00000001,
8400 } DPHY_SCRAMBLER_ADVANCE;
8401 
8402 /*
8403  * DPHY_SCRAMBLER_KCODE enum
8404  */
8405 
8406 typedef enum DPHY_SCRAMBLER_KCODE {
8407 DPHY_SCRAMBLER_KCODE_DISABLED            = 0x00000000,
8408 DPHY_SCRAMBLER_KCODE_ENABLED             = 0x00000001,
8409 } DPHY_SCRAMBLER_KCODE;
8410 
8411 /*
8412  * DPHY_LOAD_BS_COUNT_START enum
8413  */
8414 
8415 typedef enum DPHY_LOAD_BS_COUNT_START {
8416 DPHY_LOAD_BS_COUNT_STARTED               = 0x00000000,
8417 DPHY_LOAD_BS_COUNT_NOT_STARTED           = 0x00000001,
8418 } DPHY_LOAD_BS_COUNT_START;
8419 
8420 /*
8421  * DPHY_CRC_EN enum
8422  */
8423 
8424 typedef enum DPHY_CRC_EN {
8425 DPHY_CRC_DISABLED                        = 0x00000000,
8426 DPHY_CRC_ENABLED                         = 0x00000001,
8427 } DPHY_CRC_EN;
8428 
8429 /*
8430  * DPHY_CRC_CONT_EN enum
8431  */
8432 
8433 typedef enum DPHY_CRC_CONT_EN {
8434 DPHY_CRC_ONE_SHOT                        = 0x00000000,
8435 DPHY_CRC_CONTINUOUS                      = 0x00000001,
8436 } DPHY_CRC_CONT_EN;
8437 
8438 /*
8439  * DPHY_CRC_FIELD enum
8440  */
8441 
8442 typedef enum DPHY_CRC_FIELD {
8443 DPHY_CRC_START_FROM_TOP_FIELD            = 0x00000000,
8444 DPHY_CRC_START_FROM_BOTTOM_FIELD         = 0x00000001,
8445 } DPHY_CRC_FIELD;
8446 
8447 /*
8448  * DPHY_CRC_SEL enum
8449  */
8450 
8451 typedef enum DPHY_CRC_SEL {
8452 DPHY_CRC_LANE0_SELECTED                  = 0x00000000,
8453 DPHY_CRC_LANE1_SELECTED                  = 0x00000001,
8454 DPHY_CRC_LANE2_SELECTED                  = 0x00000002,
8455 DPHY_CRC_LANE3_SELECTED                  = 0x00000003,
8456 } DPHY_CRC_SEL;
8457 
8458 /*
8459  * DPHY_RX_FAST_TRAINING_CAPABLE enum
8460  */
8461 
8462 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
8463 DPHY_FAST_TRAINING_NOT_CAPABLE_0         = 0x00000000,
8464 DPHY_FAST_TRAINING_CAPABLE               = 0x00000001,
8465 } DPHY_RX_FAST_TRAINING_CAPABLE;
8466 
8467 /*
8468  * DP_SEC_COLLISION_ACK enum
8469  */
8470 
8471 typedef enum DP_SEC_COLLISION_ACK {
8472 DP_SEC_COLLISION_ACK_NO_EFFECT           = 0x00000000,
8473 DP_SEC_COLLISION_ACK_CLR_FLAG            = 0x00000001,
8474 } DP_SEC_COLLISION_ACK;
8475 
8476 /*
8477  * DP_SEC_AUDIO_MUTE enum
8478  */
8479 
8480 typedef enum DP_SEC_AUDIO_MUTE {
8481 DP_SEC_AUDIO_MUTE_HW_CTRL                = 0x00000000,
8482 DP_SEC_AUDIO_MUTE_SW_CTRL                = 0x00000001,
8483 } DP_SEC_AUDIO_MUTE;
8484 
8485 /*
8486  * DP_SEC_TIMESTAMP_MODE enum
8487  */
8488 
8489 typedef enum DP_SEC_TIMESTAMP_MODE {
8490 DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE       = 0x00000000,
8491 DP_SEC_TIMESTAMP_AUTO_CALC_MODE          = 0x00000001,
8492 } DP_SEC_TIMESTAMP_MODE;
8493 
8494 /*
8495  * DP_SEC_ASP_PRIORITY enum
8496  */
8497 
8498 typedef enum DP_SEC_ASP_PRIORITY {
8499 DP_SEC_ASP_LOW_PRIORITY                  = 0x00000000,
8500 DP_SEC_ASP_HIGH_PRIORITY                 = 0x00000001,
8501 } DP_SEC_ASP_PRIORITY;
8502 
8503 /*
8504  * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
8505  */
8506 
8507 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
8508 DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ         = 0x00000000,
8509 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED  = 0x00000001,
8510 } DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
8511 
8512 /*
8513  * DP_MSE_SAT_UPDATE_ACT enum
8514  */
8515 
8516 typedef enum DP_MSE_SAT_UPDATE_ACT {
8517 DP_MSE_SAT_UPDATE_NO_ACTION              = 0x00000000,
8518 DP_MSE_SAT_UPDATE_WITH_TRIGGER           = 0x00000001,
8519 DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER        = 0x00000002,
8520 } DP_MSE_SAT_UPDATE_ACT;
8521 
8522 /*
8523  * DP_MSE_LINK_LINE enum
8524  */
8525 
8526 typedef enum DP_MSE_LINK_LINE {
8527 DP_MSE_LINK_LINE_32_MTP_LONG             = 0x00000000,
8528 DP_MSE_LINK_LINE_64_MTP_LONG             = 0x00000001,
8529 DP_MSE_LINK_LINE_128_MTP_LONG            = 0x00000002,
8530 DP_MSE_LINK_LINE_256_MTP_LONG            = 0x00000003,
8531 } DP_MSE_LINK_LINE;
8532 
8533 /*
8534  * DP_MSE_BLANK_CODE enum
8535  */
8536 
8537 typedef enum DP_MSE_BLANK_CODE {
8538 DP_MSE_BLANK_CODE_SF_FILLED              = 0x00000000,
8539 DP_MSE_BLANK_CODE_ZERO_FILLED            = 0x00000001,
8540 } DP_MSE_BLANK_CODE;
8541 
8542 /*
8543  * DP_MSE_TIMESTAMP_MODE enum
8544  */
8545 
8546 typedef enum DP_MSE_TIMESTAMP_MODE {
8547 DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE  = 0x00000000,
8548 DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE   = 0x00000001,
8549 } DP_MSE_TIMESTAMP_MODE;
8550 
8551 /*
8552  * DP_MSE_ZERO_ENCODER enum
8553  */
8554 
8555 typedef enum DP_MSE_ZERO_ENCODER {
8556 DP_MSE_NOT_ZERO_FE_ENCODER               = 0x00000000,
8557 DP_MSE_ZERO_FE_ENCODER                   = 0x00000001,
8558 } DP_MSE_ZERO_ENCODER;
8559 
8560 /*
8561  * DP_MSE_OUTPUT_DPDBG_DATA enum
8562  */
8563 
8564 typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
8565 DP_MSE_OUTPUT_DPDBG_DATA_DIS             = 0x00000000,
8566 DP_MSE_OUTPUT_DPDBG_DATA_EN              = 0x00000001,
8567 } DP_MSE_OUTPUT_DPDBG_DATA;
8568 
8569 /*
8570  * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
8571  */
8572 
8573 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
8574 DP_DPHY_HBR2_PASS_THROUGH                = 0x00000000,
8575 DP_DPHY_HBR2_PATTERN_1                   = 0x00000001,
8576 DP_DPHY_HBR2_PATTERN_2_NEG               = 0x00000002,
8577 DP_DPHY_HBR2_PATTERN_3                   = 0x00000003,
8578 DP_DPHY_HBR2_PATTERN_2_POS               = 0x00000006,
8579 } DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
8580 
8581 /*
8582  * DPHY_CRC_MST_PHASE_ERROR_ACK enum
8583  */
8584 
8585 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
8586 DPHY_CRC_MST_PHASE_ERROR_NO_ACK          = 0x00000000,
8587 DPHY_CRC_MST_PHASE_ERROR_ACKED           = 0x00000001,
8588 } DPHY_CRC_MST_PHASE_ERROR_ACK;
8589 
8590 /*
8591  * DPHY_SW_FAST_TRAINING_START enum
8592  */
8593 
8594 typedef enum DPHY_SW_FAST_TRAINING_START {
8595 DPHY_SW_FAST_TRAINING_NOT_STARTED        = 0x00000000,
8596 DPHY_SW_FAST_TRAINING_STARTED            = 0x00000001,
8597 } DPHY_SW_FAST_TRAINING_START;
8598 
8599 /*
8600  * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
8601  */
8602 
8603 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
8604 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED  = 0x00000000,
8605 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED  = 0x00000001,
8606 } DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
8607 
8608 /*
8609  * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
8610  */
8611 
8612 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
8613 DP_DPHY_FAST_TRAINING_COMPLETE_MASKED    = 0x00000000,
8614 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED  = 0x00000001,
8615 } DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
8616 
8617 /*
8618  * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
8619  */
8620 
8621 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
8622 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED  = 0x00000000,
8623 DP_DPHY_FAST_TRAINING_COMPLETE_ACKED     = 0x00000001,
8624 } DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
8625 
8626 /*
8627  * DP_MSA_V_TIMING_OVERRIDE_EN enum
8628  */
8629 
8630 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
8631 MSA_V_TIMING_OVERRIDE_DISABLED           = 0x00000000,
8632 MSA_V_TIMING_OVERRIDE_ENABLED            = 0x00000001,
8633 } DP_MSA_V_TIMING_OVERRIDE_EN;
8634 
8635 /*
8636  * DP_SEC_GSP0_PRIORITY enum
8637  */
8638 
8639 typedef enum DP_SEC_GSP0_PRIORITY {
8640 SEC_GSP0_PRIORITY_LOW                    = 0x00000000,
8641 SEC_GSP0_PRIORITY_HIGH                   = 0x00000001,
8642 } DP_SEC_GSP0_PRIORITY;
8643 
8644 /*
8645  * DP_SEC_GSP0_SEND enum
8646  */
8647 
8648 typedef enum DP_SEC_GSP0_SEND {
8649 NOT_SENT                                 = 0x00000000,
8650 FORCE_SENT                               = 0x00000001,
8651 } DP_SEC_GSP0_SEND;
8652 
8653 /*******************************************************
8654  * COL_MAN Enums
8655  *******************************************************/
8656 
8657 /*
8658  * COL_MAN_UPDATE_LOCK enum
8659  */
8660 
8661 typedef enum COL_MAN_UPDATE_LOCK {
8662 COL_MAN_UPDATE_UNLOCKED                  = 0x00000000,
8663 COL_MAN_UPDATE_LOCKED                    = 0x00000001,
8664 } COL_MAN_UPDATE_LOCK;
8665 
8666 /*
8667  * COL_MAN_DISABLE_MULTIPLE_UPDATE enum
8668  */
8669 
8670 typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
8671 COL_MAN_MULTIPLE_UPDATE                  = 0x00000000,
8672 COL_MAN_MULTIPLE_UPDAT_EDISABLE          = 0x00000001,
8673 } COL_MAN_DISABLE_MULTIPLE_UPDATE;
8674 
8675 /*
8676  * COL_MAN_INPUTCSC_MODE enum
8677  */
8678 
8679 typedef enum COL_MAN_INPUTCSC_MODE {
8680 INPUTCSC_MODE_BYPASS                     = 0x00000000,
8681 INPUTCSC_MODE_A                          = 0x00000001,
8682 INPUTCSC_MODE_B                          = 0x00000002,
8683 INPUTCSC_MODE_UNITY                      = 0x00000003,
8684 } COL_MAN_INPUTCSC_MODE;
8685 
8686 /*
8687  * COL_MAN_INPUTCSC_TYPE enum
8688  */
8689 
8690 typedef enum COL_MAN_INPUTCSC_TYPE {
8691 INPUTCSC_TYPE_12_0                       = 0x00000000,
8692 INPUTCSC_TYPE_10_2                       = 0x00000001,
8693 INPUTCSC_TYPE_8_4                        = 0x00000002,
8694 } COL_MAN_INPUTCSC_TYPE;
8695 
8696 /*
8697  * COL_MAN_INPUTCSC_CONVERT enum
8698  */
8699 
8700 typedef enum COL_MAN_INPUTCSC_CONVERT {
8701 INPUTCSC_ROUND                           = 0x00000000,
8702 INPUTCSC_TRUNCATE                        = 0x00000001,
8703 } COL_MAN_INPUTCSC_CONVERT;
8704 
8705 /*
8706  * COL_MAN_PRESCALE_MODE enum
8707  */
8708 
8709 typedef enum COL_MAN_PRESCALE_MODE {
8710 PRESCALE_MODE_BYPASS                     = 0x00000000,
8711 PRESCALE_MODE_PROGRAM                    = 0x00000001,
8712 PRESCALE_MODE_UNITY                      = 0x00000002,
8713 } COL_MAN_PRESCALE_MODE;
8714 
8715 /*
8716  * COL_MAN_INPUT_GAMMA_MODE enum
8717  */
8718 
8719 typedef enum COL_MAN_INPUT_GAMMA_MODE {
8720 INGAMMA_MODE_BYPASS                      = 0x00000000,
8721 INGAMMA_MODE_FIX                         = 0x00000001,
8722 INGAMMA_MODE_FLOAT                       = 0x00000002,
8723 } COL_MAN_INPUT_GAMMA_MODE;
8724 
8725 /*
8726  * COL_MAN_OUTPUT_CSC_MODE enum
8727  */
8728 
8729 typedef enum COL_MAN_OUTPUT_CSC_MODE {
8730 COL_MAN_OUTPUT_CSC_BYPASS                = 0x00000000,
8731 COL_MAN_OUTPUT_CSC_RGB                   = 0x00000001,
8732 COL_MAN_OUTPUT_CSC_YCrCb601              = 0x00000002,
8733 COL_MAN_OUTPUT_CSC_YCrCb709              = 0x00000003,
8734 COL_MAN_OUTPUT_CSC_A                     = 0x00000004,
8735 COL_MAN_OUTPUT_CSC_B                     = 0x00000005,
8736 COL_MAN_OUTPUT_CSC_UNITY                 = 0x00000006,
8737 } COL_MAN_OUTPUT_CSC_MODE;
8738 
8739 /*
8740  * COL_MAN_DENORM_CLAMP_CONTROL enum
8741  */
8742 
8743 typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
8744 DENORM_CLAMP_MODE_UNITY                  = 0x00000000,
8745 DENORM_CLAMP_MODE_8                      = 0x00000001,
8746 DENORM_CLAMP_MODE_10                     = 0x00000002,
8747 DENORM_CLAMP_MODE_12                     = 0x00000003,
8748 } COL_MAN_DENORM_CLAMP_CONTROL;
8749 
8750 /*
8751  * COL_MAN_REGAMMA_MODE_CONTROL enum
8752  */
8753 
8754 typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
8755 COL_MAN_REGAMMA_MODE_BYPASS              = 0x00000000,
8756 COL_MAN_REGAMMA_MODE_ROM_A               = 0x00000001,
8757 COL_MAN_REGAMMA_MODE_ROM_B               = 0x00000002,
8758 COL_MAN_REGAMMA_MODE_A                   = 0x00000003,
8759 COL_MAN_REGAMMA_MODE_B                   = 0x00000004,
8760 } COL_MAN_REGAMMA_MODE_CONTROL;
8761 
8762 /*
8763  * COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum
8764  */
8765 
8766 typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
8767 CM_GLOBAL_PASSTHROUGH_DISBALE            = 0x00000000,
8768 CM_GLOBAL_PASSTHROUGH_ENABLE             = 0x00000001,
8769 } COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
8770 
8771 /*
8772  * COL_MAN_DEGAMMA_MODE enum
8773  */
8774 
8775 typedef enum COL_MAN_DEGAMMA_MODE {
8776 DEGAMMA_MODE_BYPASS                      = 0x00000000,
8777 DEGAMMA_MODE_A                           = 0x00000001,
8778 DEGAMMA_MODE_B                           = 0x00000002,
8779 } COL_MAN_DEGAMMA_MODE;
8780 
8781 /*
8782  * COL_MAN_GAMUT_REMAP_MODE enum
8783  */
8784 
8785 typedef enum COL_MAN_GAMUT_REMAP_MODE {
8786 GAMUT_REMAP_MODE_BYPASS                  = 0x00000000,
8787 GAMUT_REMAP_MODE_1                       = 0x00000001,
8788 GAMUT_REMAP_MODE_2                       = 0x00000002,
8789 GAMUT_REMAP_MODE_3                       = 0x00000003,
8790 } COL_MAN_GAMUT_REMAP_MODE;
8791 
8792 /*******************************************************
8793  * MCIF_WB Enums
8794  *******************************************************/
8795 
8796 /*******************************************************
8797  * DP_AUX Enums
8798  *******************************************************/
8799 
8800 /*
8801  * DP_AUX_CONTROL_HPD_SEL enum
8802  */
8803 
8804 typedef enum DP_AUX_CONTROL_HPD_SEL {
8805 DP_AUX_CONTROL_HPD1_SELECTED             = 0x00000000,
8806 DP_AUX_CONTROL_HPD2_SELECTED             = 0x00000001,
8807 DP_AUX_CONTROL_HPD3_SELECTED             = 0x00000002,
8808 DP_AUX_CONTROL_HPD4_SELECTED             = 0x00000003,
8809 DP_AUX_CONTROL_HPD5_SELECTED             = 0x00000004,
8810 DP_AUX_CONTROL_HPD6_SELECTED             = 0x00000005,
8811 } DP_AUX_CONTROL_HPD_SEL;
8812 
8813 /*
8814  * DP_AUX_CONTROL_TEST_MODE enum
8815  */
8816 
8817 typedef enum DP_AUX_CONTROL_TEST_MODE {
8818 DP_AUX_CONTROL_TEST_MODE_DISABLE         = 0x00000000,
8819 DP_AUX_CONTROL_TEST_MODE_ENABLE          = 0x00000001,
8820 } DP_AUX_CONTROL_TEST_MODE;
8821 
8822 /*
8823  * DP_AUX_SW_CONTROL_SW_GO enum
8824  */
8825 
8826 typedef enum DP_AUX_SW_CONTROL_SW_GO {
8827 DP_AUX_SW_CONTROL_SW__NOT_GO             = 0x00000000,
8828 DP_AUX_SW_CONTROL_SW__GO                 = 0x00000001,
8829 } DP_AUX_SW_CONTROL_SW_GO;
8830 
8831 /*
8832  * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
8833  */
8834 
8835 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8836 DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG      = 0x00000000,
8837 DP_AUX_SW_CONTROL_LS_READ__TRIG          = 0x00000001,
8838 } DP_AUX_SW_CONTROL_LS_READ_TRIG;
8839 
8840 /*
8841  * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
8842  */
8843 
8844 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8845 DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW  = 0x00000000,
8846 DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW  = 0x00000001,
8847 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC  = 0x00000002,
8848 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS  = 0x00000003,
8849 } DP_AUX_ARB_CONTROL_ARB_PRIORITY;
8850 
8851 /*
8852  * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
8853  */
8854 
8855 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8856 DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ  = 0x00000000,
8857 DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ      = 0x00000001,
8858 } DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
8859 
8860 /*
8861  * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
8862  */
8863 
8864 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8865 DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
8866 DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG   = 0x00000001,
8867 } DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
8868 
8869 /*
8870  * DP_AUX_INT_ACK enum
8871  */
8872 
8873 typedef enum DP_AUX_INT_ACK {
8874 DP_AUX_INT__NOT_ACK                      = 0x00000000,
8875 DP_AUX_INT__ACK                          = 0x00000001,
8876 } DP_AUX_INT_ACK;
8877 
8878 /*
8879  * DP_AUX_LS_UPDATE_ACK enum
8880  */
8881 
8882 typedef enum DP_AUX_LS_UPDATE_ACK {
8883 DP_AUX_INT_LS_UPDATE_NOT_ACK             = 0x00000000,
8884 DP_AUX_INT_LS_UPDATE_ACK                 = 0x00000001,
8885 } DP_AUX_LS_UPDATE_ACK;
8886 
8887 /*
8888  * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
8889  */
8890 
8891 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8892 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK  = 0x00000000,
8893 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF  = 0x00000001,
8894 } DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
8895 
8896 /*
8897  * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
8898  */
8899 
8900 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8901 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
8902 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
8903 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
8904 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
8905 } DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
8906 
8907 /*
8908  * DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum
8909  */
8910 
8911 typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
8912 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x00000000,
8913 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x00000001,
8914 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x00000002,
8915 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x00000003,
8916 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x00000004,
8917 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x00000005,
8918 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x00000006,
8919 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x00000007,
8920 } DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
8921 
8922 /*
8923  * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
8924  */
8925 
8926 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8927 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
8928 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
8929 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
8930 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
8931 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
8932 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
8933 } DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
8934 
8935 /*
8936  * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
8937  */
8938 
8939 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8940 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD  = 0x00000000,
8941 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD  = 0x00000001,
8942 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD  = 0x00000002,
8943 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD  = 0x00000003,
8944 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD  = 0x00000004,
8945 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD  = 0x00000005,
8946 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD  = 0x00000006,
8947 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD  = 0x00000007,
8948 } DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
8949 
8950 /*
8951  * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
8952  */
8953 
8954 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8955 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD  = 0x00000000,
8956 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD  = 0x00000001,
8957 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD  = 0x00000002,
8958 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD  = 0x00000003,
8959 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD  = 0x00000004,
8960 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD  = 0x00000005,
8961 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD  = 0x00000006,
8962 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD  = 0x00000007,
8963 } DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
8964 
8965 /*
8966  * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
8967  */
8968 
8969 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8970 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
8971 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
8972 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
8973 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
8974 } DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
8975 
8976 /*
8977  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
8978  */
8979 
8980 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8981 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
8982 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
8983 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
8984 
8985 /*
8986  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
8987  */
8988 
8989 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8990 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
8991 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
8992 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
8993 
8994 /*
8995  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
8996  */
8997 
8998 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
8999 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
9000 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
9001 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
9002 
9003 /*
9004  * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
9005  */
9006 
9007 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
9008 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
9009 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
9010 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
9011 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
9012 } DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
9013 
9014 /*
9015  * DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum
9016  */
9017 
9018 typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
9019 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x00000000,
9020 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x00000001,
9021 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x00000002,
9022 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x00000003,
9023 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x00000004,
9024 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x00000005,
9025 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x00000006,
9026 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x00000007,
9027 } DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
9028 
9029 /*
9030  * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
9031  */
9032 
9033 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
9034 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2  = 0x00000000,
9035 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4  = 0x00000001,
9036 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8  = 0x00000002,
9037 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16  = 0x00000003,
9038 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32  = 0x00000004,
9039 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64  = 0x00000005,
9040 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128  = 0x00000006,
9041 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256  = 0x00000007,
9042 } DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
9043 
9044 /*
9045  * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
9046  */
9047 
9048 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
9049 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX  = 0x00000000,
9050 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX  = 0x00000001,
9051 } DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
9052 
9053 /*
9054  * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
9055  */
9056 
9057 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
9058 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
9059 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
9060 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
9061 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
9062 } DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
9063 
9064 /*
9065  * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
9066  */
9067 
9068 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
9069 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
9070 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
9071 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
9072 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
9073 } DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
9074 
9075 /*
9076  * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
9077  */
9078 
9079 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
9080 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0  = 0x00000000,
9081 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64  = 0x00000001,
9082 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128  = 0x00000002,
9083 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256  = 0x00000003,
9084 } DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
9085 
9086 /*
9087  * DP_AUX_ERR_OCCURRED_ACK enum
9088  */
9089 
9090 typedef enum DP_AUX_ERR_OCCURRED_ACK {
9091 DP_AUX_ERR_OCCURRED__NOT_ACK             = 0x00000000,
9092 DP_AUX_ERR_OCCURRED__ACK                 = 0x00000001,
9093 } DP_AUX_ERR_OCCURRED_ACK;
9094 
9095 /*
9096  * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
9097  */
9098 
9099 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
9100 DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK    = 0x00000000,
9101 DP_AUX_POTENTIAL_ERR_REACHED__ACK        = 0x00000001,
9102 } DP_AUX_POTENTIAL_ERR_REACHED_ACK;
9103 
9104 /*
9105  * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
9106  */
9107 
9108 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
9109 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
9110 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK    = 0x00000001,
9111 } DP_AUX_DEFINITE_ERR_REACHED_ACK;
9112 
9113 /*
9114  * DP_AUX_RESET enum
9115  */
9116 
9117 typedef enum DP_AUX_RESET {
9118 DP_AUX_RESET_DEASSERTED                  = 0x00000000,
9119 DP_AUX_RESET_ASSERTED                    = 0x00000001,
9120 } DP_AUX_RESET;
9121 
9122 /*
9123  * DP_AUX_RESET_DONE enum
9124  */
9125 
9126 typedef enum DP_AUX_RESET_DONE {
9127 DP_AUX_RESET_SEQUENCE_NOT_DONE           = 0x00000000,
9128 DP_AUX_RESET_SEQUENCE_DONE               = 0x00000001,
9129 } DP_AUX_RESET_DONE;
9130 
9131 /*******************************************************
9132  * DSI Enums
9133  *******************************************************/
9134 
9135 /*
9136  * DSI_COMMAND_MODE_SRC_FORMAT enum
9137  */
9138 
9139 typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
9140 DSI_COMMAND_SRC_FORMAT_RGB8BIT           = 0x00000002,
9141 DSI_COMMAND_SRC_FORMAT_RGB332            = 0x00000003,
9142 DSI_COMMAND_SRC_FORMAT_RGB444            = 0x00000004,
9143 DSI_COMMAND_SRC_FORMAT_RGB555            = 0x00000005,
9144 DSI_COMMAND_SRC_FORMAT_RGB565            = 0x00000006,
9145 DSI_COMMAND_SRC_FORMAT_RGB888            = 0x00000008,
9146 } DSI_COMMAND_MODE_SRC_FORMAT;
9147 
9148 /*
9149  * DSI_COMMAND_MODE_DST_FORMAT enum
9150  */
9151 
9152 typedef enum DSI_COMMAND_MODE_DST_FORMAT {
9153 DSI_COMMAND_DST_FORMAT_RGB111            = 0x00000000,
9154 DSI_COMMAND_DST_FORMAT_RGB332            = 0x00000003,
9155 DSI_COMMAND_DST_FORMAT_RGB444            = 0x00000004,
9156 DSI_COMMAND_DST_FORMAT_RGB565            = 0x00000006,
9157 DSI_COMMAND_DST_FORMAT_RGB666            = 0x00000007,
9158 DSI_COMMAND_DST_FORMAT_RGB888            = 0x00000008,
9159 } DSI_COMMAND_MODE_DST_FORMAT;
9160 
9161 /*
9162  * DSI_FLAG_CLR enum
9163  */
9164 
9165 typedef enum DSI_FLAG_CLR {
9166 DSI_FLAG_NO_CLEAR                        = 0x00000000,
9167 DSI_FLAG_CLEAR                           = 0x00000001,
9168 } DSI_FLAG_CLR;
9169 
9170 /*
9171  * DSI_BIT_SWAP enum
9172  */
9173 
9174 typedef enum DSI_BIT_SWAP {
9175 DSI_BIT_SWAP_DISABLE                     = 0x00000000,
9176 DSI_BIT_SWAP_ENABLE                      = 0x00000001,
9177 } DSI_BIT_SWAP;
9178 
9179 /*
9180  * DSI_CLK_GATING enum
9181  */
9182 
9183 typedef enum DSI_CLK_GATING {
9184 DSI_CLK_GATING_ENABLE                    = 0x00000000,
9185 DSI_CLK_GATING_DISABLE                   = 0x00000001,
9186 } DSI_CLK_GATING;
9187 
9188 /*
9189  * DSI_LANE_ULPS_REQUEST enum
9190  */
9191 
9192 typedef enum DSI_LANE_ULPS_REQUEST {
9193 DSI_LANE_ULPS_REQUEST_DEASSERT           = 0x00000000,
9194 DSI_LANE_ULPS_REQUEST_ASSERT             = 0x00000001,
9195 } DSI_LANE_ULPS_REQUEST;
9196 
9197 /*
9198  * DSI_LANE_ULPS_EXIT enum
9199  */
9200 
9201 typedef enum DSI_LANE_ULPS_EXIT {
9202 DSI_LANE_ULPS_EXIT_DEASSERT              = 0x00000000,
9203 DSI_LANE_ULPS_EXIT_ASSERT                = 0x00000001,
9204 } DSI_LANE_ULPS_EXIT;
9205 
9206 /*
9207  * DSI_LANE_FORCE_TX_STOP enum
9208  */
9209 
9210 typedef enum DSI_LANE_FORCE_TX_STOP {
9211 DSI_LANE_FORCE_TX_STOP_DEASSERT          = 0x00000000,
9212 DSI_LANE_FORCE_TX_STOP_ASSERT            = 0x00000001,
9213 } DSI_LANE_FORCE_TX_STOP;
9214 
9215 /*
9216  * DSI_CLOCK_LANE_HS_FORCE_REQUEST enum
9217  */
9218 
9219 typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
9220 DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT  = 0x00000000,
9221 DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT   = 0x00000001,
9222 } DSI_CLOCK_LANE_HS_FORCE_REQUEST;
9223 
9224 /*
9225  * DSI_CONTROLLER_EN enum
9226  */
9227 
9228 typedef enum DSI_CONTROLLER_EN {
9229 DSI_CONTROLLER_DISABLE                   = 0x00000000,
9230 DSI_CONTROLLER_ENABLE                    = 0x00000001,
9231 } DSI_CONTROLLER_EN;
9232 
9233 /*
9234  * DSI_VIDEO_MODE_EN enum
9235  */
9236 
9237 typedef enum DSI_VIDEO_MODE_EN {
9238 DSI_VIDEO_MODE_DISABLE                   = 0x00000000,
9239 DSI_VIDEO_MODE_ENABLE                    = 0x00000001,
9240 } DSI_VIDEO_MODE_EN;
9241 
9242 /*
9243  * DSI_CMD_MODE_EN enum
9244  */
9245 
9246 typedef enum DSI_CMD_MODE_EN {
9247 DSI_CMD_MODE_DISABLE                     = 0x00000000,
9248 DSI_CMD_MODE_ENABLE                      = 0x00000001,
9249 } DSI_CMD_MODE_EN;
9250 
9251 /*
9252  * DSI_DATA_LANE0_EN enum
9253  */
9254 
9255 typedef enum DSI_DATA_LANE0_EN {
9256 DSI_DATA_LANE0_DISABLE                   = 0x00000000,
9257 DSI_DATA_LANE0_ENABLE                    = 0x00000001,
9258 } DSI_DATA_LANE0_EN;
9259 
9260 /*
9261  * DSI_DATA_LANE1_EN enum
9262  */
9263 
9264 typedef enum DSI_DATA_LANE1_EN {
9265 DSI_DATA_LANE1_DISABLE                   = 0x00000000,
9266 DSI_DATA_LANE1_ENABLE                    = 0x00000001,
9267 } DSI_DATA_LANE1_EN;
9268 
9269 /*
9270  * DSI_DATA_LANE2_EN enum
9271  */
9272 
9273 typedef enum DSI_DATA_LANE2_EN {
9274 DSI_DATA_LANE2_DISABLE                   = 0x00000000,
9275 DSI_DATA_LANE2_ENABLE                    = 0x00000001,
9276 } DSI_DATA_LANE2_EN;
9277 
9278 /*
9279  * DSI_DATA_LANE3_EN enum
9280  */
9281 
9282 typedef enum DSI_DATA_LANE3_EN {
9283 DSI_DATA_LANE3_DISABLE                   = 0x00000000,
9284 DSI_DATA_LANE3_ENABLE                    = 0x00000001,
9285 } DSI_DATA_LANE3_EN;
9286 
9287 /*
9288  * DSI_CLOCK_LANE_EN enum
9289  */
9290 
9291 typedef enum DSI_CLOCK_LANE_EN {
9292 DSI_CLOCK_LANE_DISABLE                   = 0x00000000,
9293 DSI_CLOCK_LANE_ENABLE                    = 0x00000001,
9294 } DSI_CLOCK_LANE_EN;
9295 
9296 /*
9297  * DSI_PHY_DATA_LANE0_EN enum
9298  */
9299 
9300 typedef enum DSI_PHY_DATA_LANE0_EN {
9301 DSI_PHY_DATA_LANE0_DISABLE               = 0x00000000,
9302 DSI_PHY_DATA_LANE0_ENABLE                = 0x00000001,
9303 } DSI_PHY_DATA_LANE0_EN;
9304 
9305 /*
9306  * DSI_PHY_DATA_LANE1_EN enum
9307  */
9308 
9309 typedef enum DSI_PHY_DATA_LANE1_EN {
9310 DSI_PHY_DATA_LANE1_DISABLE               = 0x00000000,
9311 DSI_PHY_DATA_LANE1_ENABLE                = 0x00000001,
9312 } DSI_PHY_DATA_LANE1_EN;
9313 
9314 /*
9315  * DSI_PHY_DATA_LANE2_EN enum
9316  */
9317 
9318 typedef enum DSI_PHY_DATA_LANE2_EN {
9319 DSI_PHY_DATA_LANE2_DISABLE               = 0x00000000,
9320 DSI_PHY_DATA_LANE2_ENABLE                = 0x00000001,
9321 } DSI_PHY_DATA_LANE2_EN;
9322 
9323 /*
9324  * DSI_PHY_DATA_LANE3_EN enum
9325  */
9326 
9327 typedef enum DSI_PHY_DATA_LANE3_EN {
9328 DSI_PHY_DATA_LANE3_DISABLE               = 0x00000000,
9329 DSI_PHY_DATA_LANE3_ENABLE                = 0x00000001,
9330 } DSI_PHY_DATA_LANE3_EN;
9331 
9332 /*
9333  * DSI_RESET_DISPCLK enum
9334  */
9335 
9336 typedef enum DSI_RESET_DISPCLK {
9337 DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC     = 0x00000000,
9338 DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC        = 0x00000001,
9339 } DSI_RESET_DISPCLK;
9340 
9341 /*
9342  * DSI_RESET_DSICLK enum
9343  */
9344 
9345 typedef enum DSI_RESET_DSICLK {
9346 DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC      = 0x00000000,
9347 DSI_RESET_ON_DSICLK_DOMAIN_LOGIC         = 0x00000001,
9348 } DSI_RESET_DSICLK;
9349 
9350 /*
9351  * DSI_RESET_BYTECLK enum
9352  */
9353 
9354 typedef enum DSI_RESET_BYTECLK {
9355 DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC     = 0x00000000,
9356 DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC        = 0x00000001,
9357 } DSI_RESET_BYTECLK;
9358 
9359 /*
9360  * DSI_RESET_ESCCLK enum
9361  */
9362 
9363 typedef enum DSI_RESET_ESCCLK {
9364 DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC      = 0x00000000,
9365 DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC         = 0x00000001,
9366 } DSI_RESET_ESCCLK;
9367 
9368 /*
9369  * DSI_CRTC_SEL enum
9370  */
9371 
9372 typedef enum DSI_CRTC_SEL {
9373 DSI_GET_PIXEL_STREAM_FROM_FMT0           = 0x00000000,
9374 DSI_GET_PIXEL_STREAM_FROM_FMT1           = 0x00000001,
9375 DSI_GET_PIXEL_STREAM_FROM_FMT2           = 0x00000002,
9376 DSI_GET_PIXEL_STREAM_FROM_FMT3           = 0x00000003,
9377 DSI_GET_PIXEL_STREAM_FROM_FMT4           = 0x00000004,
9378 DSI_GET_PIXEL_STREAM_FROM_FMT5           = 0x00000005,
9379 } DSI_CRTC_SEL;
9380 
9381 /*
9382  * DSI_PACKET_BYTE_MSB_LSB_FLIP enum
9383  */
9384 
9385 typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
9386 DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP     = 0x00000000,
9387 DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP        = 0x00000001,
9388 } DSI_PACKET_BYTE_MSB_LSB_FLIP;
9389 
9390 /*
9391  * DSI_VIDEO_MODE_DST_FORMAT enum
9392  */
9393 
9394 typedef enum DSI_VIDEO_MODE_DST_FORMAT {
9395 DSI_VIDEO_DST_FORMAT_RGB565              = 0x00000000,
9396 DSI_VIDEO_DST_FORMAT_RGB666_PACKED       = 0x00000001,
9397 DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 0x00000002,
9398 DSI_VIDEO_DST_FORMAT_RGB888              = 0x00000003,
9399 } DSI_VIDEO_MODE_DST_FORMAT;
9400 
9401 /*
9402  * DSI_VIDEO_TRAFFIC_MODE enum
9403  */
9404 
9405 typedef enum DSI_VIDEO_TRAFFIC_MODE {
9406 DSI_TRAFFIC_MODE_SYNC_PULSES             = 0x00000000,
9407 DSI_TRAFFIC_MODE_SYNC_EVENTS             = 0x00000001,
9408 DSI_TRAFFIC_MODE_BURST                   = 0x00000002,
9409 DSI_TRAFFIC_MODE_RESERVED                = 0x00000003,
9410 } DSI_VIDEO_TRAFFIC_MODE;
9411 
9412 /*
9413  * DSI_VIDEO_BLLP_PWR_MODE enum
9414  */
9415 
9416 typedef enum DSI_VIDEO_BLLP_PWR_MODE {
9417 DSI_VIDEO_BLLP_PWR_MODE_HS               = 0x00000000,
9418 DSI_VIDEO_BLLP_PWR_MODE_LP               = 0x00000001,
9419 } DSI_VIDEO_BLLP_PWR_MODE;
9420 
9421 /*
9422  * DSI_VIDEO_EOF_BLLP_PWR_MODE enum
9423  */
9424 
9425 typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
9426 DSI_VIDEO_EOF_BLLP_PWR_MODE_HS           = 0x00000000,
9427 DSI_VIDEO_EOF_BLLP_PWR_MODE_LP           = 0x00000001,
9428 } DSI_VIDEO_EOF_BLLP_PWR_MODE;
9429 
9430 /*
9431  * DSI_VIDEO_PWR_MODE enum
9432  */
9433 
9434 typedef enum DSI_VIDEO_PWR_MODE {
9435 DSI_VIDEO_PWR_MODE_HS                    = 0x00000000,
9436 DSI_VIDEO_PWR_MODE_LP                    = 0x00000001,
9437 } DSI_VIDEO_PWR_MODE;
9438 
9439 /*
9440  * DSI_VIDEO_PULSE_MODE_OPT enum
9441  */
9442 
9443 typedef enum DSI_VIDEO_PULSE_MODE_OPT {
9444 PULSE_MODE_OPT_NO_HSA                    = 0x00000000,
9445 PULSE_MODE_OPT_SEND                      = 0x00000001,
9446 } DSI_VIDEO_PULSE_MODE_OPT;
9447 
9448 /*
9449  * DSI_RGB_SWAP enum
9450  */
9451 
9452 typedef enum DSI_RGB_SWAP {
9453 DSI_SWAP_RGB                             = 0x00000000,
9454 DSI_SWAP_RBG                             = 0x00000001,
9455 DSI_SWAP_BGR                             = 0x00000002,
9456 DSI_SWAP_BRG                             = 0x00000003,
9457 DSI_SWAP_GRB                             = 0x00000004,
9458 DSI_SWAP_GBR                             = 0x00000005,
9459 } DSI_RGB_SWAP;
9460 
9461 /*
9462  * DSI_CMD_PACKET_TYPE enum
9463  */
9464 
9465 typedef enum DSI_CMD_PACKET_TYPE {
9466 DSI_CMD_PACKET_TYPE_SHORT                = 0x00000000,
9467 DSI_CMD_PACKET_TYPE_LONG                 = 0x00000001,
9468 } DSI_CMD_PACKET_TYPE;
9469 
9470 /*
9471  * DSI_CMD_PWR_MODE enum
9472  */
9473 
9474 typedef enum DSI_CMD_PWR_MODE {
9475 DSI_CMD_PWR_MODE_HS                      = 0x00000000,
9476 DSI_CMD_PWR_MODE_LP                      = 0x00000001,
9477 } DSI_CMD_PWR_MODE;
9478 
9479 /*
9480  * DSI_CMD_EMBEDDED_MODE enum
9481  */
9482 
9483 typedef enum DSI_CMD_EMBEDDED_MODE {
9484 CMD_EMBEDDED_MODE_DISABLE                = 0x00000000,
9485 CMD_EMBEDDED_MODE_ENABLE                 = 0x00000001,
9486 } DSI_CMD_EMBEDDED_MODE;
9487 
9488 /*
9489  * DSI_CMD_ORDER enum
9490  */
9491 
9492 typedef enum DSI_CMD_ORDER {
9493 DSI_CMD_ORDER_COMMAND_FIRST              = 0x00000000,
9494 DSI_CMD_ORDER_DATA_FIRST                 = 0x00000001,
9495 } DSI_CMD_ORDER;
9496 
9497 /*
9498  * DSI_DATA_BUFFER_ID enum
9499  */
9500 
9501 typedef enum DSI_DATA_BUFFER_ID {
9502 DSI_DATA_BUFFER_OFFSET0                  = 0x00000000,
9503 DSI_DATA_BUFFER_OFFSET1                  = 0x00000001,
9504 } DSI_DATA_BUFFER_ID;
9505 
9506 /*
9507  * DSI_DWORD_BYTE_SWAP enum
9508  */
9509 
9510 typedef enum DSI_DWORD_BYTE_SWAP {
9511 DWORD_BYTE_SWAP_NO_SWAP                  = 0x00000000,
9512 DWORD_BYTE_SWAP_BYTE_SWAP                = 0x00000001,
9513 DWORD_BYTE_SWAP_WORD_SWAP                = 0x00000002,
9514 DWORD_BYTE_SWAP_BOTH_SWAP                = 0x00000003,
9515 } DSI_DWORD_BYTE_SWAP;
9516 
9517 /*
9518  * DSI_INSERT_DCS_COMMAND enum
9519  */
9520 
9521 typedef enum DSI_INSERT_DCS_COMMAND {
9522 DSI_INSERT_DCS_COMMAND_DISABLE           = 0x00000000,
9523 DSI_INSERT_DCS_COMMAND_ENABLE            = 0x00000001,
9524 } DSI_INSERT_DCS_COMMAND;
9525 
9526 /*
9527  * DSI_DMAFIFO_WRITE_WATERMARK enum
9528  */
9529 
9530 typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
9531 DSI_DMAFIFO_WRITE_WATERMARK_HALF         = 0x00000000,
9532 DSI_DMAFIFO_WRITE_WATERMARK_FOURTH       = 0x00000001,
9533 DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH       = 0x00000002,
9534 DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH    = 0x00000003,
9535 } DSI_DMAFIFO_WRITE_WATERMARK;
9536 
9537 /*
9538  * DSI_DMAFIFO_READ_WATERMARK enum
9539  */
9540 
9541 typedef enum DSI_DMAFIFO_READ_WATERMARK {
9542 DSI_DMAFIFO_READ_WATERMARK_HALF          = 0x00000000,
9543 DSI_DMAFIFO_READ_WATERMARK_FOURTH        = 0x00000001,
9544 DSI_DMAFIFO_READ_WATERMARK_EIGHTH        = 0x00000002,
9545 DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH     = 0x00000003,
9546 } DSI_DMAFIFO_READ_WATERMARK;
9547 
9548 /*
9549  * DSI_USE_DENG_LENGTH enum
9550  */
9551 
9552 typedef enum DSI_USE_DENG_LENGTH {
9553 DSI_USE_DENG_LENGTH_DISABLE              = 0x00000000,
9554 DSI_USE_DENG_LENGTH_ENABLE               = 0x00000001,
9555 } DSI_USE_DENG_LENGTH;
9556 
9557 /*
9558  * DSI_COMMAND_TRIGGER_MODE enum
9559  */
9560 
9561 typedef enum DSI_COMMAND_TRIGGER_MODE {
9562 DSI_COMMAND_TRIGGER_MODE_AUTO            = 0x00000000,
9563 DSI_COMMAND_TRIGGER_MODE_MANUAL          = 0x00000001,
9564 } DSI_COMMAND_TRIGGER_MODE;
9565 
9566 /*
9567  * DSI_COMMAND_TRIGGER_SEL enum
9568  */
9569 
9570 typedef enum DSI_COMMAND_TRIGGER_SEL {
9571 DSI_COMMAND_TRIGGER_SEL_NONE             = 0x00000000,
9572 DSI_COMMAND_TRIGGER_SEL_CRTC             = 0x00000001,
9573 DSI_COMMAND_TRIGGER_SEL_TE               = 0x00000002,
9574 DSI_COMMAND_TRIGGER_SEL_HW               = 0x00000003,
9575 } DSI_COMMAND_TRIGGER_SEL;
9576 
9577 /*
9578  * DSI_HW_SOURCE_SEL enum
9579  */
9580 
9581 typedef enum DSI_HW_SOURCE_SEL {
9582 HW_SOURCE_SEL_NONE                       = 0x00000000,
9583 HW_SOURCE_SEL_DSC_VUP                    = 0x00000001,
9584 HW_SOURCE_SEL_DSC_VLP                    = 0x00000002,
9585 HW_SOURCE_SEL_DSC_JPEG                   = 0x00000003,
9586 } DSI_HW_SOURCE_SEL;
9587 
9588 /*
9589  * DSI_COMMAND_TRIGGER_ORDER enum
9590  */
9591 
9592 typedef enum DSI_COMMAND_TRIGGER_ORDER {
9593 DSI_COMMAND_TRIGGER_ORDER_DMA            = 0x00000000,
9594 DSI_COMMAND_TRIGGER_ORDER_DENG           = 0x00000001,
9595 } DSI_COMMAND_TRIGGER_ORDER;
9596 
9597 /*
9598  * DSI_TE_SRC_SEL enum
9599  */
9600 
9601 typedef enum DSI_TE_SRC_SEL {
9602 DSI_TE_SEL_LINK                          = 0x00000000,
9603 DSI_TE_SEL_PIN                           = 0x00000001,
9604 } DSI_TE_SRC_SEL;
9605 
9606 /*
9607  * DSI_EXT_TE_MUX enum
9608  */
9609 
9610 typedef enum DSI_EXT_TE_MUX {
9611 DSI_XT_TE_MUX_LCDD17                     = 0x00000000,
9612 DSI_XT_TE_MUX_DCLK                       = 0x00000001,
9613 DSI_XT_TE_MUX_SS                         = 0x00000002,
9614 DSI_XT_TE_MUX_GCLK                       = 0x00000003,
9615 DSI_XT_TE_MUX_GOE                        = 0x00000004,
9616 DSI_XT_TE_MUX_DINV                       = 0x00000005,
9617 DSI_XT_TE_MUX_FRAME                      = 0x00000006,
9618 DSI_XT_TE_MUX_GPIO4                      = 0x00000007,
9619 DSI_XT_TE_MUX_GPIO5                      = 0x00000008,
9620 } DSI_EXT_TE_MUX;
9621 
9622 /*
9623  * DSI_EXT_TE_MODE enum
9624  */
9625 
9626 typedef enum DSI_EXT_TE_MODE {
9627 DSI_EXT_TE_MODE_VSYNC_EDGE               = 0x00000000,
9628 DSI_EXT_TE_MODE_VSYNC_WIDTH              = 0x00000001,
9629 DSI_EXT_TE_MODE_HVSYNC_EDGE              = 0x00000002,
9630 DSI_EXT_TE_MODE_HVSYNC_WIDTH             = 0x00000003,
9631 } DSI_EXT_TE_MODE;
9632 
9633 /*
9634  * DSI_EXT_RESET_POL enum
9635  */
9636 
9637 typedef enum DSI_EXT_RESET_POL {
9638 DSI_EXT_RESET_POL_HIGH                   = 0x00000000,
9639 DSI_EXT_RESET_POL_LOW                    = 0x00000001,
9640 } DSI_EXT_RESET_POL;
9641 
9642 /*
9643  * DSI_EXT_TE_POL enum
9644  */
9645 
9646 typedef enum DSI_EXT_TE_POL {
9647 DSI_EXT_TE_POL_RISING                    = 0x00000000,
9648 DSI_EXT_TE_POL_FALLING                   = 0x00000001,
9649 } DSI_EXT_TE_POL;
9650 
9651 /*
9652  * DSI_RESET_PANEL enum
9653  */
9654 
9655 typedef enum DSI_RESET_PANEL {
9656 DSI_RESET_PANEL_DEASSERT                 = 0x00000000,
9657 DSI_RESET_PANEL_ASSERT                   = 0x00000001,
9658 } DSI_RESET_PANEL;
9659 
9660 /*
9661  * DSI_CRC_ENABLE enum
9662  */
9663 
9664 typedef enum DSI_CRC_ENABLE {
9665 DSI_CRC_CAL_DISABLE                      = 0x00000000,
9666 DSI_CRC_CAL_ENABLE                       = 0x00000001,
9667 } DSI_CRC_ENABLE;
9668 
9669 /*
9670  * DSI_TX_EOT_APPEND enum
9671  */
9672 
9673 typedef enum DSI_TX_EOT_APPEND {
9674 DSI_TX_EOT_APPEND_DISABLE                = 0x00000000,
9675 DSI_TX_EOT_APPEND_ENABLE                 = 0x00000001,
9676 } DSI_TX_EOT_APPEND;
9677 
9678 /*
9679  * DSI_RX_EOT_IGNORE enum
9680  */
9681 
9682 typedef enum DSI_RX_EOT_IGNORE {
9683 DSI_RX_EOT_IGNORE_DISABLE                = 0x00000000,
9684 DSI_RX_EOT_IGNORE_ENABLE                 = 0x00000001,
9685 } DSI_RX_EOT_IGNORE;
9686 
9687 /*
9688  * DSI_MIPI_BIST_RESET enum
9689  */
9690 
9691 typedef enum DSI_MIPI_BIST_RESET {
9692 DSI_MIPI_BIST_RESET_DEASSERT             = 0x00000000,
9693 DSI_MIPI_BIST_RESET_ASSERT               = 0x00000001,
9694 } DSI_MIPI_BIST_RESET;
9695 
9696 /*
9697  * DSI_MIPI_BIST_VIDEO_FRMT enum
9698  */
9699 
9700 typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
9701 DSI_MIPI_BIST_VIDEO_FRMT_YUV422          = 0x00000000,
9702 DSI_MIPI_BIST_VIDEO_FRMT_RAW8            = 0x00000001,
9703 } DSI_MIPI_BIST_VIDEO_FRMT;
9704 
9705 /*
9706  * DSI_MIPI_BIST_START enum
9707  */
9708 
9709 typedef enum DSI_MIPI_BIST_START {
9710 DSI_MIPI_BIST_START_DEASSERT             = 0x00000000,
9711 DSI_MIPI_BIST_START_ASSERT               = 0x00000001,
9712 } DSI_MIPI_BIST_START;
9713 
9714 /*
9715  * DSI_DBG_CLK_SEL enum
9716  */
9717 
9718 typedef enum DSI_DBG_CLK_SEL {
9719 DSI_TEST_CLK_SEL_DISPCLK_P               = 0x00000000,
9720 DSI_TEST_CLK_SEL_DISPCLK_G               = 0x00000001,
9721 DSI_TEST_CLK_SEL_DISPCLK_R               = 0x00000002,
9722 DSI_TEST_CLK_SEL_ESCCLK_G                = 0x00000003,
9723 DSI_TEST_CLK_SEL_BYTECLK_G               = 0x00000004,
9724 DSI_TEST_CLK_SEL_DSICLK_P                = 0x00000005,
9725 DSI_TEST_CLK_SEL_DSICLK_R                = 0x00000006,
9726 DSI_TEST_CLK_SEL_DSICLK_G                = 0x00000007,
9727 DSI_TEST_CLK_SEL_DSICLK_TRN              = 0x00000008,
9728 } DSI_DBG_CLK_SEL;
9729 
9730 /*
9731  * DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum
9732  */
9733 
9734 typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
9735 DSI_DENG_FIFO_LEVEL_OVERWRITE            = 0x00000000,
9736 DSI_DENG_FIFO_LEVEL_CAL_AVERAGE          = 0x00000001,
9737 } DSI_DENG_FIFO_USE_OVERWRITE_LEVEL;
9738 
9739 /*
9740  * DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum
9741  */
9742 
9743 typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
9744 DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT  = 0x00000000,
9745 DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT  = 0x00000001,
9746 } DSI_DENG_FIFO_FORCE_RECAL_AVERAGE;
9747 
9748 /*
9749  * DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum
9750  */
9751 
9752 typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
9753 DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT  = 0x00000000,
9754 DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT  = 0x00000001,
9755 } DSI_DENG_FIFO_FORCE_RECOMP_MINMAX;
9756 
9757 /*
9758  * DSI_DENG_FIFO_START enum
9759  */
9760 
9761 typedef enum DSI_DENG_FIFO_START {
9762 DSI_DENG_FIFO_START_DEASSERT             = 0x00000000,
9763 DSI_DENG_FIFO_START_ASSERT               = 0x00000001,
9764 } DSI_DENG_FIFO_START;
9765 
9766 /*
9767  * DSI_USE_CMDFIFO enum
9768  */
9769 
9770 typedef enum DSI_USE_CMDFIFO {
9771 DSI_CMD_USE_DMAFIFO                      = 0x00000000,
9772 DSI_CMD_USE_CMDFIFO                      = 0x00000001,
9773 } DSI_USE_CMDFIFO;
9774 
9775 /*
9776  * DSI_CRTC_FREEZE_TRIG enum
9777  */
9778 
9779 typedef enum DSI_CRTC_FREEZE_TRIG {
9780 DSI_CRTC_FREEZE_TRIG_DEASSERT            = 0x00000000,
9781 DSI_CRTC_FREEZE_TRIG_ASSERT              = 0x00000001,
9782 } DSI_CRTC_FREEZE_TRIG;
9783 
9784 /*
9785  * DSI_PERF_LATENCY_SEL enum
9786  */
9787 
9788 typedef enum DSI_PERF_LATENCY_SEL {
9789 DSI_PERF_LATENCY_SEL_DATA_LANE0          = 0x00000000,
9790 DSI_PERF_LATENCY_SEL_DATA_LANE1          = 0x00000001,
9791 DSI_PERF_LATENCY_SEL_DATA_LANE2          = 0x00000002,
9792 DSI_PERF_LATENCY_SEL_DATA_LANE3          = 0x00000003,
9793 } DSI_PERF_LATENCY_SEL;
9794 
9795 /*
9796  * DSI_DEBUG_DSICLK_SEL enum
9797  */
9798 
9799 typedef enum DSI_DEBUG_DSICLK_SEL {
9800 DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE        = 0x00000000,
9801 DSI_DEBUG_DSICLK_SEL_CMD_ENGINE          = 0x00000001,
9802 DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO         = 0x00000002,
9803 DSI_DEBUG_DSICLK_SEL_CMDFIFO             = 0x00000003,
9804 DSI_DEBUG_DSICLK_SEL_CMDBUFFER           = 0x00000004,
9805 DSI_DEBUG_DSICLK_SEL_AFIFO               = 0x00000005,
9806 DSI_DEBUG_DSICLK_SEL_LANECTRL            = 0x00000006,
9807 } DSI_DEBUG_DSICLK_SEL;
9808 
9809 /*
9810  * DSI_DEBUG_BYTECLK_SEL enum
9811  */
9812 
9813 typedef enum DSI_DEBUG_BYTECLK_SEL {
9814 DSI_DEBUG_BYTECLK_SEL_AFIFO              = 0x00000000,
9815 DSI_DEBUG_BYTECLK_SEL_LANEFIFO0          = 0x00000001,
9816 DSI_DEBUG_BYTECLK_SEL_LANEFIFO1          = 0x00000002,
9817 DSI_DEBUG_BYTECLK_SEL_LANEFIFO2          = 0x00000003,
9818 DSI_DEBUG_BYTECLK_SEL_LANEFIFO3          = 0x00000004,
9819 DSI_DEBUG_BYTECLK_SEL_LANEBUF0           = 0x00000005,
9820 DSI_DEBUG_BYTECLK_SEL_LANEBUF1           = 0x00000006,
9821 DSI_DEBUG_BYTECLK_SEL_LANEBUF2           = 0x00000007,
9822 DSI_DEBUG_BYTECLK_SEL_LANEBUF3           = 0x00000008,
9823 DSI_DEBUG_BYTECLK_SEL_PINGPONG0          = 0x00000009,
9824 DSI_DEBUG_BYTECLK_SEL_PINGPONG1          = 0x0000000a,
9825 DSI_DEBUG_BYTECLK_SEL_PINGPING2          = 0x0000000b,
9826 DSI_DEBUG_BYTECLK_SEL_PINGPING3          = 0x0000000c,
9827 DSI_DEBUG_BYTECLK_SEL_EOT                = 0x0000000d,
9828 DSI_DEBUG_BYTECLK_SEL_LANECTRL           = 0x0000000e,
9829 } DSI_DEBUG_BYTECLK_SEL;
9830 
9831 /*******************************************************
9832  * DCIO_CHIP Enums
9833  *******************************************************/
9834 
9835 /*
9836  * DCIOCHIP_HPD_SEL enum
9837  */
9838 
9839 typedef enum DCIOCHIP_HPD_SEL {
9840 DCIOCHIP_HPD_SEL_ASYNC                   = 0x00000000,
9841 DCIOCHIP_HPD_SEL_CLOCKED                 = 0x00000001,
9842 } DCIOCHIP_HPD_SEL;
9843 
9844 /*
9845  * DCIOCHIP_PAD_MODE enum
9846  */
9847 
9848 typedef enum DCIOCHIP_PAD_MODE {
9849 DCIOCHIP_PAD_MODE_DDC                    = 0x00000000,
9850 DCIOCHIP_PAD_MODE_DP                     = 0x00000001,
9851 } DCIOCHIP_PAD_MODE;
9852 
9853 /*
9854  * DCIOCHIP_AUXSLAVE_PAD_MODE enum
9855  */
9856 
9857 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
9858 DCIOCHIP_AUXSLAVE_PAD_MODE_I2C           = 0x00000000,
9859 DCIOCHIP_AUXSLAVE_PAD_MODE_AUX           = 0x00000001,
9860 } DCIOCHIP_AUXSLAVE_PAD_MODE;
9861 
9862 /*
9863  * DCIOCHIP_INVERT enum
9864  */
9865 
9866 typedef enum DCIOCHIP_INVERT {
9867 DCIOCHIP_POL_NON_INVERT                  = 0x00000000,
9868 DCIOCHIP_POL_INVERT                      = 0x00000001,
9869 } DCIOCHIP_INVERT;
9870 
9871 /*
9872  * DCIOCHIP_PD_EN enum
9873  */
9874 
9875 typedef enum DCIOCHIP_PD_EN {
9876 DCIOCHIP_PD_EN_NOTALLOW                  = 0x00000000,
9877 DCIOCHIP_PD_EN_ALLOW                     = 0x00000001,
9878 } DCIOCHIP_PD_EN;
9879 
9880 /*
9881  * DCIOCHIP_GPIO_MASK_EN enum
9882  */
9883 
9884 typedef enum DCIOCHIP_GPIO_MASK_EN {
9885 DCIOCHIP_GPIO_MASK_EN_HARDWARE           = 0x00000000,
9886 DCIOCHIP_GPIO_MASK_EN_SOFTWARE           = 0x00000001,
9887 } DCIOCHIP_GPIO_MASK_EN;
9888 
9889 /*
9890  * DCIOCHIP_MASK enum
9891  */
9892 
9893 typedef enum DCIOCHIP_MASK {
9894 DCIOCHIP_MASK_DISABLE                    = 0x00000000,
9895 DCIOCHIP_MASK_ENABLE                     = 0x00000001,
9896 } DCIOCHIP_MASK;
9897 
9898 /*
9899  * DCIOCHIP_GPIO_I2C_MASK enum
9900  */
9901 
9902 typedef enum DCIOCHIP_GPIO_I2C_MASK {
9903 DCIOCHIP_GPIO_I2C_MASK_DISABLE           = 0x00000000,
9904 DCIOCHIP_GPIO_I2C_MASK_ENABLE            = 0x00000001,
9905 } DCIOCHIP_GPIO_I2C_MASK;
9906 
9907 /*
9908  * DCIOCHIP_GPIO_I2C_DRIVE enum
9909  */
9910 
9911 typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
9912 DCIOCHIP_GPIO_I2C_DRIVE_LOW              = 0x00000000,
9913 DCIOCHIP_GPIO_I2C_DRIVE_HIGH             = 0x00000001,
9914 } DCIOCHIP_GPIO_I2C_DRIVE;
9915 
9916 /*
9917  * DCIOCHIP_GPIO_I2C_EN enum
9918  */
9919 
9920 typedef enum DCIOCHIP_GPIO_I2C_EN {
9921 DCIOCHIP_GPIO_I2C_DISABLE                = 0x00000000,
9922 DCIOCHIP_GPIO_I2C_ENABLE                 = 0x00000001,
9923 } DCIOCHIP_GPIO_I2C_EN;
9924 
9925 /*
9926  * DCIOCHIP_MASK_4BIT enum
9927  */
9928 
9929 typedef enum DCIOCHIP_MASK_4BIT {
9930 DCIOCHIP_MASK_4BIT_DISABLE               = 0x00000000,
9931 DCIOCHIP_MASK_4BIT_ENABLE                = 0x0000000f,
9932 } DCIOCHIP_MASK_4BIT;
9933 
9934 /*
9935  * DCIOCHIP_ENABLE_4BIT enum
9936  */
9937 
9938 typedef enum DCIOCHIP_ENABLE_4BIT {
9939 DCIOCHIP_4BIT_DISABLE                    = 0x00000000,
9940 DCIOCHIP_4BIT_ENABLE                     = 0x0000000f,
9941 } DCIOCHIP_ENABLE_4BIT;
9942 
9943 /*
9944  * DCIOCHIP_MASK_5BIT enum
9945  */
9946 
9947 typedef enum DCIOCHIP_MASK_5BIT {
9948 DCIOCHIP_MASIK_5BIT_DISABLE              = 0x00000000,
9949 DCIOCHIP_MASIK_5BIT_ENABLE               = 0x0000001f,
9950 } DCIOCHIP_MASK_5BIT;
9951 
9952 /*
9953  * DCIOCHIP_ENABLE_5BIT enum
9954  */
9955 
9956 typedef enum DCIOCHIP_ENABLE_5BIT {
9957 DCIOCHIP_5BIT_DISABLE                    = 0x00000000,
9958 DCIOCHIP_5BIT_ENABLE                     = 0x0000001f,
9959 } DCIOCHIP_ENABLE_5BIT;
9960 
9961 /*
9962  * DCIOCHIP_MASK_2BIT enum
9963  */
9964 
9965 typedef enum DCIOCHIP_MASK_2BIT {
9966 DCIOCHIP_MASK_2BIT_DISABLE               = 0x00000000,
9967 DCIOCHIP_MASK_2BIT_ENABLE                = 0x00000003,
9968 } DCIOCHIP_MASK_2BIT;
9969 
9970 /*
9971  * DCIOCHIP_ENABLE_2BIT enum
9972  */
9973 
9974 typedef enum DCIOCHIP_ENABLE_2BIT {
9975 DCIOCHIP_2BIT_DISABLE                    = 0x00000000,
9976 DCIOCHIP_2BIT_ENABLE                     = 0x00000003,
9977 } DCIOCHIP_ENABLE_2BIT;
9978 
9979 /*
9980  * DCIOCHIP_REF_27_SRC_SEL enum
9981  */
9982 
9983 typedef enum DCIOCHIP_REF_27_SRC_SEL {
9984 DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER     = 0x00000000,
9985 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER  = 0x00000001,
9986 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS      = 0x00000002,
9987 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS  = 0x00000003,
9988 } DCIOCHIP_REF_27_SRC_SEL;
9989 
9990 /*
9991  * DCIOCHIP_DVO_VREFPON enum
9992  */
9993 
9994 typedef enum DCIOCHIP_DVO_VREFPON {
9995 DCIOCHIP_DVO_VREFPON_DISABLE             = 0x00000000,
9996 DCIOCHIP_DVO_VREFPON_ENABLE              = 0x00000001,
9997 } DCIOCHIP_DVO_VREFPON;
9998 
9999 /*
10000  * DCIOCHIP_DVO_VREFSEL enum
10001  */
10002 
10003 typedef enum DCIOCHIP_DVO_VREFSEL {
10004 DCIOCHIP_DVO_VREFSEL_ONCHIP              = 0x00000000,
10005 DCIOCHIP_DVO_VREFSEL_EXTERNAL            = 0x00000001,
10006 } DCIOCHIP_DVO_VREFSEL;
10007 
10008 /*
10009  * DCIOCHIP_SPDIF1_IMODE enum
10010  */
10011 
10012 typedef enum DCIOCHIP_SPDIF1_IMODE {
10013 DCIOCHIP_SPDIF1_IMODE_OE_A               = 0x00000000,
10014 DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO          = 0x00000001,
10015 } DCIOCHIP_SPDIF1_IMODE;
10016 
10017 /*
10018  * DCIOCHIP_AUX_FALLSLEWSEL enum
10019  */
10020 
10021 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10022 DCIOCHIP_AUX_FALLSLEWSEL_LOW             = 0x00000000,
10023 DCIOCHIP_AUX_FALLSLEWSEL_HIGH0           = 0x00000001,
10024 DCIOCHIP_AUX_FALLSLEWSEL_HIGH1           = 0x00000002,
10025 DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH       = 0x00000003,
10026 } DCIOCHIP_AUX_FALLSLEWSEL;
10027 
10028 /*
10029  * DCIOCHIP_AUX_SPIKESEL enum
10030  */
10031 
10032 typedef enum DCIOCHIP_AUX_SPIKESEL {
10033 DCIOCHIP_AUX_SPIKESEL_50NS               = 0x00000000,
10034 DCIOCHIP_AUX_SPIKESEL_10NS               = 0x00000001,
10035 } DCIOCHIP_AUX_SPIKESEL;
10036 
10037 /*
10038  * DCIOCHIP_AUX_CSEL0P9 enum
10039  */
10040 
10041 typedef enum DCIOCHIP_AUX_CSEL0P9 {
10042 DCIOCHIP_AUX_CSEL_DEC1P0                 = 0x00000000,
10043 DCIOCHIP_AUX_CSEL_DEC0P9                 = 0x00000001,
10044 } DCIOCHIP_AUX_CSEL0P9;
10045 
10046 /*
10047  * DCIOCHIP_AUX_CSEL1P1 enum
10048  */
10049 
10050 typedef enum DCIOCHIP_AUX_CSEL1P1 {
10051 DCIOCHIP_AUX_CSEL_INC1P0                 = 0x00000000,
10052 DCIOCHIP_AUX_CSEL_INC1P1                 = 0x00000001,
10053 } DCIOCHIP_AUX_CSEL1P1;
10054 
10055 /*
10056  * DCIOCHIP_AUX_RSEL0P9 enum
10057  */
10058 
10059 typedef enum DCIOCHIP_AUX_RSEL0P9 {
10060 DCIOCHIP_AUX_RSEL_DEC1P0                 = 0x00000000,
10061 DCIOCHIP_AUX_RSEL_DEC0P9                 = 0x00000001,
10062 } DCIOCHIP_AUX_RSEL0P9;
10063 
10064 /*
10065  * DCIOCHIP_AUX_RSEL1P1 enum
10066  */
10067 
10068 typedef enum DCIOCHIP_AUX_RSEL1P1 {
10069 DCIOCHIP_AUX_RSEL_INC1P0                 = 0x00000000,
10070 DCIOCHIP_AUX_RSEL_INC1P1                 = 0x00000001,
10071 } DCIOCHIP_AUX_RSEL1P1;
10072 
10073 /*******************************************************
10074  * AZCONTROLLER Enums
10075  *******************************************************/
10076 
10077 /*
10078  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10079  */
10080 
10081 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10082 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE   = 0x00000000,
10083 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE    = 0x00000001,
10084 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
10085 
10086 /*
10087  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10088  */
10089 
10090 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10091 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x00000000,
10092 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED  = 0x00000001,
10093 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
10094 
10095 /*
10096  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10097  */
10098 
10099 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10100 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET  = 0x00000000,
10101 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET  = 0x00000001,
10102 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
10103 
10104 /*
10105  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10106  */
10107 
10108 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10109 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED  = 0x00000000,
10110 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED  = 0x00000001,
10111 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
10112 
10113 /*
10114  * AZ_GLOBAL_CAPABILITIES enum
10115  */
10116 
10117 typedef enum AZ_GLOBAL_CAPABILITIES {
10118 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED  = 0x00000000,
10119 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED  = 0x00000001,
10120 } AZ_GLOBAL_CAPABILITIES;
10121 
10122 /*
10123  * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10124  */
10125 
10126 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10127 ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE   = 0x00000000,
10128 ACCEPT_UNSOLICITED_RESPONSE_ENABLE       = 0x00000001,
10129 } GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
10130 
10131 /*
10132  * GLOBAL_CONTROL_FLUSH_CONTROL enum
10133  */
10134 
10135 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10136 FLUSH_CONTROL_FLUSH_NOT_STARTED          = 0x00000000,
10137 FLUSH_CONTROL_FLUSH_STARTED              = 0x00000001,
10138 } GLOBAL_CONTROL_FLUSH_CONTROL;
10139 
10140 /*
10141  * GLOBAL_CONTROL_CONTROLLER_RESET enum
10142  */
10143 
10144 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10145 CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET  = 0x00000000,
10146 CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET  = 0x00000001,
10147 } GLOBAL_CONTROL_CONTROLLER_RESET;
10148 
10149 /*
10150  * AZ_STATE_CHANGE_STATUS enum
10151  */
10152 
10153 typedef enum AZ_STATE_CHANGE_STATUS {
10154 AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT  = 0x00000000,
10155 AZ_STATE_CHANGE_STATUS_CODEC_PRESENT     = 0x00000001,
10156 } AZ_STATE_CHANGE_STATUS;
10157 
10158 /*
10159  * GLOBAL_STATUS_FLUSH_STATUS enum
10160  */
10161 
10162 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10163 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED  = 0x00000000,
10164 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED   = 0x00000001,
10165 } GLOBAL_STATUS_FLUSH_STATUS;
10166 
10167 /*
10168  * STREAM_0_SYNCHRONIZATION enum
10169  */
10170 
10171 typedef enum STREAM_0_SYNCHRONIZATION {
10172 STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10173 STREAM_0_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10174 } STREAM_0_SYNCHRONIZATION;
10175 
10176 /*
10177  * STREAM_1_SYNCHRONIZATION enum
10178  */
10179 
10180 typedef enum STREAM_1_SYNCHRONIZATION {
10181 STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10182 STREAM_1_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10183 } STREAM_1_SYNCHRONIZATION;
10184 
10185 /*
10186  * STREAM_2_SYNCHRONIZATION enum
10187  */
10188 
10189 typedef enum STREAM_2_SYNCHRONIZATION {
10190 STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10191 STREAM_2_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10192 } STREAM_2_SYNCHRONIZATION;
10193 
10194 /*
10195  * STREAM_3_SYNCHRONIZATION enum
10196  */
10197 
10198 typedef enum STREAM_3_SYNCHRONIZATION {
10199 STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10200 STREAM_3_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10201 } STREAM_3_SYNCHRONIZATION;
10202 
10203 /*
10204  * STREAM_4_SYNCHRONIZATION enum
10205  */
10206 
10207 typedef enum STREAM_4_SYNCHRONIZATION {
10208 STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10209 STREAM_4_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10210 } STREAM_4_SYNCHRONIZATION;
10211 
10212 /*
10213  * STREAM_5_SYNCHRONIZATION enum
10214  */
10215 
10216 typedef enum STREAM_5_SYNCHRONIZATION {
10217 STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10218 STREAM_5_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10219 } STREAM_5_SYNCHRONIZATION;
10220 
10221 /*
10222  * STREAM_6_SYNCHRONIZATION enum
10223  */
10224 
10225 typedef enum STREAM_6_SYNCHRONIZATION {
10226 STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10227 STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10228 } STREAM_6_SYNCHRONIZATION;
10229 
10230 /*
10231  * STREAM_7_SYNCHRONIZATION enum
10232  */
10233 
10234 typedef enum STREAM_7_SYNCHRONIZATION {
10235 STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10236 STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10237 } STREAM_7_SYNCHRONIZATION;
10238 
10239 /*
10240  * STREAM_8_SYNCHRONIZATION enum
10241  */
10242 
10243 typedef enum STREAM_8_SYNCHRONIZATION {
10244 STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10245 STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10246 } STREAM_8_SYNCHRONIZATION;
10247 
10248 /*
10249  * STREAM_9_SYNCHRONIZATION enum
10250  */
10251 
10252 typedef enum STREAM_9_SYNCHRONIZATION {
10253 STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10254 STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10255 } STREAM_9_SYNCHRONIZATION;
10256 
10257 /*
10258  * STREAM_10_SYNCHRONIZATION enum
10259  */
10260 
10261 typedef enum STREAM_10_SYNCHRONIZATION {
10262 STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10263 STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10264 } STREAM_10_SYNCHRONIZATION;
10265 
10266 /*
10267  * STREAM_11_SYNCHRONIZATION enum
10268  */
10269 
10270 typedef enum STREAM_11_SYNCHRONIZATION {
10271 STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10272 STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10273 } STREAM_11_SYNCHRONIZATION;
10274 
10275 /*
10276  * STREAM_12_SYNCHRONIZATION enum
10277  */
10278 
10279 typedef enum STREAM_12_SYNCHRONIZATION {
10280 STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10281 STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10282 } STREAM_12_SYNCHRONIZATION;
10283 
10284 /*
10285  * STREAM_13_SYNCHRONIZATION enum
10286  */
10287 
10288 typedef enum STREAM_13_SYNCHRONIZATION {
10289 STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10290 STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10291 } STREAM_13_SYNCHRONIZATION;
10292 
10293 /*
10294  * STREAM_14_SYNCHRONIZATION enum
10295  */
10296 
10297 typedef enum STREAM_14_SYNCHRONIZATION {
10298 STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10299 STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10300 } STREAM_14_SYNCHRONIZATION;
10301 
10302 /*
10303  * STREAM_15_SYNCHRONIZATION enum
10304  */
10305 
10306 typedef enum STREAM_15_SYNCHRONIZATION {
10307 STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10308 STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10309 } STREAM_15_SYNCHRONIZATION;
10310 
10311 /*
10312  * CORB_READ_POINTER_RESET enum
10313  */
10314 
10315 typedef enum CORB_READ_POINTER_RESET {
10316 CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET  = 0x00000000,
10317 CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET  = 0x00000001,
10318 } CORB_READ_POINTER_RESET;
10319 
10320 /*
10321  * AZ_CORB_SIZE enum
10322  */
10323 
10324 typedef enum AZ_CORB_SIZE {
10325 AZ_CORB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
10326 AZ_CORB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
10327 AZ_CORB_SIZE_256ENTRIES                  = 0x00000002,
10328 AZ_CORB_SIZE_RESERVED                    = 0x00000003,
10329 } AZ_CORB_SIZE;
10330 
10331 /*
10332  * AZ_RIRB_WRITE_POINTER_RESET enum
10333  */
10334 
10335 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10336 AZ_RIRB_WRITE_POINTER_NOT_RESET          = 0x00000000,
10337 AZ_RIRB_WRITE_POINTER_DO_RESET           = 0x00000001,
10338 } AZ_RIRB_WRITE_POINTER_RESET;
10339 
10340 /*
10341  * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10342  */
10343 
10344 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10345 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
10346 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
10347 } RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
10348 
10349 /*
10350  * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10351  */
10352 
10353 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10354 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
10355 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
10356 } RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
10357 
10358 /*
10359  * AZ_RIRB_SIZE enum
10360  */
10361 
10362 typedef enum AZ_RIRB_SIZE {
10363 AZ_RIRB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
10364 AZ_RIRB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
10365 AZ_RIRB_SIZE_256ENTRIES                  = 0x00000002,
10366 AZ_RIRB_SIZE_UNDEFINED                   = 0x00000003,
10367 } AZ_RIRB_SIZE;
10368 
10369 /*
10370  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10371  */
10372 
10373 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10374 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID  = 0x00000000,
10375 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID  = 0x00000001,
10376 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
10377 
10378 /*
10379  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10380  */
10381 
10382 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10383 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY  = 0x00000000,
10384 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY  = 0x00000001,
10385 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
10386 
10387 /*
10388  * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10389  */
10390 
10391 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10392 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE  = 0x00000000,
10393 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE  = 0x00000001,
10394 } DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
10395 
10396 /*******************************************************
10397  * AZENDPOINT Enums
10398  *******************************************************/
10399 
10400 /*
10401  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10402  */
10403 
10404 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10405 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
10406 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
10407 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10408 
10409 /*
10410  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10411  */
10412 
10413 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10414 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
10415 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
10416 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10417 
10418 /*
10419  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10420  */
10421 
10422 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10423 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
10424 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
10425 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
10426 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
10427 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
10428 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10429 
10430 /*
10431  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10432  */
10433 
10434 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10435 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
10436 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
10437 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
10438 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
10439 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
10440 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
10441 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
10442 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
10443 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10444 
10445 /*
10446  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10447  */
10448 
10449 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10450 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
10451 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
10452 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
10453 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
10454 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
10455 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
10456 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10457 
10458 /*
10459  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10460  */
10461 
10462 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10463 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
10464 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
10465 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
10466 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
10467 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
10468 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
10469 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
10470 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
10471 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
10472 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10473 
10474 /*
10475  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10476  */
10477 
10478 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10479 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET  = 0x00000000,
10480 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET  = 0x00000001,
10481 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
10482 
10483 /*
10484  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10485  */
10486 
10487 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10488 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET  = 0x00000000,
10489 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET  = 0x00000001,
10490 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
10491 
10492 /*
10493  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10494  */
10495 
10496 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10497 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET  = 0x00000000,
10498 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET  = 0x00000001,
10499 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
10500 
10501 /*
10502  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10503  */
10504 
10505 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10506 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET  = 0x00000000,
10507 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET  = 0x00000001,
10508 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
10509 
10510 /*
10511  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10512  */
10513 
10514 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10515 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET  = 0x00000000,
10516 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET  = 0x00000001,
10517 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
10518 
10519 /*
10520  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10521  */
10522 
10523 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10524 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON  = 0x00000000,
10525 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON  = 0x00000001,
10526 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
10527 
10528 /*
10529  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10530  */
10531 
10532 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10533 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO  = 0x00000000,
10534 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE  = 0x00000001,
10535 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
10536 
10537 /*
10538  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10539  */
10540 
10541 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10542 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
10543 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
10544 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10545 
10546 /*
10547  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10548  */
10549 
10550 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10551 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE  = 0x00000000,
10552 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE  = 0x00000001,
10553 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
10554 
10555 /*
10556  * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10557  */
10558 
10559 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10560 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF  = 0x00000000,
10561 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN  = 0x00000001,
10562 } AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
10563 
10564 /*
10565  * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10566  */
10567 
10568 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10569 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
10570 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
10571 } AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10572 
10573 /*
10574  * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10575  */
10576 
10577 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10578 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED  = 0x00000000,
10579 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN  = 0x00000001,
10580 } AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
10581 
10582 /*
10583  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10584  */
10585 
10586 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10587 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED  = 0x00000000,
10588 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED  = 0x00000001,
10589 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
10590 
10591 /*
10592  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10593  */
10594 
10595 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10596 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED  = 0x00000000,
10597 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED  = 0x00000001,
10598 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
10599 
10600 /*
10601  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10602  */
10603 
10604 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10605 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED  = 0x00000000,
10606 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED  = 0x00000001,
10607 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
10608 
10609 /*
10610  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10611  */
10612 
10613 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10614 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED  = 0x00000000,
10615 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED  = 0x00000001,
10616 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
10617 
10618 /*
10619  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10620  */
10621 
10622 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10623 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
10624 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
10625 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10626 
10627 /*
10628  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10629  */
10630 
10631 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10632 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
10633 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
10634 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10635 
10636 /*
10637  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10638  */
10639 
10640 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10641 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
10642 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
10643 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10644 
10645 /*
10646  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10647  */
10648 
10649 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10650 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
10651 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
10652 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10653 
10654 /*
10655  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10656  */
10657 
10658 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10659 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
10660 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
10661 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10662 
10663 /*******************************************************
10664  * AZF0CONTROLLER Enums
10665  *******************************************************/
10666 
10667 /*
10668  * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10669  */
10670 
10671 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10672 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET  = 0x00000000,
10673 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC  = 0x00000001,
10674 } AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
10675 
10676 /*******************************************************
10677  * AZF0ROOT Enums
10678  *******************************************************/
10679 
10680 /*
10681  * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
10682  */
10683 
10684 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10685 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL  = 0x00000000,
10686 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6  = 0x00000001,
10687 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5  = 0x00000002,
10688 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4  = 0x00000003,
10689 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3  = 0x00000004,
10690 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2  = 0x00000005,
10691 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1  = 0x00000006,
10692 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0  = 0x00000007,
10693 } CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
10694 
10695 /*
10696  * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
10697  */
10698 
10699 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10700 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL  = 0x00000000,
10701 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6  = 0x00000001,
10702 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5  = 0x00000002,
10703 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4  = 0x00000003,
10704 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3  = 0x00000004,
10705 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2  = 0x00000005,
10706 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1  = 0x00000006,
10707 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0  = 0x00000007,
10708 } CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
10709 
10710 /*******************************************************
10711  * AZINPUTENDPOINT Enums
10712  *******************************************************/
10713 
10714 /*
10715  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10716  */
10717 
10718 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10719 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
10720 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
10721 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10722 
10723 /*
10724  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10725  */
10726 
10727 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10728 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
10729 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
10730 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10731 
10732 /*
10733  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10734  */
10735 
10736 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10737 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
10738 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
10739 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
10740 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
10741 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
10742 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10743 
10744 /*
10745  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10746  */
10747 
10748 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10749 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
10750 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
10751 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
10752 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
10753 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
10754 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
10755 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
10756 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
10757 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10758 
10759 /*
10760  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10761  */
10762 
10763 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10764 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
10765 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
10766 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
10767 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
10768 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
10769 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
10770 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10771 
10772 /*
10773  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10774  */
10775 
10776 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10777 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
10778 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
10779 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
10780 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
10781 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
10782 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
10783 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
10784 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
10785 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
10786 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10787 
10788 /*
10789  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10790  */
10791 
10792 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10793 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
10794 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
10795 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10796 
10797 /*
10798  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
10799  */
10800 
10801 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10802 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF  = 0x00000000,
10803 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN  = 0x00000001,
10804 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
10805 
10806 /*
10807  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10808  */
10809 
10810 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10811 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
10812 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
10813 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10814 
10815 /*
10816  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
10817  */
10818 
10819 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10820 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED  = 0x00000000,
10821 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED  = 0x00000001,
10822 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
10823 
10824 /*
10825  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10826  */
10827 
10828 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10829 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
10830 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
10831 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10832 
10833 /*
10834  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
10835  */
10836 
10837 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10838 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED  = 0x00000000,
10839 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED  = 0x00000001,
10840 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
10841 
10842 /*
10843  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10844  */
10845 
10846 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10847 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
10848 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
10849 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10850 
10851 /*
10852  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
10853  */
10854 
10855 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10856 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED  = 0x00000000,
10857 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED  = 0x00000001,
10858 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
10859 
10860 /*
10861  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10862  */
10863 
10864 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10865 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
10866 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
10867 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10868 
10869 /*
10870  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
10871  */
10872 
10873 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10874 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED  = 0x00000000,
10875 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED  = 0x00000001,
10876 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
10877 
10878 /*
10879  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10880  */
10881 
10882 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10883 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
10884 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
10885 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10886 
10887 /*******************************************************
10888  * AZROOT Enums
10889  *******************************************************/
10890 
10891 /*
10892  * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
10893  */
10894 
10895 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10896 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET  = 0x00000000,
10897 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET  = 0x00000001,
10898 } AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
10899 
10900 /*******************************************************
10901  * DCCG Enums
10902  *******************************************************/
10903 
10904 /*
10905  * ENABLE enum
10906  */
10907 
10908 typedef enum ENABLE {
10909 DISABLE_THE_FEATURE                      = 0x00000000,
10910 ENABLE_THE_FEATURE                       = 0x00000001,
10911 } ENABLE;
10912 
10913 /*
10914  * ENABLE_CLOCK enum
10915  */
10916 
10917 typedef enum ENABLE_CLOCK {
10918 DISABLE_THE_CLOCK                        = 0x00000000,
10919 ENABLE_THE_CLOCK                         = 0x00000001,
10920 } ENABLE_CLOCK;
10921 
10922 /*
10923  * FORCE_VBI enum
10924  */
10925 
10926 typedef enum FORCE_VBI {
10927 FORCE_VBI_LOW                            = 0x00000000,
10928 FORCE_VBI_HIGH                           = 0x00000001,
10929 } FORCE_VBI;
10930 
10931 /*
10932  * OVERRIDE_CGTT_SCLK enum
10933  */
10934 
10935 typedef enum OVERRIDE_CGTT_SCLK {
10936 OVERRIDE_CGTT_SCLK_NOOP                  = 0x00000000,
10937 SET_OVERRIDE_CGTT_SCLK                   = 0x00000001,
10938 } OVERRIDE_CGTT_SCLK;
10939 
10940 /*
10941  * CLEAR_SMU_INTR enum
10942  */
10943 
10944 typedef enum CLEAR_SMU_INTR {
10945 SMU_INTR_STATUS_NOOP                     = 0x00000000,
10946 SMU_INTR_STATUS_CLEAR                    = 0x00000001,
10947 } CLEAR_SMU_INTR;
10948 
10949 /*
10950  * STATIC_SCREEN_SMU_INTR enum
10951  */
10952 
10953 typedef enum STATIC_SCREEN_SMU_INTR {
10954 STATIC_SCREEN_SMU_INTR_NOOP              = 0x00000000,
10955 SET_STATIC_SCREEN_SMU_INTR               = 0x00000001,
10956 } STATIC_SCREEN_SMU_INTR;
10957 
10958 /*
10959  * JITTER_REMOVE_DISABLE enum
10960  */
10961 
10962 typedef enum JITTER_REMOVE_DISABLE {
10963 ENABLE_JITTER_REMOVAL                    = 0x00000000,
10964 DISABLE_JITTER_REMOVAL                   = 0x00000001,
10965 } JITTER_REMOVE_DISABLE;
10966 
10967 /*
10968  * DS_REF_SRC enum
10969  */
10970 
10971 typedef enum DS_REF_SRC {
10972 DS_REF_IS_XTALIN                         = 0x00000000,
10973 DS_REF_IS_EXT_GENLOCK                    = 0x00000001,
10974 DS_REF_IS_PCIE                           = 0x00000002,
10975 } DS_REF_SRC;
10976 
10977 /*
10978  * DISABLE_CLOCK_GATING enum
10979  */
10980 
10981 typedef enum DISABLE_CLOCK_GATING {
10982 CLOCK_GATING_ENABLED                     = 0x00000000,
10983 CLOCK_GATING_DISABLED                    = 0x00000001,
10984 } DISABLE_CLOCK_GATING;
10985 
10986 /*
10987  * DISABLE_CLOCK_GATING_IN_DCO enum
10988  */
10989 
10990 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
10991 CLOCK_GATING_ENABLED_IN_DCO              = 0x00000000,
10992 CLOCK_GATING_DISABLED_IN_DCO             = 0x00000001,
10993 } DISABLE_CLOCK_GATING_IN_DCO;
10994 
10995 /*
10996  * DCCG_DEEP_COLOR_CNTL enum
10997  */
10998 
10999 typedef enum DCCG_DEEP_COLOR_CNTL {
11000 DCCG_DEEP_COLOR_DTO_DISABLE              = 0x00000000,
11001 DCCG_DEEP_COLOR_DTO_5_4_RATIO            = 0x00000001,
11002 DCCG_DEEP_COLOR_DTO_3_2_RATIO            = 0x00000002,
11003 DCCG_DEEP_COLOR_DTO_2_1_RATIO            = 0x00000003,
11004 } DCCG_DEEP_COLOR_CNTL;
11005 
11006 /*
11007  * REFCLK_CLOCK_EN enum
11008  */
11009 
11010 typedef enum REFCLK_CLOCK_EN {
11011 REFCLK_CLOCK_EN_XTALIN_CLK               = 0x00000000,
11012 REFCLK_CLOCK_EN_ALLOW_SRC_SEL            = 0x00000001,
11013 } REFCLK_CLOCK_EN;
11014 
11015 /*
11016  * REFCLK_SRC_SEL enum
11017  */
11018 
11019 typedef enum REFCLK_SRC_SEL {
11020 REFCLK_SRC_SEL_PCIE_REFCLK               = 0x00000000,
11021 REFCLK_SRC_SEL_CPL_REFCLK                = 0x00000001,
11022 } REFCLK_SRC_SEL;
11023 
11024 /*
11025  * DPREFCLK_SRC_SEL enum
11026  */
11027 
11028 typedef enum DPREFCLK_SRC_SEL {
11029 DPREFCLK_SRC_SEL_CK                      = 0x00000000,
11030 DPREFCLK_SRC_SEL_P0PLL                   = 0x00000001,
11031 DPREFCLK_SRC_SEL_P1PLL                   = 0x00000002,
11032 DPREFCLK_SRC_SEL_P2PLL                   = 0x00000003,
11033 DPREFCLK_SRC_SEL_P3PLL                   = 0x00000004,
11034 } DPREFCLK_SRC_SEL;
11035 
11036 /*
11037  * XTAL_REF_SEL enum
11038  */
11039 
11040 typedef enum XTAL_REF_SEL {
11041 XTAL_REF_SEL_1X                          = 0x00000000,
11042 XTAL_REF_SEL_2X                          = 0x00000001,
11043 } XTAL_REF_SEL;
11044 
11045 /*
11046  * XTAL_REF_CLOCK_SOURCE_SEL enum
11047  */
11048 
11049 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
11050 XTAL_REF_CLOCK_SOURCE_SEL_XTALIN         = 0x00000000,
11051 XTAL_REF_CLOCK_SOURCE_SEL_PPLL           = 0x00000001,
11052 } XTAL_REF_CLOCK_SOURCE_SEL;
11053 
11054 /*
11055  * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11056  */
11057 
11058 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11059 MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
11060 MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK  = 0x00000001,
11061 } MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11062 
11063 /*
11064  * ALLOW_SR_ON_TRANS_REQ enum
11065  */
11066 
11067 typedef enum ALLOW_SR_ON_TRANS_REQ {
11068 ALLOW_SR_ON_TRANS_REQ_ENABLE             = 0x00000000,
11069 ALLOW_SR_ON_TRANS_REQ_DISABLE            = 0x00000001,
11070 } ALLOW_SR_ON_TRANS_REQ;
11071 
11072 /*
11073  * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11074  */
11075 
11076 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11077 MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
11078 MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK  = 0x00000001,
11079 } MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11080 
11081 /*
11082  * PIPE_PIXEL_RATE_SOURCE enum
11083  */
11084 
11085 typedef enum PIPE_PIXEL_RATE_SOURCE {
11086 PIPE_PIXEL_RATE_SOURCE_P0PLL             = 0x00000000,
11087 PIPE_PIXEL_RATE_SOURCE_P1PLL             = 0x00000001,
11088 PIPE_PIXEL_RATE_SOURCE_P2PLL             = 0x00000002,
11089 } PIPE_PIXEL_RATE_SOURCE;
11090 
11091 /*
11092  * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
11093  */
11094 
11095 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
11096 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA    = 0x00000000,
11097 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB    = 0x00000001,
11098 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC    = 0x00000002,
11099 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD    = 0x00000003,
11100 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE    = 0x00000004,
11101 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF    = 0x00000005,
11102 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG    = 0x00000006,
11103 } PIPE_PHYPLL_PIXEL_RATE_SOURCE;
11104 
11105 /*
11106  * PIPE_PIXEL_RATE_PLL_SOURCE enum
11107  */
11108 
11109 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
11110 PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL        = 0x00000000,
11111 PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL       = 0x00000001,
11112 } PIPE_PIXEL_RATE_PLL_SOURCE;
11113 
11114 /*
11115  * DP_DTO_DS_DISABLE enum
11116  */
11117 
11118 typedef enum DP_DTO_DS_DISABLE {
11119 DP_DTO_DESPREAD_DISABLE                  = 0x00000000,
11120 DP_DTO_DESPREAD_ENABLE                   = 0x00000001,
11121 } DP_DTO_DS_DISABLE;
11122 
11123 /*
11124  * CRTC_ADD_PIXEL enum
11125  */
11126 
11127 typedef enum CRTC_ADD_PIXEL {
11128 CRTC_ADD_PIXEL_NOOP                      = 0x00000000,
11129 CRTC_ADD_PIXEL_FORCE                     = 0x00000001,
11130 } CRTC_ADD_PIXEL;
11131 
11132 /*
11133  * CRTC_DROP_PIXEL enum
11134  */
11135 
11136 typedef enum CRTC_DROP_PIXEL {
11137 CRTC_DROP_PIXEL_NOOP                     = 0x00000000,
11138 CRTC_DROP_PIXEL_FORCE                    = 0x00000001,
11139 } CRTC_DROP_PIXEL;
11140 
11141 /*
11142  * SYMCLK_FE_FORCE_EN enum
11143  */
11144 
11145 typedef enum SYMCLK_FE_FORCE_EN {
11146 SYMCLK_FE_FORCE_EN_DISABLE               = 0x00000000,
11147 SYMCLK_FE_FORCE_EN_ENABLE                = 0x00000001,
11148 } SYMCLK_FE_FORCE_EN;
11149 
11150 /*
11151  * SYMCLK_FE_FORCE_SRC enum
11152  */
11153 
11154 typedef enum SYMCLK_FE_FORCE_SRC {
11155 SYMCLK_FE_FORCE_SRC_UNIPHYA              = 0x00000000,
11156 SYMCLK_FE_FORCE_SRC_UNIPHYB              = 0x00000001,
11157 SYMCLK_FE_FORCE_SRC_UNIPHYC              = 0x00000002,
11158 SYMCLK_FE_FORCE_SRC_UNIPHYD              = 0x00000003,
11159 SYMCLK_FE_FORCE_SRC_UNIPHYE              = 0x00000004,
11160 SYMCLK_FE_FORCE_SRC_UNIPHYF              = 0x00000005,
11161 SYMCLK_FE_FORCE_SRC_UNIPHYG              = 0x00000006,
11162 } SYMCLK_FE_FORCE_SRC;
11163 
11164 /*
11165  * DPDBG_CLK_FORCE_EN enum
11166  */
11167 
11168 typedef enum DPDBG_CLK_FORCE_EN {
11169 DPDBG_CLK_FORCE_EN_DISABLE               = 0x00000000,
11170 DPDBG_CLK_FORCE_EN_ENABLE                = 0x00000001,
11171 } DPDBG_CLK_FORCE_EN;
11172 
11173 /*
11174  * DVOACLK_COARSE_SKEW_CNTL enum
11175  */
11176 
11177 typedef enum DVOACLK_COARSE_SKEW_CNTL {
11178 DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT   = 0x00000000,
11179 DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP    = 0x00000001,
11180 DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS   = 0x00000002,
11181 DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS   = 0x00000003,
11182 DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS   = 0x00000004,
11183 DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS   = 0x00000005,
11184 DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS   = 0x00000006,
11185 DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS   = 0x00000007,
11186 DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS   = 0x00000008,
11187 DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS   = 0x00000009,
11188 DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS  = 0x0000000a,
11189 DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS  = 0x0000000b,
11190 DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS  = 0x0000000c,
11191 DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS  = 0x0000000d,
11192 DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS  = 0x0000000e,
11193 DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS  = 0x0000000f,
11194 DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP    = 0x00000010,
11195 DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS   = 0x00000011,
11196 DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS   = 0x00000012,
11197 DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS   = 0x00000013,
11198 DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS   = 0x00000014,
11199 DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS   = 0x00000015,
11200 DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS   = 0x00000016,
11201 DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS   = 0x00000017,
11202 DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS   = 0x00000018,
11203 DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS  = 0x00000019,
11204 DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS  = 0x0000001a,
11205 DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS  = 0x0000001b,
11206 DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS  = 0x0000001c,
11207 DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS  = 0x0000001d,
11208 DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS  = 0x0000001e,
11209 } DVOACLK_COARSE_SKEW_CNTL;
11210 
11211 /*
11212  * DVOACLK_FINE_SKEW_CNTL enum
11213  */
11214 
11215 typedef enum DVOACLK_FINE_SKEW_CNTL {
11216 DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT     = 0x00000000,
11217 DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP      = 0x00000001,
11218 DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS     = 0x00000002,
11219 DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS     = 0x00000003,
11220 DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP      = 0x00000004,
11221 DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS     = 0x00000005,
11222 DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS     = 0x00000006,
11223 DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS     = 0x00000007,
11224 } DVOACLK_FINE_SKEW_CNTL;
11225 
11226 /*
11227  * DVOACLKD_IN_PHASE enum
11228  */
11229 
11230 typedef enum DVOACLKD_IN_PHASE {
11231 DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11232 DVOACLKD_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
11233 } DVOACLKD_IN_PHASE;
11234 
11235 /*
11236  * DVOACLKC_IN_PHASE enum
11237  */
11238 
11239 typedef enum DVOACLKC_IN_PHASE {
11240 DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11241 DVOACLKC_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
11242 } DVOACLKC_IN_PHASE;
11243 
11244 /*
11245  * DVOACLKC_MVP_IN_PHASE enum
11246  */
11247 
11248 typedef enum DVOACLKC_MVP_IN_PHASE {
11249 DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11250 DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO      = 0x00000001,
11251 } DVOACLKC_MVP_IN_PHASE;
11252 
11253 /*
11254  * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
11255  */
11256 
11257 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
11258 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE  = 0x00000000,
11259 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE  = 0x00000001,
11260 } DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
11261 
11262 /*
11263  * MVP_CLK_SRC_SEL enum
11264  */
11265 
11266 typedef enum MVP_CLK_SRC_SEL {
11267 MVP_CLK_SRC_SEL_RSRV                     = 0x00000000,
11268 MVP_CLK_SRC_SEL_IO_1                     = 0x00000001,
11269 MVP_CLK_SRC_SEL_IO_2                     = 0x00000002,
11270 MVP_CLK_SRC_SEL_REFCLK                   = 0x00000003,
11271 } MVP_CLK_SRC_SEL;
11272 
11273 /*
11274  * DCCG_AUDIO_DTO0_SOURCE_SEL enum
11275  */
11276 
11277 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
11278 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0         = 0x00000000,
11279 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1         = 0x00000001,
11280 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2         = 0x00000002,
11281 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3         = 0x00000003,
11282 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4         = 0x00000004,
11283 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5         = 0x00000005,
11284 DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED      = 0x00000006,
11285 } DCCG_AUDIO_DTO0_SOURCE_SEL;
11286 
11287 /*
11288  * DCCG_AUDIO_DTO_SEL enum
11289  */
11290 
11291 typedef enum DCCG_AUDIO_DTO_SEL {
11292 DCCG_AUDIO_DTO_SEL_AUDIO_DTO0            = 0x00000000,
11293 DCCG_AUDIO_DTO_SEL_AUDIO_DTO1            = 0x00000001,
11294 DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO          = 0x00000002,
11295 } DCCG_AUDIO_DTO_SEL;
11296 
11297 /*
11298  * DCCG_AUDIO_DTO2_SOURCE_SEL enum
11299  */
11300 
11301 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
11302 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0        = 0x00000000,
11303 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1        = 0x00000001,
11304 } DCCG_AUDIO_DTO2_SOURCE_SEL;
11305 
11306 /*
11307  * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
11308  */
11309 
11310 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
11311 DCCG_AUDIO_DTO_USE_128FBR_FOR_DP         = 0x00000000,
11312 DCCG_AUDIO_DTO_USE_512FBR_FOR_DP         = 0x00000001,
11313 } DCCG_AUDIO_DTO_USE_512FBR_DTO;
11314 
11315 /*
11316  * DCCG_DBG_EN enum
11317  */
11318 
11319 typedef enum DCCG_DBG_EN {
11320 DCCG_DBG_EN_DISABLE                      = 0x00000000,
11321 DCCG_DBG_EN_ENABLE                       = 0x00000001,
11322 } DCCG_DBG_EN;
11323 
11324 /*
11325  * DCCG_DBG_BLOCK_SEL enum
11326  */
11327 
11328 typedef enum DCCG_DBG_BLOCK_SEL {
11329 DCCG_DBG_BLOCK_SEL_DCCG                  = 0x00000000,
11330 DCCG_DBG_BLOCK_SEL_PMON                  = 0x00000001,
11331 DCCG_DBG_BLOCK_SEL_PMON2                 = 0x00000002,
11332 } DCCG_DBG_BLOCK_SEL;
11333 
11334 /*
11335  * DISPCLK_FREQ_RAMP_DONE enum
11336  */
11337 
11338 typedef enum DISPCLK_FREQ_RAMP_DONE {
11339 DISPCLK_FREQ_RAMP_IN_PROGRESS            = 0x00000000,
11340 DISPCLK_FREQ_RAMP_COMPLETED              = 0x00000001,
11341 } DISPCLK_FREQ_RAMP_DONE;
11342 
11343 /*
11344  * DCCG_FIFO_ERRDET_RESET enum
11345  */
11346 
11347 typedef enum DCCG_FIFO_ERRDET_RESET {
11348 DCCG_FIFO_ERRDET_RESET_NOOP              = 0x00000000,
11349 DCCG_FIFO_ERRDET_RESET_FORCE             = 0x00000001,
11350 } DCCG_FIFO_ERRDET_RESET;
11351 
11352 /*
11353  * DCCG_FIFO_ERRDET_STATE enum
11354  */
11355 
11356 typedef enum DCCG_FIFO_ERRDET_STATE {
11357 DCCG_FIFO_ERRDET_STATE_DETECTION         = 0x00000000,
11358 DCCG_FIFO_ERRDET_STATE_CALIBRATION       = 0x00000001,
11359 } DCCG_FIFO_ERRDET_STATE;
11360 
11361 /*
11362  * DCCG_FIFO_ERRDET_OVR_EN enum
11363  */
11364 
11365 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
11366 DCCG_FIFO_ERRDET_OVR_DISABLE             = 0x00000000,
11367 DCCG_FIFO_ERRDET_OVR_ENABLE              = 0x00000001,
11368 } DCCG_FIFO_ERRDET_OVR_EN;
11369 
11370 /*
11371  * DISPCLK_CHG_FWD_CORR_DISABLE enum
11372  */
11373 
11374 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
11375 DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING  = 0x00000000,
11376 DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING  = 0x00000001,
11377 } DISPCLK_CHG_FWD_CORR_DISABLE;
11378 
11379 /*
11380  * DC_MEM_GLOBAL_PWR_REQ_DIS enum
11381  */
11382 
11383 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
11384 DC_MEM_GLOBAL_PWR_REQ_ENABLE             = 0x00000000,
11385 DC_MEM_GLOBAL_PWR_REQ_DISABLE            = 0x00000001,
11386 } DC_MEM_GLOBAL_PWR_REQ_DIS;
11387 
11388 /*
11389  * DCCG_PERF_RUN enum
11390  */
11391 
11392 typedef enum DCCG_PERF_RUN {
11393 DCCG_PERF_RUN_NOOP                       = 0x00000000,
11394 DCCG_PERF_RUN_START                      = 0x00000001,
11395 } DCCG_PERF_RUN;
11396 
11397 /*
11398  * DCCG_PERF_MODE_VSYNC enum
11399  */
11400 
11401 typedef enum DCCG_PERF_MODE_VSYNC {
11402 DCCG_PERF_MODE_VSYNC_NOOP                = 0x00000000,
11403 DCCG_PERF_MODE_VSYNC_START               = 0x00000001,
11404 } DCCG_PERF_MODE_VSYNC;
11405 
11406 /*
11407  * DCCG_PERF_MODE_HSYNC enum
11408  */
11409 
11410 typedef enum DCCG_PERF_MODE_HSYNC {
11411 DCCG_PERF_MODE_HSYNC_NOOP                = 0x00000000,
11412 DCCG_PERF_MODE_HSYNC_START               = 0x00000001,
11413 } DCCG_PERF_MODE_HSYNC;
11414 
11415 /*
11416  * DCCG_PERF_CRTC_SELECT enum
11417  */
11418 
11419 typedef enum DCCG_PERF_CRTC_SELECT {
11420 DCCG_PERF_SEL_CRTC0                      = 0x00000000,
11421 DCCG_PERF_SEL_CRTC1                      = 0x00000001,
11422 DCCG_PERF_SEL_CRTC2                      = 0x00000002,
11423 DCCG_PERF_SEL_CRTC3                      = 0x00000003,
11424 DCCG_PERF_SEL_CRTC4                      = 0x00000004,
11425 DCCG_PERF_SEL_CRTC5                      = 0x00000005,
11426 } DCCG_PERF_CRTC_SELECT;
11427 
11428 /*
11429  * CLOCK_BRANCH_SOFT_RESET enum
11430  */
11431 
11432 typedef enum CLOCK_BRANCH_SOFT_RESET {
11433 CLOCK_BRANCH_SOFT_RESET_NOOP             = 0x00000000,
11434 CLOCK_BRANCH_SOFT_RESET_FORCE            = 0x00000001,
11435 } CLOCK_BRANCH_SOFT_RESET;
11436 
11437 /*
11438  * PLL_CFG_IF_SOFT_RESET enum
11439  */
11440 
11441 typedef enum PLL_CFG_IF_SOFT_RESET {
11442 PLL_CFG_IF_SOFT_RESET_NOOP               = 0x00000000,
11443 PLL_CFG_IF_SOFT_RESET_FORCE              = 0x00000001,
11444 } PLL_CFG_IF_SOFT_RESET;
11445 
11446 /*
11447  * DVO_ENABLE_RST enum
11448  */
11449 
11450 typedef enum DVO_ENABLE_RST {
11451 DVO_ENABLE_RST_DISABLE                   = 0x00000000,
11452 DVO_ENABLE_RST_ENABLE                    = 0x00000001,
11453 } DVO_ENABLE_RST;
11454 
11455 /*******************************************************
11456  * DCI Enums
11457  *******************************************************/
11458 
11459 /*
11460  * LptNumPipes enum
11461  */
11462 
11463 typedef enum LptNumPipes {
11464 LPT_NUM_PIPES_1CH                        = 0x00000000,
11465 LPT_NUM_PIPES_2CH                        = 0x00000001,
11466 LPT_NUM_PIPES_4CH                        = 0x00000002,
11467 LPT_NUM_PIPES_8CH                        = 0x00000003,
11468 } LptNumPipes;
11469 
11470 /*
11471  * LptNumBanks enum
11472  */
11473 
11474 typedef enum LptNumBanks {
11475 LPT_NUM_BANKS_2BANK                      = 0x00000000,
11476 LPT_NUM_BANKS_4BANK                      = 0x00000001,
11477 LPT_NUM_BANKS_8BANK                      = 0x00000002,
11478 LPT_NUM_BANKS_16BANK                     = 0x00000003,
11479 LPT_NUM_BANKS_32BANK                     = 0x00000004,
11480 } LptNumBanks;
11481 
11482 /*
11483  * OVERRIDE_CGTT_DCEFCLK enum
11484  */
11485 
11486 typedef enum OVERRIDE_CGTT_DCEFCLK {
11487 OVERRIDE_CGTT_DCEFCLK_NOOP               = 0x00000000,
11488 SET_OVERRIDE_CGTT_DCEFCLK                = 0x00000001,
11489 } OVERRIDE_CGTT_DCEFCLK;
11490 
11491 /*******************************************************
11492  * DCIO Enums
11493  *******************************************************/
11494 
11495 /*
11496  * DCIO_DC_GENERICA_SEL enum
11497  */
11498 
11499 typedef enum DCIO_DC_GENERICA_SEL {
11500 DCIO_GENERICA_SEL_DACA_STEREOSYNC        = 0x00000000,
11501 DCIO_GENERICA_SEL_STEREOSYNC             = 0x00000001,
11502 DCIO_GENERICA_SEL_DACA_PIXCLK            = 0x00000002,
11503 DCIO_GENERICA_SEL_DACB_PIXCLK            = 0x00000003,
11504 DCIO_GENERICA_SEL_DVOA_CTL3              = 0x00000004,
11505 DCIO_GENERICA_SEL_P1_PLLCLK              = 0x00000005,
11506 DCIO_GENERICA_SEL_P2_PLLCLK              = 0x00000006,
11507 DCIO_GENERICA_SEL_DVOA_STEREOSYNC        = 0x00000007,
11508 DCIO_GENERICA_SEL_DACA_FIELD_NUMBER      = 0x00000008,
11509 DCIO_GENERICA_SEL_DACB_FIELD_NUMBER      = 0x00000009,
11510 DCIO_GENERICA_SEL_GENERICA_DCCG          = 0x0000000a,
11511 DCIO_GENERICA_SEL_SYNCEN                 = 0x0000000b,
11512 DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
11513 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
11514 DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
11515 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
11516 DCIO_GENERICA_SEL_GENERICA_DPRX          = 0x00000010,
11517 DCIO_GENERICA_SEL_GENERICB_DPRX          = 0x00000011,
11518 } DCIO_DC_GENERICA_SEL;
11519 
11520 /*
11521  * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
11522  */
11523 
11524 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
11525 DCIO_UNIPHYA_TEST_REFDIV_CLK             = 0x00000000,
11526 DCIO_UNIPHYB_TEST_REFDIV_CLK             = 0x00000001,
11527 DCIO_UNIPHYC_TEST_REFDIV_CLK             = 0x00000002,
11528 DCIO_UNIPHYD_TEST_REFDIV_CLK             = 0x00000003,
11529 DCIO_UNIPHYE_TEST_REFDIV_CLK             = 0x00000004,
11530 DCIO_UNIPHYF_TEST_REFDIV_CLK             = 0x00000005,
11531 DCIO_UNIPHYG_TEST_REFDIV_CLK             = 0x00000006,
11532 DCIO_UNIPHYLPA_TEST_REFDIV_CLK           = 0x00000007,
11533 DCIO_UNIPHYLPB_TEST_REFDIV_CLK           = 0x00000008,
11534 } DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
11535 
11536 /*
11537  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
11538  */
11539 
11540 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
11541 DCIO_UNIPHYA_FBDIV_CLK                   = 0x00000000,
11542 DCIO_UNIPHYB_FBDIV_CLK                   = 0x00000001,
11543 DCIO_UNIPHYC_FBDIV_CLK                   = 0x00000002,
11544 DCIO_UNIPHYD_FBDIV_CLK                   = 0x00000003,
11545 DCIO_UNIPHYE_FBDIV_CLK                   = 0x00000004,
11546 DCIO_UNIPHYF_FBDIV_CLK                   = 0x00000005,
11547 DCIO_UNIPHYG_FBDIV_CLK                   = 0x00000006,
11548 DCIO_UNIPHYLPA_FBDIV_CLK                 = 0x00000007,
11549 DCIO_UNIPHYLPB_FBDIV_CLK                 = 0x00000008,
11550 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
11551 
11552 /*
11553  * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
11554  */
11555 
11556 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
11557 DCIO_UNIPHYA_FBDIV_SSC_CLK               = 0x00000000,
11558 DCIO_UNIPHYB_FBDIV_SSC_CLK               = 0x00000001,
11559 DCIO_UNIPHYC_FBDIV_SSC_CLK               = 0x00000002,
11560 DCIO_UNIPHYD_FBDIV_SSC_CLK               = 0x00000003,
11561 DCIO_UNIPHYE_FBDIV_SSC_CLK               = 0x00000004,
11562 DCIO_UNIPHYF_FBDIV_SSC_CLK               = 0x00000005,
11563 DCIO_UNIPHYG_FBDIV_SSC_CLK               = 0x00000006,
11564 DCIO_UNIPHYLPA_FBDIV_SSC_CLK             = 0x00000007,
11565 DCIO_UNIPHYLPB_FBDIV_SSC_CLK             = 0x00000008,
11566 } DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
11567 
11568 /*
11569  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
11570  */
11571 
11572 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
11573 DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2         = 0x00000000,
11574 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2         = 0x00000001,
11575 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2         = 0x00000002,
11576 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2         = 0x00000003,
11577 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2         = 0x00000004,
11578 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2         = 0x00000005,
11579 DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2         = 0x00000006,
11580 DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2       = 0x00000007,
11581 DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2       = 0x00000008,
11582 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
11583 
11584 /*
11585  * DCIO_DC_GENERICB_SEL enum
11586  */
11587 
11588 typedef enum DCIO_DC_GENERICB_SEL {
11589 DCIO_GENERICB_SEL_DACA_STEREOSYNC        = 0x00000000,
11590 DCIO_GENERICB_SEL_STEREOSYNC             = 0x00000001,
11591 DCIO_GENERICB_SEL_DACA_PIXCLK            = 0x00000002,
11592 DCIO_GENERICB_SEL_DACB_PIXCLK            = 0x00000003,
11593 DCIO_GENERICB_SEL_DVOA_CTL3              = 0x00000004,
11594 DCIO_GENERICB_SEL_P1_PLLCLK              = 0x00000005,
11595 DCIO_GENERICB_SEL_P2_PLLCLK              = 0x00000006,
11596 DCIO_GENERICB_SEL_DVOA_STEREOSYNC        = 0x00000007,
11597 DCIO_GENERICB_SEL_DACA_FIELD_NUMBER      = 0x00000008,
11598 DCIO_GENERICB_SEL_DACB_FIELD_NUMBER      = 0x00000009,
11599 DCIO_GENERICB_SEL_GENERICB_DCCG          = 0x0000000a,
11600 DCIO_GENERICB_SEL_SYNCEN                 = 0x0000000b,
11601 DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
11602 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
11603 DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
11604 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
11605 } DCIO_DC_GENERICB_SEL;
11606 
11607 /*
11608  * DCIO_DC_PAD_EXTERN_SIG_SEL enum
11609  */
11610 
11611 typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
11612 DCIO_DC_PAD_EXTERN_SIG_SEL_MVP           = 0x00000000,
11613 DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA        = 0x00000001,
11614 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK     = 0x00000002,
11615 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC   = 0x00000003,
11616 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA      = 0x00000004,
11617 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB      = 0x00000005,
11618 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC      = 0x00000006,
11619 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1          = 0x00000007,
11620 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2          = 0x00000008,
11621 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK       = 0x00000009,
11622 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA      = 0x0000000a,
11623 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK       = 0x0000000b,
11624 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA      = 0x0000000c,
11625 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1         = 0x0000000d,
11626 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0         = 0x0000000e,
11627 DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL        = 0x0000000f,
11628 } DCIO_DC_PAD_EXTERN_SIG_SEL;
11629 
11630 /*
11631  * DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum
11632  */
11633 
11634 typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
11635 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA         = 0x00000000,
11636 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE  = 0x00000001,
11637 DCIO_MVP_PIXEL_SRC_STATUS_CRTC           = 0x00000002,
11638 DCIO_MVP_PIXEL_SRC_STATUS_LB             = 0x00000003,
11639 } DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
11640 
11641 /*
11642  * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
11643  */
11644 
11645 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
11646 DCIO_HSYNCA_OUTPUT_SEL_DISABLE           = 0x00000000,
11647 DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,
11648 DCIO_HSYNCA_OUTPUT_SEL_PPLL2             = 0x00000002,
11649 DCIO_HSYNCA_OUTPUT_SEL_RESERVED          = 0x00000003,
11650 } DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
11651 
11652 /*
11653  * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
11654  */
11655 
11656 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
11657 DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE        = 0x00000000,
11658 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1          = 0x00000001,
11659 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,
11660 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3  = 0x00000003,
11661 } DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
11662 
11663 /*
11664  * DCIO_DC_GPIO_VIP_DEBUG enum
11665  */
11666 
11667 typedef enum DCIO_DC_GPIO_VIP_DEBUG {
11668 DCIO_DC_GPIO_VIP_DEBUG_NORMAL            = 0x00000000,
11669 DCIO_DC_GPIO_VIP_DEBUG_CG_BIG            = 0x00000001,
11670 } DCIO_DC_GPIO_VIP_DEBUG;
11671 
11672 /*
11673  * DCIO_DC_GPIO_MACRO_DEBUG enum
11674  */
11675 
11676 typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
11677 DCIO_DC_GPIO_MACRO_DEBUG_NORMAL          = 0x00000000,
11678 DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF        = 0x00000001,
11679 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2  = 0x00000002,
11680 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3  = 0x00000003,
11681 } DCIO_DC_GPIO_MACRO_DEBUG;
11682 
11683 /*
11684  * DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum
11685  */
11686 
11687 typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
11688 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL  = 0x00000000,
11689 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP  = 0x00000001,
11690 } DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
11691 
11692 /*
11693  * DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum
11694  */
11695 
11696 typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
11697 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS    = 0x00000000,
11698 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE    = 0x00000001,
11699 } DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
11700 
11701 /*
11702  * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
11703  */
11704 
11705 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
11706 DCIO_DPRX_LOOPBACK_ENABLE_NORMAL         = 0x00000000,
11707 DCIO_DPRX_LOOPBACK_ENABLE_LOOP           = 0x00000001,
11708 } DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
11709 
11710 /*
11711  * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
11712  */
11713 
11714 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
11715 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
11716 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
11717 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
11718 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
11719 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
11720 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
11721 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
11722 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
11723 } DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
11724 
11725 /*
11726  * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
11727  */
11728 
11729 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
11730 DCIO_UNIPHY_CHANNEL_NO_INVERSION         = 0x00000000,
11731 DCIO_UNIPHY_CHANNEL_INVERTED             = 0x00000001,
11732 } DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
11733 
11734 /*
11735  * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
11736  */
11737 
11738 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
11739 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW  = 0x00000000,
11740 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW   = 0x00000001,
11741 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED  = 0x00000002,
11742 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED  = 0x00000003,
11743 } DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
11744 
11745 /*
11746  * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
11747  */
11748 
11749 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
11750 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0      = 0x00000000,
11751 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1      = 0x00000001,
11752 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2      = 0x00000002,
11753 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3      = 0x00000003,
11754 } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
11755 
11756 /*
11757  * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
11758  */
11759 
11760 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
11761 DCIO_VIP_MUX_EN_DVO                      = 0x00000000,
11762 DCIO_VIP_MUX_EN_VIP                      = 0x00000001,
11763 } DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
11764 
11765 /*
11766  * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
11767  */
11768 
11769 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
11770 DCIO_VIP_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
11771 DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
11772 } DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
11773 
11774 /*
11775  * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
11776  */
11777 
11778 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
11779 DCIO_DVO_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
11780 DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
11781 } DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
11782 
11783 /*
11784  * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
11785  */
11786 
11787 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
11788 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE  = 0x00000000,
11789 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE  = 0x00000001,
11790 } DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
11791 
11792 /*
11793  * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
11794  */
11795 
11796 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
11797 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF   = 0x00000000,
11798 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON    = 0x00000001,
11799 } DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
11800 
11801 /*
11802  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
11803  */
11804 
11805 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
11806 DCIO_LVTMA_SYNCEN_POL_NON_INVERT         = 0x00000000,
11807 DCIO_LVTMA_SYNCEN_POL_INVERT             = 0x00000001,
11808 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
11809 
11810 /*
11811  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
11812  */
11813 
11814 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
11815 DCIO_LVTMA_DIGON_OFF                     = 0x00000000,
11816 DCIO_LVTMA_DIGON_ON                      = 0x00000001,
11817 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
11818 
11819 /*
11820  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
11821  */
11822 
11823 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
11824 DCIO_LVTMA_DIGON_POL_NON_INVERT          = 0x00000000,
11825 DCIO_LVTMA_DIGON_POL_INVERT              = 0x00000001,
11826 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
11827 
11828 /*
11829  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
11830  */
11831 
11832 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
11833 DCIO_LVTMA_BLON_OFF                      = 0x00000000,
11834 DCIO_LVTMA_BLON_ON                       = 0x00000001,
11835 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
11836 
11837 /*
11838  * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
11839  */
11840 
11841 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
11842 DCIO_LVTMA_BLON_POL_NON_INVERT           = 0x00000000,
11843 DCIO_LVTMA_BLON_POL_INVERT               = 0x00000001,
11844 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
11845 
11846 /*
11847  * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
11848  */
11849 
11850 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
11851 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON      = 0x00000000,
11852 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE  = 0x00000001,
11853 } DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
11854 
11855 /*
11856  * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
11857  */
11858 
11859 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
11860 DCIO_BL_PWM_FRACTIONAL_DISABLE           = 0x00000000,
11861 DCIO_BL_PWM_FRACTIONAL_ENABLE            = 0x00000001,
11862 } DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
11863 
11864 /*
11865  * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
11866  */
11867 
11868 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
11869 DCIO_BL_PWM_DISABLE                      = 0x00000000,
11870 DCIO_BL_PWM_ENABLE                       = 0x00000001,
11871 } DCIO_BL_PWM_CNTL_BL_PWM_EN;
11872 
11873 /*
11874  * DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
11875  */
11876 
11877 typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
11878 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL  = 0x00000000,
11879 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1  = 0x00000001,
11880 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2  = 0x00000002,
11881 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3  = 0x00000003,
11882 } DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
11883 
11884 /*
11885  * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
11886  */
11887 
11888 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
11889 DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE      = 0x00000000,
11890 DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE       = 0x00000001,
11891 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
11892 
11893 /*
11894  * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
11895  */
11896 
11897 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
11898 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL  = 0x00000000,
11899 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM  = 0x00000001,
11900 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
11901 
11902 /*
11903  * DCIO_BL_PWM_GRP1_REG_LOCK enum
11904  */
11905 
11906 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
11907 DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE        = 0x00000000,
11908 DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE         = 0x00000001,
11909 } DCIO_BL_PWM_GRP1_REG_LOCK;
11910 
11911 /*
11912  * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
11913  */
11914 
11915 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
11916 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE  = 0x00000000,
11917 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE  = 0x00000001,
11918 } DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
11919 
11920 /*
11921  * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
11922  */
11923 
11924 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
11925 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1  = 0x00000000,
11926 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2  = 0x00000001,
11927 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3  = 0x00000002,
11928 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4  = 0x00000003,
11929 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5  = 0x00000004,
11930 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6  = 0x00000005,
11931 } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
11932 
11933 /*
11934  * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
11935  */
11936 
11937 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
11938 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM  = 0x00000000,
11939 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM  = 0x00000001,
11940 } DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
11941 
11942 /*
11943  * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
11944  */
11945 
11946 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
11947 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE  = 0x00000000,
11948 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE  = 0x00000001,
11949 } DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
11950 
11951 /*
11952  * DCIO_GSL_SEL enum
11953  */
11954 
11955 typedef enum DCIO_GSL_SEL {
11956 DCIO_GSL_SEL_GROUP_0                     = 0x00000000,
11957 DCIO_GSL_SEL_GROUP_1                     = 0x00000001,
11958 DCIO_GSL_SEL_GROUP_2                     = 0x00000002,
11959 } DCIO_GSL_SEL;
11960 
11961 /*
11962  * DCIO_GENLK_CLK_GSL_MASK enum
11963  */
11964 
11965 typedef enum DCIO_GENLK_CLK_GSL_MASK {
11966 DCIO_GENLK_CLK_GSL_MASK_NO               = 0x00000000,
11967 DCIO_GENLK_CLK_GSL_MASK_TIMING           = 0x00000001,
11968 DCIO_GENLK_CLK_GSL_MASK_STEREO           = 0x00000002,
11969 } DCIO_GENLK_CLK_GSL_MASK;
11970 
11971 /*
11972  * DCIO_GENLK_VSYNC_GSL_MASK enum
11973  */
11974 
11975 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
11976 DCIO_GENLK_VSYNC_GSL_MASK_NO             = 0x00000000,
11977 DCIO_GENLK_VSYNC_GSL_MASK_TIMING         = 0x00000001,
11978 DCIO_GENLK_VSYNC_GSL_MASK_STEREO         = 0x00000002,
11979 } DCIO_GENLK_VSYNC_GSL_MASK;
11980 
11981 /*
11982  * DCIO_SWAPLOCK_A_GSL_MASK enum
11983  */
11984 
11985 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
11986 DCIO_SWAPLOCK_A_GSL_MASK_NO              = 0x00000000,
11987 DCIO_SWAPLOCK_A_GSL_MASK_TIMING          = 0x00000001,
11988 DCIO_SWAPLOCK_A_GSL_MASK_STEREO          = 0x00000002,
11989 } DCIO_SWAPLOCK_A_GSL_MASK;
11990 
11991 /*
11992  * DCIO_SWAPLOCK_B_GSL_MASK enum
11993  */
11994 
11995 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
11996 DCIO_SWAPLOCK_B_GSL_MASK_NO              = 0x00000000,
11997 DCIO_SWAPLOCK_B_GSL_MASK_TIMING          = 0x00000001,
11998 DCIO_SWAPLOCK_B_GSL_MASK_STEREO          = 0x00000002,
11999 } DCIO_SWAPLOCK_B_GSL_MASK;
12000 
12001 /*
12002  * DCIO_GSL_VSYNC_SEL enum
12003  */
12004 
12005 typedef enum DCIO_GSL_VSYNC_SEL {
12006 DCIO_GSL_VSYNC_SEL_PIPE0                 = 0x00000000,
12007 DCIO_GSL_VSYNC_SEL_PIPE1                 = 0x00000001,
12008 DCIO_GSL_VSYNC_SEL_PIPE2                 = 0x00000002,
12009 DCIO_GSL_VSYNC_SEL_PIPE3                 = 0x00000003,
12010 DCIO_GSL_VSYNC_SEL_PIPE4                 = 0x00000004,
12011 DCIO_GSL_VSYNC_SEL_PIPE5                 = 0x00000005,
12012 } DCIO_GSL_VSYNC_SEL;
12013 
12014 /*
12015  * DCIO_GSL0_TIMING_SYNC_SEL enum
12016  */
12017 
12018 typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
12019 DCIO_GSL0_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12020 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12021 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12022 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12023 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12024 } DCIO_GSL0_TIMING_SYNC_SEL;
12025 
12026 /*
12027  * DCIO_GSL0_GLOBAL_UNLOCK_SEL enum
12028  */
12029 
12030 typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
12031 DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12032 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12033 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12034 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12035 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12036 } DCIO_GSL0_GLOBAL_UNLOCK_SEL;
12037 
12038 /*
12039  * DCIO_GSL1_TIMING_SYNC_SEL enum
12040  */
12041 
12042 typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
12043 DCIO_GSL1_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12044 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12045 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12046 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12047 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12048 } DCIO_GSL1_TIMING_SYNC_SEL;
12049 
12050 /*
12051  * DCIO_GSL1_GLOBAL_UNLOCK_SEL enum
12052  */
12053 
12054 typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
12055 DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12056 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12057 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12058 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12059 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12060 } DCIO_GSL1_GLOBAL_UNLOCK_SEL;
12061 
12062 /*
12063  * DCIO_GSL2_TIMING_SYNC_SEL enum
12064  */
12065 
12066 typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
12067 DCIO_GSL2_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12068 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12069 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12070 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12071 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12072 } DCIO_GSL2_TIMING_SYNC_SEL;
12073 
12074 /*
12075  * DCIO_GSL2_GLOBAL_UNLOCK_SEL enum
12076  */
12077 
12078 typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
12079 DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12080 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12081 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12082 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12083 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12084 } DCIO_GSL2_GLOBAL_UNLOCK_SEL;
12085 
12086 /*
12087  * DCIO_DC_GPU_TIMER_START_POSITION enum
12088  */
12089 
12090 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
12091 DCIO_GPU_TIMER_START_0_END_27            = 0x00000000,
12092 DCIO_GPU_TIMER_START_1_END_28            = 0x00000001,
12093 DCIO_GPU_TIMER_START_2_END_29            = 0x00000002,
12094 DCIO_GPU_TIMER_START_3_END_30            = 0x00000003,
12095 DCIO_GPU_TIMER_START_4_END_31            = 0x00000004,
12096 DCIO_GPU_TIMER_START_6_END_33            = 0x00000005,
12097 DCIO_GPU_TIMER_START_8_END_35            = 0x00000006,
12098 DCIO_GPU_TIMER_START_10_END_37           = 0x00000007,
12099 } DCIO_DC_GPU_TIMER_START_POSITION;
12100 
12101 /*
12102  * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
12103  */
12104 
12105 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
12106 DCIO_TEST_CLK_SEL_DISPCLK                = 0x00000000,
12107 DCIO_TEST_CLK_SEL_GATED_DISPCLK          = 0x00000001,
12108 DCIO_TEST_CLK_SEL_SCLK                   = 0x00000002,
12109 } DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
12110 
12111 /*
12112  * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
12113  */
12114 
12115 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
12116 DCIO_DISPCLK_R_DCIO_GATE_DISABLE         = 0x00000000,
12117 DCIO_DISPCLK_R_DCIO_GATE_ENABLE          = 0x00000001,
12118 } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
12119 
12120 /*
12121  * DCIO_DCO_DCFE_EXT_VSYNC_MUX enum
12122  */
12123 
12124 typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
12125 DCIO_EXT_VSYNC_MUX_SWAPLOCKB             = 0x00000000,
12126 DCIO_EXT_VSYNC_MUX_CRTC0                 = 0x00000001,
12127 DCIO_EXT_VSYNC_MUX_CRTC1                 = 0x00000002,
12128 DCIO_EXT_VSYNC_MUX_CRTC2                 = 0x00000003,
12129 DCIO_EXT_VSYNC_MUX_CRTC3                 = 0x00000004,
12130 DCIO_EXT_VSYNC_MUX_CRTC4                 = 0x00000005,
12131 DCIO_EXT_VSYNC_MUX_CRTC5                 = 0x00000006,
12132 DCIO_EXT_VSYNC_MUX_GENERICB              = 0x00000007,
12133 } DCIO_DCO_DCFE_EXT_VSYNC_MUX;
12134 
12135 /*
12136  * DCIO_DCO_EXT_VSYNC_MASK enum
12137  */
12138 
12139 typedef enum DCIO_DCO_EXT_VSYNC_MASK {
12140 DCIO_EXT_VSYNC_MASK_NONE                 = 0x00000000,
12141 DCIO_EXT_VSYNC_MASK_PIPE0                = 0x00000001,
12142 DCIO_EXT_VSYNC_MASK_PIPE1                = 0x00000002,
12143 DCIO_EXT_VSYNC_MASK_PIPE2                = 0x00000003,
12144 DCIO_EXT_VSYNC_MASK_PIPE3                = 0x00000004,
12145 DCIO_EXT_VSYNC_MASK_PIPE4                = 0x00000005,
12146 DCIO_EXT_VSYNC_MASK_PIPE5                = 0x00000006,
12147 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE       = 0x00000007,
12148 } DCIO_DCO_EXT_VSYNC_MASK;
12149 
12150 /*
12151  * DCIO_DSYNC_SOFT_RESET enum
12152  */
12153 
12154 typedef enum DCIO_DSYNC_SOFT_RESET {
12155 DCIO_DSYNC_SOFT_RESET_DEASSERT           = 0x00000000,
12156 DCIO_DSYNC_SOFT_RESET_ASSERT             = 0x00000001,
12157 } DCIO_DSYNC_SOFT_RESET;
12158 
12159 /*
12160  * DCIO_DACA_SOFT_RESET enum
12161  */
12162 
12163 typedef enum DCIO_DACA_SOFT_RESET {
12164 DCIO_DACA_SOFT_RESET_DEASSERT            = 0x00000000,
12165 DCIO_DACA_SOFT_RESET_ASSERT              = 0x00000001,
12166 } DCIO_DACA_SOFT_RESET;
12167 
12168 /*
12169  * DCIO_DCRXPHY_SOFT_RESET enum
12170  */
12171 
12172 typedef enum DCIO_DCRXPHY_SOFT_RESET {
12173 DCIO_DCRXPHY_SOFT_RESET_DEASSERT         = 0x00000000,
12174 DCIO_DCRXPHY_SOFT_RESET_ASSERT           = 0x00000001,
12175 } DCIO_DCRXPHY_SOFT_RESET;
12176 
12177 /*
12178  * DCIO_DPHY_LANE_SEL enum
12179  */
12180 
12181 typedef enum DCIO_DPHY_LANE_SEL {
12182 DCIO_DPHY_LANE_SEL_LANE0                 = 0x00000000,
12183 DCIO_DPHY_LANE_SEL_LANE1                 = 0x00000001,
12184 DCIO_DPHY_LANE_SEL_LANE2                 = 0x00000002,
12185 DCIO_DPHY_LANE_SEL_LANE3                 = 0x00000003,
12186 } DCIO_DPHY_LANE_SEL;
12187 
12188 /*
12189  * DCIO_DPCS_INTERRUPT_TYPE enum
12190  */
12191 
12192 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
12193 DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED     = 0x00000000,
12194 DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED     = 0x00000001,
12195 } DCIO_DPCS_INTERRUPT_TYPE;
12196 
12197 /*
12198  * DCIO_DPCS_INTERRUPT_MASK enum
12199  */
12200 
12201 typedef enum DCIO_DPCS_INTERRUPT_MASK {
12202 DCIO_DPCS_INTERRUPT_DISABLE              = 0x00000000,
12203 DCIO_DPCS_INTERRUPT_ENABLE               = 0x00000001,
12204 } DCIO_DPCS_INTERRUPT_MASK;
12205 
12206 /*
12207  * DCIO_DC_GPU_TIMER_READ_SELECT enum
12208  */
12209 
12210 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
12211 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE  = 0x00000000,
12212 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE  = 0x00000001,
12213 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE  = 0x00000002,
12214 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE  = 0x00000003,
12215 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE  = 0x00000004,
12216 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE  = 0x00000005,
12217 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE  = 0x00000006,
12218 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE  = 0x00000007,
12219 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE  = 0x00000008,
12220 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE  = 0x00000009,
12221 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE  = 0x0000000a,
12222 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE  = 0x0000000b,
12223 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP  = 0x0000000c,
12224 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP  = 0x0000000d,
12225 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP  = 0x0000000e,
12226 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP  = 0x0000000f,
12227 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP  = 0x00000010,
12228 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP  = 0x00000011,
12229 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP  = 0x00000012,
12230 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP  = 0x00000013,
12231 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP  = 0x00000014,
12232 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP  = 0x00000015,
12233 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP  = 0x00000016,
12234 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP  = 0x00000017,
12235 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM  = 0x00000018,
12236 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM  = 0x00000019,
12237 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM  = 0x0000001a,
12238 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM  = 0x0000001b,
12239 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM  = 0x0000001c,
12240 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM  = 0x0000001d,
12241 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM  = 0x0000001e,
12242 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM  = 0x0000001f,
12243 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM  = 0x00000020,
12244 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM  = 0x00000021,
12245 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM  = 0x00000022,
12246 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM  = 0x00000023,
12247 } DCIO_DC_GPU_TIMER_READ_SELECT;
12248 
12249 /*
12250  * DCIO_IMPCAL_STEP_DELAY enum
12251  */
12252 
12253 typedef enum DCIO_IMPCAL_STEP_DELAY {
12254 DCIO_IMPCAL_STEP_DELAY_1us               = 0x00000000,
12255 DCIO_IMPCAL_STEP_DELAY_2us               = 0x00000001,
12256 DCIO_IMPCAL_STEP_DELAY_3us               = 0x00000002,
12257 DCIO_IMPCAL_STEP_DELAY_4us               = 0x00000003,
12258 DCIO_IMPCAL_STEP_DELAY_5us               = 0x00000004,
12259 DCIO_IMPCAL_STEP_DELAY_6us               = 0x00000005,
12260 DCIO_IMPCAL_STEP_DELAY_7us               = 0x00000006,
12261 DCIO_IMPCAL_STEP_DELAY_8us               = 0x00000007,
12262 DCIO_IMPCAL_STEP_DELAY_9us               = 0x00000008,
12263 DCIO_IMPCAL_STEP_DELAY_10us              = 0x00000009,
12264 DCIO_IMPCAL_STEP_DELAY_11us              = 0x0000000a,
12265 DCIO_IMPCAL_STEP_DELAY_12us              = 0x0000000b,
12266 DCIO_IMPCAL_STEP_DELAY_13us              = 0x0000000c,
12267 DCIO_IMPCAL_STEP_DELAY_14us              = 0x0000000d,
12268 DCIO_IMPCAL_STEP_DELAY_15us              = 0x0000000e,
12269 DCIO_IMPCAL_STEP_DELAY_16us              = 0x0000000f,
12270 } DCIO_IMPCAL_STEP_DELAY;
12271 
12272 /*
12273  * DCIO_UNIPHY_IMPCAL_SEL enum
12274  */
12275 
12276 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
12277 DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE       = 0x00000000,
12278 DCIO_UNIPHY_IMPCAL_SEL_BINARY            = 0x00000001,
12279 } DCIO_UNIPHY_IMPCAL_SEL;
12280 
12281 /*
12282  * DCIO_DBG_ASYNC_BLOCK_SEL enum
12283  */
12284 
12285 typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
12286 DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE        = 0x00000000,
12287 DCIO_DBG_ASYNC_BLOCK_SEL_DCCG            = 0x00000001,
12288 DCIO_DBG_ASYNC_BLOCK_SEL_DCIO            = 0x00000002,
12289 DCIO_DBG_ASYNC_BLOCK_SEL_DCO             = 0x00000003,
12290 } DCIO_DBG_ASYNC_BLOCK_SEL;
12291 
12292 /*
12293  * DCIO_DBG_ASYNC_4BIT_SEL enum
12294  */
12295 
12296 typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
12297 DCIO_DBG_ASYNC_4BIT_SEL_3TO0             = 0x00000000,
12298 DCIO_DBG_ASYNC_4BIT_SEL_7TO4             = 0x00000001,
12299 DCIO_DBG_ASYNC_4BIT_SEL_11TO8            = 0x00000002,
12300 DCIO_DBG_ASYNC_4BIT_SEL_15TO12           = 0x00000003,
12301 DCIO_DBG_ASYNC_4BIT_SEL_19TO16           = 0x00000004,
12302 DCIO_DBG_ASYNC_4BIT_SEL_23TO20           = 0x00000005,
12303 DCIO_DBG_ASYNC_4BIT_SEL_27TO24           = 0x00000006,
12304 DCIO_DBG_ASYNC_4BIT_SEL_31TO28           = 0x00000007,
12305 } DCIO_DBG_ASYNC_4BIT_SEL;
12306 
12307 /*******************************************************
12308  * AOUT Enums
12309  *******************************************************/
12310 
12311 /*
12312  * AOUT_EN enum
12313  */
12314 
12315 typedef enum AOUT_EN {
12316 AOUT_DISABLE                             = 0x00000000,
12317 AOUT_ENABLE                              = 0x00000001,
12318 } AOUT_EN;
12319 
12320 /*
12321  * AOUT_FIFO_START_ADDR enum
12322  */
12323 
12324 typedef enum AOUT_FIFO_START_ADDR {
12325 AOUT_FIFO_START_ADDR_2                   = 0x00000000,
12326 AOUT_FIFO_START_ADDR_3                   = 0x00000001,
12327 } AOUT_FIFO_START_ADDR;
12328 
12329 /*
12330  * AOUT_CRC_TEST_EN enum
12331  */
12332 
12333 typedef enum AOUT_CRC_TEST_EN {
12334 AOUT_CRC_DISABLE                         = 0x00000000,
12335 AOUT_CRC_ENABLE                          = 0x00000001,
12336 } AOUT_CRC_TEST_EN;
12337 
12338 /*
12339  * AOUT_CRC_SOFT_RESET enum
12340  */
12341 
12342 typedef enum AOUT_CRC_SOFT_RESET {
12343 AOUT_CRC_NO_RESET                        = 0x00000000,
12344 AOUT_CRC_RESET                           = 0x00000001,
12345 } AOUT_CRC_SOFT_RESET;
12346 
12347 /*
12348  * AOUT_CRC_CONT_EN enum
12349  */
12350 
12351 typedef enum AOUT_CRC_CONT_EN {
12352 AOUT_CRC_ONE_SHOT                        = 0x00000000,
12353 AOUT_CRC_CONT                            = 0x00000001,
12354 } AOUT_CRC_CONT_EN;
12355 
12356 /*
12357  * I2S_WORD_SIZE enum
12358  */
12359 
12360 typedef enum I2S_WORD_SIZE {
12361 I2S_WORD_SIZE_32                         = 0x00000000,
12362 I2S_WORD_SIZE_16                         = 0x00000001,
12363 } I2S_WORD_SIZE;
12364 
12365 /*
12366  * I2S_SAMPLE_ALIGNMENT enum
12367  */
12368 
12369 typedef enum I2S_SAMPLE_ALIGNMENT {
12370 I2S_SAMPLE_LEFT_ALIGNED                  = 0x00000000,
12371 I2S_SAMPLE_RIGHT_ALIGNED                 = 0x00000001,
12372 } I2S_SAMPLE_ALIGNMENT;
12373 
12374 /*
12375  * I2S_SAMPLE_BIT_ORDER enum
12376  */
12377 
12378 typedef enum I2S_SAMPLE_BIT_ORDER {
12379 I2S_SAMPLE_BIT_ORDER_MSB                 = 0x00000000,
12380 I2S_SAMPLE_BIT_ORDER_LSB                 = 0x00000001,
12381 } I2S_SAMPLE_BIT_ORDER;
12382 
12383 /*
12384  * I2S_LRCLK_POLARITY enum
12385  */
12386 
12387 typedef enum I2S_LRCLK_POLARITY {
12388 I2S_LRCLK_LOW_LEFT                       = 0x00000000,
12389 I2S_LRCLK_HIGH_LEFT                      = 0x00000001,
12390 } I2S_LRCLK_POLARITY;
12391 
12392 /*
12393  * I2S_WORD_ALIGNMENT enum
12394  */
12395 
12396 typedef enum I2S_WORD_ALIGNMENT {
12397 I2S_WORD_ALTERNATE_ALIGNMENT             = 0x00000000,
12398 I2S_WORD_I2S_ALIGNMENT                   = 0x00000001,
12399 } I2S_WORD_ALIGNMENT;
12400 
12401 /*
12402  * SPDIF_INVERT_EN enum
12403  */
12404 
12405 typedef enum SPDIF_INVERT_EN {
12406 SPDIF_INVERT_DISABLE                     = 0x00000000,
12407 SPDIF_INVERT_ENABLE                      = 0x00000001,
12408 } SPDIF_INVERT_EN;
12409 
12410 /*******************************************************
12411  * DCO Enums
12412  *******************************************************/
12413 
12414 /*
12415  * DPDBG_EN enum
12416  */
12417 
12418 typedef enum DPDBG_EN {
12419 DPDBG_DISABLE                            = 0x00000000,
12420 DPDBG_ENABLE                             = 0x00000001,
12421 } DPDBG_EN;
12422 
12423 /*
12424  * DPDBG_INPUT_EN enum
12425  */
12426 
12427 typedef enum DPDBG_INPUT_EN {
12428 DPDBG_INPUT_DISABLE                      = 0x00000000,
12429 DPDBG_INPUT_ENABLE                       = 0x00000001,
12430 } DPDBG_INPUT_EN;
12431 
12432 /*
12433  * DPDBG_ERROR_DETECTION_MODE enum
12434  */
12435 
12436 typedef enum DPDBG_ERROR_DETECTION_MODE {
12437 DPDBG_ERROR_DETECTION_MODE_CSC           = 0x00000000,
12438 DPDBG_ERROR_DETECTION_MODE_RS_ENCODING   = 0x00000001,
12439 } DPDBG_ERROR_DETECTION_MODE;
12440 
12441 /*
12442  * DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum
12443  */
12444 
12445 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
12446 DPDBG_FIFO_OVERFLOW_INT_DISABLE          = 0x00000000,
12447 DPDBG_FIFO_OVERFLOW_INT_ENABLE           = 0x00000001,
12448 } DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
12449 
12450 /*
12451  * DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum
12452  */
12453 
12454 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
12455 DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED      = 0x00000000,
12456 DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED      = 0x00000001,
12457 } DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
12458 
12459 /*
12460  * DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum
12461  */
12462 
12463 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
12464 DPDBG_FIFO_OVERFLOW_INT_NO_ACK           = 0x00000000,
12465 DPDBG_FIFO_OVERFLOW_INT_CLEAR            = 0x00000001,
12466 } DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
12467 
12468 /*
12469  * PM_ASSERT_RESET enum
12470  */
12471 
12472 typedef enum PM_ASSERT_RESET {
12473 PM_ASSERT_RESET_0                        = 0x00000000,
12474 PM_ASSERT_RESET_1                        = 0x00000001,
12475 } PM_ASSERT_RESET;
12476 
12477 /*
12478  * DAC_MUX_SELECT enum
12479  */
12480 
12481 typedef enum DAC_MUX_SELECT {
12482 DAC_MUX_SELECT_DACA                      = 0x00000000,
12483 DAC_MUX_SELECT_DACB                      = 0x00000001,
12484 } DAC_MUX_SELECT;
12485 
12486 /*
12487  * TMDS_DVO_MUX_SELECT enum
12488  */
12489 
12490 typedef enum TMDS_DVO_MUX_SELECT {
12491 TMDS_DVO_MUX_SELECT_B                    = 0x00000000,
12492 TMDS_DVO_MUX_SELECT_G                    = 0x00000001,
12493 TMDS_DVO_MUX_SELECT_R                    = 0x00000002,
12494 TMDS_DVO_MUX_SELECT_RESERVED             = 0x00000003,
12495 } TMDS_DVO_MUX_SELECT;
12496 
12497 /*
12498  * DACA_SOFT_RESET enum
12499  */
12500 
12501 typedef enum DACA_SOFT_RESET {
12502 DACA_SOFT_RESET_0                        = 0x00000000,
12503 DACA_SOFT_RESET_1                        = 0x00000001,
12504 } DACA_SOFT_RESET;
12505 
12506 /*
12507  * I2S0_SPDIF0_SOFT_RESET enum
12508  */
12509 
12510 typedef enum I2S0_SPDIF0_SOFT_RESET {
12511 I2S0_SPDIF0_SOFT_RESET_0                 = 0x00000000,
12512 I2S0_SPDIF0_SOFT_RESET_1                 = 0x00000001,
12513 } I2S0_SPDIF0_SOFT_RESET;
12514 
12515 /*
12516  * I2S1_SOFT_RESET enum
12517  */
12518 
12519 typedef enum I2S1_SOFT_RESET {
12520 I2S1_SOFT_RESET_0                        = 0x00000000,
12521 I2S1_SOFT_RESET_1                        = 0x00000001,
12522 } I2S1_SOFT_RESET;
12523 
12524 /*
12525  * SPDIF1_SOFT_RESET enum
12526  */
12527 
12528 typedef enum SPDIF1_SOFT_RESET {
12529 SPDIF1_SOFT_RESET_0                      = 0x00000000,
12530 SPDIF1_SOFT_RESET_1                      = 0x00000001,
12531 } SPDIF1_SOFT_RESET;
12532 
12533 /*
12534  * DB_CLK_SOFT_RESET enum
12535  */
12536 
12537 typedef enum DB_CLK_SOFT_RESET {
12538 DB_CLK_SOFT_RESET_0                      = 0x00000000,
12539 DB_CLK_SOFT_RESET_1                      = 0x00000001,
12540 } DB_CLK_SOFT_RESET;
12541 
12542 /*
12543  * FMT0_SOFT_RESET enum
12544  */
12545 
12546 typedef enum FMT0_SOFT_RESET {
12547 FMT0_SOFT_RESET_0                        = 0x00000000,
12548 FMT0_SOFT_RESET_1                        = 0x00000001,
12549 } FMT0_SOFT_RESET;
12550 
12551 /*
12552  * FMT1_SOFT_RESET enum
12553  */
12554 
12555 typedef enum FMT1_SOFT_RESET {
12556 FMT1_SOFT_RESET_0                        = 0x00000000,
12557 FMT1_SOFT_RESET_1                        = 0x00000001,
12558 } FMT1_SOFT_RESET;
12559 
12560 /*
12561  * FMT2_SOFT_RESET enum
12562  */
12563 
12564 typedef enum FMT2_SOFT_RESET {
12565 FMT2_SOFT_RESET_0                        = 0x00000000,
12566 FMT2_SOFT_RESET_1                        = 0x00000001,
12567 } FMT2_SOFT_RESET;
12568 
12569 /*
12570  * FMT3_SOFT_RESET enum
12571  */
12572 
12573 typedef enum FMT3_SOFT_RESET {
12574 FMT3_SOFT_RESET_0                        = 0x00000000,
12575 FMT3_SOFT_RESET_1                        = 0x00000001,
12576 } FMT3_SOFT_RESET;
12577 
12578 /*
12579  * FMT4_SOFT_RESET enum
12580  */
12581 
12582 typedef enum FMT4_SOFT_RESET {
12583 FMT4_SOFT_RESET_0                        = 0x00000000,
12584 FMT4_SOFT_RESET_1                        = 0x00000001,
12585 } FMT4_SOFT_RESET;
12586 
12587 /*
12588  * FMT5_SOFT_RESET enum
12589  */
12590 
12591 typedef enum FMT5_SOFT_RESET {
12592 FMT5_SOFT_RESET_0                        = 0x00000000,
12593 FMT5_SOFT_RESET_1                        = 0x00000001,
12594 } FMT5_SOFT_RESET;
12595 
12596 /*
12597  * MVP_SOFT_RESET enum
12598  */
12599 
12600 typedef enum MVP_SOFT_RESET {
12601 MVP_SOFT_RESET_0                         = 0x00000000,
12602 MVP_SOFT_RESET_1                         = 0x00000001,
12603 } MVP_SOFT_RESET;
12604 
12605 /*
12606  * ABM_SOFT_RESET enum
12607  */
12608 
12609 typedef enum ABM_SOFT_RESET {
12610 ABM_SOFT_RESET_0                         = 0x00000000,
12611 ABM_SOFT_RESET_1                         = 0x00000001,
12612 } ABM_SOFT_RESET;
12613 
12614 /*
12615  * DVO_SOFT_RESET enum
12616  */
12617 
12618 typedef enum DVO_SOFT_RESET {
12619 DVO_SOFT_RESET_0                         = 0x00000000,
12620 DVO_SOFT_RESET_1                         = 0x00000001,
12621 } DVO_SOFT_RESET;
12622 
12623 /*
12624  * DIGA_FE_SOFT_RESET enum
12625  */
12626 
12627 typedef enum DIGA_FE_SOFT_RESET {
12628 DIGA_FE_SOFT_RESET_0                     = 0x00000000,
12629 DIGA_FE_SOFT_RESET_1                     = 0x00000001,
12630 } DIGA_FE_SOFT_RESET;
12631 
12632 /*
12633  * DIGA_BE_SOFT_RESET enum
12634  */
12635 
12636 typedef enum DIGA_BE_SOFT_RESET {
12637 DIGA_BE_SOFT_RESET_0                     = 0x00000000,
12638 DIGA_BE_SOFT_RESET_1                     = 0x00000001,
12639 } DIGA_BE_SOFT_RESET;
12640 
12641 /*
12642  * DIGB_FE_SOFT_RESET enum
12643  */
12644 
12645 typedef enum DIGB_FE_SOFT_RESET {
12646 DIGB_FE_SOFT_RESET_0                     = 0x00000000,
12647 DIGB_FE_SOFT_RESET_1                     = 0x00000001,
12648 } DIGB_FE_SOFT_RESET;
12649 
12650 /*
12651  * DIGB_BE_SOFT_RESET enum
12652  */
12653 
12654 typedef enum DIGB_BE_SOFT_RESET {
12655 DIGB_BE_SOFT_RESET_0                     = 0x00000000,
12656 DIGB_BE_SOFT_RESET_1                     = 0x00000001,
12657 } DIGB_BE_SOFT_RESET;
12658 
12659 /*
12660  * DIGC_FE_SOFT_RESET enum
12661  */
12662 
12663 typedef enum DIGC_FE_SOFT_RESET {
12664 DIGC_FE_SOFT_RESET_0                     = 0x00000000,
12665 DIGC_FE_SOFT_RESET_1                     = 0x00000001,
12666 } DIGC_FE_SOFT_RESET;
12667 
12668 /*
12669  * DIGC_BE_SOFT_RESET enum
12670  */
12671 
12672 typedef enum DIGC_BE_SOFT_RESET {
12673 DIGC_BE_SOFT_RESET_0                     = 0x00000000,
12674 DIGC_BE_SOFT_RESET_1                     = 0x00000001,
12675 } DIGC_BE_SOFT_RESET;
12676 
12677 /*
12678  * DIGD_FE_SOFT_RESET enum
12679  */
12680 
12681 typedef enum DIGD_FE_SOFT_RESET {
12682 DIGD_FE_SOFT_RESET_0                     = 0x00000000,
12683 DIGD_FE_SOFT_RESET_1                     = 0x00000001,
12684 } DIGD_FE_SOFT_RESET;
12685 
12686 /*
12687  * DIGD_BE_SOFT_RESET enum
12688  */
12689 
12690 typedef enum DIGD_BE_SOFT_RESET {
12691 DIGD_BE_SOFT_RESET_0                     = 0x00000000,
12692 DIGD_BE_SOFT_RESET_1                     = 0x00000001,
12693 } DIGD_BE_SOFT_RESET;
12694 
12695 /*
12696  * DIGE_FE_SOFT_RESET enum
12697  */
12698 
12699 typedef enum DIGE_FE_SOFT_RESET {
12700 DIGE_FE_SOFT_RESET_0                     = 0x00000000,
12701 DIGE_FE_SOFT_RESET_1                     = 0x00000001,
12702 } DIGE_FE_SOFT_RESET;
12703 
12704 /*
12705  * DIGE_BE_SOFT_RESET enum
12706  */
12707 
12708 typedef enum DIGE_BE_SOFT_RESET {
12709 DIGE_BE_SOFT_RESET_0                     = 0x00000000,
12710 DIGE_BE_SOFT_RESET_1                     = 0x00000001,
12711 } DIGE_BE_SOFT_RESET;
12712 
12713 /*
12714  * DIGF_FE_SOFT_RESET enum
12715  */
12716 
12717 typedef enum DIGF_FE_SOFT_RESET {
12718 DIGF_FE_SOFT_RESET_0                     = 0x00000000,
12719 DIGF_FE_SOFT_RESET_1                     = 0x00000001,
12720 } DIGF_FE_SOFT_RESET;
12721 
12722 /*
12723  * DIGF_BE_SOFT_RESET enum
12724  */
12725 
12726 typedef enum DIGF_BE_SOFT_RESET {
12727 DIGF_BE_SOFT_RESET_0                     = 0x00000000,
12728 DIGF_BE_SOFT_RESET_1                     = 0x00000001,
12729 } DIGF_BE_SOFT_RESET;
12730 
12731 /*
12732  * DIGG_FE_SOFT_RESET enum
12733  */
12734 
12735 typedef enum DIGG_FE_SOFT_RESET {
12736 DIGG_FE_SOFT_RESET_0                     = 0x00000000,
12737 DIGG_FE_SOFT_RESET_1                     = 0x00000001,
12738 } DIGG_FE_SOFT_RESET;
12739 
12740 /*
12741  * DIGG_BE_SOFT_RESET enum
12742  */
12743 
12744 typedef enum DIGG_BE_SOFT_RESET {
12745 DIGG_BE_SOFT_RESET_0                     = 0x00000000,
12746 DIGG_BE_SOFT_RESET_1                     = 0x00000001,
12747 } DIGG_BE_SOFT_RESET;
12748 
12749 /*
12750  * DPDBG_SOFT_RESET enum
12751  */
12752 
12753 typedef enum DPDBG_SOFT_RESET {
12754 DPDBG_SOFT_RESET_0                       = 0x00000000,
12755 DPDBG_SOFT_RESET_1                       = 0x00000001,
12756 } DPDBG_SOFT_RESET;
12757 
12758 /*
12759  * DIGLPA_FE_SOFT_RESET enum
12760  */
12761 
12762 typedef enum DIGLPA_FE_SOFT_RESET {
12763 DIGLPA_FE_SOFT_RESET_0                   = 0x00000000,
12764 DIGLPA_FE_SOFT_RESET_1                   = 0x00000001,
12765 } DIGLPA_FE_SOFT_RESET;
12766 
12767 /*
12768  * DIGLPA_BE_SOFT_RESET enum
12769  */
12770 
12771 typedef enum DIGLPA_BE_SOFT_RESET {
12772 DIGLPA_BE_SOFT_RESET_0                   = 0x00000000,
12773 DIGLPA_BE_SOFT_RESET_1                   = 0x00000001,
12774 } DIGLPA_BE_SOFT_RESET;
12775 
12776 /*
12777  * DIGLPB_FE_SOFT_RESET enum
12778  */
12779 
12780 typedef enum DIGLPB_FE_SOFT_RESET {
12781 DIGLPB_FE_SOFT_RESET_0                   = 0x00000000,
12782 DIGLPB_FE_SOFT_RESET_1                   = 0x00000001,
12783 } DIGLPB_FE_SOFT_RESET;
12784 
12785 /*
12786  * DIGLPB_BE_SOFT_RESET enum
12787  */
12788 
12789 typedef enum DIGLPB_BE_SOFT_RESET {
12790 DIGLPB_BE_SOFT_RESET_0                   = 0x00000000,
12791 DIGLPB_BE_SOFT_RESET_1                   = 0x00000001,
12792 } DIGLPB_BE_SOFT_RESET;
12793 
12794 /*
12795  * GENERICA_STEREOSYNC_SEL enum
12796  */
12797 
12798 typedef enum GENERICA_STEREOSYNC_SEL {
12799 GENERICA_STEREOSYNC_SEL_D1               = 0x00000000,
12800 GENERICA_STEREOSYNC_SEL_D2               = 0x00000001,
12801 GENERICA_STEREOSYNC_SEL_D3               = 0x00000002,
12802 GENERICA_STEREOSYNC_SEL_D4               = 0x00000003,
12803 GENERICA_STEREOSYNC_SEL_D5               = 0x00000004,
12804 GENERICA_STEREOSYNC_SEL_D6               = 0x00000005,
12805 GENERICA_STEREOSYNC_SEL_RESERVED         = 0x00000006,
12806 } GENERICA_STEREOSYNC_SEL;
12807 
12808 /*
12809  * GENERICB_STEREOSYNC_SEL enum
12810  */
12811 
12812 typedef enum GENERICB_STEREOSYNC_SEL {
12813 GENERICB_STEREOSYNC_SEL_D1               = 0x00000000,
12814 GENERICB_STEREOSYNC_SEL_D2               = 0x00000001,
12815 GENERICB_STEREOSYNC_SEL_D3               = 0x00000002,
12816 GENERICB_STEREOSYNC_SEL_D4               = 0x00000003,
12817 GENERICB_STEREOSYNC_SEL_D5               = 0x00000004,
12818 GENERICB_STEREOSYNC_SEL_D6               = 0x00000005,
12819 GENERICB_STEREOSYNC_SEL_RESERVED         = 0x00000006,
12820 } GENERICB_STEREOSYNC_SEL;
12821 
12822 /*
12823  * DCO_DBG_BLOCK_SEL enum
12824  */
12825 
12826 typedef enum DCO_DBG_BLOCK_SEL {
12827 DCO_DBG_BLOCK_SEL_DCO                    = 0x00000000,
12828 DCO_DBG_BLOCK_SEL_ABM                    = 0x00000001,
12829 DCO_DBG_BLOCK_SEL_DVO                    = 0x00000002,
12830 DCO_DBG_BLOCK_SEL_DAC                    = 0x00000003,
12831 DCO_DBG_BLOCK_SEL_MVP                    = 0x00000004,
12832 DCO_DBG_BLOCK_SEL_FMT0                   = 0x00000005,
12833 DCO_DBG_BLOCK_SEL_FMT1                   = 0x00000006,
12834 DCO_DBG_BLOCK_SEL_FMT2                   = 0x00000007,
12835 DCO_DBG_BLOCK_SEL_FMT3                   = 0x00000008,
12836 DCO_DBG_BLOCK_SEL_FMT4                   = 0x00000009,
12837 DCO_DBG_BLOCK_SEL_FMT5                   = 0x0000000a,
12838 DCO_DBG_BLOCK_SEL_DIGFE_A                = 0x0000000b,
12839 DCO_DBG_BLOCK_SEL_DIGFE_B                = 0x0000000c,
12840 DCO_DBG_BLOCK_SEL_DIGFE_C                = 0x0000000d,
12841 DCO_DBG_BLOCK_SEL_DIGFE_D                = 0x0000000e,
12842 DCO_DBG_BLOCK_SEL_DIGFE_E                = 0x0000000f,
12843 DCO_DBG_BLOCK_SEL_DIGFE_F                = 0x00000010,
12844 DCO_DBG_BLOCK_SEL_DIGFE_G                = 0x00000011,
12845 DCO_DBG_BLOCK_SEL_DIGA                   = 0x00000012,
12846 DCO_DBG_BLOCK_SEL_DIGB                   = 0x00000013,
12847 DCO_DBG_BLOCK_SEL_DIGC                   = 0x00000014,
12848 DCO_DBG_BLOCK_SEL_DIGD                   = 0x00000015,
12849 DCO_DBG_BLOCK_SEL_DIGE                   = 0x00000016,
12850 DCO_DBG_BLOCK_SEL_DIGF                   = 0x00000017,
12851 DCO_DBG_BLOCK_SEL_DIGG                   = 0x00000018,
12852 DCO_DBG_BLOCK_SEL_DPFE_A                 = 0x00000019,
12853 DCO_DBG_BLOCK_SEL_DPFE_B                 = 0x0000001a,
12854 DCO_DBG_BLOCK_SEL_DPFE_C                 = 0x0000001b,
12855 DCO_DBG_BLOCK_SEL_DPFE_D                 = 0x0000001c,
12856 DCO_DBG_BLOCK_SEL_DPFE_E                 = 0x0000001d,
12857 DCO_DBG_BLOCK_SEL_DPFE_F                 = 0x0000001e,
12858 DCO_DBG_BLOCK_SEL_DPFE_G                 = 0x0000001f,
12859 DCO_DBG_BLOCK_SEL_DPA                    = 0x00000020,
12860 DCO_DBG_BLOCK_SEL_DPB                    = 0x00000021,
12861 DCO_DBG_BLOCK_SEL_DPC                    = 0x00000022,
12862 DCO_DBG_BLOCK_SEL_DPD                    = 0x00000023,
12863 DCO_DBG_BLOCK_SEL_DPE                    = 0x00000024,
12864 DCO_DBG_BLOCK_SEL_DPF                    = 0x00000025,
12865 DCO_DBG_BLOCK_SEL_DPG                    = 0x00000026,
12866 DCO_DBG_BLOCK_SEL_AUX0                   = 0x00000027,
12867 DCO_DBG_BLOCK_SEL_AUX1                   = 0x00000028,
12868 DCO_DBG_BLOCK_SEL_AUX2                   = 0x00000029,
12869 DCO_DBG_BLOCK_SEL_AUX3                   = 0x0000002a,
12870 DCO_DBG_BLOCK_SEL_AUX4                   = 0x0000002b,
12871 DCO_DBG_BLOCK_SEL_AUX5                   = 0x0000002c,
12872 DCO_DBG_BLOCK_SEL_PERFMON_DCO            = 0x0000002d,
12873 DCO_DBG_BLOCK_SEL_AUDIO_OUT              = 0x0000002e,
12874 DCO_DBG_BLOCK_SEL_DIGLPFEA               = 0x0000002f,
12875 DCO_DBG_BLOCK_SEL_DIGLPFEB               = 0x00000030,
12876 DCO_DBG_BLOCK_SEL_DIGLPA                 = 0x00000031,
12877 DCO_DBG_BLOCK_SEL_DIGLPB                 = 0x00000032,
12878 DCO_DBG_BLOCK_SEL_DPLPFEA                = 0x00000033,
12879 DCO_DBG_BLOCK_SEL_DPLPFEB                = 0x00000034,
12880 DCO_DBG_BLOCK_SEL_DPLPA                  = 0x00000035,
12881 DCO_DBG_BLOCK_SEL_DPLPB                  = 0x00000036,
12882 } DCO_DBG_BLOCK_SEL;
12883 
12884 /*
12885  * DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum
12886  */
12887 
12888 typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
12889 DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL       = 0x00000000,
12890 DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE       = 0x00000001,
12891 } DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
12892 
12893 /*
12894  * FMT420_MEMORY_SOURCE_SEL enum
12895  */
12896 
12897 typedef enum FMT420_MEMORY_SOURCE_SEL {
12898 FMT420_MEMORY_SOURCE_SEL_FMT0            = 0x00000000,
12899 FMT420_MEMORY_SOURCE_SEL_FMT1            = 0x00000001,
12900 FMT420_MEMORY_SOURCE_SEL_FMT2            = 0x00000002,
12901 FMT420_MEMORY_SOURCE_SEL_FMT3            = 0x00000003,
12902 FMT420_MEMORY_SOURCE_SEL_FMT4            = 0x00000004,
12903 FMT420_MEMORY_SOURCE_SEL_FMT5            = 0x00000005,
12904 FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED    = 0x00000006,
12905 } FMT420_MEMORY_SOURCE_SEL;
12906 
12907 /*******************************************************
12908  * DOUT_I2C Enums
12909  *******************************************************/
12910 
12911 /*
12912  * DOUT_I2C_CONTROL_GO enum
12913  */
12914 
12915 typedef enum DOUT_I2C_CONTROL_GO {
12916 DOUT_I2C_CONTROL_STOP_TRANSFER           = 0x00000000,
12917 DOUT_I2C_CONTROL_START_TRANSFER          = 0x00000001,
12918 } DOUT_I2C_CONTROL_GO;
12919 
12920 /*
12921  * DOUT_I2C_CONTROL_SOFT_RESET enum
12922  */
12923 
12924 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
12925 DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
12926 DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER    = 0x00000001,
12927 } DOUT_I2C_CONTROL_SOFT_RESET;
12928 
12929 /*
12930  * DOUT_I2C_CONTROL_SEND_RESET enum
12931  */
12932 
12933 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
12934 DOUT_I2C_CONTROL__NOT_SEND_RESET         = 0x00000000,
12935 DOUT_I2C_CONTROL__SEND_RESET             = 0x00000001,
12936 } DOUT_I2C_CONTROL_SEND_RESET;
12937 
12938 /*
12939  * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
12940  */
12941 
12942 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
12943 DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS     = 0x00000000,
12944 DOUT_I2C_CONTROL_RESET_SW_STATUS         = 0x00000001,
12945 } DOUT_I2C_CONTROL_SW_STATUS_RESET;
12946 
12947 /*
12948  * DOUT_I2C_CONTROL_DDC_SELECT enum
12949  */
12950 
12951 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
12952 DOUT_I2C_CONTROL_SELECT_DDC1             = 0x00000000,
12953 DOUT_I2C_CONTROL_SELECT_DDC2             = 0x00000001,
12954 DOUT_I2C_CONTROL_SELECT_DDC3             = 0x00000002,
12955 DOUT_I2C_CONTROL_SELECT_DDC4             = 0x00000003,
12956 DOUT_I2C_CONTROL_SELECT_DDC5             = 0x00000004,
12957 DOUT_I2C_CONTROL_SELECT_DDC6             = 0x00000005,
12958 DOUT_I2C_CONTROL_SELECT_DDCVGA           = 0x00000006,
12959 } DOUT_I2C_CONTROL_DDC_SELECT;
12960 
12961 /*
12962  * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
12963  */
12964 
12965 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
12966 DOUT_I2C_CONTROL_TRANS0                  = 0x00000000,
12967 DOUT_I2C_CONTROL_TRANS0_TRANS1           = 0x00000001,
12968 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2    = 0x00000002,
12969 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3  = 0x00000003,
12970 } DOUT_I2C_CONTROL_TRANSACTION_COUNT;
12971 
12972 /*
12973  * DOUT_I2C_CONTROL_DBG_REF_SEL enum
12974  */
12975 
12976 typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
12977 DOUT_I2C_CONTROL_NORMAL_DEBUG            = 0x00000000,
12978 DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG    = 0x00000001,
12979 } DOUT_I2C_CONTROL_DBG_REF_SEL;
12980 
12981 /*
12982  * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
12983  */
12984 
12985 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
12986 DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL  = 0x00000000,
12987 DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH    = 0x00000001,
12988 DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
12989 DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
12990 } DOUT_I2C_ARBITRATION_SW_PRIORITY;
12991 
12992 /*
12993  * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
12994  */
12995 
12996 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
12997 DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED    = 0x00000000,
12998 DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED   = 0x00000001,
12999 } DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
13000 
13001 /*
13002  * DOUT_I2C_ARBITRATION_ABORT_XFER enum
13003  */
13004 
13005 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
13006 DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
13007 DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER  = 0x00000001,
13008 } DOUT_I2C_ARBITRATION_ABORT_XFER;
13009 
13010 /*
13011  * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
13012  */
13013 
13014 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
13015 DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
13016 DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ    = 0x00000001,
13017 } DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
13018 
13019 /*
13020  * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
13021  */
13022 
13023 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
13024 DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
13025 DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG  = 0x00000001,
13026 } DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
13027 
13028 /*
13029  * DOUT_I2C_ACK enum
13030  */
13031 
13032 typedef enum DOUT_I2C_ACK {
13033 DOUT_I2C_NO_ACK                          = 0x00000000,
13034 DOUT_I2C_ACK_TO_CLEAN                    = 0x00000001,
13035 } DOUT_I2C_ACK;
13036 
13037 /*
13038  * DOUT_I2C_DDC_SPEED_THRESHOLD enum
13039  */
13040 
13041 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
13042 DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO  = 0x00000000,
13043 DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE  = 0x00000001,
13044 DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE  = 0x00000002,
13045 DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE  = 0x00000003,
13046 } DOUT_I2C_DDC_SPEED_THRESHOLD;
13047 
13048 /*
13049  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
13050  */
13051 
13052 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
13053 DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
13054 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA     = 0x00000001,
13055 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
13056 
13057 /*
13058  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
13059  */
13060 
13061 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
13062 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS  = 0x00000000,
13063 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS  = 0x00000001,
13064 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
13065 
13066 /*
13067  * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
13068  */
13069 
13070 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
13071 DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT   = 0x00000000,
13072 DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT  = 0x00000001,
13073 } DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
13074 
13075 /*
13076  * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
13077  */
13078 
13079 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
13080 DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
13081 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL     = 0x00000001,
13082 } DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
13083 
13084 /*
13085  * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
13086  */
13087 
13088 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
13089 DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS  = 0x00000000,
13090 DOUT_I2C_TRANSACTION_STOP_ALL_TRANS      = 0x00000001,
13091 } DOUT_I2C_TRANSACTION_STOP_ON_NACK;
13092 
13093 /*
13094  * DOUT_I2C_DATA_INDEX_WRITE enum
13095  */
13096 
13097 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
13098 DOUT_I2C_DATA__NOT_INDEX_WRITE           = 0x00000000,
13099 DOUT_I2C_DATA__INDEX_WRITE               = 0x00000001,
13100 } DOUT_I2C_DATA_INDEX_WRITE;
13101 
13102 /*
13103  * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
13104  */
13105 
13106 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
13107 DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
13108 DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION  = 0x00000001,
13109 } DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
13110 
13111 /*
13112  * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
13113  */
13114 
13115 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
13116 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL  = 0x00000000,
13117 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE  = 0x00000001,
13118 } DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
13119 
13120 /*******************************************************
13121  * FBC Enums
13122  *******************************************************/
13123 
13124 /*
13125  * FBC_IDLE_MASK_MASK_BITS enum
13126  */
13127 
13128 typedef enum FBC_IDLE_MASK_MASK_BITS {
13129 FBC_IDLE_MASK_DISP_REG_UPDATE            = 0x00000000,
13130 FBC_IDLE_MASK_RESERVED1                  = 0x00000001,
13131 FBC_IDLE_MASK_FBC_GRPH_COMP_EN           = 0x00000002,
13132 FBC_IDLE_MASK_FBC_MIN_COMPRESSION        = 0x00000003,
13133 FBC_IDLE_MASK_FBC_ALPHA_COMP_EN          = 0x00000004,
13134 FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN  = 0x00000005,
13135 FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF  = 0x00000006,
13136 FBC_IDLE_MASK_RESERVED7                  = 0x00000007,
13137 FBC_IDLE_MASK_RESERVED8                  = 0x00000008,
13138 FBC_IDLE_MASK_RESERVED9                  = 0x00000009,
13139 FBC_IDLE_MASK_RESERVED10                 = 0x0000000a,
13140 FBC_IDLE_MASK_RESERVED11                 = 0x0000000b,
13141 FBC_IDLE_MASK_RESERVED12                 = 0x0000000c,
13142 FBC_IDLE_MASK_RESERVED13                 = 0x0000000d,
13143 FBC_IDLE_MASK_RESERVED14                 = 0x0000000e,
13144 FBC_IDLE_MASK_RESERVED15                 = 0x0000000f,
13145 FBC_IDLE_MASK_RESERVED16                 = 0x00000010,
13146 FBC_IDLE_MASK_RESERVED17                 = 0x00000011,
13147 FBC_IDLE_MASK_RESERVED18                 = 0x00000012,
13148 FBC_IDLE_MASK_RESERVED19                 = 0x00000013,
13149 FBC_IDLE_MASK_RESERVED20                 = 0x00000014,
13150 FBC_IDLE_MASK_RESERVED21                 = 0x00000015,
13151 FBC_IDLE_MASK_RESERVED22                 = 0x00000016,
13152 FBC_IDLE_MASK_RESERVED23                 = 0x00000017,
13153 FBC_IDLE_MASK_MC_HIT_REGION_0            = 0x00000018,
13154 FBC_IDLE_MASK_MC_HIT_REGION_1            = 0x00000019,
13155 FBC_IDLE_MASK_MC_HIT_REGION_2            = 0x0000001a,
13156 FBC_IDLE_MASK_MC_HIT_REGION_3            = 0x0000001b,
13157 FBC_IDLE_MASK_MC_WRITE                   = 0x0000001c,
13158 FBC_IDLE_MASK_RESERVED29                 = 0x0000001d,
13159 FBC_IDLE_MASK_RESERVED30                 = 0x0000001e,
13160 FBC_IDLE_MASK_RESERVED31                 = 0x0000001f,
13161 } FBC_IDLE_MASK_MASK_BITS;
13162 
13163 /*******************************************************
13164  * DPCSRX Enums
13165  *******************************************************/
13166 
13167 /*
13168  * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
13169  */
13170 
13171 typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
13172 DPCSRX_BPHY_PCS_RX0_CLK                  = 0x00000000,
13173 DPCSRX_BPHY_PCS_RX1_CLK                  = 0x00000001,
13174 DPCSRX_BPHY_PCS_RX2_CLK                  = 0x00000002,
13175 DPCSRX_BPHY_PCS_RX3_CLK                  = 0x00000003,
13176 } DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;
13177 
13178 /*
13179  * DPCSRX_DBG_CFGCLK_SEL enum
13180  */
13181 
13182 typedef enum DPCSRX_DBG_CFGCLK_SEL {
13183 DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF        = 0x00000000,
13184 DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF      = 0x00000001,
13185 DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE         = 0x00000002,
13186 DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER        = 0x00000003,
13187 } DPCSRX_DBG_CFGCLK_SEL;
13188 
13189 /*
13190  * DPCSRX_RX_SYMCLK_SEL enum
13191  */
13192 
13193 typedef enum DPCSRX_RX_SYMCLK_SEL {
13194 DPCSRX_DBG_RX_SYMCLK_SEL_OUT0            = 0x00000000,
13195 DPCSRX_DBG_RX_SYMCLK_SEL_OUT1            = 0x00000001,
13196 DPCSRX_DBG_RX_SYMCLK_SEL_INT             = 0x00000002,
13197 } DPCSRX_RX_SYMCLK_SEL;
13198 
13199 /*******************************************************
13200  * DPCSTX Enums
13201  *******************************************************/
13202 
13203 /*
13204  * DPCSTX_DBG_CFGCLK_SEL enum
13205  */
13206 
13207 typedef enum DPCSTX_DBG_CFGCLK_SEL {
13208 DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF        = 0x00000000,
13209 DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF      = 0x00000001,
13210 DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE         = 0x00000002,
13211 DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER        = 0x00000003,
13212 } DPCSTX_DBG_CFGCLK_SEL;
13213 
13214 /*
13215  * DPCSTX_TX_SYMCLK_SEL enum
13216  */
13217 
13218 typedef enum DPCSTX_TX_SYMCLK_SEL {
13219 DPCSTX_DBG_TX_SYMCLK_SEL_IN0             = 0x00000000,
13220 DPCSTX_DBG_TX_SYMCLK_SEL_IN1             = 0x00000001,
13221 DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR         = 0x00000002,
13222 } DPCSTX_TX_SYMCLK_SEL;
13223 
13224 /*
13225  * DPCSTX_TX_SYMCLK_DIV2_SEL enum
13226  */
13227 
13228 typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
13229 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0       = 0x00000000,
13230 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1       = 0x00000001,
13231 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2       = 0x00000002,
13232 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3       = 0x00000003,
13233 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD    = 0x00000004,
13234 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT        = 0x00000005,
13235 } DPCSTX_TX_SYMCLK_DIV2_SEL;
13236 
13237 /*******************************************************
13238  * CB Enums
13239  *******************************************************/
13240 
13241 /*
13242  * SurfaceNumber enum
13243  */
13244 
13245 typedef enum SurfaceNumber {
13246 NUMBER_UNORM                             = 0x00000000,
13247 NUMBER_SNORM                             = 0x00000001,
13248 NUMBER_USCALED                           = 0x00000002,
13249 NUMBER_SSCALED                           = 0x00000003,
13250 NUMBER_UINT                              = 0x00000004,
13251 NUMBER_SINT                              = 0x00000005,
13252 NUMBER_SRGB                              = 0x00000006,
13253 NUMBER_FLOAT                             = 0x00000007,
13254 } SurfaceNumber;
13255 
13256 /*
13257  * SurfaceSwap enum
13258  */
13259 
13260 typedef enum SurfaceSwap {
13261 SWAP_STD                                 = 0x00000000,
13262 SWAP_ALT                                 = 0x00000001,
13263 SWAP_STD_REV                             = 0x00000002,
13264 SWAP_ALT_REV                             = 0x00000003,
13265 } SurfaceSwap;
13266 
13267 /*
13268  * CBMode enum
13269  */
13270 
13271 typedef enum CBMode {
13272 CB_DISABLE                               = 0x00000000,
13273 CB_NORMAL                                = 0x00000001,
13274 CB_ELIMINATE_FAST_CLEAR                  = 0x00000002,
13275 CB_RESOLVE                               = 0x00000003,
13276 CB_DECOMPRESS                            = 0x00000004,
13277 CB_FMASK_DECOMPRESS                      = 0x00000005,
13278 CB_DCC_DECOMPRESS                        = 0x00000006,
13279 } CBMode;
13280 
13281 /*
13282  * RoundMode enum
13283  */
13284 
13285 typedef enum RoundMode {
13286 ROUND_BY_HALF                            = 0x00000000,
13287 ROUND_TRUNCATE                           = 0x00000001,
13288 } RoundMode;
13289 
13290 /*
13291  * SourceFormat enum
13292  */
13293 
13294 typedef enum SourceFormat {
13295 EXPORT_4C_32BPC                          = 0x00000000,
13296 EXPORT_4C_16BPC                          = 0x00000001,
13297 EXPORT_2C_32BPC_GR                       = 0x00000002,
13298 EXPORT_2C_32BPC_AR                       = 0x00000003,
13299 } SourceFormat;
13300 
13301 /*
13302  * BlendOp enum
13303  */
13304 
13305 typedef enum BlendOp {
13306 BLEND_ZERO                               = 0x00000000,
13307 BLEND_ONE                                = 0x00000001,
13308 BLEND_SRC_COLOR                          = 0x00000002,
13309 BLEND_ONE_MINUS_SRC_COLOR                = 0x00000003,
13310 BLEND_SRC_ALPHA                          = 0x00000004,
13311 BLEND_ONE_MINUS_SRC_ALPHA                = 0x00000005,
13312 BLEND_DST_ALPHA                          = 0x00000006,
13313 BLEND_ONE_MINUS_DST_ALPHA                = 0x00000007,
13314 BLEND_DST_COLOR                          = 0x00000008,
13315 BLEND_ONE_MINUS_DST_COLOR                = 0x00000009,
13316 BLEND_SRC_ALPHA_SATURATE                 = 0x0000000a,
13317 BLEND_BOTH_SRC_ALPHA                     = 0x0000000b,
13318 BLEND_BOTH_INV_SRC_ALPHA                 = 0x0000000c,
13319 BLEND_CONSTANT_COLOR                     = 0x0000000d,
13320 BLEND_ONE_MINUS_CONSTANT_COLOR           = 0x0000000e,
13321 BLEND_SRC1_COLOR                         = 0x0000000f,
13322 BLEND_INV_SRC1_COLOR                     = 0x00000010,
13323 BLEND_SRC1_ALPHA                         = 0x00000011,
13324 BLEND_INV_SRC1_ALPHA                     = 0x00000012,
13325 BLEND_CONSTANT_ALPHA                     = 0x00000013,
13326 BLEND_ONE_MINUS_CONSTANT_ALPHA           = 0x00000014,
13327 } BlendOp;
13328 
13329 /*
13330  * CombFunc enum
13331  */
13332 
13333 typedef enum CombFunc {
13334 COMB_DST_PLUS_SRC                        = 0x00000000,
13335 COMB_SRC_MINUS_DST                       = 0x00000001,
13336 COMB_MIN_DST_SRC                         = 0x00000002,
13337 COMB_MAX_DST_SRC                         = 0x00000003,
13338 COMB_DST_MINUS_SRC                       = 0x00000004,
13339 } CombFunc;
13340 
13341 /*
13342  * BlendOpt enum
13343  */
13344 
13345 typedef enum BlendOpt {
13346 FORCE_OPT_AUTO                           = 0x00000000,
13347 FORCE_OPT_DISABLE                        = 0x00000001,
13348 FORCE_OPT_ENABLE_IF_SRC_A_0              = 0x00000002,
13349 FORCE_OPT_ENABLE_IF_SRC_RGB_0            = 0x00000003,
13350 FORCE_OPT_ENABLE_IF_SRC_ARGB_0           = 0x00000004,
13351 FORCE_OPT_ENABLE_IF_SRC_A_1              = 0x00000005,
13352 FORCE_OPT_ENABLE_IF_SRC_RGB_1            = 0x00000006,
13353 FORCE_OPT_ENABLE_IF_SRC_ARGB_1           = 0x00000007,
13354 } BlendOpt;
13355 
13356 /*
13357  * CmaskCode enum
13358  */
13359 
13360 typedef enum CmaskCode {
13361 CMASK_CLR00_F0                           = 0x00000000,
13362 CMASK_CLR00_F1                           = 0x00000001,
13363 CMASK_CLR00_F2                           = 0x00000002,
13364 CMASK_CLR00_FX                           = 0x00000003,
13365 CMASK_CLR01_F0                           = 0x00000004,
13366 CMASK_CLR01_F1                           = 0x00000005,
13367 CMASK_CLR01_F2                           = 0x00000006,
13368 CMASK_CLR01_FX                           = 0x00000007,
13369 CMASK_CLR10_F0                           = 0x00000008,
13370 CMASK_CLR10_F1                           = 0x00000009,
13371 CMASK_CLR10_F2                           = 0x0000000a,
13372 CMASK_CLR10_FX                           = 0x0000000b,
13373 CMASK_CLR11_F0                           = 0x0000000c,
13374 CMASK_CLR11_F1                           = 0x0000000d,
13375 CMASK_CLR11_F2                           = 0x0000000e,
13376 CMASK_CLR11_FX                           = 0x0000000f,
13377 } CmaskCode;
13378 
13379 /*
13380  * CmaskAddr enum
13381  */
13382 
13383 typedef enum CmaskAddr {
13384 CMASK_ADDR_TILED                         = 0x00000000,
13385 CMASK_ADDR_LINEAR                        = 0x00000001,
13386 CMASK_ADDR_COMPATIBLE                    = 0x00000002,
13387 } CmaskAddr;
13388 
13389 /*
13390  * MemArbMode enum
13391  */
13392 
13393 typedef enum MemArbMode {
13394 MEM_ARB_MODE_FIXED                       = 0x00000000,
13395 MEM_ARB_MODE_AGE                         = 0x00000001,
13396 MEM_ARB_MODE_WEIGHT                      = 0x00000002,
13397 MEM_ARB_MODE_BOTH                        = 0x00000003,
13398 } MemArbMode;
13399 
13400 /*
13401  * CBPerfSel enum
13402  */
13403 
13404 typedef enum CBPerfSel {
13405 CB_PERF_SEL_NONE                         = 0x00000000,
13406 CB_PERF_SEL_BUSY                         = 0x00000001,
13407 CB_PERF_SEL_CORE_SCLK_VLD                = 0x00000002,
13408 CB_PERF_SEL_REG_SCLK0_VLD                = 0x00000003,
13409 CB_PERF_SEL_REG_SCLK1_VLD                = 0x00000004,
13410 CB_PERF_SEL_DRAWN_QUAD                   = 0x00000005,
13411 CB_PERF_SEL_DRAWN_PIXEL                  = 0x00000006,
13412 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT          = 0x00000007,
13413 CB_PERF_SEL_DRAWN_TILE                   = 0x00000008,
13414 CB_PERF_SEL_DB_CB_TILE_VALID_READY       = 0x00000009,
13415 CB_PERF_SEL_DB_CB_TILE_VALID_READYB      = 0x0000000a,
13416 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY      = 0x0000000b,
13417 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB     = 0x0000000c,
13418 CB_PERF_SEL_CM_FC_TILE_VALID_READY       = 0x0000000d,
13419 CB_PERF_SEL_CM_FC_TILE_VALID_READYB      = 0x0000000e,
13420 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY      = 0x0000000f,
13421 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB     = 0x00000010,
13422 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY  = 0x00000011,
13423 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB  = 0x00000012,
13424 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY      = 0x00000013,
13425 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB     = 0x00000014,
13426 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY     = 0x00000015,
13427 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB    = 0x00000016,
13428 CB_PERF_SEL_LQUAD_NO_TILE                = 0x00000017,
13429 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R  = 0x00000018,
13430 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR  = 0x00000019,
13431 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR  = 0x0000001a,
13432 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR  = 0x0000001b,
13433 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR  = 0x0000001c,
13434 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR  = 0x0000001d,
13435 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR  = 0x0000001e,
13436 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT  = 0x0000001f,
13437 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID  = 0x00000020,
13438 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK  = 0x00000021,
13439 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK  = 0x00000022,
13440 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL  = 0x00000023,
13441 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY    = 0x00000024,
13442 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB   = 0x00000025,
13443 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY   = 0x00000026,
13444 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB  = 0x00000027,
13445 CB_PERF_SEL_FOP_IN_VALID_READY           = 0x00000028,
13446 CB_PERF_SEL_FOP_IN_VALID_READYB          = 0x00000029,
13447 CB_PERF_SEL_FOP_IN_VALIDB_READY          = 0x0000002a,
13448 CB_PERF_SEL_FOP_IN_VALIDB_READYB         = 0x0000002b,
13449 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY   = 0x0000002c,
13450 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB  = 0x0000002d,
13451 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY  = 0x0000002e,
13452 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB  = 0x0000002f,
13453 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY    = 0x00000030,
13454 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB   = 0x00000031,
13455 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY   = 0x00000032,
13456 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB  = 0x00000033,
13457 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY    = 0x00000034,
13458 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB   = 0x00000035,
13459 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY   = 0x00000036,
13460 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB  = 0x00000037,
13461 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY  = 0x00000038,
13462 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB  = 0x00000039,
13463 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY  = 0x0000003a,
13464 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB  = 0x0000003b,
13465 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY  = 0x0000003c,
13466 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB  = 0x0000003d,
13467 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY  = 0x0000003e,
13468 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB  = 0x0000003f,
13469 CB_PERF_SEL_CC_BC_CS_FRAG_VALID          = 0x00000040,
13470 CB_PERF_SEL_CM_CACHE_HIT                 = 0x00000041,
13471 CB_PERF_SEL_CM_CACHE_TAG_MISS            = 0x00000042,
13472 CB_PERF_SEL_CM_CACHE_SECTOR_MISS         = 0x00000043,
13473 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL    = 0x00000044,
13474 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000045,
13475 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000046,
13476 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000047,
13477 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL   = 0x00000048,
13478 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL  = 0x00000049,
13479 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL    = 0x0000004a,
13480 CB_PERF_SEL_CM_CACHE_STALL               = 0x0000004b,
13481 CB_PERF_SEL_CM_CACHE_FLUSH               = 0x0000004c,
13482 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED        = 0x0000004d,
13483 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED     = 0x0000004e,
13484 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000004f,
13485 CB_PERF_SEL_FC_CACHE_HIT                 = 0x00000050,
13486 CB_PERF_SEL_FC_CACHE_TAG_MISS            = 0x00000051,
13487 CB_PERF_SEL_FC_CACHE_SECTOR_MISS         = 0x00000052,
13488 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL    = 0x00000053,
13489 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000054,
13490 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000055,
13491 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000056,
13492 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL   = 0x00000057,
13493 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL  = 0x00000058,
13494 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL    = 0x00000059,
13495 CB_PERF_SEL_FC_CACHE_STALL               = 0x0000005a,
13496 CB_PERF_SEL_FC_CACHE_FLUSH               = 0x0000005b,
13497 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED        = 0x0000005c,
13498 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED     = 0x0000005d,
13499 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000005e,
13500 CB_PERF_SEL_CC_CACHE_HIT                 = 0x0000005f,
13501 CB_PERF_SEL_CC_CACHE_TAG_MISS            = 0x00000060,
13502 CB_PERF_SEL_CC_CACHE_SECTOR_MISS         = 0x00000061,
13503 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL    = 0x00000062,
13504 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000063,
13505 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000064,
13506 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000065,
13507 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL   = 0x00000066,
13508 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL  = 0x00000067,
13509 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL    = 0x00000068,
13510 CB_PERF_SEL_CC_CACHE_STALL               = 0x00000069,
13511 CB_PERF_SEL_CC_CACHE_FLUSH               = 0x0000006a,
13512 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED        = 0x0000006b,
13513 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED     = 0x0000006c,
13514 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000006d,
13515 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION  = 0x0000006e,
13516 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC  = 0x0000006f,
13517 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY     = 0x00000070,
13518 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB    = 0x00000071,
13519 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY    = 0x00000072,
13520 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB   = 0x00000073,
13521 CB_PERF_SEL_CM_MC_WRITE_REQUEST          = 0x00000074,
13522 CB_PERF_SEL_FC_MC_WRITE_REQUEST          = 0x00000075,
13523 CB_PERF_SEL_CC_MC_WRITE_REQUEST          = 0x00000076,
13524 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000077,
13525 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000078,
13526 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000079,
13527 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY     = 0x0000007a,
13528 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB    = 0x0000007b,
13529 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY    = 0x0000007c,
13530 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB   = 0x0000007d,
13531 CB_PERF_SEL_CM_MC_READ_REQUEST           = 0x0000007e,
13532 CB_PERF_SEL_FC_MC_READ_REQUEST           = 0x0000007f,
13533 CB_PERF_SEL_CC_MC_READ_REQUEST           = 0x00000080,
13534 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000081,
13535 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000082,
13536 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000083,
13537 CB_PERF_SEL_CM_TQ_FULL                   = 0x00000084,
13538 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL  = 0x00000085,
13539 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL      = 0x00000086,
13540 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL      = 0x00000087,
13541 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL  = 0x00000088,
13542 CB_PERF_SEL_FOP_FMASK_RAW_STALL          = 0x00000089,
13543 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL       = 0x0000008a,
13544 CB_PERF_SEL_CC_SF_FULL                   = 0x0000008b,
13545 CB_PERF_SEL_CC_RB_FULL                   = 0x0000008c,
13546 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL  = 0x0000008d,
13547 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL  = 0x0000008e,
13548 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL     = 0x0000008f,
13549 CB_PERF_SEL_EVENT                        = 0x00000090,
13550 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS         = 0x00000091,
13551 CB_PERF_SEL_EVENT_CONTEXT_DONE           = 0x00000092,
13552 CB_PERF_SEL_EVENT_CACHE_FLUSH            = 0x00000093,
13553 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT  = 0x00000094,
13554 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT  = 0x00000095,
13555 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS  = 0x00000096,
13556 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META  = 0x00000097,
13557 CB_PERF_SEL_CC_SURFACE_SYNC              = 0x00000098,
13558 CB_PERF_SEL_CMASK_READ_DATA_0xC          = 0x00000099,
13559 CB_PERF_SEL_CMASK_READ_DATA_0xD          = 0x0000009a,
13560 CB_PERF_SEL_CMASK_READ_DATA_0xE          = 0x0000009b,
13561 CB_PERF_SEL_CMASK_READ_DATA_0xF          = 0x0000009c,
13562 CB_PERF_SEL_CMASK_WRITE_DATA_0xC         = 0x0000009d,
13563 CB_PERF_SEL_CMASK_WRITE_DATA_0xD         = 0x0000009e,
13564 CB_PERF_SEL_CMASK_WRITE_DATA_0xE         = 0x0000009f,
13565 CB_PERF_SEL_CMASK_WRITE_DATA_0xF         = 0x000000a0,
13566 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT      = 0x000000a1,
13567 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT  = 0x000000a2,
13568 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT  = 0x000000a3,
13569 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE  = 0x000000a4,
13570 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE  = 0x000000a5,
13571 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE  = 0x000000a6,
13572 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE  = 0x000000a7,
13573 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE  = 0x000000a8,
13574 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE  = 0x000000a9,
13575 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE  = 0x000000aa,
13576 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE  = 0x000000ab,
13577 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE  = 0x000000ac,
13578 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE  = 0x000000ad,
13579 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE  = 0x000000ae,
13580 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE  = 0x000000af,
13581 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE  = 0x000000b0,
13582 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE  = 0x000000b1,
13583 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE  = 0x000000b2,
13584 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE  = 0x000000b3,
13585 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT        = 0x000000b4,
13586 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS       = 0x000000b5,
13587 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS       = 0x000000b6,
13588 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS       = 0x000000b7,
13589 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS       = 0x000000b8,
13590 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS       = 0x000000b9,
13591 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS       = 0x000000ba,
13592 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT      = 0x000000bb,
13593 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS     = 0x000000bc,
13594 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS     = 0x000000bd,
13595 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS     = 0x000000be,
13596 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS     = 0x000000bf,
13597 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS     = 0x000000c0,
13598 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS     = 0x000000c1,
13599 CB_PERF_SEL_QUAD_READS_FRAGMENT_0        = 0x000000c2,
13600 CB_PERF_SEL_QUAD_READS_FRAGMENT_1        = 0x000000c3,
13601 CB_PERF_SEL_QUAD_READS_FRAGMENT_2        = 0x000000c4,
13602 CB_PERF_SEL_QUAD_READS_FRAGMENT_3        = 0x000000c5,
13603 CB_PERF_SEL_QUAD_READS_FRAGMENT_4        = 0x000000c6,
13604 CB_PERF_SEL_QUAD_READS_FRAGMENT_5        = 0x000000c7,
13605 CB_PERF_SEL_QUAD_READS_FRAGMENT_6        = 0x000000c8,
13606 CB_PERF_SEL_QUAD_READS_FRAGMENT_7        = 0x000000c9,
13607 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0       = 0x000000ca,
13608 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1       = 0x000000cb,
13609 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2       = 0x000000cc,
13610 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3       = 0x000000cd,
13611 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4       = 0x000000ce,
13612 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5       = 0x000000cf,
13613 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6       = 0x000000d0,
13614 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7       = 0x000000d1,
13615 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST  = 0x000000d2,
13616 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS  = 0x000000d3,
13617 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS  = 0x000000d4,
13618 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED  = 0x000000d5,
13619 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED  = 0x000000d6,
13620 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED  = 0x000000d7,
13621 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST  = 0x000000d8,
13622 CB_PERF_SEL_DRAWN_BUSY                   = 0x000000d9,
13623 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY      = 0x000000da,
13624 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY       = 0x000000db,
13625 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY       = 0x000000dc,
13626 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY       = 0x000000dd,
13627 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED  = 0x000000de,
13628 CB_PERF_SEL_FC_SEQUENCER_CLEAR           = 0x000000df,
13629 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR  = 0x000000e0,
13630 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS  = 0x000000e1,
13631 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE  = 0x000000e2,
13632 CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL     = 0x000000e3,
13633 CB_PERF_SEL_FC_DOC_IS_STALLED            = 0x000000e4,
13634 CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED     = 0x000000e5,
13635 CB_PERF_SEL_FC_DOC_MRTS_COMBINED         = 0x000000e6,
13636 CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS        = 0x000000e7,
13637 CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT         = 0x000000e8,
13638 CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS        = 0x000000e9,
13639 CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT         = 0x000000ea,
13640 CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL  = 0x000000eb,
13641 CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR    = 0x000000ec,
13642 CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS   = 0x000000ed,
13643 CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS   = 0x000000ee,
13644 CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS   = 0x000000ef,
13645 CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS  = 0x000000f0,
13646 CB_PERF_SEL_FC_DCC_CACHE_HIT             = 0x000000f1,
13647 CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS        = 0x000000f2,
13648 CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS     = 0x000000f3,
13649 CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL  = 0x000000f4,
13650 CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x000000f5,
13651 CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x000000f6,
13652 CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x000000f7,
13653 CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL  = 0x000000f8,
13654 CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL  = 0x000000f9,
13655 CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL  = 0x000000fa,
13656 CB_PERF_SEL_FC_DCC_CACHE_STALL           = 0x000000fb,
13657 CB_PERF_SEL_FC_DCC_CACHE_FLUSH           = 0x000000fc,
13658 CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED    = 0x000000fd,
13659 CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED  = 0x000000fe,
13660 CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x000000ff,
13661 CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT     = 0x00000100,
13662 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST      = 0x00000101,
13663 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000102,
13664 CB_PERF_SEL_FC_MC_DCC_READ_REQUEST       = 0x00000103,
13665 CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT  = 0x00000104,
13666 CB_PERF_SEL_CC_DCC_RDREQ_STALL           = 0x00000105,
13667 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN    = 0x00000106,
13668 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT   = 0x00000107,
13669 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN      = 0x00000108,
13670 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT     = 0x00000109,
13671 CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR      = 0x0000010a,
13672 CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1  = 0x0000010b,
13673 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2  = 0x0000010c,
13674 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x0000010d,
13675 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1  = 0x0000010e,
13676 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1  = 0x0000010f,
13677 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2  = 0x00000110,
13678 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1  = 0x00000111,
13679 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000112,
13680 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000113,
13681 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1  = 0x00000114,
13682 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2  = 0x00000115,
13683 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2  = 0x00000116,
13684 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2  = 0x00000117,
13685 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000118,
13686 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1  = 0x00000119,
13687 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1  = 0x0000011a,
13688 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2  = 0x0000011b,
13689 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3  = 0x0000011c,
13690 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4  = 0x0000011d,
13691 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1  = 0x0000011e,
13692 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2  = 0x0000011f,
13693 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3  = 0x00000120,
13694 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4  = 0x00000121,
13695 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1  = 0x00000122,
13696 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2  = 0x00000123,
13697 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3  = 0x00000124,
13698 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4  = 0x00000125,
13699 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1  = 0x00000126,
13700 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2  = 0x00000127,
13701 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3  = 0x00000128,
13702 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1  = 0x00000129,
13703 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2  = 0x0000012a,
13704 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3  = 0x0000012b,
13705 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4  = 0x0000012c,
13706 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1  = 0x0000012d,
13707 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2  = 0x0000012e,
13708 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3  = 0x0000012f,
13709 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4  = 0x00000130,
13710 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1  = 0x00000131,
13711 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2  = 0x00000132,
13712 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3  = 0x00000133,
13713 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4  = 0x00000134,
13714 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1  = 0x00000135,
13715 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2  = 0x00000136,
13716 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3  = 0x00000137,
13717 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1  = 0x00000138,
13718 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1  = 0x00000139,
13719 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1  = 0x0000013a,
13720 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1  = 0x0000013b,
13721 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1  = 0x0000013c,
13722 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1  = 0x0000013d,
13723 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1  = 0x0000013e,
13724 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1  = 0x0000013f,
13725 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2  = 0x00000140,
13726 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2  = 0x00000141,
13727 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2  = 0x00000142,
13728 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2  = 0x00000143,
13729 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2  = 0x00000144,
13730 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2  = 0x00000145,
13731 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2  = 0x00000146,
13732 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1  = 0x00000147,
13733 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1  = 0x00000148,
13734 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1  = 0x00000149,
13735 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1  = 0x0000014a,
13736 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2  = 0x0000014b,
13737 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2  = 0x0000014c,
13738 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2  = 0x0000014d,
13739 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2  = 0x0000014e,
13740 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x0000014f,
13741 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000150,
13742 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000151,
13743 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000152,
13744 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000153,
13745 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000154,
13746 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000155,
13747 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1  = 0x00000156,
13748 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2  = 0x00000157,
13749 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3  = 0x00000158,
13750 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4  = 0x00000159,
13751 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5  = 0x0000015a,
13752 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6  = 0x0000015b,
13753 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0  = 0x0000015c,
13754 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1  = 0x0000015d,
13755 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1  = 0x0000015e,
13756 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2  = 0x0000015f,
13757 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3  = 0x00000160,
13758 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4  = 0x00000161,
13759 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5  = 0x00000162,
13760 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0  = 0x00000163,
13761 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1  = 0x00000164,
13762 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1  = 0x00000165,
13763 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1  = 0x00000166,
13764 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1  = 0x00000167,
13765 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1  = 0x00000168,
13766 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1  = 0x00000169,
13767 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1  = 0x0000016a,
13768 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1  = 0x0000016b,
13769 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1  = 0x0000016c,
13770 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2  = 0x0000016d,
13771 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2  = 0x0000016e,
13772 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2  = 0x0000016f,
13773 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2  = 0x00000170,
13774 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2  = 0x00000171,
13775 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2  = 0x00000172,
13776 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2  = 0x00000173,
13777 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1  = 0x00000174,
13778 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2  = 0x00000175,
13779 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3  = 0x00000176,
13780 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4  = 0x00000177,
13781 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5  = 0x00000178,
13782 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6  = 0x00000179,
13783 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7  = 0x0000017a,
13784 CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED  = 0x0000017b,
13785 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1   = 0x0000017c,
13786 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1   = 0x0000017d,
13787 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2   = 0x0000017e,
13788 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3   = 0x0000017f,
13789 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1   = 0x00000180,
13790 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2   = 0x00000181,
13791 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3   = 0x00000182,
13792 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4   = 0x00000183,
13793 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5   = 0x00000184,
13794 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1   = 0x00000185,
13795 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2   = 0x00000186,
13796 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3   = 0x00000187,
13797 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4   = 0x00000188,
13798 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5   = 0x00000189,
13799 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6   = 0x0000018a,
13800 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7   = 0x0000018b,
13801 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH     = 0x0000018c,
13802 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT     = 0x0000018d,
13803 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT    = 0x0000018e,
13804 CB_PERF_SEL_RBP_SPLIT_MICROTILE          = 0x0000018f,
13805 CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK     = 0x00000190,
13806 CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK  = 0x00000191,
13807 CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING  = 0x00000192,
13808 CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS  = 0x00000193,
13809 CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD  = 0x00000194,
13810 } CBPerfSel;
13811 
13812 /*
13813  * CBPerfOpFilterSel enum
13814  */
13815 
13816 typedef enum CBPerfOpFilterSel {
13817 CB_PERF_OP_FILTER_SEL_WRITE_ONLY         = 0x00000000,
13818 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION  = 0x00000001,
13819 CB_PERF_OP_FILTER_SEL_RESOLVE            = 0x00000002,
13820 CB_PERF_OP_FILTER_SEL_DECOMPRESS         = 0x00000003,
13821 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS   = 0x00000004,
13822 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR  = 0x00000005,
13823 } CBPerfOpFilterSel;
13824 
13825 /*
13826  * CBPerfClearFilterSel enum
13827  */
13828 
13829 typedef enum CBPerfClearFilterSel {
13830 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR        = 0x00000000,
13831 CB_PERF_CLEAR_FILTER_SEL_CLEAR           = 0x00000001,
13832 } CBPerfClearFilterSel;
13833 
13834 /*******************************************************
13835  * TC Enums
13836  *******************************************************/
13837 
13838 /*
13839  * TC_OP_MASKS enum
13840  */
13841 
13842 typedef enum TC_OP_MASKS {
13843 TC_OP_MASK_FLUSH_DENROM                  = 0x00000008,
13844 TC_OP_MASK_64                            = 0x00000020,
13845 TC_OP_MASK_NO_RTN                        = 0x00000040,
13846 } TC_OP_MASKS;
13847 
13848 /*
13849  * TC_OP enum
13850  */
13851 
13852 typedef enum TC_OP {
13853 TC_OP_READ                               = 0x00000000,
13854 TC_OP_ATOMIC_FCMPSWAP_RTN_32             = 0x00000001,
13855 TC_OP_ATOMIC_FMIN_RTN_32                 = 0x00000002,
13856 TC_OP_ATOMIC_FMAX_RTN_32                 = 0x00000003,
13857 TC_OP_RESERVED_FOP_RTN_32_0              = 0x00000004,
13858 TC_OP_RESERVED_FOP_RTN_32_1              = 0x00000005,
13859 TC_OP_RESERVED_FOP_RTN_32_2              = 0x00000006,
13860 TC_OP_ATOMIC_SWAP_RTN_32                 = 0x00000007,
13861 TC_OP_ATOMIC_CMPSWAP_RTN_32              = 0x00000008,
13862 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32  = 0x00000009,
13863 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32    = 0x0000000a,
13864 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32    = 0x0000000b,
13865 TC_OP_PROBE_FILTER                       = 0x0000000c,
13866 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1  = 0x0000000d,
13867 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2  = 0x0000000e,
13868 TC_OP_ATOMIC_ADD_RTN_32                  = 0x0000000f,
13869 TC_OP_ATOMIC_SUB_RTN_32                  = 0x00000010,
13870 TC_OP_ATOMIC_SMIN_RTN_32                 = 0x00000011,
13871 TC_OP_ATOMIC_UMIN_RTN_32                 = 0x00000012,
13872 TC_OP_ATOMIC_SMAX_RTN_32                 = 0x00000013,
13873 TC_OP_ATOMIC_UMAX_RTN_32                 = 0x00000014,
13874 TC_OP_ATOMIC_AND_RTN_32                  = 0x00000015,
13875 TC_OP_ATOMIC_OR_RTN_32                   = 0x00000016,
13876 TC_OP_ATOMIC_XOR_RTN_32                  = 0x00000017,
13877 TC_OP_ATOMIC_INC_RTN_32                  = 0x00000018,
13878 TC_OP_ATOMIC_DEC_RTN_32                  = 0x00000019,
13879 TC_OP_WBINVL1_VOL                        = 0x0000001a,
13880 TC_OP_WBINVL1_SD                         = 0x0000001b,
13881 TC_OP_RESERVED_NON_FLOAT_RTN_32_0        = 0x0000001c,
13882 TC_OP_RESERVED_NON_FLOAT_RTN_32_1        = 0x0000001d,
13883 TC_OP_RESERVED_NON_FLOAT_RTN_32_2        = 0x0000001e,
13884 TC_OP_RESERVED_NON_FLOAT_RTN_32_3        = 0x0000001f,
13885 TC_OP_WRITE                              = 0x00000020,
13886 TC_OP_ATOMIC_FCMPSWAP_RTN_64             = 0x00000021,
13887 TC_OP_ATOMIC_FMIN_RTN_64                 = 0x00000022,
13888 TC_OP_ATOMIC_FMAX_RTN_64                 = 0x00000023,
13889 TC_OP_RESERVED_FOP_RTN_64_0              = 0x00000024,
13890 TC_OP_RESERVED_FOP_RTN_64_1              = 0x00000025,
13891 TC_OP_RESERVED_FOP_RTN_64_2              = 0x00000026,
13892 TC_OP_ATOMIC_SWAP_RTN_64                 = 0x00000027,
13893 TC_OP_ATOMIC_CMPSWAP_RTN_64              = 0x00000028,
13894 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64  = 0x00000029,
13895 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64    = 0x0000002a,
13896 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64    = 0x0000002b,
13897 TC_OP_WBINVL2_SD                         = 0x0000002c,
13898 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0  = 0x0000002d,
13899 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1  = 0x0000002e,
13900 TC_OP_ATOMIC_ADD_RTN_64                  = 0x0000002f,
13901 TC_OP_ATOMIC_SUB_RTN_64                  = 0x00000030,
13902 TC_OP_ATOMIC_SMIN_RTN_64                 = 0x00000031,
13903 TC_OP_ATOMIC_UMIN_RTN_64                 = 0x00000032,
13904 TC_OP_ATOMIC_SMAX_RTN_64                 = 0x00000033,
13905 TC_OP_ATOMIC_UMAX_RTN_64                 = 0x00000034,
13906 TC_OP_ATOMIC_AND_RTN_64                  = 0x00000035,
13907 TC_OP_ATOMIC_OR_RTN_64                   = 0x00000036,
13908 TC_OP_ATOMIC_XOR_RTN_64                  = 0x00000037,
13909 TC_OP_ATOMIC_INC_RTN_64                  = 0x00000038,
13910 TC_OP_ATOMIC_DEC_RTN_64                  = 0x00000039,
13911 TC_OP_WBL2_NC                            = 0x0000003a,
13912 TC_OP_WBL2_WC                            = 0x0000003b,
13913 TC_OP_RESERVED_NON_FLOAT_RTN_64_1        = 0x0000003c,
13914 TC_OP_RESERVED_NON_FLOAT_RTN_64_2        = 0x0000003d,
13915 TC_OP_RESERVED_NON_FLOAT_RTN_64_3        = 0x0000003e,
13916 TC_OP_RESERVED_NON_FLOAT_RTN_64_4        = 0x0000003f,
13917 TC_OP_WBINVL1                            = 0x00000040,
13918 TC_OP_ATOMIC_FCMPSWAP_32                 = 0x00000041,
13919 TC_OP_ATOMIC_FMIN_32                     = 0x00000042,
13920 TC_OP_ATOMIC_FMAX_32                     = 0x00000043,
13921 TC_OP_RESERVED_FOP_32_0                  = 0x00000044,
13922 TC_OP_RESERVED_FOP_32_1                  = 0x00000045,
13923 TC_OP_RESERVED_FOP_32_2                  = 0x00000046,
13924 TC_OP_ATOMIC_SWAP_32                     = 0x00000047,
13925 TC_OP_ATOMIC_CMPSWAP_32                  = 0x00000048,
13926 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32    = 0x00000049,
13927 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32        = 0x0000004a,
13928 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32        = 0x0000004b,
13929 TC_OP_INV_METADATA                       = 0x0000004c,
13930 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1     = 0x0000004d,
13931 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2     = 0x0000004e,
13932 TC_OP_ATOMIC_ADD_32                      = 0x0000004f,
13933 TC_OP_ATOMIC_SUB_32                      = 0x00000050,
13934 TC_OP_ATOMIC_SMIN_32                     = 0x00000051,
13935 TC_OP_ATOMIC_UMIN_32                     = 0x00000052,
13936 TC_OP_ATOMIC_SMAX_32                     = 0x00000053,
13937 TC_OP_ATOMIC_UMAX_32                     = 0x00000054,
13938 TC_OP_ATOMIC_AND_32                      = 0x00000055,
13939 TC_OP_ATOMIC_OR_32                       = 0x00000056,
13940 TC_OP_ATOMIC_XOR_32                      = 0x00000057,
13941 TC_OP_ATOMIC_INC_32                      = 0x00000058,
13942 TC_OP_ATOMIC_DEC_32                      = 0x00000059,
13943 TC_OP_INVL2_NC                           = 0x0000005a,
13944 TC_OP_NOP_RTN0                           = 0x0000005b,
13945 TC_OP_RESERVED_NON_FLOAT_32_1            = 0x0000005c,
13946 TC_OP_RESERVED_NON_FLOAT_32_2            = 0x0000005d,
13947 TC_OP_RESERVED_NON_FLOAT_32_3            = 0x0000005e,
13948 TC_OP_RESERVED_NON_FLOAT_32_4            = 0x0000005f,
13949 TC_OP_WBINVL2                            = 0x00000060,
13950 TC_OP_ATOMIC_FCMPSWAP_64                 = 0x00000061,
13951 TC_OP_ATOMIC_FMIN_64                     = 0x00000062,
13952 TC_OP_ATOMIC_FMAX_64                     = 0x00000063,
13953 TC_OP_RESERVED_FOP_64_0                  = 0x00000064,
13954 TC_OP_RESERVED_FOP_64_1                  = 0x00000065,
13955 TC_OP_RESERVED_FOP_64_2                  = 0x00000066,
13956 TC_OP_ATOMIC_SWAP_64                     = 0x00000067,
13957 TC_OP_ATOMIC_CMPSWAP_64                  = 0x00000068,
13958 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64    = 0x00000069,
13959 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64        = 0x0000006a,
13960 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64        = 0x0000006b,
13961 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0     = 0x0000006c,
13962 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1     = 0x0000006d,
13963 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2     = 0x0000006e,
13964 TC_OP_ATOMIC_ADD_64                      = 0x0000006f,
13965 TC_OP_ATOMIC_SUB_64                      = 0x00000070,
13966 TC_OP_ATOMIC_SMIN_64                     = 0x00000071,
13967 TC_OP_ATOMIC_UMIN_64                     = 0x00000072,
13968 TC_OP_ATOMIC_SMAX_64                     = 0x00000073,
13969 TC_OP_ATOMIC_UMAX_64                     = 0x00000074,
13970 TC_OP_ATOMIC_AND_64                      = 0x00000075,
13971 TC_OP_ATOMIC_OR_64                       = 0x00000076,
13972 TC_OP_ATOMIC_XOR_64                      = 0x00000077,
13973 TC_OP_ATOMIC_INC_64                      = 0x00000078,
13974 TC_OP_ATOMIC_DEC_64                      = 0x00000079,
13975 TC_OP_WBINVL2_NC                         = 0x0000007a,
13976 TC_OP_NOP_ACK                            = 0x0000007b,
13977 TC_OP_RESERVED_NON_FLOAT_64_1            = 0x0000007c,
13978 TC_OP_RESERVED_NON_FLOAT_64_2            = 0x0000007d,
13979 TC_OP_RESERVED_NON_FLOAT_64_3            = 0x0000007e,
13980 TC_OP_RESERVED_NON_FLOAT_64_4            = 0x0000007f,
13981 } TC_OP;
13982 
13983 /*
13984  * TC_CHUB_REQ_CREDITS_ENUM enum
13985  */
13986 
13987 typedef enum TC_CHUB_REQ_CREDITS_ENUM {
13988 TC_CHUB_REQ_CREDITS                      = 0x00000010,
13989 } TC_CHUB_REQ_CREDITS_ENUM;
13990 
13991 /*
13992  * CHUB_TC_RET_CREDITS_ENUM enum
13993  */
13994 
13995 typedef enum CHUB_TC_RET_CREDITS_ENUM {
13996 CHUB_TC_RET_CREDITS                      = 0x00000020,
13997 } CHUB_TC_RET_CREDITS_ENUM;
13998 
13999 /*
14000  * TC_NACKS enum
14001  */
14002 
14003 typedef enum TC_NACKS {
14004 TC_NACK_NO_FAULT                         = 0x00000000,
14005 TC_NACK_PAGE_FAULT                       = 0x00000001,
14006 TC_NACK_PROTECTION_FAULT                 = 0x00000002,
14007 TC_NACK_DATA_ERROR                       = 0x00000003,
14008 } TC_NACKS;
14009 
14010 /*
14011  * TC_EA_CID enum
14012  */
14013 
14014 typedef enum TC_EA_CID {
14015 TC_EA_CID_RT                             = 0x00000000,
14016 TC_EA_CID_FMASK                          = 0x00000001,
14017 TC_EA_CID_DCC                            = 0x00000002,
14018 TC_EA_CID_TCPMETA                        = 0x00000003,
14019 TC_EA_CID_Z                              = 0x00000004,
14020 TC_EA_CID_STENCIL                        = 0x00000005,
14021 TC_EA_CID_HTILE                          = 0x00000006,
14022 TC_EA_CID_MISC                           = 0x00000007,
14023 TC_EA_CID_TCP                            = 0x00000008,
14024 TC_EA_CID_SQC                            = 0x00000009,
14025 TC_EA_CID_CPF                            = 0x0000000a,
14026 TC_EA_CID_CPG                            = 0x0000000b,
14027 TC_EA_CID_IA                             = 0x0000000c,
14028 TC_EA_CID_WD                             = 0x0000000d,
14029 TC_EA_CID_PA                             = 0x0000000e,
14030 TC_EA_CID_UTCL2_TPI                      = 0x0000000f,
14031 } TC_EA_CID;
14032 
14033 /*******************************************************
14034  * SPI Enums
14035  *******************************************************/
14036 
14037 /*
14038  * SPI_SAMPLE_CNTL enum
14039  */
14040 
14041 typedef enum SPI_SAMPLE_CNTL {
14042 CENTROIDS_ONLY                           = 0x00000000,
14043 CENTERS_ONLY                             = 0x00000001,
14044 CENTROIDS_AND_CENTERS                    = 0x00000002,
14045 UNDEF                                    = 0x00000003,
14046 } SPI_SAMPLE_CNTL;
14047 
14048 /*
14049  * SPI_FOG_MODE enum
14050  */
14051 
14052 typedef enum SPI_FOG_MODE {
14053 SPI_FOG_NONE                             = 0x00000000,
14054 SPI_FOG_EXP                              = 0x00000001,
14055 SPI_FOG_EXP2                             = 0x00000002,
14056 SPI_FOG_LINEAR                           = 0x00000003,
14057 } SPI_FOG_MODE;
14058 
14059 /*
14060  * SPI_PNT_SPRITE_OVERRIDE enum
14061  */
14062 
14063 typedef enum SPI_PNT_SPRITE_OVERRIDE {
14064 SPI_PNT_SPRITE_SEL_0                     = 0x00000000,
14065 SPI_PNT_SPRITE_SEL_1                     = 0x00000001,
14066 SPI_PNT_SPRITE_SEL_S                     = 0x00000002,
14067 SPI_PNT_SPRITE_SEL_T                     = 0x00000003,
14068 SPI_PNT_SPRITE_SEL_NONE                  = 0x00000004,
14069 } SPI_PNT_SPRITE_OVERRIDE;
14070 
14071 /*
14072  * SPI_PERFCNT_SEL enum
14073  */
14074 
14075 typedef enum SPI_PERFCNT_SEL {
14076 SPI_PERF_VS_WINDOW_VALID                 = 0x00000000,
14077 SPI_PERF_VS_BUSY                         = 0x00000001,
14078 SPI_PERF_VS_FIRST_WAVE                   = 0x00000002,
14079 SPI_PERF_VS_LAST_WAVE                    = 0x00000003,
14080 SPI_PERF_VS_LSHS_DEALLOC                 = 0x00000004,
14081 SPI_PERF_VS_PC_STALL                     = 0x00000005,
14082 SPI_PERF_VS_POS0_STALL                   = 0x00000006,
14083 SPI_PERF_VS_POS1_STALL                   = 0x00000007,
14084 SPI_PERF_VS_CRAWLER_STALL                = 0x00000008,
14085 SPI_PERF_VS_EVENT_WAVE                   = 0x00000009,
14086 SPI_PERF_VS_WAVE                         = 0x0000000a,
14087 SPI_PERF_VS_PERS_UPD_FULL0               = 0x0000000b,
14088 SPI_PERF_VS_PERS_UPD_FULL1               = 0x0000000c,
14089 SPI_PERF_VS_LATE_ALLOC_FULL              = 0x0000000d,
14090 SPI_PERF_VS_FIRST_SUBGRP                 = 0x0000000e,
14091 SPI_PERF_VS_LAST_SUBGRP                  = 0x0000000f,
14092 SPI_PERF_GS_WINDOW_VALID                 = 0x00000010,
14093 SPI_PERF_GS_BUSY                         = 0x00000011,
14094 SPI_PERF_GS_CRAWLER_STALL                = 0x00000012,
14095 SPI_PERF_GS_EVENT_WAVE                   = 0x00000013,
14096 SPI_PERF_GS_WAVE                         = 0x00000014,
14097 SPI_PERF_GS_PERS_UPD_FULL0               = 0x00000015,
14098 SPI_PERF_GS_PERS_UPD_FULL1               = 0x00000016,
14099 SPI_PERF_GS_FIRST_SUBGRP                 = 0x00000017,
14100 SPI_PERF_GS_LAST_SUBGRP                  = 0x00000018,
14101 SPI_PERF_ES_WINDOW_VALID                 = 0x00000019,
14102 SPI_PERF_ES_BUSY                         = 0x0000001a,
14103 SPI_PERF_ES_CRAWLER_STALL                = 0x0000001b,
14104 SPI_PERF_ES_FIRST_WAVE                   = 0x0000001c,
14105 SPI_PERF_ES_LAST_WAVE                    = 0x0000001d,
14106 SPI_PERF_ES_LSHS_DEALLOC                 = 0x0000001e,
14107 SPI_PERF_ES_EVENT_WAVE                   = 0x0000001f,
14108 SPI_PERF_ES_WAVE                         = 0x00000020,
14109 SPI_PERF_ES_PERS_UPD_FULL0               = 0x00000021,
14110 SPI_PERF_ES_PERS_UPD_FULL1               = 0x00000022,
14111 SPI_PERF_ES_FIRST_SUBGRP                 = 0x00000023,
14112 SPI_PERF_ES_LAST_SUBGRP                  = 0x00000024,
14113 SPI_PERF_HS_WINDOW_VALID                 = 0x00000025,
14114 SPI_PERF_HS_BUSY                         = 0x00000026,
14115 SPI_PERF_HS_CRAWLER_STALL                = 0x00000027,
14116 SPI_PERF_HS_FIRST_WAVE                   = 0x00000028,
14117 SPI_PERF_HS_LAST_WAVE                    = 0x00000029,
14118 SPI_PERF_HS_LSHS_DEALLOC                 = 0x0000002a,
14119 SPI_PERF_HS_EVENT_WAVE                   = 0x0000002b,
14120 SPI_PERF_HS_WAVE                         = 0x0000002c,
14121 SPI_PERF_HS_PERS_UPD_FULL0               = 0x0000002d,
14122 SPI_PERF_HS_PERS_UPD_FULL1               = 0x0000002e,
14123 SPI_PERF_LS_WINDOW_VALID                 = 0x0000002f,
14124 SPI_PERF_LS_BUSY                         = 0x00000030,
14125 SPI_PERF_LS_CRAWLER_STALL                = 0x00000031,
14126 SPI_PERF_LS_FIRST_WAVE                   = 0x00000032,
14127 SPI_PERF_LS_LAST_WAVE                    = 0x00000033,
14128 SPI_PERF_OFFCHIP_LDS_STALL_LS            = 0x00000034,
14129 SPI_PERF_LS_EVENT_WAVE                   = 0x00000035,
14130 SPI_PERF_LS_WAVE                         = 0x00000036,
14131 SPI_PERF_LS_PERS_UPD_FULL0               = 0x00000037,
14132 SPI_PERF_LS_PERS_UPD_FULL1               = 0x00000038,
14133 SPI_PERF_CSG_WINDOW_VALID                = 0x00000039,
14134 SPI_PERF_CSG_BUSY                        = 0x0000003a,
14135 SPI_PERF_CSG_NUM_THREADGROUPS            = 0x0000003b,
14136 SPI_PERF_CSG_CRAWLER_STALL               = 0x0000003c,
14137 SPI_PERF_CSG_EVENT_WAVE                  = 0x0000003d,
14138 SPI_PERF_CSG_WAVE                        = 0x0000003e,
14139 SPI_PERF_CSN_WINDOW_VALID                = 0x0000003f,
14140 SPI_PERF_CSN_BUSY                        = 0x00000040,
14141 SPI_PERF_CSN_NUM_THREADGROUPS            = 0x00000041,
14142 SPI_PERF_CSN_CRAWLER_STALL               = 0x00000042,
14143 SPI_PERF_CSN_EVENT_WAVE                  = 0x00000043,
14144 SPI_PERF_CSN_WAVE                        = 0x00000044,
14145 SPI_PERF_PS_CTL_WINDOW_VALID             = 0x00000045,
14146 SPI_PERF_PS_CTL_BUSY                     = 0x00000046,
14147 SPI_PERF_PS_CTL_ACTIVE                   = 0x00000047,
14148 SPI_PERF_PS_CTL_DEALLOC_BIN0             = 0x00000048,
14149 SPI_PERF_PS_CTL_FPOS_BIN1_STALL          = 0x00000049,
14150 SPI_PERF_PS_CTL_EVENT_WAVE               = 0x0000004a,
14151 SPI_PERF_PS_CTL_WAVE                     = 0x0000004b,
14152 SPI_PERF_PS_CTL_OPT_WAVE                 = 0x0000004c,
14153 SPI_PERF_PS_CTL_PASS_BIN0                = 0x0000004d,
14154 SPI_PERF_PS_CTL_PASS_BIN1                = 0x0000004e,
14155 SPI_PERF_PS_CTL_FPOS_BIN2                = 0x0000004f,
14156 SPI_PERF_PS_CTL_PRIM_BIN0                = 0x00000050,
14157 SPI_PERF_PS_CTL_PRIM_BIN1                = 0x00000051,
14158 SPI_PERF_PS_CTL_CNF_BIN2                 = 0x00000052,
14159 SPI_PERF_PS_CTL_CNF_BIN3                 = 0x00000053,
14160 SPI_PERF_PS_CTL_CRAWLER_STALL            = 0x00000054,
14161 SPI_PERF_PS_CTL_LDS_RES_FULL             = 0x00000055,
14162 SPI_PERF_PS_PERS_UPD_FULL0               = 0x00000056,
14163 SPI_PERF_PS_PERS_UPD_FULL1               = 0x00000057,
14164 SPI_PERF_PIX_ALLOC_PEND_CNT              = 0x00000058,
14165 SPI_PERF_PIX_ALLOC_SCB_STALL             = 0x00000059,
14166 SPI_PERF_PIX_ALLOC_DB0_STALL             = 0x0000005a,
14167 SPI_PERF_PIX_ALLOC_DB1_STALL             = 0x0000005b,
14168 SPI_PERF_PIX_ALLOC_DB2_STALL             = 0x0000005c,
14169 SPI_PERF_PIX_ALLOC_DB3_STALL             = 0x0000005d,
14170 SPI_PERF_LDS0_PC_VALID                   = 0x0000005e,
14171 SPI_PERF_LDS1_PC_VALID                   = 0x0000005f,
14172 SPI_PERF_RA_PIPE_REQ_BIN2                = 0x00000060,
14173 SPI_PERF_RA_TASK_REQ_BIN3                = 0x00000061,
14174 SPI_PERF_RA_WR_CTL_FULL                  = 0x00000062,
14175 SPI_PERF_RA_REQ_NO_ALLOC                 = 0x00000063,
14176 SPI_PERF_RA_REQ_NO_ALLOC_PS              = 0x00000064,
14177 SPI_PERF_RA_REQ_NO_ALLOC_VS              = 0x00000065,
14178 SPI_PERF_RA_REQ_NO_ALLOC_GS              = 0x00000066,
14179 SPI_PERF_RA_REQ_NO_ALLOC_ES              = 0x00000067,
14180 SPI_PERF_RA_REQ_NO_ALLOC_HS              = 0x00000068,
14181 SPI_PERF_RA_REQ_NO_ALLOC_LS              = 0x00000069,
14182 SPI_PERF_RA_REQ_NO_ALLOC_CSG             = 0x0000006a,
14183 SPI_PERF_RA_REQ_NO_ALLOC_CSN             = 0x0000006b,
14184 SPI_PERF_RA_RES_STALL_PS                 = 0x0000006c,
14185 SPI_PERF_RA_RES_STALL_VS                 = 0x0000006d,
14186 SPI_PERF_RA_RES_STALL_GS                 = 0x0000006e,
14187 SPI_PERF_RA_RES_STALL_ES                 = 0x0000006f,
14188 SPI_PERF_RA_RES_STALL_HS                 = 0x00000070,
14189 SPI_PERF_RA_RES_STALL_LS                 = 0x00000071,
14190 SPI_PERF_RA_RES_STALL_CSG                = 0x00000072,
14191 SPI_PERF_RA_RES_STALL_CSN                = 0x00000073,
14192 SPI_PERF_RA_TMP_STALL_PS                 = 0x00000074,
14193 SPI_PERF_RA_TMP_STALL_VS                 = 0x00000075,
14194 SPI_PERF_RA_TMP_STALL_GS                 = 0x00000076,
14195 SPI_PERF_RA_TMP_STALL_ES                 = 0x00000077,
14196 SPI_PERF_RA_TMP_STALL_HS                 = 0x00000078,
14197 SPI_PERF_RA_TMP_STALL_LS                 = 0x00000079,
14198 SPI_PERF_RA_TMP_STALL_CSG                = 0x0000007a,
14199 SPI_PERF_RA_TMP_STALL_CSN                = 0x0000007b,
14200 SPI_PERF_RA_WAVE_SIMD_FULL_PS            = 0x0000007c,
14201 SPI_PERF_RA_WAVE_SIMD_FULL_VS            = 0x0000007d,
14202 SPI_PERF_RA_WAVE_SIMD_FULL_GS            = 0x0000007e,
14203 SPI_PERF_RA_WAVE_SIMD_FULL_ES            = 0x0000007f,
14204 SPI_PERF_RA_WAVE_SIMD_FULL_HS            = 0x00000080,
14205 SPI_PERF_RA_WAVE_SIMD_FULL_LS            = 0x00000081,
14206 SPI_PERF_RA_WAVE_SIMD_FULL_CSG           = 0x00000082,
14207 SPI_PERF_RA_WAVE_SIMD_FULL_CSN           = 0x00000083,
14208 SPI_PERF_RA_VGPR_SIMD_FULL_PS            = 0x00000084,
14209 SPI_PERF_RA_VGPR_SIMD_FULL_VS            = 0x00000085,
14210 SPI_PERF_RA_VGPR_SIMD_FULL_GS            = 0x00000086,
14211 SPI_PERF_RA_VGPR_SIMD_FULL_ES            = 0x00000087,
14212 SPI_PERF_RA_VGPR_SIMD_FULL_HS            = 0x00000088,
14213 SPI_PERF_RA_VGPR_SIMD_FULL_LS            = 0x00000089,
14214 SPI_PERF_RA_VGPR_SIMD_FULL_CSG           = 0x0000008a,
14215 SPI_PERF_RA_VGPR_SIMD_FULL_CSN           = 0x0000008b,
14216 SPI_PERF_RA_SGPR_SIMD_FULL_PS            = 0x0000008c,
14217 SPI_PERF_RA_SGPR_SIMD_FULL_VS            = 0x0000008d,
14218 SPI_PERF_RA_SGPR_SIMD_FULL_GS            = 0x0000008e,
14219 SPI_PERF_RA_SGPR_SIMD_FULL_ES            = 0x0000008f,
14220 SPI_PERF_RA_SGPR_SIMD_FULL_HS            = 0x00000090,
14221 SPI_PERF_RA_SGPR_SIMD_FULL_LS            = 0x00000091,
14222 SPI_PERF_RA_SGPR_SIMD_FULL_CSG           = 0x00000092,
14223 SPI_PERF_RA_SGPR_SIMD_FULL_CSN           = 0x00000093,
14224 SPI_PERF_RA_LDS_CU_FULL_PS               = 0x00000094,
14225 SPI_PERF_RA_LDS_CU_FULL_LS               = 0x00000095,
14226 SPI_PERF_RA_LDS_CU_FULL_ES               = 0x00000096,
14227 SPI_PERF_RA_LDS_CU_FULL_CSG              = 0x00000097,
14228 SPI_PERF_RA_LDS_CU_FULL_CSN              = 0x00000098,
14229 SPI_PERF_RA_BAR_CU_FULL_HS               = 0x00000099,
14230 SPI_PERF_RA_BAR_CU_FULL_CSG              = 0x0000009a,
14231 SPI_PERF_RA_BAR_CU_FULL_CSN              = 0x0000009b,
14232 SPI_PERF_RA_BULKY_CU_FULL_CSG            = 0x0000009c,
14233 SPI_PERF_RA_BULKY_CU_FULL_CSN            = 0x0000009d,
14234 SPI_PERF_RA_TGLIM_CU_FULL_CSG            = 0x0000009e,
14235 SPI_PERF_RA_TGLIM_CU_FULL_CSN            = 0x0000009f,
14236 SPI_PERF_RA_WVLIM_STALL_PS               = 0x000000a0,
14237 SPI_PERF_RA_WVLIM_STALL_VS               = 0x000000a1,
14238 SPI_PERF_RA_WVLIM_STALL_GS               = 0x000000a2,
14239 SPI_PERF_RA_WVLIM_STALL_ES               = 0x000000a3,
14240 SPI_PERF_RA_WVLIM_STALL_HS               = 0x000000a4,
14241 SPI_PERF_RA_WVLIM_STALL_LS               = 0x000000a5,
14242 SPI_PERF_RA_WVLIM_STALL_CSG              = 0x000000a6,
14243 SPI_PERF_RA_WVLIM_STALL_CSN              = 0x000000a7,
14244 SPI_PERF_RA_PS_LOCK_NA                   = 0x000000a8,
14245 SPI_PERF_RA_VS_LOCK                      = 0x000000a9,
14246 SPI_PERF_RA_GS_LOCK                      = 0x000000aa,
14247 SPI_PERF_RA_ES_LOCK                      = 0x000000ab,
14248 SPI_PERF_RA_HS_LOCK                      = 0x000000ac,
14249 SPI_PERF_RA_LS_LOCK                      = 0x000000ad,
14250 SPI_PERF_RA_CSG_LOCK                     = 0x000000ae,
14251 SPI_PERF_RA_CSN_LOCK                     = 0x000000af,
14252 SPI_PERF_RA_RSV_UPD                      = 0x000000b0,
14253 SPI_PERF_EXP_ARB_COL_CNT                 = 0x000000b1,
14254 SPI_PERF_EXP_ARB_PAR_CNT                 = 0x000000b2,
14255 SPI_PERF_EXP_ARB_POS_CNT                 = 0x000000b3,
14256 SPI_PERF_EXP_ARB_GDS_CNT                 = 0x000000b4,
14257 SPI_PERF_CLKGATE_BUSY_STALL              = 0x000000b5,
14258 SPI_PERF_CLKGATE_ACTIVE_STALL            = 0x000000b6,
14259 SPI_PERF_CLKGATE_ALL_CLOCKS_ON           = 0x000000b7,
14260 SPI_PERF_CLKGATE_CGTT_DYN_ON             = 0x000000b8,
14261 SPI_PERF_CLKGATE_CGTT_REG_ON             = 0x000000b9,
14262 SPI_PERF_NUM_VS_POS_EXPORTS              = 0x000000ba,
14263 SPI_PERF_NUM_VS_PARAM_EXPORTS            = 0x000000bb,
14264 SPI_PERF_NUM_PS_COL_EXPORTS              = 0x000000bc,
14265 SPI_PERF_ES_GRP_FIFO_FULL                = 0x000000bd,
14266 SPI_PERF_GS_GRP_FIFO_FULL                = 0x000000be,
14267 SPI_PERF_HS_GRP_FIFO_FULL                = 0x000000bf,
14268 SPI_PERF_LS_GRP_FIFO_FULL                = 0x000000c0,
14269 SPI_PERF_VS_ALLOC_CNT                    = 0x000000c1,
14270 SPI_PERF_VS_LATE_ALLOC_ACCUM             = 0x000000c2,
14271 SPI_PERF_PC_ALLOC_CNT                    = 0x000000c3,
14272 SPI_PERF_PC_ALLOC_ACCUM                  = 0x000000c4,
14273 } SPI_PERFCNT_SEL;
14274 
14275 /*
14276  * SPI_SHADER_FORMAT enum
14277  */
14278 
14279 typedef enum SPI_SHADER_FORMAT {
14280 SPI_SHADER_NONE                          = 0x00000000,
14281 SPI_SHADER_1COMP                         = 0x00000001,
14282 SPI_SHADER_2COMP                         = 0x00000002,
14283 SPI_SHADER_4COMPRESS                     = 0x00000003,
14284 SPI_SHADER_4COMP                         = 0x00000004,
14285 } SPI_SHADER_FORMAT;
14286 
14287 /*
14288  * SPI_SHADER_EX_FORMAT enum
14289  */
14290 
14291 typedef enum SPI_SHADER_EX_FORMAT {
14292 SPI_SHADER_ZERO                          = 0x00000000,
14293 SPI_SHADER_32_R                          = 0x00000001,
14294 SPI_SHADER_32_GR                         = 0x00000002,
14295 SPI_SHADER_32_AR                         = 0x00000003,
14296 SPI_SHADER_FP16_ABGR                     = 0x00000004,
14297 SPI_SHADER_UNORM16_ABGR                  = 0x00000005,
14298 SPI_SHADER_SNORM16_ABGR                  = 0x00000006,
14299 SPI_SHADER_UINT16_ABGR                   = 0x00000007,
14300 SPI_SHADER_SINT16_ABGR                   = 0x00000008,
14301 SPI_SHADER_32_ABGR                       = 0x00000009,
14302 } SPI_SHADER_EX_FORMAT;
14303 
14304 /*
14305  * CLKGATE_SM_MODE enum
14306  */
14307 
14308 typedef enum CLKGATE_SM_MODE {
14309 ON_SEQ                                   = 0x00000000,
14310 OFF_SEQ                                  = 0x00000001,
14311 PROG_SEQ                                 = 0x00000002,
14312 READ_SEQ                                 = 0x00000003,
14313 SM_MODE_RESERVED                         = 0x00000004,
14314 } CLKGATE_SM_MODE;
14315 
14316 /*
14317  * CLKGATE_BASE_MODE enum
14318  */
14319 
14320 typedef enum CLKGATE_BASE_MODE {
14321 MULT_8                                   = 0x00000000,
14322 MULT_16                                  = 0x00000001,
14323 } CLKGATE_BASE_MODE;
14324 
14325 /*******************************************************
14326  * SQ Enums
14327  *******************************************************/
14328 
14329 /*
14330  * SQ_TEX_CLAMP enum
14331  */
14332 
14333 typedef enum SQ_TEX_CLAMP {
14334 SQ_TEX_WRAP                              = 0x00000000,
14335 SQ_TEX_MIRROR                            = 0x00000001,
14336 SQ_TEX_CLAMP_LAST_TEXEL                  = 0x00000002,
14337 SQ_TEX_MIRROR_ONCE_LAST_TEXEL            = 0x00000003,
14338 SQ_TEX_CLAMP_HALF_BORDER                 = 0x00000004,
14339 SQ_TEX_MIRROR_ONCE_HALF_BORDER           = 0x00000005,
14340 SQ_TEX_CLAMP_BORDER                      = 0x00000006,
14341 SQ_TEX_MIRROR_ONCE_BORDER                = 0x00000007,
14342 } SQ_TEX_CLAMP;
14343 
14344 /*
14345  * SQ_TEX_XY_FILTER enum
14346  */
14347 
14348 typedef enum SQ_TEX_XY_FILTER {
14349 SQ_TEX_XY_FILTER_POINT                   = 0x00000000,
14350 SQ_TEX_XY_FILTER_BILINEAR                = 0x00000001,
14351 SQ_TEX_XY_FILTER_ANISO_POINT             = 0x00000002,
14352 SQ_TEX_XY_FILTER_ANISO_BILINEAR          = 0x00000003,
14353 } SQ_TEX_XY_FILTER;
14354 
14355 /*
14356  * SQ_TEX_Z_FILTER enum
14357  */
14358 
14359 typedef enum SQ_TEX_Z_FILTER {
14360 SQ_TEX_Z_FILTER_NONE                     = 0x00000000,
14361 SQ_TEX_Z_FILTER_POINT                    = 0x00000001,
14362 SQ_TEX_Z_FILTER_LINEAR                   = 0x00000002,
14363 } SQ_TEX_Z_FILTER;
14364 
14365 /*
14366  * SQ_TEX_MIP_FILTER enum
14367  */
14368 
14369 typedef enum SQ_TEX_MIP_FILTER {
14370 SQ_TEX_MIP_FILTER_NONE                   = 0x00000000,
14371 SQ_TEX_MIP_FILTER_POINT                  = 0x00000001,
14372 SQ_TEX_MIP_FILTER_LINEAR                 = 0x00000002,
14373 SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ        = 0x00000003,
14374 } SQ_TEX_MIP_FILTER;
14375 
14376 /*
14377  * SQ_TEX_ANISO_RATIO enum
14378  */
14379 
14380 typedef enum SQ_TEX_ANISO_RATIO {
14381 SQ_TEX_ANISO_RATIO_1                     = 0x00000000,
14382 SQ_TEX_ANISO_RATIO_2                     = 0x00000001,
14383 SQ_TEX_ANISO_RATIO_4                     = 0x00000002,
14384 SQ_TEX_ANISO_RATIO_8                     = 0x00000003,
14385 SQ_TEX_ANISO_RATIO_16                    = 0x00000004,
14386 } SQ_TEX_ANISO_RATIO;
14387 
14388 /*
14389  * SQ_TEX_DEPTH_COMPARE enum
14390  */
14391 
14392 typedef enum SQ_TEX_DEPTH_COMPARE {
14393 SQ_TEX_DEPTH_COMPARE_NEVER               = 0x00000000,
14394 SQ_TEX_DEPTH_COMPARE_LESS                = 0x00000001,
14395 SQ_TEX_DEPTH_COMPARE_EQUAL               = 0x00000002,
14396 SQ_TEX_DEPTH_COMPARE_LESSEQUAL           = 0x00000003,
14397 SQ_TEX_DEPTH_COMPARE_GREATER             = 0x00000004,
14398 SQ_TEX_DEPTH_COMPARE_NOTEQUAL            = 0x00000005,
14399 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL        = 0x00000006,
14400 SQ_TEX_DEPTH_COMPARE_ALWAYS              = 0x00000007,
14401 } SQ_TEX_DEPTH_COMPARE;
14402 
14403 /*
14404  * SQ_TEX_BORDER_COLOR enum
14405  */
14406 
14407 typedef enum SQ_TEX_BORDER_COLOR {
14408 SQ_TEX_BORDER_COLOR_TRANS_BLACK          = 0x00000000,
14409 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK         = 0x00000001,
14410 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE         = 0x00000002,
14411 SQ_TEX_BORDER_COLOR_REGISTER             = 0x00000003,
14412 } SQ_TEX_BORDER_COLOR;
14413 
14414 /*
14415  * SQ_RSRC_BUF_TYPE enum
14416  */
14417 
14418 typedef enum SQ_RSRC_BUF_TYPE {
14419 SQ_RSRC_BUF                              = 0x00000000,
14420 SQ_RSRC_BUF_RSVD_1                       = 0x00000001,
14421 SQ_RSRC_BUF_RSVD_2                       = 0x00000002,
14422 SQ_RSRC_BUF_RSVD_3                       = 0x00000003,
14423 } SQ_RSRC_BUF_TYPE;
14424 
14425 /*
14426  * SQ_RSRC_IMG_TYPE enum
14427  */
14428 
14429 typedef enum SQ_RSRC_IMG_TYPE {
14430 SQ_RSRC_IMG_RSVD_0                       = 0x00000000,
14431 SQ_RSRC_IMG_RSVD_1                       = 0x00000001,
14432 SQ_RSRC_IMG_RSVD_2                       = 0x00000002,
14433 SQ_RSRC_IMG_RSVD_3                       = 0x00000003,
14434 SQ_RSRC_IMG_RSVD_4                       = 0x00000004,
14435 SQ_RSRC_IMG_RSVD_5                       = 0x00000005,
14436 SQ_RSRC_IMG_RSVD_6                       = 0x00000006,
14437 SQ_RSRC_IMG_RSVD_7                       = 0x00000007,
14438 SQ_RSRC_IMG_1D                           = 0x00000008,
14439 SQ_RSRC_IMG_2D                           = 0x00000009,
14440 SQ_RSRC_IMG_3D                           = 0x0000000a,
14441 SQ_RSRC_IMG_CUBE                         = 0x0000000b,
14442 SQ_RSRC_IMG_1D_ARRAY                     = 0x0000000c,
14443 SQ_RSRC_IMG_2D_ARRAY                     = 0x0000000d,
14444 SQ_RSRC_IMG_2D_MSAA                      = 0x0000000e,
14445 SQ_RSRC_IMG_2D_MSAA_ARRAY                = 0x0000000f,
14446 } SQ_RSRC_IMG_TYPE;
14447 
14448 /*
14449  * SQ_RSRC_FLAT_TYPE enum
14450  */
14451 
14452 typedef enum SQ_RSRC_FLAT_TYPE {
14453 SQ_RSRC_FLAT_RSVD_0                      = 0x00000000,
14454 SQ_RSRC_FLAT                             = 0x00000001,
14455 SQ_RSRC_FLAT_RSVD_2                      = 0x00000002,
14456 SQ_RSRC_FLAT_RSVD_3                      = 0x00000003,
14457 } SQ_RSRC_FLAT_TYPE;
14458 
14459 /*
14460  * SQ_IMG_FILTER_TYPE enum
14461  */
14462 
14463 typedef enum SQ_IMG_FILTER_TYPE {
14464 SQ_IMG_FILTER_MODE_BLEND                 = 0x00000000,
14465 SQ_IMG_FILTER_MODE_MIN                   = 0x00000001,
14466 SQ_IMG_FILTER_MODE_MAX                   = 0x00000002,
14467 } SQ_IMG_FILTER_TYPE;
14468 
14469 /*
14470  * SQ_SEL_XYZW01 enum
14471  */
14472 
14473 typedef enum SQ_SEL_XYZW01 {
14474 SQ_SEL_0                                 = 0x00000000,
14475 SQ_SEL_1                                 = 0x00000001,
14476 SQ_SEL_RESERVED_0                        = 0x00000002,
14477 SQ_SEL_RESERVED_1                        = 0x00000003,
14478 SQ_SEL_X                                 = 0x00000004,
14479 SQ_SEL_Y                                 = 0x00000005,
14480 SQ_SEL_Z                                 = 0x00000006,
14481 SQ_SEL_W                                 = 0x00000007,
14482 } SQ_SEL_XYZW01;
14483 
14484 /*
14485  * SQ_WAVE_TYPE enum
14486  */
14487 
14488 typedef enum SQ_WAVE_TYPE {
14489 SQ_WAVE_TYPE_PS                          = 0x00000000,
14490 SQ_WAVE_TYPE_VS                          = 0x00000001,
14491 SQ_WAVE_TYPE_GS                          = 0x00000002,
14492 SQ_WAVE_TYPE_ES                          = 0x00000003,
14493 SQ_WAVE_TYPE_HS                          = 0x00000004,
14494 SQ_WAVE_TYPE_LS                          = 0x00000005,
14495 SQ_WAVE_TYPE_CS                          = 0x00000006,
14496 SQ_WAVE_TYPE_PS1                         = 0x00000007,
14497 } SQ_WAVE_TYPE;
14498 
14499 /*
14500  * SQ_THREAD_TRACE_TOKEN_TYPE enum
14501  */
14502 
14503 typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
14504 SQ_THREAD_TRACE_TOKEN_MISC               = 0x00000000,
14505 SQ_THREAD_TRACE_TOKEN_TIMESTAMP          = 0x00000001,
14506 SQ_THREAD_TRACE_TOKEN_REG                = 0x00000002,
14507 SQ_THREAD_TRACE_TOKEN_WAVE_START         = 0x00000003,
14508 SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC         = 0x00000004,
14509 SQ_THREAD_TRACE_TOKEN_REG_CSPRIV         = 0x00000005,
14510 SQ_THREAD_TRACE_TOKEN_WAVE_END           = 0x00000006,
14511 SQ_THREAD_TRACE_TOKEN_EVENT              = 0x00000007,
14512 SQ_THREAD_TRACE_TOKEN_EVENT_CS           = 0x00000008,
14513 SQ_THREAD_TRACE_TOKEN_EVENT_GFX1         = 0x00000009,
14514 SQ_THREAD_TRACE_TOKEN_INST               = 0x0000000a,
14515 SQ_THREAD_TRACE_TOKEN_INST_PC            = 0x0000000b,
14516 SQ_THREAD_TRACE_TOKEN_INST_USERDATA      = 0x0000000c,
14517 SQ_THREAD_TRACE_TOKEN_ISSUE              = 0x0000000d,
14518 SQ_THREAD_TRACE_TOKEN_PERF               = 0x0000000e,
14519 SQ_THREAD_TRACE_TOKEN_REG_CS             = 0x0000000f,
14520 } SQ_THREAD_TRACE_TOKEN_TYPE;
14521 
14522 /*
14523  * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum
14524  */
14525 
14526 typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
14527 SQ_THREAD_TRACE_MISC_TOKEN_TIME          = 0x00000000,
14528 SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET    = 0x00000001,
14529 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST   = 0x00000002,
14530 SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC     = 0x00000003,
14531 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN  = 0x00000004,
14532 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END  = 0x00000005,
14533 SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX       = 0x00000006,
14534 SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN    = 0x00000007,
14535 } SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
14536 
14537 /*
14538  * SQ_THREAD_TRACE_INST_TYPE enum
14539  */
14540 
14541 typedef enum SQ_THREAD_TRACE_INST_TYPE {
14542 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD        = 0x00000000,
14543 SQ_THREAD_TRACE_INST_TYPE_SALU_32        = 0x00000001,
14544 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD        = 0x00000002,
14545 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR        = 0x00000003,
14546 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR        = 0x00000004,
14547 SQ_THREAD_TRACE_INST_TYPE_VALU_32        = 0x00000005,
14548 SQ_THREAD_TRACE_INST_TYPE_LDS            = 0x00000006,
14549 SQ_THREAD_TRACE_INST_TYPE_PC             = 0x00000007,
14550 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS     = 0x00000008,
14551 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX     = 0x00000009,
14552 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL  = 0x0000000a,
14553 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS  = 0x0000000b,
14554 SQ_THREAD_TRACE_INST_TYPE_JUMP           = 0x0000000c,
14555 SQ_THREAD_TRACE_INST_TYPE_NEXT           = 0x0000000d,
14556 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD        = 0x0000000e,
14557 SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG      = 0x0000000f,
14558 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR        = 0x00000010,
14559 SQ_THREAD_TRACE_INST_TYPE_SALU_64        = 0x00000011,
14560 SQ_THREAD_TRACE_INST_TYPE_VALU_64        = 0x00000012,
14561 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY  = 0x00000013,
14562 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY  = 0x00000014,
14563 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY  = 0x00000015,
14564 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY  = 0x00000016,
14565 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY  = 0x00000017,
14566 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY  = 0x00000018,
14567 SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT     = 0x00000019,
14568 } SQ_THREAD_TRACE_INST_TYPE;
14569 
14570 /*
14571  * SQ_THREAD_TRACE_REG_TYPE enum
14572  */
14573 
14574 typedef enum SQ_THREAD_TRACE_REG_TYPE {
14575 SQ_THREAD_TRACE_REG_TYPE_EVENT           = 0x00000000,
14576 SQ_THREAD_TRACE_REG_TYPE_DRAW            = 0x00000001,
14577 SQ_THREAD_TRACE_REG_TYPE_DISPATCH        = 0x00000002,
14578 SQ_THREAD_TRACE_REG_TYPE_USERDATA        = 0x00000003,
14579 SQ_THREAD_TRACE_REG_TYPE_MARKER          = 0x00000004,
14580 SQ_THREAD_TRACE_REG_TYPE_GFXDEC          = 0x00000005,
14581 SQ_THREAD_TRACE_REG_TYPE_SHDEC           = 0x00000006,
14582 SQ_THREAD_TRACE_REG_TYPE_OTHER           = 0x00000007,
14583 } SQ_THREAD_TRACE_REG_TYPE;
14584 
14585 /*
14586  * SQ_THREAD_TRACE_REG_OP enum
14587  */
14588 
14589 typedef enum SQ_THREAD_TRACE_REG_OP {
14590 SQ_THREAD_TRACE_REG_OP_READ              = 0x00000000,
14591 SQ_THREAD_TRACE_REG_OP_WRITE             = 0x00000001,
14592 } SQ_THREAD_TRACE_REG_OP;
14593 
14594 /*
14595  * SQ_THREAD_TRACE_MODE_SEL enum
14596  */
14597 
14598 typedef enum SQ_THREAD_TRACE_MODE_SEL {
14599 SQ_THREAD_TRACE_MODE_OFF                 = 0x00000000,
14600 SQ_THREAD_TRACE_MODE_ON                  = 0x00000001,
14601 } SQ_THREAD_TRACE_MODE_SEL;
14602 
14603 /*
14604  * SQ_THREAD_TRACE_CAPTURE_MODE enum
14605  */
14606 
14607 typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
14608 SQ_THREAD_TRACE_CAPTURE_MODE_ALL         = 0x00000000,
14609 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT      = 0x00000001,
14610 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL  = 0x00000002,
14611 } SQ_THREAD_TRACE_CAPTURE_MODE;
14612 
14613 /*
14614  * SQ_THREAD_TRACE_VM_ID_MASK enum
14615  */
14616 
14617 typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
14618 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE        = 0x00000000,
14619 SQ_THREAD_TRACE_VM_ID_MASK_ALL           = 0x00000001,
14620 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL  = 0x00000002,
14621 } SQ_THREAD_TRACE_VM_ID_MASK;
14622 
14623 /*
14624  * SQ_THREAD_TRACE_WAVE_MASK enum
14625  */
14626 
14627 typedef enum SQ_THREAD_TRACE_WAVE_MASK {
14628 SQ_THREAD_TRACE_WAVE_MASK_NONE           = 0x00000000,
14629 SQ_THREAD_TRACE_WAVE_MASK_ALL            = 0x00000001,
14630 } SQ_THREAD_TRACE_WAVE_MASK;
14631 
14632 /*
14633  * SQ_THREAD_TRACE_ISSUE enum
14634  */
14635 
14636 typedef enum SQ_THREAD_TRACE_ISSUE {
14637 SQ_THREAD_TRACE_ISSUE_NULL               = 0x00000000,
14638 SQ_THREAD_TRACE_ISSUE_STALL              = 0x00000001,
14639 SQ_THREAD_TRACE_ISSUE_INST               = 0x00000002,
14640 SQ_THREAD_TRACE_ISSUE_IMMED              = 0x00000003,
14641 } SQ_THREAD_TRACE_ISSUE;
14642 
14643 /*
14644  * SQ_THREAD_TRACE_ISSUE_MASK enum
14645  */
14646 
14647 typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
14648 SQ_THREAD_TRACE_ISSUE_MASK_ALL           = 0x00000000,
14649 SQ_THREAD_TRACE_ISSUE_MASK_STALLED       = 0x00000001,
14650 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED  = 0x00000002,
14651 SQ_THREAD_TRACE_ISSUE_MASK_IMMED         = 0x00000003,
14652 } SQ_THREAD_TRACE_ISSUE_MASK;
14653 
14654 /*
14655  * SQ_PERF_SEL enum
14656  */
14657 
14658 typedef enum SQ_PERF_SEL {
14659 SQ_PERF_SEL_NONE                         = 0x00000000,
14660 SQ_PERF_SEL_ACCUM_PREV                   = 0x00000001,
14661 SQ_PERF_SEL_CYCLES                       = 0x00000002,
14662 SQ_PERF_SEL_BUSY_CYCLES                  = 0x00000003,
14663 SQ_PERF_SEL_WAVES                        = 0x00000004,
14664 SQ_PERF_SEL_LEVEL_WAVES                  = 0x00000005,
14665 SQ_PERF_SEL_WAVES_EQ_64                  = 0x00000006,
14666 SQ_PERF_SEL_WAVES_LT_64                  = 0x00000007,
14667 SQ_PERF_SEL_WAVES_LT_48                  = 0x00000008,
14668 SQ_PERF_SEL_WAVES_LT_32                  = 0x00000009,
14669 SQ_PERF_SEL_WAVES_LT_16                  = 0x0000000a,
14670 SQ_PERF_SEL_WAVES_CU                     = 0x0000000b,
14671 SQ_PERF_SEL_LEVEL_WAVES_CU               = 0x0000000c,
14672 SQ_PERF_SEL_BUSY_CU_CYCLES               = 0x0000000d,
14673 SQ_PERF_SEL_ITEMS                        = 0x0000000e,
14674 SQ_PERF_SEL_QUADS                        = 0x0000000f,
14675 SQ_PERF_SEL_EVENTS                       = 0x00000010,
14676 SQ_PERF_SEL_SURF_SYNCS                   = 0x00000011,
14677 SQ_PERF_SEL_TTRACE_REQS                  = 0x00000012,
14678 SQ_PERF_SEL_TTRACE_INFLIGHT_REQS         = 0x00000013,
14679 SQ_PERF_SEL_TTRACE_STALL                 = 0x00000014,
14680 SQ_PERF_SEL_MSG_CNTR                     = 0x00000015,
14681 SQ_PERF_SEL_MSG_PERF                     = 0x00000016,
14682 SQ_PERF_SEL_MSG_GSCNT                    = 0x00000017,
14683 SQ_PERF_SEL_MSG_INTERRUPT                = 0x00000018,
14684 SQ_PERF_SEL_INSTS                        = 0x00000019,
14685 SQ_PERF_SEL_INSTS_VALU                   = 0x0000001a,
14686 SQ_PERF_SEL_INSTS_VMEM_WR                = 0x0000001b,
14687 SQ_PERF_SEL_INSTS_VMEM_RD                = 0x0000001c,
14688 SQ_PERF_SEL_INSTS_VMEM                   = 0x0000001d,
14689 SQ_PERF_SEL_INSTS_SALU                   = 0x0000001e,
14690 SQ_PERF_SEL_INSTS_SMEM                   = 0x0000001f,
14691 SQ_PERF_SEL_INSTS_FLAT                   = 0x00000020,
14692 SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY          = 0x00000021,
14693 SQ_PERF_SEL_INSTS_LDS                    = 0x00000022,
14694 SQ_PERF_SEL_INSTS_GDS                    = 0x00000023,
14695 SQ_PERF_SEL_INSTS_EXP                    = 0x00000024,
14696 SQ_PERF_SEL_INSTS_EXP_GDS                = 0x00000025,
14697 SQ_PERF_SEL_INSTS_BRANCH                 = 0x00000026,
14698 SQ_PERF_SEL_INSTS_SENDMSG                = 0x00000027,
14699 SQ_PERF_SEL_INSTS_VSKIPPED               = 0x00000028,
14700 SQ_PERF_SEL_INST_LEVEL_VMEM              = 0x00000029,
14701 SQ_PERF_SEL_INST_LEVEL_SMEM              = 0x0000002a,
14702 SQ_PERF_SEL_INST_LEVEL_LDS               = 0x0000002b,
14703 SQ_PERF_SEL_INST_LEVEL_GDS               = 0x0000002c,
14704 SQ_PERF_SEL_INST_LEVEL_EXP               = 0x0000002d,
14705 SQ_PERF_SEL_WAVE_CYCLES                  = 0x0000002e,
14706 SQ_PERF_SEL_WAVE_READY                   = 0x0000002f,
14707 SQ_PERF_SEL_WAIT_CNT_VM                  = 0x00000030,
14708 SQ_PERF_SEL_WAIT_CNT_LGKM                = 0x00000031,
14709 SQ_PERF_SEL_WAIT_CNT_EXP                 = 0x00000032,
14710 SQ_PERF_SEL_WAIT_CNT_ANY                 = 0x00000033,
14711 SQ_PERF_SEL_WAIT_BARRIER                 = 0x00000034,
14712 SQ_PERF_SEL_WAIT_EXP_ALLOC               = 0x00000035,
14713 SQ_PERF_SEL_WAIT_SLEEP                   = 0x00000036,
14714 SQ_PERF_SEL_WAIT_SLEEP_XNACK             = 0x00000037,
14715 SQ_PERF_SEL_WAIT_OTHER                   = 0x00000038,
14716 SQ_PERF_SEL_WAIT_ANY                     = 0x00000039,
14717 SQ_PERF_SEL_WAIT_TTRACE                  = 0x0000003a,
14718 SQ_PERF_SEL_WAIT_IFETCH                  = 0x0000003b,
14719 SQ_PERF_SEL_WAIT_INST_ANY                = 0x0000003c,
14720 SQ_PERF_SEL_WAIT_INST_VMEM               = 0x0000003d,
14721 SQ_PERF_SEL_WAIT_INST_SCA                = 0x0000003e,
14722 SQ_PERF_SEL_WAIT_INST_LDS                = 0x0000003f,
14723 SQ_PERF_SEL_WAIT_INST_VALU               = 0x00000040,
14724 SQ_PERF_SEL_WAIT_INST_EXP_GDS            = 0x00000041,
14725 SQ_PERF_SEL_WAIT_INST_MISC               = 0x00000042,
14726 SQ_PERF_SEL_WAIT_INST_FLAT               = 0x00000043,
14727 SQ_PERF_SEL_ACTIVE_INST_ANY              = 0x00000044,
14728 SQ_PERF_SEL_ACTIVE_INST_VMEM             = 0x00000045,
14729 SQ_PERF_SEL_ACTIVE_INST_LDS              = 0x00000046,
14730 SQ_PERF_SEL_ACTIVE_INST_VALU             = 0x00000047,
14731 SQ_PERF_SEL_ACTIVE_INST_SCA              = 0x00000048,
14732 SQ_PERF_SEL_ACTIVE_INST_EXP_GDS          = 0x00000049,
14733 SQ_PERF_SEL_ACTIVE_INST_MISC             = 0x0000004a,
14734 SQ_PERF_SEL_ACTIVE_INST_FLAT             = 0x0000004b,
14735 SQ_PERF_SEL_INST_CYCLES_VMEM_WR          = 0x0000004c,
14736 SQ_PERF_SEL_INST_CYCLES_VMEM_RD          = 0x0000004d,
14737 SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR        = 0x0000004e,
14738 SQ_PERF_SEL_INST_CYCLES_VMEM_DATA        = 0x0000004f,
14739 SQ_PERF_SEL_INST_CYCLES_VMEM_CMD         = 0x00000050,
14740 SQ_PERF_SEL_INST_CYCLES_EXP              = 0x00000051,
14741 SQ_PERF_SEL_INST_CYCLES_GDS              = 0x00000052,
14742 SQ_PERF_SEL_INST_CYCLES_SMEM             = 0x00000053,
14743 SQ_PERF_SEL_INST_CYCLES_SALU             = 0x00000054,
14744 SQ_PERF_SEL_THREAD_CYCLES_VALU           = 0x00000055,
14745 SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX       = 0x00000056,
14746 SQ_PERF_SEL_IFETCH                       = 0x00000057,
14747 SQ_PERF_SEL_IFETCH_LEVEL                 = 0x00000058,
14748 SQ_PERF_SEL_CBRANCH_FORK                 = 0x00000059,
14749 SQ_PERF_SEL_CBRANCH_FORK_SPLIT           = 0x0000005a,
14750 SQ_PERF_SEL_VALU_LDS_DIRECT_RD           = 0x0000005b,
14751 SQ_PERF_SEL_VALU_LDS_INTERP_OP           = 0x0000005c,
14752 SQ_PERF_SEL_LDS_BANK_CONFLICT            = 0x0000005d,
14753 SQ_PERF_SEL_LDS_ADDR_CONFLICT            = 0x0000005e,
14754 SQ_PERF_SEL_LDS_UNALIGNED_STALL          = 0x0000005f,
14755 SQ_PERF_SEL_LDS_MEM_VIOLATIONS           = 0x00000060,
14756 SQ_PERF_SEL_LDS_ATOMIC_RETURN            = 0x00000061,
14757 SQ_PERF_SEL_LDS_IDX_ACTIVE               = 0x00000062,
14758 SQ_PERF_SEL_VALU_DEP_STALL               = 0x00000063,
14759 SQ_PERF_SEL_VALU_STARVE                  = 0x00000064,
14760 SQ_PERF_SEL_EXP_REQ_FIFO_FULL            = 0x00000065,
14761 SQ_PERF_SEL_LDS_DATA_FIFO_FULL           = 0x00000066,
14762 SQ_PERF_SEL_LDS_CMD_FIFO_FULL            = 0x00000067,
14763 SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL       = 0x00000068,
14764 SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL        = 0x00000069,
14765 SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY        = 0x0000006a,
14766 SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL    = 0x0000006b,
14767 SQ_PERF_SEL_VALU_SRC_C_CONFLICT          = 0x0000006c,
14768 SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT      = 0x0000006d,
14769 SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT      = 0x0000006e,
14770 SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT         = 0x0000006f,
14771 SQ_PERF_SEL_LDS_SRC_CD_CONFLICT          = 0x00000070,
14772 SQ_PERF_SEL_SRC_CD_BUSY                  = 0x00000071,
14773 SQ_PERF_SEL_PT_POWER_STALL               = 0x00000072,
14774 SQ_PERF_SEL_USER0                        = 0x00000073,
14775 SQ_PERF_SEL_USER1                        = 0x00000074,
14776 SQ_PERF_SEL_USER2                        = 0x00000075,
14777 SQ_PERF_SEL_USER3                        = 0x00000076,
14778 SQ_PERF_SEL_USER4                        = 0x00000077,
14779 SQ_PERF_SEL_USER5                        = 0x00000078,
14780 SQ_PERF_SEL_USER6                        = 0x00000079,
14781 SQ_PERF_SEL_USER7                        = 0x0000007a,
14782 SQ_PERF_SEL_USER8                        = 0x0000007b,
14783 SQ_PERF_SEL_USER9                        = 0x0000007c,
14784 SQ_PERF_SEL_USER10                       = 0x0000007d,
14785 SQ_PERF_SEL_USER11                       = 0x0000007e,
14786 SQ_PERF_SEL_USER12                       = 0x0000007f,
14787 SQ_PERF_SEL_USER13                       = 0x00000080,
14788 SQ_PERF_SEL_USER14                       = 0x00000081,
14789 SQ_PERF_SEL_USER15                       = 0x00000082,
14790 SQ_PERF_SEL_USER_LEVEL0                  = 0x00000083,
14791 SQ_PERF_SEL_USER_LEVEL1                  = 0x00000084,
14792 SQ_PERF_SEL_USER_LEVEL2                  = 0x00000085,
14793 SQ_PERF_SEL_USER_LEVEL3                  = 0x00000086,
14794 SQ_PERF_SEL_USER_LEVEL4                  = 0x00000087,
14795 SQ_PERF_SEL_USER_LEVEL5                  = 0x00000088,
14796 SQ_PERF_SEL_USER_LEVEL6                  = 0x00000089,
14797 SQ_PERF_SEL_USER_LEVEL7                  = 0x0000008a,
14798 SQ_PERF_SEL_USER_LEVEL8                  = 0x0000008b,
14799 SQ_PERF_SEL_USER_LEVEL9                  = 0x0000008c,
14800 SQ_PERF_SEL_USER_LEVEL10                 = 0x0000008d,
14801 SQ_PERF_SEL_USER_LEVEL11                 = 0x0000008e,
14802 SQ_PERF_SEL_USER_LEVEL12                 = 0x0000008f,
14803 SQ_PERF_SEL_USER_LEVEL13                 = 0x00000090,
14804 SQ_PERF_SEL_USER_LEVEL14                 = 0x00000091,
14805 SQ_PERF_SEL_USER_LEVEL15                 = 0x00000092,
14806 SQ_PERF_SEL_POWER_VALU                   = 0x00000093,
14807 SQ_PERF_SEL_POWER_VALU0                  = 0x00000094,
14808 SQ_PERF_SEL_POWER_VALU1                  = 0x00000095,
14809 SQ_PERF_SEL_POWER_VALU2                  = 0x00000096,
14810 SQ_PERF_SEL_POWER_GPR_RD                 = 0x00000097,
14811 SQ_PERF_SEL_POWER_GPR_WR                 = 0x00000098,
14812 SQ_PERF_SEL_POWER_LDS_BUSY               = 0x00000099,
14813 SQ_PERF_SEL_POWER_ALU_BUSY               = 0x0000009a,
14814 SQ_PERF_SEL_POWER_TEX_BUSY               = 0x0000009b,
14815 SQ_PERF_SEL_ACCUM_PREV_HIRES             = 0x0000009c,
14816 SQ_PERF_SEL_WAVES_RESTORED               = 0x0000009d,
14817 SQ_PERF_SEL_WAVES_SAVED                  = 0x0000009e,
14818 SQ_PERF_SEL_INSTS_SMEM_NORM              = 0x0000009f,
14819 SQ_PERF_SEL_ATC_INSTS_VMEM               = 0x000000a0,
14820 SQ_PERF_SEL_ATC_INST_LEVEL_VMEM          = 0x000000a1,
14821 SQ_PERF_SEL_ATC_XNACK_FIRST              = 0x000000a2,
14822 SQ_PERF_SEL_ATC_XNACK_ALL                = 0x000000a3,
14823 SQ_PERF_SEL_ATC_XNACK_FIFO_FULL          = 0x000000a4,
14824 SQ_PERF_SEL_ATC_INSTS_SMEM               = 0x000000a5,
14825 SQ_PERF_SEL_ATC_INST_LEVEL_SMEM          = 0x000000a6,
14826 SQ_PERF_SEL_IFETCH_XNACK                 = 0x000000a7,
14827 SQ_PERF_SEL_TLB_SHOOTDOWN                = 0x000000a8,
14828 SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES         = 0x000000a9,
14829 SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY         = 0x000000aa,
14830 SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY         = 0x000000ab,
14831 SQ_PERF_SEL_INSTS_VMEM_REPLAY            = 0x000000ac,
14832 SQ_PERF_SEL_INSTS_SMEM_REPLAY            = 0x000000ad,
14833 SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY       = 0x000000ae,
14834 SQ_PERF_SEL_INSTS_FLAT_REPLAY            = 0x000000af,
14835 SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY        = 0x000000b0,
14836 SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY        = 0x000000b1,
14837 SQ_PERF_SEL_UTCL1_TRANSLATION_MISS       = 0x000000b2,
14838 SQ_PERF_SEL_UTCL1_PERMISSION_MISS        = 0x000000b3,
14839 SQ_PERF_SEL_UTCL1_REQUEST                = 0x000000b4,
14840 SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL    = 0x000000b5,
14841 SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX     = 0x000000b6,
14842 SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT     = 0x000000b7,
14843 SQ_PERF_SEL_UTCL1_LFIFO_FULL             = 0x000000b8,
14844 SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES    = 0x000000b9,
14845 SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x000000ba,
14846 SQ_PERF_SEL_DUMMY_END                    = 0x000000bb,
14847 SQ_PERF_SEL_DUMMY_LAST                   = 0x000000ff,
14848 SQC_PERF_SEL_ICACHE_INPUT_VALID_READY    = 0x00000100,
14849 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB   = 0x00000101,
14850 SQC_PERF_SEL_ICACHE_INPUT_VALIDB         = 0x00000102,
14851 SQC_PERF_SEL_DCACHE_INPUT_VALID_READY    = 0x00000103,
14852 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB   = 0x00000104,
14853 SQC_PERF_SEL_DCACHE_INPUT_VALIDB         = 0x00000105,
14854 SQC_PERF_SEL_TC_REQ                      = 0x00000106,
14855 SQC_PERF_SEL_TC_INST_REQ                 = 0x00000107,
14856 SQC_PERF_SEL_TC_DATA_READ_REQ            = 0x00000108,
14857 SQC_PERF_SEL_TC_DATA_WRITE_REQ           = 0x00000109,
14858 SQC_PERF_SEL_TC_DATA_ATOMIC_REQ          = 0x0000010a,
14859 SQC_PERF_SEL_TC_STALL                    = 0x0000010b,
14860 SQC_PERF_SEL_TC_STARVE                   = 0x0000010c,
14861 SQC_PERF_SEL_ICACHE_BUSY_CYCLES          = 0x0000010d,
14862 SQC_PERF_SEL_ICACHE_REQ                  = 0x0000010e,
14863 SQC_PERF_SEL_ICACHE_HITS                 = 0x0000010f,
14864 SQC_PERF_SEL_ICACHE_MISSES               = 0x00000110,
14865 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE     = 0x00000111,
14866 SQC_PERF_SEL_ICACHE_INVAL_INST           = 0x00000112,
14867 SQC_PERF_SEL_ICACHE_INVAL_ASYNC          = 0x00000113,
14868 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT  = 0x00000114,
14869 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB  = 0x00000115,
14870 SQC_PERF_SEL_ICACHE_CACHE_STALLED        = 0x00000116,
14871 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO  = 0x00000117,
14872 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX  = 0x00000118,
14873 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT   = 0x00000119,
14874 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO  = 0x0000011a,
14875 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0x0000011b,
14876 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF  = 0x0000011c,
14877 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT  = 0x0000011d,
14878 SQC_PERF_SEL_ICACHE_PREFETCH_1           = 0x0000011e,
14879 SQC_PERF_SEL_ICACHE_PREFETCH_2           = 0x0000011f,
14880 SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED    = 0x00000120,
14881 SQC_PERF_SEL_DCACHE_BUSY_CYCLES          = 0x00000121,
14882 SQC_PERF_SEL_DCACHE_REQ                  = 0x00000122,
14883 SQC_PERF_SEL_DCACHE_HITS                 = 0x00000123,
14884 SQC_PERF_SEL_DCACHE_MISSES               = 0x00000124,
14885 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE     = 0x00000125,
14886 SQC_PERF_SEL_DCACHE_HIT_LRU_READ         = 0x00000126,
14887 SQC_PERF_SEL_DCACHE_MISS_EVICT_READ      = 0x00000127,
14888 SQC_PERF_SEL_DCACHE_WC_LRU_WRITE         = 0x00000128,
14889 SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE       = 0x00000129,
14890 SQC_PERF_SEL_DCACHE_ATOMIC               = 0x0000012a,
14891 SQC_PERF_SEL_DCACHE_VOLATILE             = 0x0000012b,
14892 SQC_PERF_SEL_DCACHE_INVAL_INST           = 0x0000012c,
14893 SQC_PERF_SEL_DCACHE_INVAL_ASYNC          = 0x0000012d,
14894 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST  = 0x0000012e,
14895 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC  = 0x0000012f,
14896 SQC_PERF_SEL_DCACHE_WB_INST              = 0x00000130,
14897 SQC_PERF_SEL_DCACHE_WB_ASYNC             = 0x00000131,
14898 SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST     = 0x00000132,
14899 SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC    = 0x00000133,
14900 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT  = 0x00000134,
14901 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB  = 0x00000135,
14902 SQC_PERF_SEL_DCACHE_CACHE_STALLED        = 0x00000136,
14903 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX  = 0x00000137,
14904 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT   = 0x00000138,
14905 SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT    = 0x00000139,
14906 SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED  = 0x0000013a,
14907 SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE  = 0x0000013b,
14908 SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT  = 0x0000013c,
14909 SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH  = 0x0000013d,
14910 SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE  = 0x0000013e,
14911 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO  = 0x0000013f,
14912 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0x00000140,
14913 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF  = 0x00000141,
14914 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT  = 0x00000142,
14915 SQC_PERF_SEL_DCACHE_REQ_READ_1           = 0x00000143,
14916 SQC_PERF_SEL_DCACHE_REQ_READ_2           = 0x00000144,
14917 SQC_PERF_SEL_DCACHE_REQ_READ_4           = 0x00000145,
14918 SQC_PERF_SEL_DCACHE_REQ_READ_8           = 0x00000146,
14919 SQC_PERF_SEL_DCACHE_REQ_READ_16          = 0x00000147,
14920 SQC_PERF_SEL_DCACHE_REQ_TIME             = 0x00000148,
14921 SQC_PERF_SEL_DCACHE_REQ_WRITE_1          = 0x00000149,
14922 SQC_PERF_SEL_DCACHE_REQ_WRITE_2          = 0x0000014a,
14923 SQC_PERF_SEL_DCACHE_REQ_WRITE_4          = 0x0000014b,
14924 SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE        = 0x0000014c,
14925 SQC_PERF_SEL_SQ_DCACHE_REQS              = 0x0000014d,
14926 SQC_PERF_SEL_DCACHE_FLAT_REQ             = 0x0000014e,
14927 SQC_PERF_SEL_DCACHE_NONFLAT_REQ          = 0x0000014f,
14928 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL       = 0x00000150,
14929 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL       = 0x00000151,
14930 SQC_PERF_SEL_TC_INFLIGHT_LEVEL           = 0x00000152,
14931 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL    = 0x00000153,
14932 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL    = 0x00000154,
14933 SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS  = 0x00000155,
14934 SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS  = 0x00000156,
14935 SQC_PERF_SEL_ICACHE_GATCL1_REQUEST       = 0x00000157,
14936 SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX  = 0x00000158,
14937 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT  = 0x00000159,
14938 SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL    = 0x0000015a,
14939 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES  = 0x0000015b,
14940 SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS  = 0x0000015c,
14941 SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT  = 0x0000015d,
14942 SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL  = 0x0000015e,
14943 SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS  = 0x0000015f,
14944 SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS  = 0x00000160,
14945 SQC_PERF_SEL_DCACHE_GATCL1_REQUEST       = 0x00000161,
14946 SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX  = 0x00000162,
14947 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT  = 0x00000163,
14948 SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL    = 0x00000164,
14949 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES  = 0x00000165,
14950 SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS  = 0x00000166,
14951 SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT  = 0x00000167,
14952 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL  = 0x00000168,
14953 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS  = 0x00000169,
14954 SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL  = 0x0000016a,
14955 SQC_PERF_SEL_DUMMY_LAST                  = 0x0000016b,
14956 } SQ_PERF_SEL;
14957 
14958 /*
14959  * SQ_CAC_POWER_SEL enum
14960  */
14961 
14962 typedef enum SQ_CAC_POWER_SEL {
14963 SQ_CAC_POWER_VALU                        = 0x00000000,
14964 SQ_CAC_POWER_VALU0                       = 0x00000001,
14965 SQ_CAC_POWER_VALU1                       = 0x00000002,
14966 SQ_CAC_POWER_VALU2                       = 0x00000003,
14967 SQ_CAC_POWER_GPR_RD                      = 0x00000004,
14968 SQ_CAC_POWER_GPR_WR                      = 0x00000005,
14969 SQ_CAC_POWER_LDS_BUSY                    = 0x00000006,
14970 SQ_CAC_POWER_ALU_BUSY                    = 0x00000007,
14971 SQ_CAC_POWER_TEX_BUSY                    = 0x00000008,
14972 } SQ_CAC_POWER_SEL;
14973 
14974 /*
14975  * SQ_IND_CMD_CMD enum
14976  */
14977 
14978 typedef enum SQ_IND_CMD_CMD {
14979 SQ_IND_CMD_CMD_NULL                      = 0x00000000,
14980 SQ_IND_CMD_CMD_SETHALT                   = 0x00000001,
14981 SQ_IND_CMD_CMD_SAVECTX                   = 0x00000002,
14982 SQ_IND_CMD_CMD_KILL                      = 0x00000003,
14983 SQ_IND_CMD_CMD_DEBUG                     = 0x00000004,
14984 SQ_IND_CMD_CMD_TRAP                      = 0x00000005,
14985 SQ_IND_CMD_CMD_SET_SPI_PRIO              = 0x00000006,
14986 SQ_IND_CMD_CMD_SETFATALHALT              = 0x00000007,
14987 } SQ_IND_CMD_CMD;
14988 
14989 /*
14990  * SQ_IND_CMD_MODE enum
14991  */
14992 
14993 typedef enum SQ_IND_CMD_MODE {
14994 SQ_IND_CMD_MODE_SINGLE                   = 0x00000000,
14995 SQ_IND_CMD_MODE_BROADCAST                = 0x00000001,
14996 SQ_IND_CMD_MODE_BROADCAST_QUEUE          = 0x00000002,
14997 SQ_IND_CMD_MODE_BROADCAST_PIPE           = 0x00000003,
14998 SQ_IND_CMD_MODE_BROADCAST_ME             = 0x00000004,
14999 } SQ_IND_CMD_MODE;
15000 
15001 /*
15002  * SQ_EDC_INFO_SOURCE enum
15003  */
15004 
15005 typedef enum SQ_EDC_INFO_SOURCE {
15006 SQ_EDC_INFO_SOURCE_INVALID               = 0x00000000,
15007 SQ_EDC_INFO_SOURCE_INST                  = 0x00000001,
15008 SQ_EDC_INFO_SOURCE_SGPR                  = 0x00000002,
15009 SQ_EDC_INFO_SOURCE_VGPR                  = 0x00000003,
15010 SQ_EDC_INFO_SOURCE_LDS                   = 0x00000004,
15011 SQ_EDC_INFO_SOURCE_GDS                   = 0x00000005,
15012 SQ_EDC_INFO_SOURCE_TA                    = 0x00000006,
15013 } SQ_EDC_INFO_SOURCE;
15014 
15015 /*
15016  * SQ_ROUND_MODE enum
15017  */
15018 
15019 typedef enum SQ_ROUND_MODE {
15020 SQ_ROUND_NEAREST_EVEN                    = 0x00000000,
15021 SQ_ROUND_PLUS_INFINITY                   = 0x00000001,
15022 SQ_ROUND_MINUS_INFINITY                  = 0x00000002,
15023 SQ_ROUND_TO_ZERO                         = 0x00000003,
15024 } SQ_ROUND_MODE;
15025 
15026 /*
15027  * SQ_INTERRUPT_WORD_ENCODING enum
15028  */
15029 
15030 typedef enum SQ_INTERRUPT_WORD_ENCODING {
15031 SQ_INTERRUPT_WORD_ENCODING_AUTO          = 0x00000000,
15032 SQ_INTERRUPT_WORD_ENCODING_INST          = 0x00000001,
15033 SQ_INTERRUPT_WORD_ENCODING_ERROR         = 0x00000002,
15034 } SQ_INTERRUPT_WORD_ENCODING;
15035 
15036 /*
15037  * ENUM_SQ_EXPORT_RAT_INST enum
15038  */
15039 
15040 typedef enum ENUM_SQ_EXPORT_RAT_INST {
15041 SQ_EXPORT_RAT_INST_NOP                   = 0x00000000,
15042 SQ_EXPORT_RAT_INST_STORE_TYPED           = 0x00000001,
15043 SQ_EXPORT_RAT_INST_STORE_RAW             = 0x00000002,
15044 SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM     = 0x00000003,
15045 SQ_EXPORT_RAT_INST_CMPXCHG_INT           = 0x00000004,
15046 SQ_EXPORT_RAT_INST_CMPXCHG_FLT           = 0x00000005,
15047 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM       = 0x00000006,
15048 SQ_EXPORT_RAT_INST_ADD                   = 0x00000007,
15049 SQ_EXPORT_RAT_INST_SUB                   = 0x00000008,
15050 SQ_EXPORT_RAT_INST_RSUB                  = 0x00000009,
15051 SQ_EXPORT_RAT_INST_MIN_INT               = 0x0000000a,
15052 SQ_EXPORT_RAT_INST_MIN_UINT              = 0x0000000b,
15053 SQ_EXPORT_RAT_INST_MAX_INT               = 0x0000000c,
15054 SQ_EXPORT_RAT_INST_MAX_UINT              = 0x0000000d,
15055 SQ_EXPORT_RAT_INST_AND                   = 0x0000000e,
15056 SQ_EXPORT_RAT_INST_OR                    = 0x0000000f,
15057 SQ_EXPORT_RAT_INST_XOR                   = 0x00000010,
15058 SQ_EXPORT_RAT_INST_MSKOR                 = 0x00000011,
15059 SQ_EXPORT_RAT_INST_INC_UINT              = 0x00000012,
15060 SQ_EXPORT_RAT_INST_DEC_UINT              = 0x00000013,
15061 SQ_EXPORT_RAT_INST_STORE_DWORD           = 0x00000014,
15062 SQ_EXPORT_RAT_INST_STORE_SHORT           = 0x00000015,
15063 SQ_EXPORT_RAT_INST_STORE_BYTE            = 0x00000016,
15064 SQ_EXPORT_RAT_INST_NOP_RTN               = 0x00000020,
15065 SQ_EXPORT_RAT_INST_XCHG_RTN              = 0x00000022,
15066 SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN      = 0x00000023,
15067 SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN       = 0x00000024,
15068 SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN       = 0x00000025,
15069 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN   = 0x00000026,
15070 SQ_EXPORT_RAT_INST_ADD_RTN               = 0x00000027,
15071 SQ_EXPORT_RAT_INST_SUB_RTN               = 0x00000028,
15072 SQ_EXPORT_RAT_INST_RSUB_RTN              = 0x00000029,
15073 SQ_EXPORT_RAT_INST_MIN_INT_RTN           = 0x0000002a,
15074 SQ_EXPORT_RAT_INST_MIN_UINT_RTN          = 0x0000002b,
15075 SQ_EXPORT_RAT_INST_MAX_INT_RTN           = 0x0000002c,
15076 SQ_EXPORT_RAT_INST_MAX_UINT_RTN          = 0x0000002d,
15077 SQ_EXPORT_RAT_INST_AND_RTN               = 0x0000002e,
15078 SQ_EXPORT_RAT_INST_OR_RTN                = 0x0000002f,
15079 SQ_EXPORT_RAT_INST_XOR_RTN               = 0x00000030,
15080 SQ_EXPORT_RAT_INST_MSKOR_RTN             = 0x00000031,
15081 SQ_EXPORT_RAT_INST_INC_UINT_RTN          = 0x00000032,
15082 SQ_EXPORT_RAT_INST_DEC_UINT_RTN          = 0x00000033,
15083 } ENUM_SQ_EXPORT_RAT_INST;
15084 
15085 /*
15086  * SQ_IBUF_ST enum
15087  */
15088 
15089 typedef enum SQ_IBUF_ST {
15090 SQ_IBUF_IB_IDLE                          = 0x00000000,
15091 SQ_IBUF_IB_INI_WAIT_GNT                  = 0x00000001,
15092 SQ_IBUF_IB_INI_WAIT_DRET                 = 0x00000002,
15093 SQ_IBUF_IB_LE_4DW                        = 0x00000003,
15094 SQ_IBUF_IB_WAIT_DRET                     = 0x00000004,
15095 SQ_IBUF_IB_EMPTY_WAIT_DRET               = 0x00000005,
15096 SQ_IBUF_IB_DRET                          = 0x00000006,
15097 SQ_IBUF_IB_EMPTY_WAIT_GNT                = 0x00000007,
15098 } SQ_IBUF_ST;
15099 
15100 /*
15101  * SQ_INST_STR_ST enum
15102  */
15103 
15104 typedef enum SQ_INST_STR_ST {
15105 SQ_INST_STR_IB_WAVE_NORML                = 0x00000000,
15106 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV    = 0x00000001,
15107 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV     = 0x00000002,
15108 SQ_INST_STR_IB_WAVE_INST_SKIP_AV         = 0x00000003,
15109 SQ_INST_STR_IB_WAVE_SETVSKIP_ST0         = 0x00000004,
15110 SQ_INST_STR_IB_WAVE_SETVSKIP_ST1         = 0x00000005,
15111 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT       = 0x00000006,
15112 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT  = 0x00000007,
15113 } SQ_INST_STR_ST;
15114 
15115 /*
15116  * SQ_WAVE_IB_ECC_ST enum
15117  */
15118 
15119 typedef enum SQ_WAVE_IB_ECC_ST {
15120 SQ_WAVE_IB_ECC_CLEAN                     = 0x00000000,
15121 SQ_WAVE_IB_ECC_ERR_CONTINUE              = 0x00000001,
15122 SQ_WAVE_IB_ECC_ERR_HALT                  = 0x00000002,
15123 SQ_WAVE_IB_ECC_WITH_ERR_MSG              = 0x00000003,
15124 } SQ_WAVE_IB_ECC_ST;
15125 
15126 /*
15127  * SH_MEM_ADDRESS_MODE enum
15128  */
15129 
15130 typedef enum SH_MEM_ADDRESS_MODE {
15131 SH_MEM_ADDRESS_MODE_64                   = 0x00000000,
15132 SH_MEM_ADDRESS_MODE_32                   = 0x00000001,
15133 } SH_MEM_ADDRESS_MODE;
15134 
15135 /*
15136  * SH_MEM_ALIGNMENT_MODE enum
15137  */
15138 
15139 typedef enum SH_MEM_ALIGNMENT_MODE {
15140 SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,
15141 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT       = 0x00000001,
15142 SH_MEM_ALIGNMENT_MODE_STRICT             = 0x00000002,
15143 SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000003,
15144 } SH_MEM_ALIGNMENT_MODE;
15145 
15146 /*
15147  * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum
15148  */
15149 
15150 typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
15151 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC  = 0x00000018,
15152 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE  = 0x00000019,
15153 } SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
15154 
15155 /*
15156  * SQ_LB_CTR_SEL_VALUES enum
15157  */
15158 
15159 typedef enum SQ_LB_CTR_SEL_VALUES {
15160 SQ_LB_CTR_SEL_ALU_CYCLES                 = 0x00000000,
15161 SQ_LB_CTR_SEL_ALU_STALLS                 = 0x00000001,
15162 SQ_LB_CTR_SEL_TEX_CYCLES                 = 0x00000002,
15163 SQ_LB_CTR_SEL_TEX_STALLS                 = 0x00000003,
15164 SQ_LB_CTR_SEL_SALU_CYCLES                = 0x00000004,
15165 SQ_LB_CTR_SEL_SCALAR_STALLS              = 0x00000005,
15166 SQ_LB_CTR_SEL_SMEM_CYCLES                = 0x00000006,
15167 SQ_LB_CTR_SEL_ICACHE_STALLS              = 0x00000007,
15168 SQ_LB_CTR_SEL_DCACHE_STALLS              = 0x00000008,
15169 SQ_LB_CTR_SEL_RESERVED0                  = 0x00000009,
15170 SQ_LB_CTR_SEL_RESERVED1                  = 0x0000000a,
15171 SQ_LB_CTR_SEL_RESERVED2                  = 0x0000000b,
15172 SQ_LB_CTR_SEL_RESERVED3                  = 0x0000000c,
15173 SQ_LB_CTR_SEL_RESERVED4                  = 0x0000000d,
15174 SQ_LB_CTR_SEL_RESERVED5                  = 0x0000000e,
15175 SQ_LB_CTR_SEL_RESERVED6                  = 0x0000000f,
15176 } SQ_LB_CTR_SEL_VALUES;
15177 
15178 /*
15179  * SQ_WAVE_TYPE value
15180  */
15181 
15182 #define SQ_WAVE_TYPE_PS0               0x00000000
15183 
15184 /*
15185  * SQIND_PARTITIONS value
15186  */
15187 
15188 #define SQIND_GLOBAL_REGS_OFFSET       0x00000000
15189 #define SQIND_GLOBAL_REGS_SIZE         0x00000008
15190 #define SQIND_LOCAL_REGS_OFFSET        0x00000008
15191 #define SQIND_LOCAL_REGS_SIZE          0x00000008
15192 #define SQIND_WAVE_HWREGS_OFFSET       0x00000010
15193 #define SQIND_WAVE_HWREGS_SIZE         0x000001f0
15194 #define SQIND_WAVE_SGPRS_OFFSET        0x00000200
15195 #define SQIND_WAVE_SGPRS_SIZE          0x00000200
15196 #define SQIND_WAVE_VGPRS_OFFSET        0x00000400
15197 #define SQIND_WAVE_VGPRS_SIZE          0x00000100
15198 
15199 /*
15200  * SQ_GFXDEC value
15201  */
15202 
15203 #define SQ_GFXDEC_BEGIN                0x0000a000
15204 #define SQ_GFXDEC_END                  0x0000c000
15205 #define SQ_GFXDEC_STATE_ID_SHIFT       0x0000000a
15206 
15207 /*
15208  * SQDEC value
15209  */
15210 
15211 #define SQDEC_BEGIN                    0x00002300
15212 #define SQDEC_END                      0x000023ff
15213 
15214 /*
15215  * SQPERFSDEC value
15216  */
15217 
15218 #define SQPERFSDEC_BEGIN               0x0000d9c0
15219 #define SQPERFSDEC_END                 0x0000da40
15220 
15221 /*
15222  * SQPERFDDEC value
15223  */
15224 
15225 #define SQPERFDDEC_BEGIN               0x0000d1c0
15226 #define SQPERFDDEC_END                 0x0000d240
15227 
15228 /*
15229  * SQGFXUDEC value
15230  */
15231 
15232 #define SQGFXUDEC_BEGIN                0x0000c330
15233 #define SQGFXUDEC_END                  0x0000c380
15234 
15235 /*
15236  * SQPWRDEC value
15237  */
15238 
15239 #define SQPWRDEC_BEGIN                 0x0000f08c
15240 #define SQPWRDEC_END                   0x0000f094
15241 
15242 /*
15243  * SQ_DISPATCHER value
15244  */
15245 
15246 #define SQ_DISPATCHER_GFX_MIN          0x00000010
15247 #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
15248 
15249 /*
15250  * SQ_MAX value
15251  */
15252 
15253 #define SQ_MAX_PGM_SGPRS               0x00000068
15254 #define SQ_MAX_PGM_VGPRS               0x00000100
15255 
15256 /*
15257  * SQ_THREAD_TRACE_TIME_UNIT value
15258  */
15259 
15260 #define SQ_THREAD_TRACE_TIME_UNIT      0x00000004
15261 
15262 /*
15263  * SQ_EXCP_BITS value
15264  */
15265 
15266 #define SQ_EX_MODE_EXCP_VALU_BASE      0x00000000
15267 #define SQ_EX_MODE_EXCP_VALU_SIZE      0x00000007
15268 #define SQ_EX_MODE_EXCP_INVALID        0x00000000
15269 #define SQ_EX_MODE_EXCP_INPUT_DENORM   0x00000001
15270 #define SQ_EX_MODE_EXCP_DIV0           0x00000002
15271 #define SQ_EX_MODE_EXCP_OVERFLOW       0x00000003
15272 #define SQ_EX_MODE_EXCP_UNDERFLOW      0x00000004
15273 #define SQ_EX_MODE_EXCP_INEXACT        0x00000005
15274 #define SQ_EX_MODE_EXCP_INT_DIV0       0x00000006
15275 #define SQ_EX_MODE_EXCP_ADDR_WATCH0    0x00000007
15276 #define SQ_EX_MODE_EXCP_MEM_VIOL       0x00000008
15277 
15278 /*
15279  * SQ_EXCP_HI_BITS value
15280  */
15281 
15282 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
15283 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
15284 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
15285 
15286 /*
15287  * HW_INSERTED_INST_ID value
15288  */
15289 
15290 #define INST_ID_PRIV_START             0x80000000
15291 #define INST_ID_ECC_INTERRUPT_MSG      0xfffffff0
15292 #define INST_ID_TTRACE_NEW_PC_MSG      0xfffffff1
15293 #define INST_ID_HW_TRAP                0xfffffff2
15294 #define INST_ID_KILL_SEQ               0xfffffff3
15295 #define INST_ID_SPI_WREXEC             0xfffffff4
15296 #define INST_ID_HOST_REG_TRAP_MSG      0xfffffffe
15297 
15298 /*
15299  * SIMM16_WAITCNT_PARTITIONS value
15300  */
15301 
15302 #define SIMM16_WAITCNT_VM_CNT_START    0x00000000
15303 #define SIMM16_WAITCNT_VM_CNT_SIZE     0x00000004
15304 #define SIMM16_WAITCNT_EXP_CNT_START   0x00000004
15305 #define SIMM16_WAITCNT_EXP_CNT_SIZE    0x00000003
15306 #define SIMM16_WAITCNT_LGKM_CNT_START  0x00000008
15307 #define SIMM16_WAITCNT_LGKM_CNT_SIZE   0x00000004
15308 #define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e
15309 #define SIMM16_WAITCNT_VM_CNT_HI_SIZE  0x00000002
15310 
15311 /*
15312  * SQ_EDC_FUE_CNTL_BITS value
15313  */
15314 
15315 #define SQ_EDC_FUE_CNTL_SQ             0x00000000
15316 #define SQ_EDC_FUE_CNTL_LDS            0x00000001
15317 #define SQ_EDC_FUE_CNTL_SIMD0          0x00000002
15318 #define SQ_EDC_FUE_CNTL_SIMD1          0x00000003
15319 #define SQ_EDC_FUE_CNTL_SIMD2          0x00000004
15320 #define SQ_EDC_FUE_CNTL_SIMD3          0x00000005
15321 #define SQ_EDC_FUE_CNTL_TA             0x00000006
15322 #define SQ_EDC_FUE_CNTL_TD             0x00000007
15323 #define SQ_EDC_FUE_CNTL_TCP            0x00000008
15324 
15325 /*******************************************************
15326  * COMP Enums
15327  *******************************************************/
15328 
15329 /*
15330  * CSDATA_TYPE enum
15331  */
15332 
15333 typedef enum CSDATA_TYPE {
15334 CSDATA_TYPE_TG                           = 0x00000000,
15335 CSDATA_TYPE_STATE                        = 0x00000001,
15336 CSDATA_TYPE_EVENT                        = 0x00000002,
15337 CSDATA_TYPE_PRIVATE                      = 0x00000003,
15338 } CSDATA_TYPE;
15339 
15340 /*
15341  * CSDATA_TYPE_WIDTH value
15342  */
15343 
15344 #define CSDATA_TYPE_WIDTH              0x00000002
15345 
15346 /*
15347  * CSDATA_ADDR_WIDTH value
15348  */
15349 
15350 #define CSDATA_ADDR_WIDTH              0x00000007
15351 
15352 /*
15353  * CSDATA_DATA_WIDTH value
15354  */
15355 
15356 #define CSDATA_DATA_WIDTH              0x00000020
15357 
15358 /*******************************************************
15359  * VGT Enums
15360  *******************************************************/
15361 
15362 /*
15363  * VGT_OUT_PRIM_TYPE enum
15364  */
15365 
15366 typedef enum VGT_OUT_PRIM_TYPE {
15367 VGT_OUT_POINT                            = 0x00000000,
15368 VGT_OUT_LINE                             = 0x00000001,
15369 VGT_OUT_TRI                              = 0x00000002,
15370 VGT_OUT_RECT_V0                          = 0x00000003,
15371 VGT_OUT_RECT_V1                          = 0x00000004,
15372 VGT_OUT_RECT_V2                          = 0x00000005,
15373 VGT_OUT_RECT_V3                          = 0x00000006,
15374 VGT_OUT_2D_RECT                          = 0x00000007,
15375 VGT_TE_QUAD                              = 0x00000008,
15376 VGT_TE_PRIM_INDEX_LINE                   = 0x00000009,
15377 VGT_TE_PRIM_INDEX_TRI                    = 0x0000000a,
15378 VGT_TE_PRIM_INDEX_QUAD                   = 0x0000000b,
15379 VGT_OUT_LINE_ADJ                         = 0x0000000c,
15380 VGT_OUT_TRI_ADJ                          = 0x0000000d,
15381 VGT_OUT_PATCH                            = 0x0000000e,
15382 } VGT_OUT_PRIM_TYPE;
15383 
15384 /*
15385  * VGT_DI_PRIM_TYPE enum
15386  */
15387 
15388 typedef enum VGT_DI_PRIM_TYPE {
15389 DI_PT_NONE                               = 0x00000000,
15390 DI_PT_POINTLIST                          = 0x00000001,
15391 DI_PT_LINELIST                           = 0x00000002,
15392 DI_PT_LINESTRIP                          = 0x00000003,
15393 DI_PT_TRILIST                            = 0x00000004,
15394 DI_PT_TRIFAN                             = 0x00000005,
15395 DI_PT_TRISTRIP                           = 0x00000006,
15396 DI_PT_2D_RECTANGLE                       = 0x00000007,
15397 DI_PT_UNUSED_1                           = 0x00000008,
15398 DI_PT_PATCH                              = 0x00000009,
15399 DI_PT_LINELIST_ADJ                       = 0x0000000a,
15400 DI_PT_LINESTRIP_ADJ                      = 0x0000000b,
15401 DI_PT_TRILIST_ADJ                        = 0x0000000c,
15402 DI_PT_TRISTRIP_ADJ                       = 0x0000000d,
15403 DI_PT_UNUSED_3                           = 0x0000000e,
15404 DI_PT_UNUSED_4                           = 0x0000000f,
15405 DI_PT_TRI_WITH_WFLAGS                    = 0x00000010,
15406 DI_PT_RECTLIST                           = 0x00000011,
15407 DI_PT_LINELOOP                           = 0x00000012,
15408 DI_PT_QUADLIST                           = 0x00000013,
15409 DI_PT_QUADSTRIP                          = 0x00000014,
15410 DI_PT_POLYGON                            = 0x00000015,
15411 } VGT_DI_PRIM_TYPE;
15412 
15413 /*
15414  * VGT_DI_SOURCE_SELECT enum
15415  */
15416 
15417 typedef enum VGT_DI_SOURCE_SELECT {
15418 DI_SRC_SEL_DMA                           = 0x00000000,
15419 DI_SRC_SEL_IMMEDIATE                     = 0x00000001,
15420 DI_SRC_SEL_AUTO_INDEX                    = 0x00000002,
15421 DI_SRC_SEL_RESERVED                      = 0x00000003,
15422 } VGT_DI_SOURCE_SELECT;
15423 
15424 /*
15425  * VGT_DI_MAJOR_MODE_SELECT enum
15426  */
15427 
15428 typedef enum VGT_DI_MAJOR_MODE_SELECT {
15429 DI_MAJOR_MODE_0                          = 0x00000000,
15430 DI_MAJOR_MODE_1                          = 0x00000001,
15431 } VGT_DI_MAJOR_MODE_SELECT;
15432 
15433 /*
15434  * VGT_DI_INDEX_SIZE enum
15435  */
15436 
15437 typedef enum VGT_DI_INDEX_SIZE {
15438 DI_INDEX_SIZE_16_BIT                     = 0x00000000,
15439 DI_INDEX_SIZE_32_BIT                     = 0x00000001,
15440 DI_INDEX_SIZE_8_BIT                      = 0x00000002,
15441 } VGT_DI_INDEX_SIZE;
15442 
15443 /*
15444  * VGT_EVENT_TYPE enum
15445  */
15446 
15447 typedef enum VGT_EVENT_TYPE {
15448 Reserved_0x00                            = 0x00000000,
15449 SAMPLE_STREAMOUTSTATS1                   = 0x00000001,
15450 SAMPLE_STREAMOUTSTATS2                   = 0x00000002,
15451 SAMPLE_STREAMOUTSTATS3                   = 0x00000003,
15452 CACHE_FLUSH_TS                           = 0x00000004,
15453 CONTEXT_DONE                             = 0x00000005,
15454 CACHE_FLUSH                              = 0x00000006,
15455 CS_PARTIAL_FLUSH                         = 0x00000007,
15456 VGT_STREAMOUT_SYNC                       = 0x00000008,
15457 Reserved_0x09                            = 0x00000009,
15458 VGT_STREAMOUT_RESET                      = 0x0000000a,
15459 END_OF_PIPE_INCR_DE                      = 0x0000000b,
15460 END_OF_PIPE_IB_END                       = 0x0000000c,
15461 RST_PIX_CNT                              = 0x0000000d,
15462 BREAK_BATCH                              = 0x0000000e,
15463 VS_PARTIAL_FLUSH                         = 0x0000000f,
15464 PS_PARTIAL_FLUSH                         = 0x00000010,
15465 FLUSH_HS_OUTPUT                          = 0x00000011,
15466 FLUSH_DFSM                               = 0x00000012,
15467 RESET_TO_LOWEST_VGT                      = 0x00000013,
15468 CACHE_FLUSH_AND_INV_TS_EVENT             = 0x00000014,
15469 ZPASS_DONE                               = 0x00000015,
15470 CACHE_FLUSH_AND_INV_EVENT                = 0x00000016,
15471 PERFCOUNTER_START                        = 0x00000017,
15472 PERFCOUNTER_STOP                         = 0x00000018,
15473 PIPELINESTAT_START                       = 0x00000019,
15474 PIPELINESTAT_STOP                        = 0x0000001a,
15475 PERFCOUNTER_SAMPLE                       = 0x0000001b,
15476 Available_0x1c                           = 0x0000001c,
15477 Available_0x1d                           = 0x0000001d,
15478 SAMPLE_PIPELINESTAT                      = 0x0000001e,
15479 SO_VGTSTREAMOUT_FLUSH                    = 0x0000001f,
15480 SAMPLE_STREAMOUTSTATS                    = 0x00000020,
15481 RESET_VTX_CNT                            = 0x00000021,
15482 BLOCK_CONTEXT_DONE                       = 0x00000022,
15483 CS_CONTEXT_DONE                          = 0x00000023,
15484 VGT_FLUSH                                = 0x00000024,
15485 TGID_ROLLOVER                            = 0x00000025,
15486 SQ_NON_EVENT                             = 0x00000026,
15487 SC_SEND_DB_VPZ                           = 0x00000027,
15488 BOTTOM_OF_PIPE_TS                        = 0x00000028,
15489 FLUSH_SX_TS                              = 0x00000029,
15490 DB_CACHE_FLUSH_AND_INV                   = 0x0000002a,
15491 FLUSH_AND_INV_DB_DATA_TS                 = 0x0000002b,
15492 FLUSH_AND_INV_DB_META                    = 0x0000002c,
15493 FLUSH_AND_INV_CB_DATA_TS                 = 0x0000002d,
15494 FLUSH_AND_INV_CB_META                    = 0x0000002e,
15495 CS_DONE                                  = 0x0000002f,
15496 PS_DONE                                  = 0x00000030,
15497 FLUSH_AND_INV_CB_PIXEL_DATA              = 0x00000031,
15498 SX_CB_RAT_ACK_REQUEST                    = 0x00000032,
15499 THREAD_TRACE_START                       = 0x00000033,
15500 THREAD_TRACE_STOP                        = 0x00000034,
15501 THREAD_TRACE_MARKER                      = 0x00000035,
15502 THREAD_TRACE_FLUSH                       = 0x00000036,
15503 THREAD_TRACE_FINISH                      = 0x00000037,
15504 PIXEL_PIPE_STAT_CONTROL                  = 0x00000038,
15505 PIXEL_PIPE_STAT_DUMP                     = 0x00000039,
15506 PIXEL_PIPE_STAT_RESET                    = 0x0000003a,
15507 CONTEXT_SUSPEND                          = 0x0000003b,
15508 OFFCHIP_HS_DEALLOC                       = 0x0000003c,
15509 ENABLE_NGG_PIPELINE                      = 0x0000003d,
15510 ENABLE_LEGACY_PIPELINE                   = 0x0000003e,
15511 Reserved_0x3f                            = 0x0000003f,
15512 } VGT_EVENT_TYPE;
15513 
15514 /*
15515  * VGT_DMA_SWAP_MODE enum
15516  */
15517 
15518 typedef enum VGT_DMA_SWAP_MODE {
15519 VGT_DMA_SWAP_NONE                        = 0x00000000,
15520 VGT_DMA_SWAP_16_BIT                      = 0x00000001,
15521 VGT_DMA_SWAP_32_BIT                      = 0x00000002,
15522 VGT_DMA_SWAP_WORD                        = 0x00000003,
15523 } VGT_DMA_SWAP_MODE;
15524 
15525 /*
15526  * VGT_INDEX_TYPE_MODE enum
15527  */
15528 
15529 typedef enum VGT_INDEX_TYPE_MODE {
15530 VGT_INDEX_16                             = 0x00000000,
15531 VGT_INDEX_32                             = 0x00000001,
15532 VGT_INDEX_8                              = 0x00000002,
15533 } VGT_INDEX_TYPE_MODE;
15534 
15535 /*
15536  * VGT_DMA_BUF_TYPE enum
15537  */
15538 
15539 typedef enum VGT_DMA_BUF_TYPE {
15540 VGT_DMA_BUF_MEM                          = 0x00000000,
15541 VGT_DMA_BUF_RING                         = 0x00000001,
15542 VGT_DMA_BUF_SETUP                        = 0x00000002,
15543 VGT_DMA_PTR_UPDATE                       = 0x00000003,
15544 } VGT_DMA_BUF_TYPE;
15545 
15546 /*
15547  * VGT_OUTPATH_SELECT enum
15548  */
15549 
15550 typedef enum VGT_OUTPATH_SELECT {
15551 VGT_OUTPATH_VTX_REUSE                    = 0x00000000,
15552 VGT_OUTPATH_TESS_EN                      = 0x00000001,
15553 VGT_OUTPATH_PASSTHRU                     = 0x00000002,
15554 VGT_OUTPATH_GS_BLOCK                     = 0x00000003,
15555 VGT_OUTPATH_HS_BLOCK                     = 0x00000004,
15556 VGT_OUTPATH_PRIM_GEN                     = 0x00000005,
15557 } VGT_OUTPATH_SELECT;
15558 
15559 /*
15560  * VGT_GRP_PRIM_TYPE enum
15561  */
15562 
15563 typedef enum VGT_GRP_PRIM_TYPE {
15564 VGT_GRP_3D_POINT                         = 0x00000000,
15565 VGT_GRP_3D_LINE                          = 0x00000001,
15566 VGT_GRP_3D_TRI                           = 0x00000002,
15567 VGT_GRP_3D_RECT                          = 0x00000003,
15568 VGT_GRP_3D_QUAD                          = 0x00000004,
15569 VGT_GRP_2D_COPY_RECT_V0                  = 0x00000005,
15570 VGT_GRP_2D_COPY_RECT_V1                  = 0x00000006,
15571 VGT_GRP_2D_COPY_RECT_V2                  = 0x00000007,
15572 VGT_GRP_2D_COPY_RECT_V3                  = 0x00000008,
15573 VGT_GRP_2D_FILL_RECT                     = 0x00000009,
15574 VGT_GRP_2D_LINE                          = 0x0000000a,
15575 VGT_GRP_2D_TRI                           = 0x0000000b,
15576 VGT_GRP_PRIM_INDEX_LINE                  = 0x0000000c,
15577 VGT_GRP_PRIM_INDEX_TRI                   = 0x0000000d,
15578 VGT_GRP_PRIM_INDEX_QUAD                  = 0x0000000e,
15579 VGT_GRP_3D_LINE_ADJ                      = 0x0000000f,
15580 VGT_GRP_3D_TRI_ADJ                       = 0x00000010,
15581 VGT_GRP_3D_PATCH                         = 0x00000011,
15582 VGT_GRP_2D_RECT                          = 0x00000012,
15583 } VGT_GRP_PRIM_TYPE;
15584 
15585 /*
15586  * VGT_GRP_PRIM_ORDER enum
15587  */
15588 
15589 typedef enum VGT_GRP_PRIM_ORDER {
15590 VGT_GRP_LIST                             = 0x00000000,
15591 VGT_GRP_STRIP                            = 0x00000001,
15592 VGT_GRP_FAN                              = 0x00000002,
15593 VGT_GRP_LOOP                             = 0x00000003,
15594 VGT_GRP_POLYGON                          = 0x00000004,
15595 } VGT_GRP_PRIM_ORDER;
15596 
15597 /*
15598  * VGT_GROUP_CONV_SEL enum
15599  */
15600 
15601 typedef enum VGT_GROUP_CONV_SEL {
15602 VGT_GRP_INDEX_16                         = 0x00000000,
15603 VGT_GRP_INDEX_32                         = 0x00000001,
15604 VGT_GRP_UINT_16                          = 0x00000002,
15605 VGT_GRP_UINT_32                          = 0x00000003,
15606 VGT_GRP_SINT_16                          = 0x00000004,
15607 VGT_GRP_SINT_32                          = 0x00000005,
15608 VGT_GRP_FLOAT_32                         = 0x00000006,
15609 VGT_GRP_AUTO_PRIM                        = 0x00000007,
15610 VGT_GRP_FIX_1_23_TO_FLOAT                = 0x00000008,
15611 } VGT_GROUP_CONV_SEL;
15612 
15613 /*
15614  * VGT_GS_MODE_TYPE enum
15615  */
15616 
15617 typedef enum VGT_GS_MODE_TYPE {
15618 GS_OFF                                   = 0x00000000,
15619 GS_SCENARIO_A                            = 0x00000001,
15620 GS_SCENARIO_B                            = 0x00000002,
15621 GS_SCENARIO_G                            = 0x00000003,
15622 GS_SCENARIO_C                            = 0x00000004,
15623 SPRITE_EN                                = 0x00000005,
15624 } VGT_GS_MODE_TYPE;
15625 
15626 /*
15627  * VGT_GS_CUT_MODE enum
15628  */
15629 
15630 typedef enum VGT_GS_CUT_MODE {
15631 GS_CUT_1024                              = 0x00000000,
15632 GS_CUT_512                               = 0x00000001,
15633 GS_CUT_256                               = 0x00000002,
15634 GS_CUT_128                               = 0x00000003,
15635 } VGT_GS_CUT_MODE;
15636 
15637 /*
15638  * VGT_GS_OUTPRIM_TYPE enum
15639  */
15640 
15641 typedef enum VGT_GS_OUTPRIM_TYPE {
15642 POINTLIST                                = 0x00000000,
15643 LINESTRIP                                = 0x00000001,
15644 TRISTRIP                                 = 0x00000002,
15645 RECTLIST                                 = 0x00000003,
15646 } VGT_GS_OUTPRIM_TYPE;
15647 
15648 /*
15649  * VGT_CACHE_INVALID_MODE enum
15650  */
15651 
15652 typedef enum VGT_CACHE_INVALID_MODE {
15653 VC_ONLY                                  = 0x00000000,
15654 TC_ONLY                                  = 0x00000001,
15655 VC_AND_TC                                = 0x00000002,
15656 } VGT_CACHE_INVALID_MODE;
15657 
15658 /*
15659  * VGT_TESS_TYPE enum
15660  */
15661 
15662 typedef enum VGT_TESS_TYPE {
15663 TESS_ISOLINE                             = 0x00000000,
15664 TESS_TRIANGLE                            = 0x00000001,
15665 TESS_QUAD                                = 0x00000002,
15666 } VGT_TESS_TYPE;
15667 
15668 /*
15669  * VGT_TESS_PARTITION enum
15670  */
15671 
15672 typedef enum VGT_TESS_PARTITION {
15673 PART_INTEGER                             = 0x00000000,
15674 PART_POW2                                = 0x00000001,
15675 PART_FRAC_ODD                            = 0x00000002,
15676 PART_FRAC_EVEN                           = 0x00000003,
15677 } VGT_TESS_PARTITION;
15678 
15679 /*
15680  * VGT_TESS_TOPOLOGY enum
15681  */
15682 
15683 typedef enum VGT_TESS_TOPOLOGY {
15684 OUTPUT_POINT                             = 0x00000000,
15685 OUTPUT_LINE                              = 0x00000001,
15686 OUTPUT_TRIANGLE_CW                       = 0x00000002,
15687 OUTPUT_TRIANGLE_CCW                      = 0x00000003,
15688 } VGT_TESS_TOPOLOGY;
15689 
15690 /*
15691  * VGT_RDREQ_POLICY enum
15692  */
15693 
15694 typedef enum VGT_RDREQ_POLICY {
15695 VGT_POLICY_LRU                           = 0x00000000,
15696 VGT_POLICY_STREAM                        = 0x00000001,
15697 } VGT_RDREQ_POLICY;
15698 
15699 /*
15700  * VGT_DIST_MODE enum
15701  */
15702 
15703 typedef enum VGT_DIST_MODE {
15704 NO_DIST                                  = 0x00000000,
15705 PATCHES                                  = 0x00000001,
15706 DONUTS                                   = 0x00000002,
15707 TRAPEZOIDS                               = 0x00000003,
15708 } VGT_DIST_MODE;
15709 
15710 /*
15711  * VGT_STAGES_LS_EN enum
15712  */
15713 
15714 typedef enum VGT_STAGES_LS_EN {
15715 LS_STAGE_OFF                             = 0x00000000,
15716 LS_STAGE_ON                              = 0x00000001,
15717 CS_STAGE_ON                              = 0x00000002,
15718 RESERVED_LS                              = 0x00000003,
15719 } VGT_STAGES_LS_EN;
15720 
15721 /*
15722  * VGT_STAGES_HS_EN enum
15723  */
15724 
15725 typedef enum VGT_STAGES_HS_EN {
15726 HS_STAGE_OFF                             = 0x00000000,
15727 HS_STAGE_ON                              = 0x00000001,
15728 } VGT_STAGES_HS_EN;
15729 
15730 /*
15731  * VGT_STAGES_ES_EN enum
15732  */
15733 
15734 typedef enum VGT_STAGES_ES_EN {
15735 ES_STAGE_OFF                             = 0x00000000,
15736 ES_STAGE_DS                              = 0x00000001,
15737 ES_STAGE_REAL                            = 0x00000002,
15738 RESERVED_ES                              = 0x00000003,
15739 } VGT_STAGES_ES_EN;
15740 
15741 /*
15742  * VGT_STAGES_GS_EN enum
15743  */
15744 
15745 typedef enum VGT_STAGES_GS_EN {
15746 GS_STAGE_OFF                             = 0x00000000,
15747 GS_STAGE_ON                              = 0x00000001,
15748 } VGT_STAGES_GS_EN;
15749 
15750 /*
15751  * VGT_STAGES_VS_EN enum
15752  */
15753 
15754 typedef enum VGT_STAGES_VS_EN {
15755 VS_STAGE_REAL                            = 0x00000000,
15756 VS_STAGE_DS                              = 0x00000001,
15757 VS_STAGE_COPY_SHADER                     = 0x00000002,
15758 RESERVED_VS                              = 0x00000003,
15759 } VGT_STAGES_VS_EN;
15760 
15761 /*
15762  * VGT_PERFCOUNT_SELECT enum
15763  */
15764 
15765 typedef enum VGT_PERFCOUNT_SELECT {
15766 vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000000,
15767 vgt_perf_VGT_SPI_ESVERT_VALID            = 0x00000001,
15768 vgt_perf_VGT_SPI_ESVERT_EOV              = 0x00000002,
15769 vgt_perf_VGT_SPI_ESVERT_STALLED          = 0x00000003,
15770 vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY     = 0x00000004,
15771 vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE     = 0x00000005,
15772 vgt_perf_VGT_SPI_ESVERT_STATIC           = 0x00000006,
15773 vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT       = 0x00000007,
15774 vgt_perf_VGT_SPI_ESTHREAD_SEND           = 0x00000008,
15775 vgt_perf_VGT_SPI_GSPRIM_VALID            = 0x00000009,
15776 vgt_perf_VGT_SPI_GSPRIM_EOV              = 0x0000000a,
15777 vgt_perf_VGT_SPI_GSPRIM_CONT             = 0x0000000b,
15778 vgt_perf_VGT_SPI_GSPRIM_STALLED          = 0x0000000c,
15779 vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY     = 0x0000000d,
15780 vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE     = 0x0000000e,
15781 vgt_perf_VGT_SPI_GSPRIM_STATIC           = 0x0000000f,
15782 vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000010,
15783 vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT       = 0x00000011,
15784 vgt_perf_VGT_SPI_GSTHREAD_SEND           = 0x00000012,
15785 vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000013,
15786 vgt_perf_VGT_SPI_VSVERT_SEND             = 0x00000014,
15787 vgt_perf_VGT_SPI_VSVERT_EOV              = 0x00000015,
15788 vgt_perf_VGT_SPI_VSVERT_STALLED          = 0x00000016,
15789 vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY     = 0x00000017,
15790 vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE     = 0x00000018,
15791 vgt_perf_VGT_SPI_VSVERT_STATIC           = 0x00000019,
15792 vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT       = 0x0000001a,
15793 vgt_perf_VGT_SPI_VSTHREAD_SEND           = 0x0000001b,
15794 vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE      = 0x0000001c,
15795 vgt_perf_VGT_PA_CLIPV_SEND               = 0x0000001d,
15796 vgt_perf_VGT_PA_CLIPV_FIRSTVERT          = 0x0000001e,
15797 vgt_perf_VGT_PA_CLIPV_STALLED            = 0x0000001f,
15798 vgt_perf_VGT_PA_CLIPV_STARVED_BUSY       = 0x00000020,
15799 vgt_perf_VGT_PA_CLIPV_STARVED_IDLE       = 0x00000021,
15800 vgt_perf_VGT_PA_CLIPV_STATIC             = 0x00000022,
15801 vgt_perf_VGT_PA_CLIPP_SEND               = 0x00000023,
15802 vgt_perf_VGT_PA_CLIPP_EOP                = 0x00000024,
15803 vgt_perf_VGT_PA_CLIPP_IS_EVENT           = 0x00000025,
15804 vgt_perf_VGT_PA_CLIPP_NULL_PRIM          = 0x00000026,
15805 vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT       = 0x00000027,
15806 vgt_perf_VGT_PA_CLIPP_STALLED            = 0x00000028,
15807 vgt_perf_VGT_PA_CLIPP_STARVED_BUSY       = 0x00000029,
15808 vgt_perf_VGT_PA_CLIPP_STARVED_IDLE       = 0x0000002a,
15809 vgt_perf_VGT_PA_CLIPP_STATIC             = 0x0000002b,
15810 vgt_perf_VGT_PA_CLIPS_SEND               = 0x0000002c,
15811 vgt_perf_VGT_PA_CLIPS_STALLED            = 0x0000002d,
15812 vgt_perf_VGT_PA_CLIPS_STARVED_BUSY       = 0x0000002e,
15813 vgt_perf_VGT_PA_CLIPS_STARVED_IDLE       = 0x0000002f,
15814 vgt_perf_VGT_PA_CLIPS_STATIC             = 0x00000030,
15815 vgt_perf_vsvert_ds_send                  = 0x00000031,
15816 vgt_perf_vsvert_api_send                 = 0x00000032,
15817 vgt_perf_hs_tif_stall                    = 0x00000033,
15818 vgt_perf_hs_input_stall                  = 0x00000034,
15819 vgt_perf_hs_interface_stall              = 0x00000035,
15820 vgt_perf_hs_tfm_stall                    = 0x00000036,
15821 vgt_perf_te11_starved                    = 0x00000037,
15822 vgt_perf_gs_event_stall                  = 0x00000038,
15823 vgt_perf_vgt_pa_clipp_send_not_event     = 0x00000039,
15824 vgt_perf_vgt_pa_clipp_valid_prim         = 0x0000003a,
15825 vgt_perf_reused_es_indices               = 0x0000003b,
15826 vgt_perf_vs_cache_hits                   = 0x0000003c,
15827 vgt_perf_gs_cache_hits                   = 0x0000003d,
15828 vgt_perf_ds_cache_hits                   = 0x0000003e,
15829 vgt_perf_total_cache_hits                = 0x0000003f,
15830 vgt_perf_vgt_busy                        = 0x00000040,
15831 vgt_perf_vgt_gs_busy                     = 0x00000041,
15832 vgt_perf_esvert_stalled_es_tbl           = 0x00000042,
15833 vgt_perf_esvert_stalled_gs_tbl           = 0x00000043,
15834 vgt_perf_esvert_stalled_gs_event         = 0x00000044,
15835 vgt_perf_esvert_stalled_gsprim           = 0x00000045,
15836 vgt_perf_gsprim_stalled_es_tbl           = 0x00000046,
15837 vgt_perf_gsprim_stalled_gs_tbl           = 0x00000047,
15838 vgt_perf_gsprim_stalled_gs_event         = 0x00000048,
15839 vgt_perf_gsprim_stalled_esvert           = 0x00000049,
15840 vgt_perf_esthread_stalled_es_rb_full     = 0x0000004a,
15841 vgt_perf_esthread_stalled_spi_bp         = 0x0000004b,
15842 vgt_perf_counters_avail_stalled          = 0x0000004c,
15843 vgt_perf_gs_rb_space_avail_stalled       = 0x0000004d,
15844 vgt_perf_gs_issue_rtr_stalled            = 0x0000004e,
15845 vgt_perf_gsthread_stalled                = 0x0000004f,
15846 vgt_perf_strmout_stalled                 = 0x00000050,
15847 vgt_perf_wait_for_es_done_stalled        = 0x00000051,
15848 vgt_perf_cm_stalled_by_gog               = 0x00000052,
15849 vgt_perf_cm_reading_stalled              = 0x00000053,
15850 vgt_perf_cm_stalled_by_gsfetch_done      = 0x00000054,
15851 vgt_perf_gog_vs_tbl_stalled              = 0x00000055,
15852 vgt_perf_gog_out_indx_stalled            = 0x00000056,
15853 vgt_perf_gog_out_prim_stalled            = 0x00000057,
15854 vgt_perf_waveid_stalled                  = 0x00000058,
15855 vgt_perf_gog_busy                        = 0x00000059,
15856 vgt_perf_reused_vs_indices               = 0x0000005a,
15857 vgt_perf_sclk_reg_vld_event              = 0x0000005b,
15858 vgt_perf_vs_conflicting_indices          = 0x0000005c,
15859 vgt_perf_sclk_core_vld_event             = 0x0000005d,
15860 vgt_perf_hswave_stalled                  = 0x0000005e,
15861 vgt_perf_sclk_gs_vld_event               = 0x0000005f,
15862 vgt_perf_VGT_SPI_LSVERT_VALID            = 0x00000060,
15863 vgt_perf_VGT_SPI_LSVERT_EOV              = 0x00000061,
15864 vgt_perf_VGT_SPI_LSVERT_STALLED          = 0x00000062,
15865 vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY     = 0x00000063,
15866 vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE     = 0x00000064,
15867 vgt_perf_VGT_SPI_LSVERT_STATIC           = 0x00000065,
15868 vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE  = 0x00000066,
15869 vgt_perf_VGT_SPI_LSWAVE_IS_EVENT         = 0x00000067,
15870 vgt_perf_VGT_SPI_LSWAVE_SEND             = 0x00000068,
15871 vgt_perf_VGT_SPI_HSVERT_VALID            = 0x00000069,
15872 vgt_perf_VGT_SPI_HSVERT_EOV              = 0x0000006a,
15873 vgt_perf_VGT_SPI_HSVERT_STALLED          = 0x0000006b,
15874 vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY     = 0x0000006c,
15875 vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE     = 0x0000006d,
15876 vgt_perf_VGT_SPI_HSVERT_STATIC           = 0x0000006e,
15877 vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE  = 0x0000006f,
15878 vgt_perf_VGT_SPI_HSWAVE_IS_EVENT         = 0x00000070,
15879 vgt_perf_VGT_SPI_HSWAVE_SEND             = 0x00000071,
15880 vgt_perf_ds_prims                        = 0x00000072,
15881 vgt_perf_ds_RESERVED                     = 0x00000073,
15882 vgt_perf_ls_thread_groups                = 0x00000074,
15883 vgt_perf_hs_thread_groups                = 0x00000075,
15884 vgt_perf_es_thread_groups                = 0x00000076,
15885 vgt_perf_vs_thread_groups                = 0x00000077,
15886 vgt_perf_ls_done_latency                 = 0x00000078,
15887 vgt_perf_hs_done_latency                 = 0x00000079,
15888 vgt_perf_es_done_latency                 = 0x0000007a,
15889 vgt_perf_gs_done_latency                 = 0x0000007b,
15890 vgt_perf_vgt_hs_busy                     = 0x0000007c,
15891 vgt_perf_vgt_te11_busy                   = 0x0000007d,
15892 vgt_perf_ls_flush                        = 0x0000007e,
15893 vgt_perf_hs_flush                        = 0x0000007f,
15894 vgt_perf_es_flush                        = 0x00000080,
15895 vgt_perf_vgt_pa_clipp_eopg               = 0x00000081,
15896 vgt_perf_ls_done                         = 0x00000082,
15897 vgt_perf_hs_done                         = 0x00000083,
15898 vgt_perf_es_done                         = 0x00000084,
15899 vgt_perf_gs_done                         = 0x00000085,
15900 vgt_perf_vsfetch_done                    = 0x00000086,
15901 vgt_perf_gs_done_received                = 0x00000087,
15902 vgt_perf_es_ring_high_water_mark         = 0x00000088,
15903 vgt_perf_gs_ring_high_water_mark         = 0x00000089,
15904 vgt_perf_vs_table_high_water_mark        = 0x0000008a,
15905 vgt_perf_hs_tgs_active_high_water_mark   = 0x0000008b,
15906 vgt_perf_pa_clipp_dealloc                = 0x0000008c,
15907 vgt_perf_cut_mem_flush_stalled           = 0x0000008d,
15908 vgt_perf_vsvert_work_received            = 0x0000008e,
15909 vgt_perf_vgt_pa_clipp_starved_after_work  = 0x0000008f,
15910 vgt_perf_te11_con_starved_after_work     = 0x00000090,
15911 vgt_perf_hs_waiting_on_ls_done_stall     = 0x00000091,
15912 vgt_spi_vsvert_valid                     = 0x00000092,
15913 } VGT_PERFCOUNT_SELECT;
15914 
15915 /*
15916  * IA_PERFCOUNT_SELECT enum
15917  */
15918 
15919 typedef enum IA_PERFCOUNT_SELECT {
15920 ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE    = 0x00000000,
15921 ia_perf_dma_data_fifo_full               = 0x00000001,
15922 ia_perf_RESERVED1                        = 0x00000002,
15923 ia_perf_RESERVED2                        = 0x00000003,
15924 ia_perf_RESERVED3                        = 0x00000004,
15925 ia_perf_RESERVED4                        = 0x00000005,
15926 ia_perf_RESERVED5                        = 0x00000006,
15927 ia_perf_MC_LAT_BIN_0                     = 0x00000007,
15928 ia_perf_MC_LAT_BIN_1                     = 0x00000008,
15929 ia_perf_MC_LAT_BIN_2                     = 0x00000009,
15930 ia_perf_MC_LAT_BIN_3                     = 0x0000000a,
15931 ia_perf_MC_LAT_BIN_4                     = 0x0000000b,
15932 ia_perf_MC_LAT_BIN_5                     = 0x0000000c,
15933 ia_perf_MC_LAT_BIN_6                     = 0x0000000d,
15934 ia_perf_MC_LAT_BIN_7                     = 0x0000000e,
15935 ia_perf_ia_busy                          = 0x0000000f,
15936 ia_perf_ia_sclk_reg_vld_event            = 0x00000010,
15937 ia_perf_RESERVED6                        = 0x00000011,
15938 ia_perf_ia_sclk_core_vld_event           = 0x00000012,
15939 ia_perf_RESERVED7                        = 0x00000013,
15940 ia_perf_ia_dma_return                    = 0x00000014,
15941 ia_perf_ia_stalled                       = 0x00000015,
15942 ia_perf_shift_starved_pipe0_event        = 0x00000016,
15943 ia_perf_shift_starved_pipe1_event        = 0x00000017,
15944 } IA_PERFCOUNT_SELECT;
15945 
15946 /*
15947  * WD_PERFCOUNT_SELECT enum
15948  */
15949 
15950 typedef enum WD_PERFCOUNT_SELECT {
15951 wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE   = 0x00000000,
15952 wd_perf_RBIU_DR_FIFO_STARVED             = 0x00000001,
15953 wd_perf_RBIU_DR_FIFO_STALLED             = 0x00000002,
15954 wd_perf_RBIU_DI_FIFO_STARVED             = 0x00000003,
15955 wd_perf_RBIU_DI_FIFO_STALLED             = 0x00000004,
15956 wd_perf_wd_busy                          = 0x00000005,
15957 wd_perf_wd_sclk_reg_vld_event            = 0x00000006,
15958 wd_perf_wd_sclk_input_vld_event          = 0x00000007,
15959 wd_perf_wd_sclk_core_vld_event           = 0x00000008,
15960 wd_perf_wd_stalled                       = 0x00000009,
15961 wd_perf_inside_tf_bin_0                  = 0x0000000a,
15962 wd_perf_inside_tf_bin_1                  = 0x0000000b,
15963 wd_perf_inside_tf_bin_2                  = 0x0000000c,
15964 wd_perf_inside_tf_bin_3                  = 0x0000000d,
15965 wd_perf_inside_tf_bin_4                  = 0x0000000e,
15966 wd_perf_inside_tf_bin_5                  = 0x0000000f,
15967 wd_perf_inside_tf_bin_6                  = 0x00000010,
15968 wd_perf_inside_tf_bin_7                  = 0x00000011,
15969 wd_perf_inside_tf_bin_8                  = 0x00000012,
15970 wd_perf_tfreq_lat_bin_0                  = 0x00000013,
15971 wd_perf_tfreq_lat_bin_1                  = 0x00000014,
15972 wd_perf_tfreq_lat_bin_2                  = 0x00000015,
15973 wd_perf_tfreq_lat_bin_3                  = 0x00000016,
15974 wd_perf_tfreq_lat_bin_4                  = 0x00000017,
15975 wd_perf_tfreq_lat_bin_5                  = 0x00000018,
15976 wd_perf_tfreq_lat_bin_6                  = 0x00000019,
15977 wd_perf_tfreq_lat_bin_7                  = 0x0000001a,
15978 wd_starved_on_hs_done                    = 0x0000001b,
15979 wd_perf_se0_hs_done_latency              = 0x0000001c,
15980 wd_perf_se1_hs_done_latency              = 0x0000001d,
15981 wd_perf_se2_hs_done_latency              = 0x0000001e,
15982 wd_perf_se3_hs_done_latency              = 0x0000001f,
15983 wd_perf_hs_done_se0                      = 0x00000020,
15984 wd_perf_hs_done_se1                      = 0x00000021,
15985 wd_perf_hs_done_se2                      = 0x00000022,
15986 wd_perf_hs_done_se3                      = 0x00000023,
15987 wd_perf_null_patches                     = 0x00000024,
15988 } WD_PERFCOUNT_SELECT;
15989 
15990 /*
15991  * WD_IA_DRAW_TYPE enum
15992  */
15993 
15994 typedef enum WD_IA_DRAW_TYPE {
15995 WD_IA_DRAW_TYPE_DI_MM0                   = 0x00000000,
15996 WD_IA_DRAW_TYPE_REG_XFER                 = 0x00000001,
15997 WD_IA_DRAW_TYPE_EVENT_INIT               = 0x00000002,
15998 WD_IA_DRAW_TYPE_EVENT_ADDR               = 0x00000003,
15999 WD_IA_DRAW_TYPE_MIN_INDX                 = 0x00000004,
16000 WD_IA_DRAW_TYPE_MAX_INDX                 = 0x00000005,
16001 WD_IA_DRAW_TYPE_INDX_OFF                 = 0x00000006,
16002 WD_IA_DRAW_TYPE_IMM_DATA                 = 0x00000007,
16003 } WD_IA_DRAW_TYPE;
16004 
16005 /*
16006  * WD_IA_DRAW_REG_XFER enum
16007  */
16008 
16009 typedef enum WD_IA_DRAW_REG_XFER {
16010 WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM   = 0x00000000,
16011 WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
16012 } WD_IA_DRAW_REG_XFER;
16013 
16014 /*
16015  * WD_IA_DRAW_SOURCE enum
16016  */
16017 
16018 typedef enum WD_IA_DRAW_SOURCE {
16019 WD_IA_DRAW_SOURCE_DMA                    = 0x00000000,
16020 WD_IA_DRAW_SOURCE_IMMD                   = 0x00000001,
16021 WD_IA_DRAW_SOURCE_AUTO                   = 0x00000002,
16022 WD_IA_DRAW_SOURCE_OPAQ                   = 0x00000003,
16023 } WD_IA_DRAW_SOURCE;
16024 
16025 /*
16026  * GS_THREADID_SIZE value
16027  */
16028 
16029 #define GSTHREADID_SIZE                0x00000002
16030 
16031 /*******************************************************
16032  * GB Enums
16033  *******************************************************/
16034 
16035 /*
16036  * GB_EDC_DED_MODE enum
16037  */
16038 
16039 typedef enum GB_EDC_DED_MODE {
16040 GB_EDC_DED_MODE_LOG                      = 0x00000000,
16041 GB_EDC_DED_MODE_HALT                     = 0x00000001,
16042 GB_EDC_DED_MODE_INT_HALT                 = 0x00000002,
16043 } GB_EDC_DED_MODE;
16044 
16045 /*
16046  * VALUE_GB_TILING_CONFIG_TABLE_SIZE value
16047  */
16048 
16049 #define GB_TILING_CONFIG_TABLE_SIZE    0x00000020
16050 
16051 /*
16052  * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value
16053  */
16054 
16055 #define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010
16056 
16057 /*******************************************************
16058  * TP Enums
16059  *******************************************************/
16060 
16061 /*
16062  * TA_TC_ADDR_MODES enum
16063  */
16064 
16065 typedef enum TA_TC_ADDR_MODES {
16066 TA_TC_ADDR_MODE_DEFAULT                  = 0x00000000,
16067 TA_TC_ADDR_MODE_COMP0                    = 0x00000001,
16068 TA_TC_ADDR_MODE_COMP1                    = 0x00000002,
16069 TA_TC_ADDR_MODE_COMP2                    = 0x00000003,
16070 TA_TC_ADDR_MODE_COMP3                    = 0x00000004,
16071 TA_TC_ADDR_MODE_UNALIGNED                = 0x00000005,
16072 TA_TC_ADDR_MODE_BORDER_COLOR             = 0x00000006,
16073 } TA_TC_ADDR_MODES;
16074 
16075 /*
16076  * TA_PERFCOUNT_SEL enum
16077  */
16078 
16079 typedef enum TA_PERFCOUNT_SEL {
16080 TA_PERF_SEL_NULL                         = 0x00000000,
16081 TA_PERF_SEL_sh_fifo_busy                 = 0x00000001,
16082 TA_PERF_SEL_sh_fifo_cmd_busy             = 0x00000002,
16083 TA_PERF_SEL_sh_fifo_addr_busy            = 0x00000003,
16084 TA_PERF_SEL_sh_fifo_data_busy            = 0x00000004,
16085 TA_PERF_SEL_sh_fifo_data_sfifo_busy      = 0x00000005,
16086 TA_PERF_SEL_sh_fifo_data_tfifo_busy      = 0x00000006,
16087 TA_PERF_SEL_gradient_busy                = 0x00000007,
16088 TA_PERF_SEL_gradient_fifo_busy           = 0x00000008,
16089 TA_PERF_SEL_lod_busy                     = 0x00000009,
16090 TA_PERF_SEL_lod_fifo_busy                = 0x0000000a,
16091 TA_PERF_SEL_addresser_busy               = 0x0000000b,
16092 TA_PERF_SEL_addresser_fifo_busy          = 0x0000000c,
16093 TA_PERF_SEL_aligner_busy                 = 0x0000000d,
16094 TA_PERF_SEL_write_path_busy              = 0x0000000e,
16095 TA_PERF_SEL_ta_busy                      = 0x0000000f,
16096 TA_PERF_SEL_sq_ta_cmd_cycles             = 0x00000010,
16097 TA_PERF_SEL_sp_ta_addr_cycles            = 0x00000011,
16098 TA_PERF_SEL_sp_ta_data_cycles            = 0x00000012,
16099 TA_PERF_SEL_ta_fa_data_state_cycles      = 0x00000013,
16100 TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles  = 0x00000014,
16101 TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles  = 0x00000015,
16102 TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles  = 0x00000016,
16103 TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles  = 0x00000017,
16104 TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles  = 0x00000018,
16105 TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles  = 0x00000019,
16106 TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles  = 0x0000001a,
16107 TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles  = 0x0000001b,
16108 TA_PERF_SEL_RESERVED_28                  = 0x0000001c,
16109 TA_PERF_SEL_RESERVED_29                  = 0x0000001d,
16110 TA_PERF_SEL_sh_fifo_addr_cycles          = 0x0000001e,
16111 TA_PERF_SEL_sh_fifo_data_cycles          = 0x0000001f,
16112 TA_PERF_SEL_total_wavefronts             = 0x00000020,
16113 TA_PERF_SEL_gradient_cycles              = 0x00000021,
16114 TA_PERF_SEL_walker_cycles                = 0x00000022,
16115 TA_PERF_SEL_aligner_cycles               = 0x00000023,
16116 TA_PERF_SEL_image_wavefronts             = 0x00000024,
16117 TA_PERF_SEL_image_read_wavefronts        = 0x00000025,
16118 TA_PERF_SEL_image_write_wavefronts       = 0x00000026,
16119 TA_PERF_SEL_image_atomic_wavefronts      = 0x00000027,
16120 TA_PERF_SEL_image_total_cycles           = 0x00000028,
16121 TA_PERF_SEL_RESERVED_41                  = 0x00000029,
16122 TA_PERF_SEL_RESERVED_42                  = 0x0000002a,
16123 TA_PERF_SEL_RESERVED_43                  = 0x0000002b,
16124 TA_PERF_SEL_buffer_wavefronts            = 0x0000002c,
16125 TA_PERF_SEL_buffer_read_wavefronts       = 0x0000002d,
16126 TA_PERF_SEL_buffer_write_wavefronts      = 0x0000002e,
16127 TA_PERF_SEL_buffer_atomic_wavefronts     = 0x0000002f,
16128 TA_PERF_SEL_buffer_coalescable_wavefronts  = 0x00000030,
16129 TA_PERF_SEL_buffer_total_cycles          = 0x00000031,
16130 TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles  = 0x00000032,
16131 TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles  = 0x00000033,
16132 TA_PERF_SEL_buffer_coalesced_read_cycles  = 0x00000034,
16133 TA_PERF_SEL_buffer_coalesced_write_cycles  = 0x00000035,
16134 TA_PERF_SEL_addr_stalled_by_tc_cycles    = 0x00000036,
16135 TA_PERF_SEL_addr_stalled_by_td_cycles    = 0x00000037,
16136 TA_PERF_SEL_data_stalled_by_tc_cycles    = 0x00000038,
16137 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles  = 0x00000039,
16138 TA_PERF_SEL_addresser_stalled_cycles     = 0x0000003a,
16139 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles  = 0x0000003b,
16140 TA_PERF_SEL_aniso_stalled_cycles         = 0x0000003c,
16141 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles  = 0x0000003d,
16142 TA_PERF_SEL_deriv_stalled_cycles         = 0x0000003e,
16143 TA_PERF_SEL_aniso_gt1_cycle_quads        = 0x0000003f,
16144 TA_PERF_SEL_color_1_cycle_pixels         = 0x00000040,
16145 TA_PERF_SEL_color_2_cycle_pixels         = 0x00000041,
16146 TA_PERF_SEL_color_3_cycle_pixels         = 0x00000042,
16147 TA_PERF_SEL_color_4_cycle_pixels         = 0x00000043,
16148 TA_PERF_SEL_mip_1_cycle_pixels           = 0x00000044,
16149 TA_PERF_SEL_mip_2_cycle_pixels           = 0x00000045,
16150 TA_PERF_SEL_vol_1_cycle_pixels           = 0x00000046,
16151 TA_PERF_SEL_vol_2_cycle_pixels           = 0x00000047,
16152 TA_PERF_SEL_bilin_point_1_cycle_pixels   = 0x00000048,
16153 TA_PERF_SEL_mipmap_lod_0_samples         = 0x00000049,
16154 TA_PERF_SEL_mipmap_lod_1_samples         = 0x0000004a,
16155 TA_PERF_SEL_mipmap_lod_2_samples         = 0x0000004b,
16156 TA_PERF_SEL_mipmap_lod_3_samples         = 0x0000004c,
16157 TA_PERF_SEL_mipmap_lod_4_samples         = 0x0000004d,
16158 TA_PERF_SEL_mipmap_lod_5_samples         = 0x0000004e,
16159 TA_PERF_SEL_mipmap_lod_6_samples         = 0x0000004f,
16160 TA_PERF_SEL_mipmap_lod_7_samples         = 0x00000050,
16161 TA_PERF_SEL_mipmap_lod_8_samples         = 0x00000051,
16162 TA_PERF_SEL_mipmap_lod_9_samples         = 0x00000052,
16163 TA_PERF_SEL_mipmap_lod_10_samples        = 0x00000053,
16164 TA_PERF_SEL_mipmap_lod_11_samples        = 0x00000054,
16165 TA_PERF_SEL_mipmap_lod_12_samples        = 0x00000055,
16166 TA_PERF_SEL_mipmap_lod_13_samples        = 0x00000056,
16167 TA_PERF_SEL_mipmap_lod_14_samples        = 0x00000057,
16168 TA_PERF_SEL_mipmap_invalid_samples       = 0x00000058,
16169 TA_PERF_SEL_aniso_1_cycle_quads          = 0x00000059,
16170 TA_PERF_SEL_aniso_2_cycle_quads          = 0x0000005a,
16171 TA_PERF_SEL_aniso_4_cycle_quads          = 0x0000005b,
16172 TA_PERF_SEL_aniso_6_cycle_quads          = 0x0000005c,
16173 TA_PERF_SEL_aniso_8_cycle_quads          = 0x0000005d,
16174 TA_PERF_SEL_aniso_10_cycle_quads         = 0x0000005e,
16175 TA_PERF_SEL_aniso_12_cycle_quads         = 0x0000005f,
16176 TA_PERF_SEL_aniso_14_cycle_quads         = 0x00000060,
16177 TA_PERF_SEL_aniso_16_cycle_quads         = 0x00000061,
16178 TA_PERF_SEL_write_path_input_cycles      = 0x00000062,
16179 TA_PERF_SEL_write_path_output_cycles     = 0x00000063,
16180 TA_PERF_SEL_flat_wavefronts              = 0x00000064,
16181 TA_PERF_SEL_flat_read_wavefronts         = 0x00000065,
16182 TA_PERF_SEL_flat_write_wavefronts        = 0x00000066,
16183 TA_PERF_SEL_flat_atomic_wavefronts       = 0x00000067,
16184 TA_PERF_SEL_flat_coalesceable_wavefronts  = 0x00000068,
16185 TA_PERF_SEL_reg_sclk_vld                 = 0x00000069,
16186 TA_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x0000006a,
16187 TA_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x0000006b,
16188 TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en  = 0x0000006c,
16189 TA_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x0000006d,
16190 TA_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x0000006e,
16191 TA_PERF_SEL_xnack_on_phase0              = 0x0000006f,
16192 TA_PERF_SEL_xnack_on_phase1              = 0x00000070,
16193 TA_PERF_SEL_xnack_on_phase2              = 0x00000071,
16194 TA_PERF_SEL_xnack_on_phase3              = 0x00000072,
16195 TA_PERF_SEL_first_xnack_on_phase0        = 0x00000073,
16196 TA_PERF_SEL_first_xnack_on_phase1        = 0x00000074,
16197 TA_PERF_SEL_first_xnack_on_phase2        = 0x00000075,
16198 TA_PERF_SEL_first_xnack_on_phase3        = 0x00000076,
16199 } TA_PERFCOUNT_SEL;
16200 
16201 /*
16202  * TD_PERFCOUNT_SEL enum
16203  */
16204 
16205 typedef enum TD_PERFCOUNT_SEL {
16206 TD_PERF_SEL_none                         = 0x00000000,
16207 TD_PERF_SEL_td_busy                      = 0x00000001,
16208 TD_PERF_SEL_input_busy                   = 0x00000002,
16209 TD_PERF_SEL_output_busy                  = 0x00000003,
16210 TD_PERF_SEL_lerp_busy                    = 0x00000004,
16211 TD_PERF_SEL_reg_sclk_vld                 = 0x00000005,
16212 TD_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x00000006,
16213 TD_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x00000007,
16214 TD_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x00000008,
16215 TD_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x00000009,
16216 TD_PERF_SEL_tc_td_fifo_full              = 0x0000000a,
16217 TD_PERF_SEL_constant_state_full          = 0x0000000b,
16218 TD_PERF_SEL_sample_state_full            = 0x0000000c,
16219 TD_PERF_SEL_output_fifo_full             = 0x0000000d,
16220 TD_PERF_SEL_RESERVED_14                  = 0x0000000e,
16221 TD_PERF_SEL_tc_stall                     = 0x0000000f,
16222 TD_PERF_SEL_pc_stall                     = 0x00000010,
16223 TD_PERF_SEL_gds_stall                    = 0x00000011,
16224 TD_PERF_SEL_RESERVED_18                  = 0x00000012,
16225 TD_PERF_SEL_RESERVED_19                  = 0x00000013,
16226 TD_PERF_SEL_gather4_wavefront            = 0x00000014,
16227 TD_PERF_SEL_gather4h_wavefront           = 0x00000015,
16228 TD_PERF_SEL_gather4h_packed_wavefront    = 0x00000016,
16229 TD_PERF_SEL_gather8h_packed_wavefront    = 0x00000017,
16230 TD_PERF_SEL_sample_c_wavefront           = 0x00000018,
16231 TD_PERF_SEL_load_wavefront               = 0x00000019,
16232 TD_PERF_SEL_atomic_wavefront             = 0x0000001a,
16233 TD_PERF_SEL_store_wavefront              = 0x0000001b,
16234 TD_PERF_SEL_ldfptr_wavefront             = 0x0000001c,
16235 TD_PERF_SEL_d16_en_wavefront             = 0x0000001d,
16236 TD_PERF_SEL_bypass_filter_wavefront      = 0x0000001e,
16237 TD_PERF_SEL_min_max_filter_wavefront     = 0x0000001f,
16238 TD_PERF_SEL_coalescable_wavefront        = 0x00000020,
16239 TD_PERF_SEL_coalesced_phase              = 0x00000021,
16240 TD_PERF_SEL_four_phase_wavefront         = 0x00000022,
16241 TD_PERF_SEL_eight_phase_wavefront        = 0x00000023,
16242 TD_PERF_SEL_sixteen_phase_wavefront      = 0x00000024,
16243 TD_PERF_SEL_four_phase_forward_wavefront  = 0x00000025,
16244 TD_PERF_SEL_write_ack_wavefront          = 0x00000026,
16245 TD_PERF_SEL_RESERVED_39                  = 0x00000027,
16246 TD_PERF_SEL_user_defined_border          = 0x00000028,
16247 TD_PERF_SEL_white_border                 = 0x00000029,
16248 TD_PERF_SEL_opaque_black_border          = 0x0000002a,
16249 TD_PERF_SEL_RESERVED_43                  = 0x0000002b,
16250 TD_PERF_SEL_RESERVED_44                  = 0x0000002c,
16251 TD_PERF_SEL_nack                         = 0x0000002d,
16252 TD_PERF_SEL_td_sp_traffic                = 0x0000002e,
16253 TD_PERF_SEL_consume_gds_traffic          = 0x0000002f,
16254 TD_PERF_SEL_addresscmd_poison            = 0x00000030,
16255 TD_PERF_SEL_data_poison                  = 0x00000031,
16256 TD_PERF_SEL_start_cycle_0                = 0x00000032,
16257 TD_PERF_SEL_start_cycle_1                = 0x00000033,
16258 TD_PERF_SEL_start_cycle_2                = 0x00000034,
16259 TD_PERF_SEL_start_cycle_3                = 0x00000035,
16260 TD_PERF_SEL_null_cycle_output            = 0x00000036,
16261 TD_PERF_SEL_d16_data_packed              = 0x00000037,
16262 TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt  = 0x00000038,
16263 } TD_PERFCOUNT_SEL;
16264 
16265 /*
16266  * TCP_PERFCOUNT_SELECT enum
16267  */
16268 
16269 typedef enum TCP_PERFCOUNT_SELECT {
16270 TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES   = 0x00000000,
16271 TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES   = 0x00000001,
16272 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES    = 0x00000002,
16273 TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES    = 0x00000003,
16274 TCP_PERF_SEL_TD_TCP_STALL_CYCLES         = 0x00000004,
16275 TCP_PERF_SEL_TCR_TCP_STALL_CYCLES        = 0x00000005,
16276 TCP_PERF_SEL_LOD_STALL_CYCLES            = 0x00000006,
16277 TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES  = 0x00000007,
16278 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES  = 0x00000008,
16279 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES  = 0x00000009,
16280 TCP_PERF_SEL_ALLOC_STALL_CYCLES          = 0x0000000a,
16281 TCP_PERF_SEL_LFIFO_STALL_CYCLES          = 0x0000000b,
16282 TCP_PERF_SEL_RFIFO_STALL_CYCLES          = 0x0000000c,
16283 TCP_PERF_SEL_TCR_RDRET_STALL             = 0x0000000d,
16284 TCP_PERF_SEL_WRITE_CONFLICT_STALL        = 0x0000000e,
16285 TCP_PERF_SEL_HOLE_READ_STALL             = 0x0000000f,
16286 TCP_PERF_SEL_READCONFLICT_STALL_CYCLES   = 0x00000010,
16287 TCP_PERF_SEL_PENDING_STALL_CYCLES        = 0x00000011,
16288 TCP_PERF_SEL_READFIFO_STALL_CYCLES       = 0x00000012,
16289 TCP_PERF_SEL_TCP_LATENCY                 = 0x00000013,
16290 TCP_PERF_SEL_TCC_READ_REQ_LATENCY        = 0x00000014,
16291 TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY       = 0x00000015,
16292 TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY  = 0x00000016,
16293 TCP_PERF_SEL_TCC_READ_REQ                = 0x00000017,
16294 TCP_PERF_SEL_TCC_WRITE_REQ               = 0x00000018,
16295 TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ     = 0x00000019,
16296 TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ  = 0x0000001a,
16297 TCP_PERF_SEL_TOTAL_LOCAL_READ            = 0x0000001b,
16298 TCP_PERF_SEL_TOTAL_GLOBAL_READ           = 0x0000001c,
16299 TCP_PERF_SEL_TOTAL_LOCAL_WRITE           = 0x0000001d,
16300 TCP_PERF_SEL_TOTAL_GLOBAL_WRITE          = 0x0000001e,
16301 TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET       = 0x0000001f,
16302 TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET    = 0x00000020,
16303 TCP_PERF_SEL_TOTAL_WBINVL1               = 0x00000021,
16304 TCP_PERF_SEL_IMG_READ_FMT_1              = 0x00000022,
16305 TCP_PERF_SEL_IMG_READ_FMT_8              = 0x00000023,
16306 TCP_PERF_SEL_IMG_READ_FMT_16             = 0x00000024,
16307 TCP_PERF_SEL_IMG_READ_FMT_32             = 0x00000025,
16308 TCP_PERF_SEL_IMG_READ_FMT_32_AS_8        = 0x00000026,
16309 TCP_PERF_SEL_IMG_READ_FMT_32_AS_16       = 0x00000027,
16310 TCP_PERF_SEL_IMG_READ_FMT_32_AS_128      = 0x00000028,
16311 TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE     = 0x00000029,
16312 TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE     = 0x0000002a,
16313 TCP_PERF_SEL_IMG_READ_FMT_96             = 0x0000002b,
16314 TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE    = 0x0000002c,
16315 TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE    = 0x0000002d,
16316 TCP_PERF_SEL_IMG_READ_FMT_BC1            = 0x0000002e,
16317 TCP_PERF_SEL_IMG_READ_FMT_BC2            = 0x0000002f,
16318 TCP_PERF_SEL_IMG_READ_FMT_BC3            = 0x00000030,
16319 TCP_PERF_SEL_IMG_READ_FMT_BC4            = 0x00000031,
16320 TCP_PERF_SEL_IMG_READ_FMT_BC5            = 0x00000032,
16321 TCP_PERF_SEL_IMG_READ_FMT_BC6            = 0x00000033,
16322 TCP_PERF_SEL_IMG_READ_FMT_BC7            = 0x00000034,
16323 TCP_PERF_SEL_IMG_READ_FMT_I8             = 0x00000035,
16324 TCP_PERF_SEL_IMG_READ_FMT_I16            = 0x00000036,
16325 TCP_PERF_SEL_IMG_READ_FMT_I32            = 0x00000037,
16326 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8       = 0x00000038,
16327 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16      = 0x00000039,
16328 TCP_PERF_SEL_IMG_READ_FMT_D8             = 0x0000003a,
16329 TCP_PERF_SEL_IMG_READ_FMT_D16            = 0x0000003b,
16330 TCP_PERF_SEL_IMG_READ_FMT_D32            = 0x0000003c,
16331 TCP_PERF_SEL_IMG_WRITE_FMT_8             = 0x0000003d,
16332 TCP_PERF_SEL_IMG_WRITE_FMT_16            = 0x0000003e,
16333 TCP_PERF_SEL_IMG_WRITE_FMT_32            = 0x0000003f,
16334 TCP_PERF_SEL_IMG_WRITE_FMT_64            = 0x00000040,
16335 TCP_PERF_SEL_IMG_WRITE_FMT_128           = 0x00000041,
16336 TCP_PERF_SEL_IMG_WRITE_FMT_D8            = 0x00000042,
16337 TCP_PERF_SEL_IMG_WRITE_FMT_D16           = 0x00000043,
16338 TCP_PERF_SEL_IMG_WRITE_FMT_D32           = 0x00000044,
16339 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32  = 0x00000045,
16340 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32  = 0x00000046,
16341 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64  = 0x00000047,
16342 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64  = 0x00000048,
16343 TCP_PERF_SEL_BUF_READ_FMT_8              = 0x00000049,
16344 TCP_PERF_SEL_BUF_READ_FMT_16             = 0x0000004a,
16345 TCP_PERF_SEL_BUF_READ_FMT_32             = 0x0000004b,
16346 TCP_PERF_SEL_BUF_WRITE_FMT_8             = 0x0000004c,
16347 TCP_PERF_SEL_BUF_WRITE_FMT_16            = 0x0000004d,
16348 TCP_PERF_SEL_BUF_WRITE_FMT_32            = 0x0000004e,
16349 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32  = 0x0000004f,
16350 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32  = 0x00000050,
16351 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64  = 0x00000051,
16352 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64  = 0x00000052,
16353 TCP_PERF_SEL_ARR_LINEAR_GENERAL          = 0x00000053,
16354 TCP_PERF_SEL_ARR_LINEAR_ALIGNED          = 0x00000054,
16355 TCP_PERF_SEL_ARR_1D_THIN1                = 0x00000055,
16356 TCP_PERF_SEL_ARR_1D_THICK                = 0x00000056,
16357 TCP_PERF_SEL_ARR_2D_THIN1                = 0x00000057,
16358 TCP_PERF_SEL_ARR_2D_THICK                = 0x00000058,
16359 TCP_PERF_SEL_ARR_2D_XTHICK               = 0x00000059,
16360 TCP_PERF_SEL_ARR_3D_THIN1                = 0x0000005a,
16361 TCP_PERF_SEL_ARR_3D_THICK                = 0x0000005b,
16362 TCP_PERF_SEL_ARR_3D_XTHICK               = 0x0000005c,
16363 TCP_PERF_SEL_DIM_1D                      = 0x0000005d,
16364 TCP_PERF_SEL_DIM_2D                      = 0x0000005e,
16365 TCP_PERF_SEL_DIM_3D                      = 0x0000005f,
16366 TCP_PERF_SEL_DIM_1D_ARRAY                = 0x00000060,
16367 TCP_PERF_SEL_DIM_2D_ARRAY                = 0x00000061,
16368 TCP_PERF_SEL_DIM_2D_MSAA                 = 0x00000062,
16369 TCP_PERF_SEL_DIM_2D_ARRAY_MSAA           = 0x00000063,
16370 TCP_PERF_SEL_DIM_CUBE_ARRAY              = 0x00000064,
16371 TCP_PERF_SEL_CP_TCP_INVALIDATE           = 0x00000065,
16372 TCP_PERF_SEL_TA_TCP_STATE_READ           = 0x00000066,
16373 TCP_PERF_SEL_TAGRAM0_REQ                 = 0x00000067,
16374 TCP_PERF_SEL_TAGRAM1_REQ                 = 0x00000068,
16375 TCP_PERF_SEL_TAGRAM2_REQ                 = 0x00000069,
16376 TCP_PERF_SEL_TAGRAM3_REQ                 = 0x0000006a,
16377 TCP_PERF_SEL_GATE_EN1                    = 0x0000006b,
16378 TCP_PERF_SEL_GATE_EN2                    = 0x0000006c,
16379 TCP_PERF_SEL_CORE_REG_SCLK_VLD           = 0x0000006d,
16380 TCP_PERF_SEL_TCC_REQ                     = 0x0000006e,
16381 TCP_PERF_SEL_TCC_NON_READ_REQ            = 0x0000006f,
16382 TCP_PERF_SEL_TCC_BYPASS_READ_REQ         = 0x00000070,
16383 TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ     = 0x00000071,
16384 TCP_PERF_SEL_TCC_VOLATILE_READ_REQ       = 0x00000072,
16385 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ  = 0x00000073,
16386 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ  = 0x00000074,
16387 TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ        = 0x00000075,
16388 TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ    = 0x00000076,
16389 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ  = 0x00000077,
16390 TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ      = 0x00000078,
16391 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ  = 0x00000079,
16392 TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ       = 0x0000007a,
16393 TCP_PERF_SEL_TCC_ATOMIC_REQ              = 0x0000007b,
16394 TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ     = 0x0000007c,
16395 TCP_PERF_SEL_TCC_DATA_BUS_BUSY           = 0x0000007d,
16396 TCP_PERF_SEL_TOTAL_ACCESSES              = 0x0000007e,
16397 TCP_PERF_SEL_TOTAL_READ                  = 0x0000007f,
16398 TCP_PERF_SEL_TOTAL_HIT_LRU_READ          = 0x00000080,
16399 TCP_PERF_SEL_TOTAL_HIT_EVICT_READ        = 0x00000081,
16400 TCP_PERF_SEL_TOTAL_MISS_LRU_READ         = 0x00000082,
16401 TCP_PERF_SEL_TOTAL_MISS_EVICT_READ       = 0x00000083,
16402 TCP_PERF_SEL_TOTAL_NON_READ              = 0x00000084,
16403 TCP_PERF_SEL_TOTAL_WRITE                 = 0x00000085,
16404 TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE        = 0x00000086,
16405 TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE      = 0x00000087,
16406 TCP_PERF_SEL_TOTAL_WBINVL1_VOL           = 0x00000088,
16407 TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES  = 0x00000089,
16408 TCP_PERF_SEL_DISPLAY_MICROTILING         = 0x0000008a,
16409 TCP_PERF_SEL_THIN_MICROTILING            = 0x0000008b,
16410 TCP_PERF_SEL_DEPTH_MICROTILING           = 0x0000008c,
16411 TCP_PERF_SEL_ARR_PRT_THIN1               = 0x0000008d,
16412 TCP_PERF_SEL_ARR_PRT_2D_THIN1            = 0x0000008e,
16413 TCP_PERF_SEL_ARR_PRT_3D_THIN1            = 0x0000008f,
16414 TCP_PERF_SEL_ARR_PRT_THICK               = 0x00000090,
16415 TCP_PERF_SEL_ARR_PRT_2D_THICK            = 0x00000091,
16416 TCP_PERF_SEL_ARR_PRT_3D_THICK            = 0x00000092,
16417 TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL       = 0x00000093,
16418 TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL       = 0x00000094,
16419 TCP_PERF_SEL_UNALIGNED                   = 0x00000095,
16420 TCP_PERF_SEL_ROTATED_MICROTILING         = 0x00000096,
16421 TCP_PERF_SEL_THICK_MICROTILING           = 0x00000097,
16422 TCP_PERF_SEL_ATC                         = 0x00000098,
16423 TCP_PERF_SEL_POWER_STALL                 = 0x00000099,
16424 TCP_PERF_SEL_RESERVED_154                = 0x0000009a,
16425 TCP_PERF_SEL_TCC_LRU_REQ                 = 0x0000009b,
16426 TCP_PERF_SEL_TCC_STREAM_REQ              = 0x0000009c,
16427 TCP_PERF_SEL_TCC_NC_READ_REQ             = 0x0000009d,
16428 TCP_PERF_SEL_TCC_NC_WRITE_REQ            = 0x0000009e,
16429 TCP_PERF_SEL_TCC_NC_ATOMIC_REQ           = 0x0000009f,
16430 TCP_PERF_SEL_TCC_UC_READ_REQ             = 0x000000a0,
16431 TCP_PERF_SEL_TCC_UC_WRITE_REQ            = 0x000000a1,
16432 TCP_PERF_SEL_TCC_UC_ATOMIC_REQ           = 0x000000a2,
16433 TCP_PERF_SEL_TCC_CC_READ_REQ             = 0x000000a3,
16434 TCP_PERF_SEL_TCC_CC_WRITE_REQ            = 0x000000a4,
16435 TCP_PERF_SEL_TCC_CC_ATOMIC_REQ           = 0x000000a5,
16436 TCP_PERF_SEL_TCC_DCC_REQ                 = 0x000000a6,
16437 TCP_PERF_SEL_TCC_PHYSICAL_REQ            = 0x000000a7,
16438 TCP_PERF_SEL_UNORDERED_MTYPE_STALL       = 0x000000a8,
16439 TCP_PERF_SEL_VOLATILE                    = 0x000000a9,
16440 TCP_PERF_SEL_TC_TA_XNACK_STALL           = 0x000000aa,
16441 TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL   = 0x000000ab,
16442 TCP_PERF_SEL_SHOOTDOWN                   = 0x000000ac,
16443 TCP_PERF_SEL_UTCL1_TRANSLATION_MISS      = 0x000000ad,
16444 TCP_PERF_SEL_UTCL1_PERMISSION_MISS       = 0x000000ae,
16445 TCP_PERF_SEL_UTCL1_REQUEST               = 0x000000af,
16446 TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX    = 0x000000b0,
16447 TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT    = 0x000000b1,
16448 TCP_PERF_SEL_UTCL1_LFIFO_FULL            = 0x000000b2,
16449 TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES   = 0x000000b3,
16450 TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x000000b4,
16451 TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT        = 0x000000b5,
16452 TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL   = 0x000000b6,
16453 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB       = 0x000000b7,
16454 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA      = 0x000000b8,
16455 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1     = 0x000000b9,
16456 TCP_PERF_SEL_IMG_READ_FMT_ETC2_R         = 0x000000ba,
16457 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG        = 0x000000bb,
16458 TCP_PERF_SEL_IMG_READ_FMT_8_AS_32        = 0x000000bc,
16459 TCP_PERF_SEL_IMG_READ_FMT_8_AS_64        = 0x000000bd,
16460 TCP_PERF_SEL_IMG_READ_FMT_16_AS_64       = 0x000000be,
16461 TCP_PERF_SEL_IMG_READ_FMT_16_AS_128      = 0x000000bf,
16462 TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32       = 0x000000c0,
16463 TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64       = 0x000000c1,
16464 TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64      = 0x000000c2,
16465 TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128     = 0x000000c3,
16466 } TCP_PERFCOUNT_SELECT;
16467 
16468 /*
16469  * TCP_CACHE_POLICIES enum
16470  */
16471 
16472 typedef enum TCP_CACHE_POLICIES {
16473 TCP_CACHE_POLICY_MISS_LRU                = 0x00000000,
16474 TCP_CACHE_POLICY_MISS_EVICT              = 0x00000001,
16475 TCP_CACHE_POLICY_HIT_LRU                 = 0x00000002,
16476 TCP_CACHE_POLICY_HIT_EVICT               = 0x00000003,
16477 } TCP_CACHE_POLICIES;
16478 
16479 /*
16480  * TCP_CACHE_STORE_POLICIES enum
16481  */
16482 
16483 typedef enum TCP_CACHE_STORE_POLICIES {
16484 TCP_CACHE_STORE_POLICY_WT_LRU            = 0x00000000,
16485 TCP_CACHE_STORE_POLICY_WT_EVICT          = 0x00000001,
16486 } TCP_CACHE_STORE_POLICIES;
16487 
16488 /*
16489  * TCP_WATCH_MODES enum
16490  */
16491 
16492 typedef enum TCP_WATCH_MODES {
16493 TCP_WATCH_MODE_READ                      = 0x00000000,
16494 TCP_WATCH_MODE_NONREAD                   = 0x00000001,
16495 TCP_WATCH_MODE_ATOMIC                    = 0x00000002,
16496 TCP_WATCH_MODE_ALL                       = 0x00000003,
16497 } TCP_WATCH_MODES;
16498 
16499 /*
16500  * TCP_DSM_DATA_SEL enum
16501  */
16502 
16503 typedef enum TCP_DSM_DATA_SEL {
16504 TCP_DSM_DISABLE                          = 0x00000000,
16505 TCP_DSM_SEL0                             = 0x00000001,
16506 TCP_DSM_SEL1                             = 0x00000002,
16507 TCP_DSM_SEL_BOTH                         = 0x00000003,
16508 } TCP_DSM_DATA_SEL;
16509 
16510 /*
16511  * TCP_DSM_SINGLE_WRITE enum
16512  */
16513 
16514 typedef enum TCP_DSM_SINGLE_WRITE {
16515 TCP_DSM_SINGLE_WRITE_DIS                 = 0x00000000,
16516 TCP_DSM_SINGLE_WRITE_EN                  = 0x00000001,
16517 } TCP_DSM_SINGLE_WRITE;
16518 
16519 /*
16520  * TCP_DSM_INJECT_SEL enum
16521  */
16522 
16523 typedef enum TCP_DSM_INJECT_SEL {
16524 TCP_DSM_INJECT_SEL0                      = 0x00000000,
16525 TCP_DSM_INJECT_SEL1                      = 0x00000001,
16526 TCP_DSM_INJECT_SEL2                      = 0x00000002,
16527 TCP_DSM_INJECT_SEL3                      = 0x00000003,
16528 } TCP_DSM_INJECT_SEL;
16529 
16530 /*******************************************************
16531  * TCC Enums
16532  *******************************************************/
16533 
16534 /*
16535  * TCC_PERF_SEL enum
16536  */
16537 
16538 typedef enum TCC_PERF_SEL {
16539 TCC_PERF_SEL_NONE                        = 0x00000000,
16540 TCC_PERF_SEL_CYCLE                       = 0x00000001,
16541 TCC_PERF_SEL_BUSY                        = 0x00000002,
16542 TCC_PERF_SEL_REQ                         = 0x00000003,
16543 TCC_PERF_SEL_STREAMING_REQ               = 0x00000004,
16544 TCC_PERF_SEL_EXE_REQ                     = 0x00000005,
16545 TCC_PERF_SEL_COMPRESSED_REQ              = 0x00000006,
16546 TCC_PERF_SEL_COMPRESSED_0_REQ            = 0x00000007,
16547 TCC_PERF_SEL_METADATA_REQ                = 0x00000008,
16548 TCC_PERF_SEL_NC_VIRTUAL_REQ              = 0x00000009,
16549 TCC_PERF_SEL_UC_VIRTUAL_REQ              = 0x0000000a,
16550 TCC_PERF_SEL_CC_PHYSICAL_REQ             = 0x0000000b,
16551 TCC_PERF_SEL_PROBE                       = 0x0000000c,
16552 TCC_PERF_SEL_PROBE_ALL                   = 0x0000000d,
16553 TCC_PERF_SEL_READ                        = 0x0000000e,
16554 TCC_PERF_SEL_WRITE                       = 0x0000000f,
16555 TCC_PERF_SEL_ATOMIC                      = 0x00000010,
16556 TCC_PERF_SEL_HIT                         = 0x00000011,
16557 TCC_PERF_SEL_SECTOR_HIT                  = 0x00000012,
16558 TCC_PERF_SEL_MISS                        = 0x00000013,
16559 TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT        = 0x00000014,
16560 TCC_PERF_SEL_FULLY_WRITTEN_HIT           = 0x00000015,
16561 TCC_PERF_SEL_WRITEBACK                   = 0x00000016,
16562 TCC_PERF_SEL_LATENCY_FIFO_FULL           = 0x00000017,
16563 TCC_PERF_SEL_SRC_FIFO_FULL               = 0x00000018,
16564 TCC_PERF_SEL_HOLE_FIFO_FULL              = 0x00000019,
16565 TCC_PERF_SEL_EA_WRREQ                    = 0x0000001a,
16566 TCC_PERF_SEL_EA_WRREQ_64B                = 0x0000001b,
16567 TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND      = 0x0000001c,
16568 TCC_PERF_SEL_EA_WR_UNCACHED_32B          = 0x0000001d,
16569 TCC_PERF_SEL_EA_WRREQ_STALL              = 0x0000001e,
16570 TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL       = 0x0000001f,
16571 TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL    = 0x00000020,
16572 TCC_PERF_SEL_EA_WRREQ_LEVEL              = 0x00000021,
16573 TCC_PERF_SEL_EA_ATOMIC                   = 0x00000022,
16574 TCC_PERF_SEL_EA_ATOMIC_LEVEL             = 0x00000023,
16575 TCC_PERF_SEL_EA_RDREQ                    = 0x00000024,
16576 TCC_PERF_SEL_EA_RDREQ_32B                = 0x00000025,
16577 TCC_PERF_SEL_EA_RD_UNCACHED_32B          = 0x00000026,
16578 TCC_PERF_SEL_EA_RD_MDC_32B               = 0x00000027,
16579 TCC_PERF_SEL_EA_RD_COMPRESSED_32B        = 0x00000028,
16580 TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL       = 0x00000029,
16581 TCC_PERF_SEL_EA_RDREQ_LEVEL              = 0x0000002a,
16582 TCC_PERF_SEL_TAG_STALL                   = 0x0000002b,
16583 TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL  = 0x0000002c,
16584 TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x0000002d,
16585 TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL  = 0x0000002e,
16586 TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL  = 0x0000002f,
16587 TCC_PERF_SEL_TAG_PROBE_STALL             = 0x00000030,
16588 TCC_PERF_SEL_TAG_PROBE_FILTER_STALL      = 0x00000031,
16589 TCC_PERF_SEL_READ_RETURN_TIMEOUT         = 0x00000032,
16590 TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT      = 0x00000033,
16591 TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE     = 0x00000034,
16592 TCC_PERF_SEL_BUBBLE                      = 0x00000035,
16593 TCC_PERF_SEL_RETURN_ACK                  = 0x00000036,
16594 TCC_PERF_SEL_RETURN_DATA                 = 0x00000037,
16595 TCC_PERF_SEL_RETURN_HOLE                 = 0x00000038,
16596 TCC_PERF_SEL_RETURN_ACK_HOLE             = 0x00000039,
16597 TCC_PERF_SEL_IB_REQ                      = 0x0000003a,
16598 TCC_PERF_SEL_IB_STALL                    = 0x0000003b,
16599 TCC_PERF_SEL_IB_TAG_STALL                = 0x0000003c,
16600 TCC_PERF_SEL_IB_MDC_STALL                = 0x0000003d,
16601 TCC_PERF_SEL_TCA_LEVEL                   = 0x0000003e,
16602 TCC_PERF_SEL_HOLE_LEVEL                  = 0x0000003f,
16603 TCC_PERF_SEL_NORMAL_WRITEBACK            = 0x00000040,
16604 TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK     = 0x00000041,
16605 TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK     = 0x00000042,
16606 TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK     = 0x00000043,
16607 TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK  = 0x00000044,
16608 TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK  = 0x00000045,
16609 TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK      = 0x00000046,
16610 TCC_PERF_SEL_NORMAL_EVICT                = 0x00000047,
16611 TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT         = 0x00000048,
16612 TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT         = 0x00000049,
16613 TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT        = 0x0000004a,
16614 TCC_PERF_SEL_TC_OP_WBINVL2_EVICT         = 0x0000004b,
16615 TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT      = 0x0000004c,
16616 TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT      = 0x0000004d,
16617 TCC_PERF_SEL_ALL_TC_OP_INV_EVICT         = 0x0000004e,
16618 TCC_PERF_SEL_PROBE_EVICT                 = 0x0000004f,
16619 TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE         = 0x00000050,
16620 TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE         = 0x00000051,
16621 TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE        = 0x00000052,
16622 TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE         = 0x00000053,
16623 TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE      = 0x00000054,
16624 TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE      = 0x00000055,
16625 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE   = 0x00000056,
16626 TCC_PERF_SEL_TC_OP_WBL2_NC_START         = 0x00000057,
16627 TCC_PERF_SEL_TC_OP_WBL2_WC_START         = 0x00000058,
16628 TCC_PERF_SEL_TC_OP_INVL2_NC_START        = 0x00000059,
16629 TCC_PERF_SEL_TC_OP_WBINVL2_START         = 0x0000005a,
16630 TCC_PERF_SEL_TC_OP_WBINVL2_NC_START      = 0x0000005b,
16631 TCC_PERF_SEL_TC_OP_WBINVL2_SD_START      = 0x0000005c,
16632 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START   = 0x0000005d,
16633 TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH        = 0x0000005e,
16634 TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH        = 0x0000005f,
16635 TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH       = 0x00000060,
16636 TCC_PERF_SEL_TC_OP_WBINVL2_FINISH        = 0x00000061,
16637 TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH     = 0x00000062,
16638 TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH     = 0x00000063,
16639 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH  = 0x00000064,
16640 TCC_PERF_SEL_MDC_REQ                     = 0x00000065,
16641 TCC_PERF_SEL_MDC_LEVEL                   = 0x00000066,
16642 TCC_PERF_SEL_MDC_TAG_HIT                 = 0x00000067,
16643 TCC_PERF_SEL_MDC_SECTOR_HIT              = 0x00000068,
16644 TCC_PERF_SEL_MDC_SECTOR_MISS             = 0x00000069,
16645 TCC_PERF_SEL_MDC_TAG_STALL               = 0x0000006a,
16646 TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL  = 0x0000006b,
16647 TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL  = 0x0000006c,
16648 TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL  = 0x0000006d,
16649 TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION  = 0x0000006e,
16650 TCC_PERF_SEL_PROBE_FILTER_DISABLED       = 0x0000006f,
16651 TCC_PERF_SEL_CLIENT0_REQ                 = 0x00000080,
16652 TCC_PERF_SEL_CLIENT1_REQ                 = 0x00000081,
16653 TCC_PERF_SEL_CLIENT2_REQ                 = 0x00000082,
16654 TCC_PERF_SEL_CLIENT3_REQ                 = 0x00000083,
16655 TCC_PERF_SEL_CLIENT4_REQ                 = 0x00000084,
16656 TCC_PERF_SEL_CLIENT5_REQ                 = 0x00000085,
16657 TCC_PERF_SEL_CLIENT6_REQ                 = 0x00000086,
16658 TCC_PERF_SEL_CLIENT7_REQ                 = 0x00000087,
16659 TCC_PERF_SEL_CLIENT8_REQ                 = 0x00000088,
16660 TCC_PERF_SEL_CLIENT9_REQ                 = 0x00000089,
16661 TCC_PERF_SEL_CLIENT10_REQ                = 0x0000008a,
16662 TCC_PERF_SEL_CLIENT11_REQ                = 0x0000008b,
16663 TCC_PERF_SEL_CLIENT12_REQ                = 0x0000008c,
16664 TCC_PERF_SEL_CLIENT13_REQ                = 0x0000008d,
16665 TCC_PERF_SEL_CLIENT14_REQ                = 0x0000008e,
16666 TCC_PERF_SEL_CLIENT15_REQ                = 0x0000008f,
16667 TCC_PERF_SEL_CLIENT16_REQ                = 0x00000090,
16668 TCC_PERF_SEL_CLIENT17_REQ                = 0x00000091,
16669 TCC_PERF_SEL_CLIENT18_REQ                = 0x00000092,
16670 TCC_PERF_SEL_CLIENT19_REQ                = 0x00000093,
16671 TCC_PERF_SEL_CLIENT20_REQ                = 0x00000094,
16672 TCC_PERF_SEL_CLIENT21_REQ                = 0x00000095,
16673 TCC_PERF_SEL_CLIENT22_REQ                = 0x00000096,
16674 TCC_PERF_SEL_CLIENT23_REQ                = 0x00000097,
16675 TCC_PERF_SEL_CLIENT24_REQ                = 0x00000098,
16676 TCC_PERF_SEL_CLIENT25_REQ                = 0x00000099,
16677 TCC_PERF_SEL_CLIENT26_REQ                = 0x0000009a,
16678 TCC_PERF_SEL_CLIENT27_REQ                = 0x0000009b,
16679 TCC_PERF_SEL_CLIENT28_REQ                = 0x0000009c,
16680 TCC_PERF_SEL_CLIENT29_REQ                = 0x0000009d,
16681 TCC_PERF_SEL_CLIENT30_REQ                = 0x0000009e,
16682 TCC_PERF_SEL_CLIENT31_REQ                = 0x0000009f,
16683 TCC_PERF_SEL_CLIENT32_REQ                = 0x000000a0,
16684 TCC_PERF_SEL_CLIENT33_REQ                = 0x000000a1,
16685 TCC_PERF_SEL_CLIENT34_REQ                = 0x000000a2,
16686 TCC_PERF_SEL_CLIENT35_REQ                = 0x000000a3,
16687 TCC_PERF_SEL_CLIENT36_REQ                = 0x000000a4,
16688 TCC_PERF_SEL_CLIENT37_REQ                = 0x000000a5,
16689 TCC_PERF_SEL_CLIENT38_REQ                = 0x000000a6,
16690 TCC_PERF_SEL_CLIENT39_REQ                = 0x000000a7,
16691 TCC_PERF_SEL_CLIENT40_REQ                = 0x000000a8,
16692 TCC_PERF_SEL_CLIENT41_REQ                = 0x000000a9,
16693 TCC_PERF_SEL_CLIENT42_REQ                = 0x000000aa,
16694 TCC_PERF_SEL_CLIENT43_REQ                = 0x000000ab,
16695 TCC_PERF_SEL_CLIENT44_REQ                = 0x000000ac,
16696 TCC_PERF_SEL_CLIENT45_REQ                = 0x000000ad,
16697 TCC_PERF_SEL_CLIENT46_REQ                = 0x000000ae,
16698 TCC_PERF_SEL_CLIENT47_REQ                = 0x000000af,
16699 TCC_PERF_SEL_CLIENT48_REQ                = 0x000000b0,
16700 TCC_PERF_SEL_CLIENT49_REQ                = 0x000000b1,
16701 TCC_PERF_SEL_CLIENT50_REQ                = 0x000000b2,
16702 TCC_PERF_SEL_CLIENT51_REQ                = 0x000000b3,
16703 TCC_PERF_SEL_CLIENT52_REQ                = 0x000000b4,
16704 TCC_PERF_SEL_CLIENT53_REQ                = 0x000000b5,
16705 TCC_PERF_SEL_CLIENT54_REQ                = 0x000000b6,
16706 TCC_PERF_SEL_CLIENT55_REQ                = 0x000000b7,
16707 TCC_PERF_SEL_CLIENT56_REQ                = 0x000000b8,
16708 TCC_PERF_SEL_CLIENT57_REQ                = 0x000000b9,
16709 TCC_PERF_SEL_CLIENT58_REQ                = 0x000000ba,
16710 TCC_PERF_SEL_CLIENT59_REQ                = 0x000000bb,
16711 TCC_PERF_SEL_CLIENT60_REQ                = 0x000000bc,
16712 TCC_PERF_SEL_CLIENT61_REQ                = 0x000000bd,
16713 TCC_PERF_SEL_CLIENT62_REQ                = 0x000000be,
16714 TCC_PERF_SEL_CLIENT63_REQ                = 0x000000bf,
16715 TCC_PERF_SEL_CLIENT64_REQ                = 0x000000c0,
16716 TCC_PERF_SEL_CLIENT65_REQ                = 0x000000c1,
16717 TCC_PERF_SEL_CLIENT66_REQ                = 0x000000c2,
16718 TCC_PERF_SEL_CLIENT67_REQ                = 0x000000c3,
16719 TCC_PERF_SEL_CLIENT68_REQ                = 0x000000c4,
16720 TCC_PERF_SEL_CLIENT69_REQ                = 0x000000c5,
16721 TCC_PERF_SEL_CLIENT70_REQ                = 0x000000c6,
16722 TCC_PERF_SEL_CLIENT71_REQ                = 0x000000c7,
16723 TCC_PERF_SEL_CLIENT72_REQ                = 0x000000c8,
16724 TCC_PERF_SEL_CLIENT73_REQ                = 0x000000c9,
16725 TCC_PERF_SEL_CLIENT74_REQ                = 0x000000ca,
16726 TCC_PERF_SEL_CLIENT75_REQ                = 0x000000cb,
16727 TCC_PERF_SEL_CLIENT76_REQ                = 0x000000cc,
16728 TCC_PERF_SEL_CLIENT77_REQ                = 0x000000cd,
16729 TCC_PERF_SEL_CLIENT78_REQ                = 0x000000ce,
16730 TCC_PERF_SEL_CLIENT79_REQ                = 0x000000cf,
16731 TCC_PERF_SEL_CLIENT80_REQ                = 0x000000d0,
16732 TCC_PERF_SEL_CLIENT81_REQ                = 0x000000d1,
16733 TCC_PERF_SEL_CLIENT82_REQ                = 0x000000d2,
16734 TCC_PERF_SEL_CLIENT83_REQ                = 0x000000d3,
16735 TCC_PERF_SEL_CLIENT84_REQ                = 0x000000d4,
16736 TCC_PERF_SEL_CLIENT85_REQ                = 0x000000d5,
16737 TCC_PERF_SEL_CLIENT86_REQ                = 0x000000d6,
16738 TCC_PERF_SEL_CLIENT87_REQ                = 0x000000d7,
16739 TCC_PERF_SEL_CLIENT88_REQ                = 0x000000d8,
16740 TCC_PERF_SEL_CLIENT89_REQ                = 0x000000d9,
16741 TCC_PERF_SEL_CLIENT90_REQ                = 0x000000da,
16742 TCC_PERF_SEL_CLIENT91_REQ                = 0x000000db,
16743 TCC_PERF_SEL_CLIENT92_REQ                = 0x000000dc,
16744 TCC_PERF_SEL_CLIENT93_REQ                = 0x000000dd,
16745 TCC_PERF_SEL_CLIENT94_REQ                = 0x000000de,
16746 TCC_PERF_SEL_CLIENT95_REQ                = 0x000000df,
16747 TCC_PERF_SEL_CLIENT96_REQ                = 0x000000e0,
16748 TCC_PERF_SEL_CLIENT97_REQ                = 0x000000e1,
16749 TCC_PERF_SEL_CLIENT98_REQ                = 0x000000e2,
16750 TCC_PERF_SEL_CLIENT99_REQ                = 0x000000e3,
16751 TCC_PERF_SEL_CLIENT100_REQ               = 0x000000e4,
16752 TCC_PERF_SEL_CLIENT101_REQ               = 0x000000e5,
16753 TCC_PERF_SEL_CLIENT102_REQ               = 0x000000e6,
16754 TCC_PERF_SEL_CLIENT103_REQ               = 0x000000e7,
16755 TCC_PERF_SEL_CLIENT104_REQ               = 0x000000e8,
16756 TCC_PERF_SEL_CLIENT105_REQ               = 0x000000e9,
16757 TCC_PERF_SEL_CLIENT106_REQ               = 0x000000ea,
16758 TCC_PERF_SEL_CLIENT107_REQ               = 0x000000eb,
16759 TCC_PERF_SEL_CLIENT108_REQ               = 0x000000ec,
16760 TCC_PERF_SEL_CLIENT109_REQ               = 0x000000ed,
16761 TCC_PERF_SEL_CLIENT110_REQ               = 0x000000ee,
16762 TCC_PERF_SEL_CLIENT111_REQ               = 0x000000ef,
16763 TCC_PERF_SEL_CLIENT112_REQ               = 0x000000f0,
16764 TCC_PERF_SEL_CLIENT113_REQ               = 0x000000f1,
16765 TCC_PERF_SEL_CLIENT114_REQ               = 0x000000f2,
16766 TCC_PERF_SEL_CLIENT115_REQ               = 0x000000f3,
16767 TCC_PERF_SEL_CLIENT116_REQ               = 0x000000f4,
16768 TCC_PERF_SEL_CLIENT117_REQ               = 0x000000f5,
16769 TCC_PERF_SEL_CLIENT118_REQ               = 0x000000f6,
16770 TCC_PERF_SEL_CLIENT119_REQ               = 0x000000f7,
16771 TCC_PERF_SEL_CLIENT120_REQ               = 0x000000f8,
16772 TCC_PERF_SEL_CLIENT121_REQ               = 0x000000f9,
16773 TCC_PERF_SEL_CLIENT122_REQ               = 0x000000fa,
16774 TCC_PERF_SEL_CLIENT123_REQ               = 0x000000fb,
16775 TCC_PERF_SEL_CLIENT124_REQ               = 0x000000fc,
16776 TCC_PERF_SEL_CLIENT125_REQ               = 0x000000fd,
16777 TCC_PERF_SEL_CLIENT126_REQ               = 0x000000fe,
16778 TCC_PERF_SEL_CLIENT127_REQ               = 0x000000ff,
16779 } TCC_PERF_SEL;
16780 
16781 /*
16782  * TCA_PERF_SEL enum
16783  */
16784 
16785 typedef enum TCA_PERF_SEL {
16786 TCA_PERF_SEL_NONE                        = 0x00000000,
16787 TCA_PERF_SEL_CYCLE                       = 0x00000001,
16788 TCA_PERF_SEL_BUSY                        = 0x00000002,
16789 TCA_PERF_SEL_FORCED_HOLE_TCC0            = 0x00000003,
16790 TCA_PERF_SEL_FORCED_HOLE_TCC1            = 0x00000004,
16791 TCA_PERF_SEL_FORCED_HOLE_TCC2            = 0x00000005,
16792 TCA_PERF_SEL_FORCED_HOLE_TCC3            = 0x00000006,
16793 TCA_PERF_SEL_FORCED_HOLE_TCC4            = 0x00000007,
16794 TCA_PERF_SEL_FORCED_HOLE_TCC5            = 0x00000008,
16795 TCA_PERF_SEL_FORCED_HOLE_TCC6            = 0x00000009,
16796 TCA_PERF_SEL_FORCED_HOLE_TCC7            = 0x0000000a,
16797 TCA_PERF_SEL_REQ_TCC0                    = 0x0000000b,
16798 TCA_PERF_SEL_REQ_TCC1                    = 0x0000000c,
16799 TCA_PERF_SEL_REQ_TCC2                    = 0x0000000d,
16800 TCA_PERF_SEL_REQ_TCC3                    = 0x0000000e,
16801 TCA_PERF_SEL_REQ_TCC4                    = 0x0000000f,
16802 TCA_PERF_SEL_REQ_TCC5                    = 0x00000010,
16803 TCA_PERF_SEL_REQ_TCC6                    = 0x00000011,
16804 TCA_PERF_SEL_REQ_TCC7                    = 0x00000012,
16805 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0    = 0x00000013,
16806 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1    = 0x00000014,
16807 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2    = 0x00000015,
16808 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3    = 0x00000016,
16809 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4    = 0x00000017,
16810 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5    = 0x00000018,
16811 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6    = 0x00000019,
16812 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7    = 0x0000001a,
16813 TCA_PERF_SEL_CROSSBAR_STALL_TCC0         = 0x0000001b,
16814 TCA_PERF_SEL_CROSSBAR_STALL_TCC1         = 0x0000001c,
16815 TCA_PERF_SEL_CROSSBAR_STALL_TCC2         = 0x0000001d,
16816 TCA_PERF_SEL_CROSSBAR_STALL_TCC3         = 0x0000001e,
16817 TCA_PERF_SEL_CROSSBAR_STALL_TCC4         = 0x0000001f,
16818 TCA_PERF_SEL_CROSSBAR_STALL_TCC5         = 0x00000020,
16819 TCA_PERF_SEL_CROSSBAR_STALL_TCC6         = 0x00000021,
16820 TCA_PERF_SEL_CROSSBAR_STALL_TCC7         = 0x00000022,
16821 } TCA_PERF_SEL;
16822 
16823 /*******************************************************
16824  * GRBM Enums
16825  *******************************************************/
16826 
16827 /*
16828  * GRBM_PERF_SEL enum
16829  */
16830 
16831 typedef enum GRBM_PERF_SEL {
16832 GRBM_PERF_SEL_COUNT                      = 0x00000000,
16833 GRBM_PERF_SEL_USER_DEFINED               = 0x00000001,
16834 GRBM_PERF_SEL_GUI_ACTIVE                 = 0x00000002,
16835 GRBM_PERF_SEL_CP_BUSY                    = 0x00000003,
16836 GRBM_PERF_SEL_CP_COHER_BUSY              = 0x00000004,
16837 GRBM_PERF_SEL_CP_DMA_BUSY                = 0x00000005,
16838 GRBM_PERF_SEL_CB_BUSY                    = 0x00000006,
16839 GRBM_PERF_SEL_DB_BUSY                    = 0x00000007,
16840 GRBM_PERF_SEL_PA_BUSY                    = 0x00000008,
16841 GRBM_PERF_SEL_SC_BUSY                    = 0x00000009,
16842 GRBM_PERF_SEL_RESERVED_6                 = 0x0000000a,
16843 GRBM_PERF_SEL_SPI_BUSY                   = 0x0000000b,
16844 GRBM_PERF_SEL_SX_BUSY                    = 0x0000000c,
16845 GRBM_PERF_SEL_TA_BUSY                    = 0x0000000d,
16846 GRBM_PERF_SEL_CB_CLEAN                   = 0x0000000e,
16847 GRBM_PERF_SEL_DB_CLEAN                   = 0x0000000f,
16848 GRBM_PERF_SEL_RESERVED_5                 = 0x00000010,
16849 GRBM_PERF_SEL_VGT_BUSY                   = 0x00000011,
16850 GRBM_PERF_SEL_RESERVED_4                 = 0x00000012,
16851 GRBM_PERF_SEL_RESERVED_3                 = 0x00000013,
16852 GRBM_PERF_SEL_RESERVED_2                 = 0x00000014,
16853 GRBM_PERF_SEL_RESERVED_1                 = 0x00000015,
16854 GRBM_PERF_SEL_RESERVED_0                 = 0x00000016,
16855 GRBM_PERF_SEL_IA_BUSY                    = 0x00000017,
16856 GRBM_PERF_SEL_IA_NO_DMA_BUSY             = 0x00000018,
16857 GRBM_PERF_SEL_GDS_BUSY                   = 0x00000019,
16858 GRBM_PERF_SEL_BCI_BUSY                   = 0x0000001a,
16859 GRBM_PERF_SEL_RLC_BUSY                   = 0x0000001b,
16860 GRBM_PERF_SEL_TC_BUSY                    = 0x0000001c,
16861 GRBM_PERF_SEL_CPG_BUSY                   = 0x0000001d,
16862 GRBM_PERF_SEL_CPC_BUSY                   = 0x0000001e,
16863 GRBM_PERF_SEL_CPF_BUSY                   = 0x0000001f,
16864 GRBM_PERF_SEL_WD_BUSY                    = 0x00000020,
16865 GRBM_PERF_SEL_WD_NO_DMA_BUSY             = 0x00000021,
16866 GRBM_PERF_SEL_UTCL2_BUSY                 = 0x00000022,
16867 GRBM_PERF_SEL_EA_BUSY                    = 0x00000023,
16868 GRBM_PERF_SEL_RMI_BUSY                   = 0x00000024,
16869 GRBM_PERF_SEL_CPAXI_BUSY                 = 0x00000025,
16870 } GRBM_PERF_SEL;
16871 
16872 /*
16873  * GRBM_SE0_PERF_SEL enum
16874  */
16875 
16876 typedef enum GRBM_SE0_PERF_SEL {
16877 GRBM_SE0_PERF_SEL_COUNT                  = 0x00000000,
16878 GRBM_SE0_PERF_SEL_USER_DEFINED           = 0x00000001,
16879 GRBM_SE0_PERF_SEL_CB_BUSY                = 0x00000002,
16880 GRBM_SE0_PERF_SEL_DB_BUSY                = 0x00000003,
16881 GRBM_SE0_PERF_SEL_SC_BUSY                = 0x00000004,
16882 GRBM_SE0_PERF_SEL_RESERVED_1             = 0x00000005,
16883 GRBM_SE0_PERF_SEL_SPI_BUSY               = 0x00000006,
16884 GRBM_SE0_PERF_SEL_SX_BUSY                = 0x00000007,
16885 GRBM_SE0_PERF_SEL_TA_BUSY                = 0x00000008,
16886 GRBM_SE0_PERF_SEL_CB_CLEAN               = 0x00000009,
16887 GRBM_SE0_PERF_SEL_DB_CLEAN               = 0x0000000a,
16888 GRBM_SE0_PERF_SEL_RESERVED_0             = 0x0000000b,
16889 GRBM_SE0_PERF_SEL_PA_BUSY                = 0x0000000c,
16890 GRBM_SE0_PERF_SEL_VGT_BUSY               = 0x0000000d,
16891 GRBM_SE0_PERF_SEL_BCI_BUSY               = 0x0000000e,
16892 GRBM_SE0_PERF_SEL_RMI_BUSY               = 0x0000000f,
16893 } GRBM_SE0_PERF_SEL;
16894 
16895 /*
16896  * GRBM_SE1_PERF_SEL enum
16897  */
16898 
16899 typedef enum GRBM_SE1_PERF_SEL {
16900 GRBM_SE1_PERF_SEL_COUNT                  = 0x00000000,
16901 GRBM_SE1_PERF_SEL_USER_DEFINED           = 0x00000001,
16902 GRBM_SE1_PERF_SEL_CB_BUSY                = 0x00000002,
16903 GRBM_SE1_PERF_SEL_DB_BUSY                = 0x00000003,
16904 GRBM_SE1_PERF_SEL_SC_BUSY                = 0x00000004,
16905 GRBM_SE1_PERF_SEL_RESERVED_1             = 0x00000005,
16906 GRBM_SE1_PERF_SEL_SPI_BUSY               = 0x00000006,
16907 GRBM_SE1_PERF_SEL_SX_BUSY                = 0x00000007,
16908 GRBM_SE1_PERF_SEL_TA_BUSY                = 0x00000008,
16909 GRBM_SE1_PERF_SEL_CB_CLEAN               = 0x00000009,
16910 GRBM_SE1_PERF_SEL_DB_CLEAN               = 0x0000000a,
16911 GRBM_SE1_PERF_SEL_RESERVED_0             = 0x0000000b,
16912 GRBM_SE1_PERF_SEL_PA_BUSY                = 0x0000000c,
16913 GRBM_SE1_PERF_SEL_VGT_BUSY               = 0x0000000d,
16914 GRBM_SE1_PERF_SEL_BCI_BUSY               = 0x0000000e,
16915 GRBM_SE1_PERF_SEL_RMI_BUSY               = 0x0000000f,
16916 } GRBM_SE1_PERF_SEL;
16917 
16918 /*
16919  * GRBM_SE2_PERF_SEL enum
16920  */
16921 
16922 typedef enum GRBM_SE2_PERF_SEL {
16923 GRBM_SE2_PERF_SEL_COUNT                  = 0x00000000,
16924 GRBM_SE2_PERF_SEL_USER_DEFINED           = 0x00000001,
16925 GRBM_SE2_PERF_SEL_CB_BUSY                = 0x00000002,
16926 GRBM_SE2_PERF_SEL_DB_BUSY                = 0x00000003,
16927 GRBM_SE2_PERF_SEL_SC_BUSY                = 0x00000004,
16928 GRBM_SE2_PERF_SEL_RESERVED_1             = 0x00000005,
16929 GRBM_SE2_PERF_SEL_SPI_BUSY               = 0x00000006,
16930 GRBM_SE2_PERF_SEL_SX_BUSY                = 0x00000007,
16931 GRBM_SE2_PERF_SEL_TA_BUSY                = 0x00000008,
16932 GRBM_SE2_PERF_SEL_CB_CLEAN               = 0x00000009,
16933 GRBM_SE2_PERF_SEL_DB_CLEAN               = 0x0000000a,
16934 GRBM_SE2_PERF_SEL_RESERVED_0             = 0x0000000b,
16935 GRBM_SE2_PERF_SEL_PA_BUSY                = 0x0000000c,
16936 GRBM_SE2_PERF_SEL_VGT_BUSY               = 0x0000000d,
16937 GRBM_SE2_PERF_SEL_BCI_BUSY               = 0x0000000e,
16938 GRBM_SE2_PERF_SEL_RMI_BUSY               = 0x0000000f,
16939 } GRBM_SE2_PERF_SEL;
16940 
16941 /*
16942  * GRBM_SE3_PERF_SEL enum
16943  */
16944 
16945 typedef enum GRBM_SE3_PERF_SEL {
16946 GRBM_SE3_PERF_SEL_COUNT                  = 0x00000000,
16947 GRBM_SE3_PERF_SEL_USER_DEFINED           = 0x00000001,
16948 GRBM_SE3_PERF_SEL_CB_BUSY                = 0x00000002,
16949 GRBM_SE3_PERF_SEL_DB_BUSY                = 0x00000003,
16950 GRBM_SE3_PERF_SEL_SC_BUSY                = 0x00000004,
16951 GRBM_SE3_PERF_SEL_RESERVED_1             = 0x00000005,
16952 GRBM_SE3_PERF_SEL_SPI_BUSY               = 0x00000006,
16953 GRBM_SE3_PERF_SEL_SX_BUSY                = 0x00000007,
16954 GRBM_SE3_PERF_SEL_TA_BUSY                = 0x00000008,
16955 GRBM_SE3_PERF_SEL_CB_CLEAN               = 0x00000009,
16956 GRBM_SE3_PERF_SEL_DB_CLEAN               = 0x0000000a,
16957 GRBM_SE3_PERF_SEL_RESERVED_0             = 0x0000000b,
16958 GRBM_SE3_PERF_SEL_PA_BUSY                = 0x0000000c,
16959 GRBM_SE3_PERF_SEL_VGT_BUSY               = 0x0000000d,
16960 GRBM_SE3_PERF_SEL_BCI_BUSY               = 0x0000000e,
16961 GRBM_SE3_PERF_SEL_RMI_BUSY               = 0x0000000f,
16962 } GRBM_SE3_PERF_SEL;
16963 
16964 /*******************************************************
16965  * CP Enums
16966  *******************************************************/
16967 
16968 /*
16969  * CP_RING_ID enum
16970  */
16971 
16972 typedef enum CP_RING_ID {
16973 RINGID0                                  = 0x00000000,
16974 RINGID1                                  = 0x00000001,
16975 RINGID2                                  = 0x00000002,
16976 RINGID3                                  = 0x00000003,
16977 } CP_RING_ID;
16978 
16979 /*
16980  * CP_PIPE_ID enum
16981  */
16982 
16983 typedef enum CP_PIPE_ID {
16984 PIPE_ID0                                 = 0x00000000,
16985 PIPE_ID1                                 = 0x00000001,
16986 PIPE_ID2                                 = 0x00000002,
16987 PIPE_ID3                                 = 0x00000003,
16988 } CP_PIPE_ID;
16989 
16990 /*
16991  * CP_ME_ID enum
16992  */
16993 
16994 typedef enum CP_ME_ID {
16995 ME_ID0                                   = 0x00000000,
16996 ME_ID1                                   = 0x00000001,
16997 ME_ID2                                   = 0x00000002,
16998 ME_ID3                                   = 0x00000003,
16999 } CP_ME_ID;
17000 
17001 /*
17002  * SPM_PERFMON_STATE enum
17003  */
17004 
17005 typedef enum SPM_PERFMON_STATE {
17006 STRM_PERFMON_STATE_DISABLE_AND_RESET     = 0x00000000,
17007 STRM_PERFMON_STATE_START_COUNTING        = 0x00000001,
17008 STRM_PERFMON_STATE_STOP_COUNTING         = 0x00000002,
17009 STRM_PERFMON_STATE_RESERVED_3            = 0x00000003,
17010 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM  = 0x00000004,
17011 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
17012 } SPM_PERFMON_STATE;
17013 
17014 /*
17015  * CP_PERFMON_STATE enum
17016  */
17017 
17018 typedef enum CP_PERFMON_STATE {
17019 CP_PERFMON_STATE_DISABLE_AND_RESET       = 0x00000000,
17020 CP_PERFMON_STATE_START_COUNTING          = 0x00000001,
17021 CP_PERFMON_STATE_STOP_COUNTING           = 0x00000002,
17022 CP_PERFMON_STATE_RESERVED_3              = 0x00000003,
17023 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM  = 0x00000004,
17024 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
17025 } CP_PERFMON_STATE;
17026 
17027 /*
17028  * CP_PERFMON_ENABLE_MODE enum
17029  */
17030 
17031 typedef enum CP_PERFMON_ENABLE_MODE {
17032 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT      = 0x00000000,
17033 CP_PERFMON_ENABLE_MODE_RESERVED_1        = 0x00000001,
17034 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE  = 0x00000002,
17035 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE  = 0x00000003,
17036 } CP_PERFMON_ENABLE_MODE;
17037 
17038 /*
17039  * CPG_PERFCOUNT_SEL enum
17040  */
17041 
17042 typedef enum CPG_PERFCOUNT_SEL {
17043 CPG_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17044 CPG_PERF_SEL_RBIU_FIFO_FULL              = 0x00000001,
17045 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR     = 0x00000002,
17046 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL  = 0x00000003,
17047 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT         = 0x00000004,
17048 CPG_PERF_SEL_ME_PARSER_BUSY              = 0x00000005,
17049 CPG_PERF_SEL_COUNT_TYPE0_PACKETS         = 0x00000006,
17050 CPG_PERF_SEL_COUNT_TYPE3_PACKETS         = 0x00000007,
17051 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x00000008,
17052 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS      = 0x00000009,
17053 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS  = 0x0000000a,
17054 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS  = 0x0000000b,
17055 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ     = 0x0000000c,
17056 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ    = 0x0000000d,
17057 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX  = 0x0000000e,
17058 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS  = 0x0000000f,
17059 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE  = 0x00000010,
17060 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM  = 0x00000011,
17061 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY    = 0x00000012,
17062 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY    = 0x00000013,
17063 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY   = 0x00000014,
17064 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ  = 0x00000015,
17065 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP  = 0x00000016,
17066 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ  = 0x00000017,
17067 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX  = 0x00000018,
17068 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU  = 0x00000019,
17069 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS  = 0x0000001a,
17070 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH  = 0x0000001b,
17071 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER       = 0x0000001c,
17072 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER     = 0x0000001d,
17073 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS  = 0x0000001e,
17074 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY  = 0x0000001f,
17075 CPG_PERF_SEL_DYNAMIC_CLK_VALID           = 0x00000020,
17076 CPG_PERF_SEL_REGISTER_CLK_VALID          = 0x00000021,
17077 CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT      = 0x00000022,
17078 CPG_PERF_SEL_MIU_READ_REQUEST_SENT       = 0x00000023,
17079 CPG_PERF_SEL_CE_STALL_RAM_DUMP           = 0x00000024,
17080 CPG_PERF_SEL_CE_STALL_RAM_WRITE          = 0x00000025,
17081 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO        = 0x00000026,
17082 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO     = 0x00000027,
17083 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU   = 0x00000028,
17084 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ   = 0x00000029,
17085 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG  = 0x0000002a,
17086 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER      = 0x0000002b,
17087 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x0000002c,
17088 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS     = 0x0000002d,
17089 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x0000002e,
17090 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x0000002f,
17091 CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000030,
17092 } CPG_PERFCOUNT_SEL;
17093 
17094 /*
17095  * CPF_PERFCOUNT_SEL enum
17096  */
17097 
17098 typedef enum CPF_PERFCOUNT_SEL {
17099 CPF_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17100 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE  = 0x00000001,
17101 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE  = 0x00000002,
17102 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS  = 0x00000003,
17103 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING  = 0x00000004,
17104 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1   = 0x00000005,
17105 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2   = 0x00000006,
17106 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE  = 0x00000007,
17107 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS  = 0x00000008,
17108 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR         = 0x00000009,
17109 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR      = 0x0000000a,
17110 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x0000000b,
17111 CPF_PERF_SEL_GRBM_DWORDS_SENT            = 0x0000000c,
17112 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID         = 0x0000000d,
17113 CPF_PERF_SEL_REGISTER_CLOCK_VALID        = 0x0000000e,
17114 CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND      = 0x0000000f,
17115 CPF_PERF_SEL_MIU_READ_REQUEST_SEND       = 0x00000010,
17116 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000011,
17117 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000012,
17118 CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000013,
17119 CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000014,
17120 } CPF_PERFCOUNT_SEL;
17121 
17122 /*
17123  * CPC_PERFCOUNT_SEL enum
17124  */
17125 
17126 typedef enum CPC_PERFCOUNT_SEL {
17127 CPC_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17128 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000001,
17129 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION   = 0x00000002,
17130 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE     = 0x00000003,
17131 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE     = 0x00000004,
17132 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x00000005,
17133 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY  = 0x00000006,
17134 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF  = 0x00000007,
17135 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ  = 0x00000008,
17136 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ  = 0x00000009,
17137 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE  = 0x0000000a,
17138 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ  = 0x0000000b,
17139 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF  = 0x0000000c,
17140 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE  = 0x0000000d,
17141 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY  = 0x0000000e,
17142 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF  = 0x0000000f,
17143 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ  = 0x00000010,
17144 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ  = 0x00000011,
17145 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE  = 0x00000012,
17146 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ  = 0x00000013,
17147 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF  = 0x00000014,
17148 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE  = 0x00000015,
17149 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000016,
17150 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000017,
17151 CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000018,
17152 } CPC_PERFCOUNT_SEL;
17153 
17154 /*
17155  * CP_ALPHA_TAG_RAM_SEL enum
17156  */
17157 
17158 typedef enum CP_ALPHA_TAG_RAM_SEL {
17159 CPG_TAG_RAM                              = 0x00000000,
17160 CPC_TAG_RAM                              = 0x00000001,
17161 CPF_TAG_RAM                              = 0x00000002,
17162 RSV_TAG_RAM                              = 0x00000003,
17163 } CP_ALPHA_TAG_RAM_SEL;
17164 
17165 /*
17166  * SEM_RESPONSE value
17167  */
17168 
17169 #define SEM_ECC_ERROR                  0x00000000
17170 #define SEM_TRANS_ERROR                0x00000001
17171 #define SEM_FAILED                     0x00000002
17172 #define SEM_PASSED                     0x00000003
17173 
17174 /*
17175  * IQ_RETRY_TYPE value
17176  */
17177 
17178 #define IQ_QUEUE_SLEEP                 0x00000000
17179 #define IQ_OFFLOAD_RETRY               0x00000001
17180 #define IQ_SCH_WAVE_MSG                0x00000002
17181 #define IQ_SEM_REARM                   0x00000003
17182 #define IQ_DEQUEUE_RETRY               0x00000004
17183 
17184 /*
17185  * IQ_INTR_TYPE value
17186  */
17187 
17188 #define IQ_INTR_TYPE_PQ                0x00000000
17189 #define IQ_INTR_TYPE_IB                0x00000001
17190 #define IQ_INTR_TYPE_MQD               0x00000002
17191 
17192 /*
17193  * VMID_SIZE value
17194  */
17195 
17196 #define VMID_SZ                        0x00000004
17197 
17198 /*
17199  * CONFIG_SPACE value
17200  */
17201 
17202 #define CONFIG_SPACE_START             0x00002000
17203 #define CONFIG_SPACE_END               0x00009fff
17204 
17205 /*
17206  * CONFIG_SPACE1 value
17207  */
17208 
17209 #define CONFIG_SPACE1_START            0x00002000
17210 #define CONFIG_SPACE1_END              0x00002bff
17211 
17212 /*
17213  * CONFIG_SPACE2 value
17214  */
17215 
17216 #define CONFIG_SPACE2_START            0x00003000
17217 #define CONFIG_SPACE2_END              0x00009fff
17218 
17219 /*
17220  * UCONFIG_SPACE value
17221  */
17222 
17223 #define UCONFIG_SPACE_START            0x0000c000
17224 #define UCONFIG_SPACE_END              0x0000ffff
17225 
17226 /*
17227  * PERSISTENT_SPACE value
17228  */
17229 
17230 #define PERSISTENT_SPACE_START         0x00002c00
17231 #define PERSISTENT_SPACE_END           0x00002fff
17232 
17233 /*
17234  * CONTEXT_SPACE value
17235  */
17236 
17237 #define CONTEXT_SPACE_START            0x0000a000
17238 #define CONTEXT_SPACE_END              0x0000bfff
17239 
17240 /*******************************************************
17241  * SQ_UC Enums
17242  *******************************************************/
17243 
17244 /*
17245  * VALUE_SQ_ENC_SOP1 value
17246  */
17247 
17248 #define SQ_ENC_SOP1_BITS               0xbe800000
17249 #define SQ_ENC_SOP1_MASK               0xff800000
17250 #define SQ_ENC_SOP1_FIELD              0x0000017d
17251 
17252 /*
17253  * VALUE_SQ_ENC_SOPC value
17254  */
17255 
17256 #define SQ_ENC_SOPC_BITS               0xbf000000
17257 #define SQ_ENC_SOPC_MASK               0xff800000
17258 #define SQ_ENC_SOPC_FIELD              0x0000017e
17259 
17260 /*
17261  * VALUE_SQ_ENC_SOPP value
17262  */
17263 
17264 #define SQ_ENC_SOPP_BITS               0xbf800000
17265 #define SQ_ENC_SOPP_MASK               0xff800000
17266 #define SQ_ENC_SOPP_FIELD              0x0000017f
17267 
17268 /*
17269  * VALUE_SQ_ENC_SOPK value
17270  */
17271 
17272 #define SQ_ENC_SOPK_BITS               0xb0000000
17273 #define SQ_ENC_SOPK_MASK               0xf0000000
17274 #define SQ_ENC_SOPK_FIELD              0x0000000b
17275 
17276 /*
17277  * VALUE_SQ_ENC_SOP2 value
17278  */
17279 
17280 #define SQ_ENC_SOP2_BITS               0x80000000
17281 #define SQ_ENC_SOP2_MASK               0xc0000000
17282 #define SQ_ENC_SOP2_FIELD              0x00000002
17283 
17284 /*
17285  * VALUE_SQ_ENC_SMEM value
17286  */
17287 
17288 #define SQ_ENC_SMEM_BITS               0xc0000000
17289 #define SQ_ENC_SMEM_MASK               0xfc000000
17290 #define SQ_ENC_SMEM_FIELD              0x00000030
17291 
17292 /*
17293  * VALUE_SQ_ENC_VOP1 value
17294  */
17295 
17296 #define SQ_ENC_VOP1_BITS               0x7e000000
17297 #define SQ_ENC_VOP1_MASK               0xfe000000
17298 #define SQ_ENC_VOP1_FIELD              0x0000003f
17299 
17300 /*
17301  * VALUE_SQ_ENC_VOPC value
17302  */
17303 
17304 #define SQ_ENC_VOPC_BITS               0x7c000000
17305 #define SQ_ENC_VOPC_MASK               0xfe000000
17306 #define SQ_ENC_VOPC_FIELD              0x0000003e
17307 
17308 /*
17309  * VALUE_SQ_ENC_VOP2 value
17310  */
17311 
17312 #define SQ_ENC_VOP2_BITS               0x00000000
17313 #define SQ_ENC_VOP2_MASK               0x80000000
17314 #define SQ_ENC_VOP2_FIELD              0x00000000
17315 
17316 /*
17317  * VALUE_SQ_ENC_VINTRP value
17318  */
17319 
17320 #define SQ_ENC_VINTRP_BITS             0xd4000000
17321 #define SQ_ENC_VINTRP_MASK             0xfc000000
17322 #define SQ_ENC_VINTRP_FIELD            0x00000035
17323 
17324 /*
17325  * VALUE_SQ_ENC_VOP3P value
17326  */
17327 
17328 #define SQ_ENC_VOP3P_BITS              0xd3800000
17329 #define SQ_ENC_VOP3P_MASK              0xff800000
17330 #define SQ_ENC_VOP3P_FIELD             0x000001a7
17331 
17332 /*
17333  * VALUE_SQ_ENC_VOP3 value
17334  */
17335 
17336 #define SQ_ENC_VOP3_BITS               0xd0000000
17337 #define SQ_ENC_VOP3_MASK               0xfc000000
17338 #define SQ_ENC_VOP3_FIELD              0x00000034
17339 
17340 /*
17341  * VALUE_SQ_ENC_DS value
17342  */
17343 
17344 #define SQ_ENC_DS_BITS                 0xd8000000
17345 #define SQ_ENC_DS_MASK                 0xfc000000
17346 #define SQ_ENC_DS_FIELD                0x00000036
17347 
17348 /*
17349  * VALUE_SQ_ENC_MUBUF value
17350  */
17351 
17352 #define SQ_ENC_MUBUF_BITS              0xe0000000
17353 #define SQ_ENC_MUBUF_MASK              0xfc000000
17354 #define SQ_ENC_MUBUF_FIELD             0x00000038
17355 
17356 /*
17357  * VALUE_SQ_ENC_MTBUF value
17358  */
17359 
17360 #define SQ_ENC_MTBUF_BITS              0xe8000000
17361 #define SQ_ENC_MTBUF_MASK              0xfc000000
17362 #define SQ_ENC_MTBUF_FIELD             0x0000003a
17363 
17364 /*
17365  * VALUE_SQ_ENC_MIMG value
17366  */
17367 
17368 #define SQ_ENC_MIMG_BITS               0xf0000000
17369 #define SQ_ENC_MIMG_MASK               0xfc000000
17370 #define SQ_ENC_MIMG_FIELD              0x0000003c
17371 
17372 /*
17373  * VALUE_SQ_ENC_EXP value
17374  */
17375 
17376 #define SQ_ENC_EXP_BITS                0xc4000000
17377 #define SQ_ENC_EXP_MASK                0xfc000000
17378 #define SQ_ENC_EXP_FIELD               0x00000031
17379 
17380 /*
17381  * VALUE_SQ_ENC_FLAT value
17382  */
17383 
17384 #define SQ_ENC_FLAT_BITS               0xdc000000
17385 #define SQ_ENC_FLAT_MASK               0xfc000000
17386 #define SQ_ENC_FLAT_FIELD              0x00000037
17387 
17388 /*
17389  * VALUE_SQ_V_OP3_INTRP_COUNT value
17390  */
17391 
17392 #define SQ_V_OP3_INTRP_COUNT           0x0000000c
17393 
17394 /*
17395  * VALUE_SQ_SENDMSG_SYSTEM_SIZE value
17396  */
17397 
17398 #define SQ_SENDMSG_SYSTEM_SIZE         0x00000003
17399 
17400 /*
17401  * VALUE_SQ_HWREG_ID_SIZE value
17402  */
17403 
17404 #define SQ_HWREG_ID_SIZE               0x00000006
17405 
17406 /*
17407  * VALUE_SQ_V_OPC_COUNT value
17408  */
17409 
17410 #define SQ_V_OPC_COUNT                 0x00000100
17411 
17412 /*
17413  * VALUE_SQ_NUM_VGPR value
17414  */
17415 
17416 #define SQ_NUM_VGPR                    0x00000100
17417 
17418 /*
17419  * VALUE_SQ_WAITCNT_LGKM_SHIFT value
17420  */
17421 
17422 #define SQ_WAITCNT_LGKM_SHIFT          0x00000008
17423 
17424 /*
17425  * VALUE_SQ_HWREG_ID_SHIFT value
17426  */
17427 
17428 #define SQ_HWREG_ID_SHIFT              0x00000000
17429 
17430 /*
17431  * VALUE_SQ_EXP_NUM_POS value
17432  */
17433 
17434 #define SQ_EXP_NUM_POS                 0x00000004
17435 
17436 /*
17437  * VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value
17438  */
17439 
17440 #define SQ_XLATE_VOP3_TO_VOPC_OFFSET   0x00000000
17441 
17442 /*
17443  * VALUE_SQ_V_OP3_2IN_OFFSET value
17444  */
17445 
17446 #define SQ_V_OP3_2IN_OFFSET            0x00000280
17447 
17448 /*
17449  * VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value
17450  */
17451 
17452 #define SQ_XLATE_VOP3_TO_VOP2_OFFSET   0x00000100
17453 
17454 /*
17455  * VALUE_SQ_EXP_NUM_MRT value
17456  */
17457 
17458 #define SQ_EXP_NUM_MRT                 0x00000008
17459 
17460 /*
17461  * VALUE_SQ_NUM_TTMP value
17462  */
17463 
17464 #define SQ_NUM_TTMP                    0x00000010
17465 
17466 /*
17467  * VALUE_SQ_SENDMSG_STREAMID_SHIFT value
17468  */
17469 
17470 #define SQ_SENDMSG_STREAMID_SHIFT      0x00000008
17471 
17472 /*
17473  * VALUE_SQ_V_OP1_COUNT value
17474  */
17475 
17476 #define SQ_V_OP1_COUNT                 0x00000080
17477 
17478 /*
17479  * VALUE_SQ_WAITCNT_LGKM_SIZE value
17480  */
17481 
17482 #define SQ_WAITCNT_LGKM_SIZE           0x00000004
17483 
17484 /*
17485  * VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value
17486  */
17487 
17488 #define SQ_XLATE_VOP3_TO_VOPC_COUNT    0x00000100
17489 
17490 /*
17491  * VALUE_SQ_SENDMSG_MSG_SHIFT value
17492  */
17493 
17494 #define SQ_SENDMSG_MSG_SHIFT           0x00000000
17495 
17496 /*
17497  * VALUE_SQ_V_OP3_3IN_OFFSET value
17498  */
17499 
17500 #define SQ_V_OP3_3IN_OFFSET            0x000001c0
17501 
17502 /*
17503  * VALUE_SQ_HWREG_OFFSET_SHIFT value
17504  */
17505 
17506 #define SQ_HWREG_OFFSET_SHIFT          0x00000006
17507 
17508 /*
17509  * VALUE_SQ_HWREG_SIZE_SHIFT value
17510  */
17511 
17512 #define SQ_HWREG_SIZE_SHIFT            0x0000000b
17513 
17514 /*
17515  * VALUE_SQ_HWREG_OFFSET_SIZE value
17516  */
17517 
17518 #define SQ_HWREG_OFFSET_SIZE           0x00000005
17519 
17520 /*
17521  * VALUE_SQ_V_OP3_3IN_COUNT value
17522  */
17523 
17524 #define SQ_V_OP3_3IN_COUNT             0x000000b0
17525 
17526 /*
17527  * VALUE_SQ_SENDMSG_MSG_SIZE value
17528  */
17529 
17530 #define SQ_SENDMSG_MSG_SIZE            0x00000004
17531 
17532 /*
17533  * VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value
17534  */
17535 
17536 #define SQ_XLATE_VOP3_TO_VOP1_COUNT    0x00000080
17537 
17538 /*
17539  * VALUE_SQ_EXP_NUM_GDS value
17540  */
17541 
17542 #define SQ_EXP_NUM_GDS                 0x00000005
17543 
17544 /*
17545  * VALUE_SQ_V_OP2_COUNT value
17546  */
17547 
17548 #define SQ_V_OP2_COUNT                 0x00000040
17549 
17550 /*
17551  * VALUE_SQ_SENDMSG_GSOP_SIZE value
17552  */
17553 
17554 #define SQ_SENDMSG_GSOP_SIZE           0x00000002
17555 
17556 /*
17557  * VALUE_SQ_WAITCNT_VM_SHIFT value
17558  */
17559 
17560 #define SQ_WAITCNT_VM_SHIFT            0x00000000
17561 
17562 /*
17563  * VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value
17564  */
17565 
17566 #define SQ_XLATE_VOP3_TO_VOP3P_COUNT   0x00000080
17567 
17568 /*
17569  * VALUE_SQ_V_OP3_2IN_COUNT value
17570  */
17571 
17572 #define SQ_V_OP3_2IN_COUNT             0x00000080
17573 
17574 /*
17575  * VALUE_SQ_SENDMSG_SYSTEM_SHIFT value
17576  */
17577 
17578 #define SQ_SENDMSG_SYSTEM_SHIFT        0x00000004
17579 
17580 /*
17581  * VALUE_SQ_WAITCNT_VM_SIZE value
17582  */
17583 
17584 #define SQ_WAITCNT_VM_SIZE             0x00000004
17585 
17586 /*
17587  * VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value
17588  */
17589 
17590 #define SQ_XLATE_VOP3_TO_VOP3P_OFFSET  0x00000380
17591 
17592 /*
17593  * VALUE_SQ_WAITCNT_EXP_SHIFT value
17594  */
17595 
17596 #define SQ_WAITCNT_EXP_SHIFT           0x00000004
17597 
17598 /*
17599  * VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value
17600  */
17601 
17602 #define SQ_XLATE_VOP3_TO_VOP2_COUNT    0x00000040
17603 
17604 /*
17605  * VALUE_SQ_EXP_NUM_PARAM value
17606  */
17607 
17608 #define SQ_EXP_NUM_PARAM               0x00000020
17609 
17610 /*
17611  * VALUE_SQ_HWREG_SIZE_SIZE value
17612  */
17613 
17614 #define SQ_HWREG_SIZE_SIZE             0x00000005
17615 
17616 /*
17617  * VALUE_SQ_WAITCNT_EXP_SIZE value
17618  */
17619 
17620 #define SQ_WAITCNT_EXP_SIZE            0x00000003
17621 
17622 /*
17623  * VALUE_SQ_V_OP3_INTRP_OFFSET value
17624  */
17625 
17626 #define SQ_V_OP3_INTRP_OFFSET          0x00000274
17627 
17628 /*
17629  * VALUE_SQ_SENDMSG_GSOP_SHIFT value
17630  */
17631 
17632 #define SQ_SENDMSG_GSOP_SHIFT          0x00000004
17633 
17634 /*
17635  * VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value
17636  */
17637 
17638 #define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270
17639 
17640 /*
17641  * VALUE_SQ_NUM_ATTR value
17642  */
17643 
17644 #define SQ_NUM_ATTR                    0x00000021
17645 
17646 /*
17647  * VALUE_SQ_NUM_SGPR value
17648  */
17649 
17650 #define SQ_NUM_SGPR                    0x00000066
17651 
17652 /*
17653  * VALUE_SQ_SRC_VGPR_BIT value
17654  */
17655 
17656 #define SQ_SRC_VGPR_BIT                0x00000100
17657 
17658 /*
17659  * VALUE_SQ_V_INTRP_COUNT value
17660  */
17661 
17662 #define SQ_V_INTRP_COUNT               0x00000004
17663 
17664 /*
17665  * VALUE_SQ_SENDMSG_STREAMID_SIZE value
17666  */
17667 
17668 #define SQ_SENDMSG_STREAMID_SIZE       0x00000002
17669 
17670 /*
17671  * VALUE_SQ_V_OP3P_COUNT value
17672  */
17673 
17674 #define SQ_V_OP3P_COUNT                0x00000080
17675 
17676 /*
17677  * VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value
17678  */
17679 
17680 #define SQ_XLATE_VOP3_TO_VOP1_OFFSET   0x00000140
17681 
17682 /*
17683  * VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value
17684  */
17685 
17686 #define SQ_XLATE_VOP3_TO_VINTRP_COUNT  0x00000004
17687 
17688 /*
17689  * VALUE_SQ_SSRC_SPECIAL_DPP value
17690  */
17691 
17692 #define SQ_SRC_DPP                     0x000000fa
17693 
17694 /*
17695  * VALUE_SQ_OP_MTBUF value
17696  */
17697 
17698 #define SQ_TBUFFER_LOAD_FORMAT_X       0x00000000
17699 #define SQ_TBUFFER_LOAD_FORMAT_XY      0x00000001
17700 #define SQ_TBUFFER_LOAD_FORMAT_XYZ     0x00000002
17701 #define SQ_TBUFFER_LOAD_FORMAT_XYZW    0x00000003
17702 #define SQ_TBUFFER_STORE_FORMAT_X      0x00000004
17703 #define SQ_TBUFFER_STORE_FORMAT_XY     0x00000005
17704 #define SQ_TBUFFER_STORE_FORMAT_XYZ    0x00000006
17705 #define SQ_TBUFFER_STORE_FORMAT_XYZW   0x00000007
17706 #define SQ_TBUFFER_LOAD_FORMAT_D16_X   0x00000008
17707 #define SQ_TBUFFER_LOAD_FORMAT_D16_XY  0x00000009
17708 #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
17709 #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
17710 #define SQ_TBUFFER_STORE_FORMAT_D16_X  0x0000000c
17711 #define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d
17712 #define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
17713 #define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
17714 
17715 /*
17716  * VALUE_SQ_OP_FLAT_GLBL value
17717  */
17718 
17719 #define SQ_GLOBAL_LOAD_UBYTE           0x00000010
17720 #define SQ_GLOBAL_LOAD_SBYTE           0x00000011
17721 #define SQ_GLOBAL_LOAD_USHORT          0x00000012
17722 #define SQ_GLOBAL_LOAD_SSHORT          0x00000013
17723 #define SQ_GLOBAL_LOAD_DWORD           0x00000014
17724 #define SQ_GLOBAL_LOAD_DWORDX2         0x00000015
17725 #define SQ_GLOBAL_LOAD_DWORDX3         0x00000016
17726 #define SQ_GLOBAL_LOAD_DWORDX4         0x00000017
17727 #define SQ_GLOBAL_STORE_BYTE           0x00000018
17728 #define SQ_GLOBAL_STORE_SHORT          0x0000001a
17729 #define SQ_GLOBAL_STORE_DWORD          0x0000001c
17730 #define SQ_GLOBAL_STORE_DWORDX2        0x0000001d
17731 #define SQ_GLOBAL_STORE_DWORDX3        0x0000001e
17732 #define SQ_GLOBAL_STORE_DWORDX4        0x0000001f
17733 #define SQ_GLOBAL_ATOMIC_SWAP          0x00000040
17734 #define SQ_GLOBAL_ATOMIC_CMPSWAP       0x00000041
17735 #define SQ_GLOBAL_ATOMIC_ADD           0x00000042
17736 #define SQ_GLOBAL_ATOMIC_SUB           0x00000043
17737 #define SQ_GLOBAL_ATOMIC_SMIN          0x00000044
17738 #define SQ_GLOBAL_ATOMIC_UMIN          0x00000045
17739 #define SQ_GLOBAL_ATOMIC_SMAX          0x00000046
17740 #define SQ_GLOBAL_ATOMIC_UMAX          0x00000047
17741 #define SQ_GLOBAL_ATOMIC_AND           0x00000048
17742 #define SQ_GLOBAL_ATOMIC_OR            0x00000049
17743 #define SQ_GLOBAL_ATOMIC_XOR           0x0000004a
17744 #define SQ_GLOBAL_ATOMIC_INC           0x0000004b
17745 #define SQ_GLOBAL_ATOMIC_DEC           0x0000004c
17746 #define SQ_GLOBAL_ATOMIC_SWAP_X2       0x00000060
17747 #define SQ_GLOBAL_ATOMIC_CMPSWAP_X2    0x00000061
17748 #define SQ_GLOBAL_ATOMIC_ADD_X2        0x00000062
17749 #define SQ_GLOBAL_ATOMIC_SUB_X2        0x00000063
17750 #define SQ_GLOBAL_ATOMIC_SMIN_X2       0x00000064
17751 #define SQ_GLOBAL_ATOMIC_UMIN_X2       0x00000065
17752 #define SQ_GLOBAL_ATOMIC_SMAX_X2       0x00000066
17753 #define SQ_GLOBAL_ATOMIC_UMAX_X2       0x00000067
17754 #define SQ_GLOBAL_ATOMIC_AND_X2        0x00000068
17755 #define SQ_GLOBAL_ATOMIC_OR_X2         0x00000069
17756 #define SQ_GLOBAL_ATOMIC_XOR_X2        0x0000006a
17757 #define SQ_GLOBAL_ATOMIC_INC_X2        0x0000006b
17758 #define SQ_GLOBAL_ATOMIC_DEC_X2        0x0000006c
17759 
17760 /*
17761  * VALUE_SQ_VGPR value
17762  */
17763 
17764 #define SQ_VGPR0                       0x00000000
17765 
17766 /*
17767  * VALUE_SQ_OP_FLAT_SCRATCH value
17768  */
17769 
17770 #define SQ_SCRATCH_LOAD_UBYTE          0x00000010
17771 #define SQ_SCRATCH_LOAD_SBYTE          0x00000011
17772 #define SQ_SCRATCH_LOAD_USHORT         0x00000012
17773 #define SQ_SCRATCH_LOAD_SSHORT         0x00000013
17774 #define SQ_SCRATCH_LOAD_DWORD          0x00000014
17775 #define SQ_SCRATCH_LOAD_DWORDX2        0x00000015
17776 #define SQ_SCRATCH_LOAD_DWORDX3        0x00000016
17777 #define SQ_SCRATCH_LOAD_DWORDX4        0x00000017
17778 #define SQ_SCRATCH_STORE_BYTE          0x00000018
17779 #define SQ_SCRATCH_STORE_SHORT         0x0000001a
17780 #define SQ_SCRATCH_STORE_DWORD         0x0000001c
17781 #define SQ_SCRATCH_STORE_DWORDX2       0x0000001d
17782 #define SQ_SCRATCH_STORE_DWORDX3       0x0000001e
17783 #define SQ_SCRATCH_STORE_DWORDX4       0x0000001f
17784 
17785 /*
17786  * VALUE_SQ_VCC value
17787  */
17788 
17789 #define SQ_VCC_ALL                     0x00000000
17790 
17791 /*
17792  * VALUE_SQ_SSRC_0_63_INLINES value
17793  */
17794 
17795 #define SQ_SRC_0                       0x00000080
17796 #define SQ_SRC_1_INT                   0x00000081
17797 #define SQ_SRC_2_INT                   0x00000082
17798 #define SQ_SRC_3_INT                   0x00000083
17799 #define SQ_SRC_4_INT                   0x00000084
17800 #define SQ_SRC_5_INT                   0x00000085
17801 #define SQ_SRC_6_INT                   0x00000086
17802 #define SQ_SRC_7_INT                   0x00000087
17803 #define SQ_SRC_8_INT                   0x00000088
17804 #define SQ_SRC_9_INT                   0x00000089
17805 #define SQ_SRC_10_INT                  0x0000008a
17806 #define SQ_SRC_11_INT                  0x0000008b
17807 #define SQ_SRC_12_INT                  0x0000008c
17808 #define SQ_SRC_13_INT                  0x0000008d
17809 #define SQ_SRC_14_INT                  0x0000008e
17810 #define SQ_SRC_15_INT                  0x0000008f
17811 #define SQ_SRC_16_INT                  0x00000090
17812 #define SQ_SRC_17_INT                  0x00000091
17813 #define SQ_SRC_18_INT                  0x00000092
17814 #define SQ_SRC_19_INT                  0x00000093
17815 #define SQ_SRC_20_INT                  0x00000094
17816 #define SQ_SRC_21_INT                  0x00000095
17817 #define SQ_SRC_22_INT                  0x00000096
17818 #define SQ_SRC_23_INT                  0x00000097
17819 #define SQ_SRC_24_INT                  0x00000098
17820 #define SQ_SRC_25_INT                  0x00000099
17821 #define SQ_SRC_26_INT                  0x0000009a
17822 #define SQ_SRC_27_INT                  0x0000009b
17823 #define SQ_SRC_28_INT                  0x0000009c
17824 #define SQ_SRC_29_INT                  0x0000009d
17825 #define SQ_SRC_30_INT                  0x0000009e
17826 #define SQ_SRC_31_INT                  0x0000009f
17827 #define SQ_SRC_32_INT                  0x000000a0
17828 #define SQ_SRC_33_INT                  0x000000a1
17829 #define SQ_SRC_34_INT                  0x000000a2
17830 #define SQ_SRC_35_INT                  0x000000a3
17831 #define SQ_SRC_36_INT                  0x000000a4
17832 #define SQ_SRC_37_INT                  0x000000a5
17833 #define SQ_SRC_38_INT                  0x000000a6
17834 #define SQ_SRC_39_INT                  0x000000a7
17835 #define SQ_SRC_40_INT                  0x000000a8
17836 #define SQ_SRC_41_INT                  0x000000a9
17837 #define SQ_SRC_42_INT                  0x000000aa
17838 #define SQ_SRC_43_INT                  0x000000ab
17839 #define SQ_SRC_44_INT                  0x000000ac
17840 #define SQ_SRC_45_INT                  0x000000ad
17841 #define SQ_SRC_46_INT                  0x000000ae
17842 #define SQ_SRC_47_INT                  0x000000af
17843 #define SQ_SRC_48_INT                  0x000000b0
17844 #define SQ_SRC_49_INT                  0x000000b1
17845 #define SQ_SRC_50_INT                  0x000000b2
17846 #define SQ_SRC_51_INT                  0x000000b3
17847 #define SQ_SRC_52_INT                  0x000000b4
17848 #define SQ_SRC_53_INT                  0x000000b5
17849 #define SQ_SRC_54_INT                  0x000000b6
17850 #define SQ_SRC_55_INT                  0x000000b7
17851 #define SQ_SRC_56_INT                  0x000000b8
17852 #define SQ_SRC_57_INT                  0x000000b9
17853 #define SQ_SRC_58_INT                  0x000000ba
17854 #define SQ_SRC_59_INT                  0x000000bb
17855 #define SQ_SRC_60_INT                  0x000000bc
17856 #define SQ_SRC_61_INT                  0x000000bd
17857 #define SQ_SRC_62_INT                  0x000000be
17858 #define SQ_SRC_63_INT                  0x000000bf
17859 
17860 /*
17861  * VALUE_SQ_OP_MIMG value
17862  */
17863 
17864 #define SQ_IMAGE_LOAD                  0x00000000
17865 #define SQ_IMAGE_LOAD_MIP              0x00000001
17866 #define SQ_IMAGE_LOAD_PCK              0x00000002
17867 #define SQ_IMAGE_LOAD_PCK_SGN          0x00000003
17868 #define SQ_IMAGE_LOAD_MIP_PCK          0x00000004
17869 #define SQ_IMAGE_LOAD_MIP_PCK_SGN      0x00000005
17870 #define SQ_IMAGE_STORE                 0x00000008
17871 #define SQ_IMAGE_STORE_MIP             0x00000009
17872 #define SQ_IMAGE_STORE_PCK             0x0000000a
17873 #define SQ_IMAGE_STORE_MIP_PCK         0x0000000b
17874 #define SQ_IMAGE_GET_RESINFO           0x0000000e
17875 #define SQ_IMAGE_ATOMIC_SWAP           0x00000010
17876 #define SQ_IMAGE_ATOMIC_CMPSWAP        0x00000011
17877 #define SQ_IMAGE_ATOMIC_ADD            0x00000012
17878 #define SQ_IMAGE_ATOMIC_SUB            0x00000013
17879 #define SQ_IMAGE_ATOMIC_SMIN           0x00000014
17880 #define SQ_IMAGE_ATOMIC_UMIN           0x00000015
17881 #define SQ_IMAGE_ATOMIC_SMAX           0x00000016
17882 #define SQ_IMAGE_ATOMIC_UMAX           0x00000017
17883 #define SQ_IMAGE_ATOMIC_AND            0x00000018
17884 #define SQ_IMAGE_ATOMIC_OR             0x00000019
17885 #define SQ_IMAGE_ATOMIC_XOR            0x0000001a
17886 #define SQ_IMAGE_ATOMIC_INC            0x0000001b
17887 #define SQ_IMAGE_ATOMIC_DEC            0x0000001c
17888 #define SQ_IMAGE_SAMPLE                0x00000020
17889 #define SQ_IMAGE_SAMPLE_CL             0x00000021
17890 #define SQ_IMAGE_SAMPLE_D              0x00000022
17891 #define SQ_IMAGE_SAMPLE_D_CL           0x00000023
17892 #define SQ_IMAGE_SAMPLE_L              0x00000024
17893 #define SQ_IMAGE_SAMPLE_B              0x00000025
17894 #define SQ_IMAGE_SAMPLE_B_CL           0x00000026
17895 #define SQ_IMAGE_SAMPLE_LZ             0x00000027
17896 #define SQ_IMAGE_SAMPLE_C              0x00000028
17897 #define SQ_IMAGE_SAMPLE_C_CL           0x00000029
17898 #define SQ_IMAGE_SAMPLE_C_D            0x0000002a
17899 #define SQ_IMAGE_SAMPLE_C_D_CL         0x0000002b
17900 #define SQ_IMAGE_SAMPLE_C_L            0x0000002c
17901 #define SQ_IMAGE_SAMPLE_C_B            0x0000002d
17902 #define SQ_IMAGE_SAMPLE_C_B_CL         0x0000002e
17903 #define SQ_IMAGE_SAMPLE_C_LZ           0x0000002f
17904 #define SQ_IMAGE_SAMPLE_O              0x00000030
17905 #define SQ_IMAGE_SAMPLE_CL_O           0x00000031
17906 #define SQ_IMAGE_SAMPLE_D_O            0x00000032
17907 #define SQ_IMAGE_SAMPLE_D_CL_O         0x00000033
17908 #define SQ_IMAGE_SAMPLE_L_O            0x00000034
17909 #define SQ_IMAGE_SAMPLE_B_O            0x00000035
17910 #define SQ_IMAGE_SAMPLE_B_CL_O         0x00000036
17911 #define SQ_IMAGE_SAMPLE_LZ_O           0x00000037
17912 #define SQ_IMAGE_SAMPLE_C_O            0x00000038
17913 #define SQ_IMAGE_SAMPLE_C_CL_O         0x00000039
17914 #define SQ_IMAGE_SAMPLE_C_D_O          0x0000003a
17915 #define SQ_IMAGE_SAMPLE_C_D_CL_O       0x0000003b
17916 #define SQ_IMAGE_SAMPLE_C_L_O          0x0000003c
17917 #define SQ_IMAGE_SAMPLE_C_B_O          0x0000003d
17918 #define SQ_IMAGE_SAMPLE_C_B_CL_O       0x0000003e
17919 #define SQ_IMAGE_SAMPLE_C_LZ_O         0x0000003f
17920 #define SQ_IMAGE_GATHER4               0x00000040
17921 #define SQ_IMAGE_GATHER4_CL            0x00000041
17922 #define SQ_IMAGE_GATHER4H              0x00000042
17923 #define SQ_IMAGE_GATHER4_L             0x00000044
17924 #define SQ_IMAGE_GATHER4_B             0x00000045
17925 #define SQ_IMAGE_GATHER4_B_CL          0x00000046
17926 #define SQ_IMAGE_GATHER4_LZ            0x00000047
17927 #define SQ_IMAGE_GATHER4_C             0x00000048
17928 #define SQ_IMAGE_GATHER4_C_CL          0x00000049
17929 #define SQ_IMAGE_GATHER4H_PCK          0x0000004a
17930 #define SQ_IMAGE_GATHER8H_PCK          0x0000004b
17931 #define SQ_IMAGE_GATHER4_C_L           0x0000004c
17932 #define SQ_IMAGE_GATHER4_C_B           0x0000004d
17933 #define SQ_IMAGE_GATHER4_C_B_CL        0x0000004e
17934 #define SQ_IMAGE_GATHER4_C_LZ          0x0000004f
17935 #define SQ_IMAGE_GATHER4_O             0x00000050
17936 #define SQ_IMAGE_GATHER4_CL_O          0x00000051
17937 #define SQ_IMAGE_GATHER4_L_O           0x00000054
17938 #define SQ_IMAGE_GATHER4_B_O           0x00000055
17939 #define SQ_IMAGE_GATHER4_B_CL_O        0x00000056
17940 #define SQ_IMAGE_GATHER4_LZ_O          0x00000057
17941 #define SQ_IMAGE_GATHER4_C_O           0x00000058
17942 #define SQ_IMAGE_GATHER4_C_CL_O        0x00000059
17943 #define SQ_IMAGE_GATHER4_C_L_O         0x0000005c
17944 #define SQ_IMAGE_GATHER4_C_B_O         0x0000005d
17945 #define SQ_IMAGE_GATHER4_C_B_CL_O      0x0000005e
17946 #define SQ_IMAGE_GATHER4_C_LZ_O        0x0000005f
17947 #define SQ_IMAGE_GET_LOD               0x00000060
17948 #define SQ_IMAGE_SAMPLE_CD             0x00000068
17949 #define SQ_IMAGE_SAMPLE_CD_CL          0x00000069
17950 #define SQ_IMAGE_SAMPLE_C_CD           0x0000006a
17951 #define SQ_IMAGE_SAMPLE_C_CD_CL        0x0000006b
17952 #define SQ_IMAGE_SAMPLE_CD_O           0x0000006c
17953 #define SQ_IMAGE_SAMPLE_CD_CL_O        0x0000006d
17954 #define SQ_IMAGE_SAMPLE_C_CD_O         0x0000006e
17955 #define SQ_IMAGE_SAMPLE_C_CD_CL_O      0x0000006f
17956 #define SQ_IMAGE_RSRC256               0x0000007e
17957 #define SQ_IMAGE_SAMPLER               0x0000007f
17958 
17959 /*
17960  * VALUE_SQ_HW_REG value
17961  */
17962 
17963 #define SQ_HW_REG_MODE                 0x00000001
17964 #define SQ_HW_REG_STATUS               0x00000002
17965 #define SQ_HW_REG_TRAPSTS              0x00000003
17966 #define SQ_HW_REG_HW_ID                0x00000004
17967 #define SQ_HW_REG_GPR_ALLOC            0x00000005
17968 #define SQ_HW_REG_LDS_ALLOC            0x00000006
17969 #define SQ_HW_REG_IB_STS               0x00000007
17970 #define SQ_HW_REG_PC_LO                0x00000008
17971 #define SQ_HW_REG_PC_HI                0x00000009
17972 #define SQ_HW_REG_INST_DW0             0x0000000a
17973 #define SQ_HW_REG_INST_DW1             0x0000000b
17974 #define SQ_HW_REG_IB_DBG0              0x0000000c
17975 #define SQ_HW_REG_IB_DBG1              0x0000000d
17976 #define SQ_HW_REG_FLUSH_IB             0x0000000e
17977 #define SQ_HW_REG_SH_MEM_BASES         0x0000000f
17978 #define SQ_HW_REG_SQ_SHADER_TBA_LO     0x00000010
17979 #define SQ_HW_REG_SQ_SHADER_TBA_HI     0x00000011
17980 #define SQ_HW_REG_SQ_SHADER_TMA_LO     0x00000012
17981 #define SQ_HW_REG_SQ_SHADER_TMA_HI     0x00000013
17982 
17983 /*
17984  * VALUE_SQ_OP_SOP1 value
17985  */
17986 
17987 #define SQ_S_MOV_B32                   0x00000000
17988 #define SQ_S_MOV_B64                   0x00000001
17989 #define SQ_S_CMOV_B32                  0x00000002
17990 #define SQ_S_CMOV_B64                  0x00000003
17991 #define SQ_S_NOT_B32                   0x00000004
17992 #define SQ_S_NOT_B64                   0x00000005
17993 #define SQ_S_WQM_B32                   0x00000006
17994 #define SQ_S_WQM_B64                   0x00000007
17995 #define SQ_S_BREV_B32                  0x00000008
17996 #define SQ_S_BREV_B64                  0x00000009
17997 #define SQ_S_BCNT0_I32_B32             0x0000000a
17998 #define SQ_S_BCNT0_I32_B64             0x0000000b
17999 #define SQ_S_BCNT1_I32_B32             0x0000000c
18000 #define SQ_S_BCNT1_I32_B64             0x0000000d
18001 #define SQ_S_FF0_I32_B32               0x0000000e
18002 #define SQ_S_FF0_I32_B64               0x0000000f
18003 #define SQ_S_FF1_I32_B32               0x00000010
18004 #define SQ_S_FF1_I32_B64               0x00000011
18005 #define SQ_S_FLBIT_I32_B32             0x00000012
18006 #define SQ_S_FLBIT_I32_B64             0x00000013
18007 #define SQ_S_FLBIT_I32                 0x00000014
18008 #define SQ_S_FLBIT_I32_I64             0x00000015
18009 #define SQ_S_SEXT_I32_I8               0x00000016
18010 #define SQ_S_SEXT_I32_I16              0x00000017
18011 #define SQ_S_BITSET0_B32               0x00000018
18012 #define SQ_S_BITSET0_B64               0x00000019
18013 #define SQ_S_BITSET1_B32               0x0000001a
18014 #define SQ_S_BITSET1_B64               0x0000001b
18015 #define SQ_S_GETPC_B64                 0x0000001c
18016 #define SQ_S_SETPC_B64                 0x0000001d
18017 #define SQ_S_SWAPPC_B64                0x0000001e
18018 #define SQ_S_RFE_B64                   0x0000001f
18019 #define SQ_S_AND_SAVEEXEC_B64          0x00000020
18020 #define SQ_S_OR_SAVEEXEC_B64           0x00000021
18021 #define SQ_S_XOR_SAVEEXEC_B64          0x00000022
18022 #define SQ_S_ANDN2_SAVEEXEC_B64        0x00000023
18023 #define SQ_S_ORN2_SAVEEXEC_B64         0x00000024
18024 #define SQ_S_NAND_SAVEEXEC_B64         0x00000025
18025 #define SQ_S_NOR_SAVEEXEC_B64          0x00000026
18026 #define SQ_S_XNOR_SAVEEXEC_B64         0x00000027
18027 #define SQ_S_QUADMASK_B32              0x00000028
18028 #define SQ_S_QUADMASK_B64              0x00000029
18029 #define SQ_S_MOVRELS_B32               0x0000002a
18030 #define SQ_S_MOVRELS_B64               0x0000002b
18031 #define SQ_S_MOVRELD_B32               0x0000002c
18032 #define SQ_S_MOVRELD_B64               0x0000002d
18033 #define SQ_S_CBRANCH_JOIN              0x0000002e
18034 #define SQ_S_MOV_REGRD_B32             0x0000002f
18035 #define SQ_S_ABS_I32                   0x00000030
18036 #define SQ_S_MOV_FED_B32               0x00000031
18037 #define SQ_S_SET_GPR_IDX_IDX           0x00000032
18038 #define SQ_S_ANDN1_SAVEEXEC_B64        0x00000033
18039 #define SQ_S_ORN1_SAVEEXEC_B64         0x00000034
18040 #define SQ_S_ANDN1_WREXEC_B64          0x00000035
18041 #define SQ_S_ANDN2_WREXEC_B64          0x00000036
18042 #define SQ_S_BITREPLICATE_B64_B32      0x00000037
18043 
18044 /*
18045  * VALUE_SQ_CNT value
18046  */
18047 
18048 #define SQ_CNT1                        0x00000000
18049 #define SQ_CNT2                        0x00000001
18050 #define SQ_CNT3                        0x00000002
18051 #define SQ_CNT4                        0x00000003
18052 
18053 /*
18054  * VALUE_SQ_OP_VOP3 value
18055  */
18056 
18057 #define SQ_V_MAD_LEGACY_F32            0x000001c0
18058 #define SQ_V_MAD_F32                   0x000001c1
18059 #define SQ_V_MAD_I32_I24               0x000001c2
18060 #define SQ_V_MAD_U32_U24               0x000001c3
18061 #define SQ_V_CUBEID_F32                0x000001c4
18062 #define SQ_V_CUBESC_F32                0x000001c5
18063 #define SQ_V_CUBETC_F32                0x000001c6
18064 #define SQ_V_CUBEMA_F32                0x000001c7
18065 #define SQ_V_BFE_U32                   0x000001c8
18066 #define SQ_V_BFE_I32                   0x000001c9
18067 #define SQ_V_BFI_B32                   0x000001ca
18068 #define SQ_V_FMA_F32                   0x000001cb
18069 #define SQ_V_FMA_F64                   0x000001cc
18070 #define SQ_V_LERP_U8                   0x000001cd
18071 #define SQ_V_ALIGNBIT_B32              0x000001ce
18072 #define SQ_V_ALIGNBYTE_B32             0x000001cf
18073 #define SQ_V_MIN3_F32                  0x000001d0
18074 #define SQ_V_MIN3_I32                  0x000001d1
18075 #define SQ_V_MIN3_U32                  0x000001d2
18076 #define SQ_V_MAX3_F32                  0x000001d3
18077 #define SQ_V_MAX3_I32                  0x000001d4
18078 #define SQ_V_MAX3_U32                  0x000001d5
18079 #define SQ_V_MED3_F32                  0x000001d6
18080 #define SQ_V_MED3_I32                  0x000001d7
18081 #define SQ_V_MED3_U32                  0x000001d8
18082 #define SQ_V_SAD_U8                    0x000001d9
18083 #define SQ_V_SAD_HI_U8                 0x000001da
18084 #define SQ_V_SAD_U16                   0x000001db
18085 #define SQ_V_SAD_U32                   0x000001dc
18086 #define SQ_V_CVT_PK_U8_F32             0x000001dd
18087 #define SQ_V_DIV_FIXUP_F32             0x000001de
18088 #define SQ_V_DIV_FIXUP_F64             0x000001df
18089 #define SQ_V_DIV_SCALE_F32             0x000001e0
18090 #define SQ_V_DIV_SCALE_F64             0x000001e1
18091 #define SQ_V_DIV_FMAS_F32              0x000001e2
18092 #define SQ_V_DIV_FMAS_F64              0x000001e3
18093 #define SQ_V_MSAD_U8                   0x000001e4
18094 #define SQ_V_QSAD_PK_U16_U8            0x000001e5
18095 #define SQ_V_MQSAD_PK_U16_U8           0x000001e6
18096 #define SQ_V_MQSAD_U32_U8              0x000001e7
18097 #define SQ_V_MAD_U64_U32               0x000001e8
18098 #define SQ_V_MAD_I64_I32               0x000001e9
18099 #define SQ_V_MAD_LEGACY_F16            0x000001ea
18100 #define SQ_V_MAD_LEGACY_U16            0x000001eb
18101 #define SQ_V_MAD_LEGACY_I16            0x000001ec
18102 #define SQ_V_PERM_B32                  0x000001ed
18103 #define SQ_V_FMA_LEGACY_F16            0x000001ee
18104 #define SQ_V_DIV_FIXUP_LEGACY_F16      0x000001ef
18105 #define SQ_V_CVT_PKACCUM_U8_F32        0x000001f0
18106 #define SQ_V_MAD_U32_U16               0x000001f1
18107 #define SQ_V_MAD_I32_I16               0x000001f2
18108 #define SQ_V_XAD_U32                   0x000001f3
18109 #define SQ_V_MIN3_F16                  0x000001f4
18110 #define SQ_V_MIN3_I16                  0x000001f5
18111 #define SQ_V_MIN3_U16                  0x000001f6
18112 #define SQ_V_MAX3_F16                  0x000001f7
18113 #define SQ_V_MAX3_I16                  0x000001f8
18114 #define SQ_V_MAX3_U16                  0x000001f9
18115 #define SQ_V_MED3_F16                  0x000001fa
18116 #define SQ_V_MED3_I16                  0x000001fb
18117 #define SQ_V_MED3_U16                  0x000001fc
18118 #define SQ_V_LSHL_ADD_U32              0x000001fd
18119 #define SQ_V_ADD_LSHL_U32              0x000001fe
18120 #define SQ_V_ADD3_U32                  0x000001ff
18121 #define SQ_V_LSHL_OR_B32               0x00000200
18122 #define SQ_V_AND_OR_B32                0x00000201
18123 #define SQ_V_OR3_B32                   0x00000202
18124 #define SQ_V_MAD_F16                   0x00000203
18125 #define SQ_V_MAD_U16                   0x00000204
18126 #define SQ_V_MAD_I16                   0x00000205
18127 #define SQ_V_FMA_F16                   0x00000206
18128 #define SQ_V_DIV_FIXUP_F16             0x00000207
18129 #define SQ_V_INTERP_P1LL_F16           0x00000274
18130 #define SQ_V_INTERP_P1LV_F16           0x00000275
18131 #define SQ_V_INTERP_P2_LEGACY_F16      0x00000276
18132 #define SQ_V_INTERP_P2_F16             0x00000277
18133 #define SQ_V_ADD_F64                   0x00000280
18134 #define SQ_V_MUL_F64                   0x00000281
18135 #define SQ_V_MIN_F64                   0x00000282
18136 #define SQ_V_MAX_F64                   0x00000283
18137 #define SQ_V_LDEXP_F64                 0x00000284
18138 #define SQ_V_MUL_LO_U32                0x00000285
18139 #define SQ_V_MUL_HI_U32                0x00000286
18140 #define SQ_V_MUL_HI_I32                0x00000287
18141 #define SQ_V_LDEXP_F32                 0x00000288
18142 #define SQ_V_READLANE_B32              0x00000289
18143 #define SQ_V_WRITELANE_B32             0x0000028a
18144 #define SQ_V_BCNT_U32_B32              0x0000028b
18145 #define SQ_V_MBCNT_LO_U32_B32          0x0000028c
18146 #define SQ_V_MBCNT_HI_U32_B32          0x0000028d
18147 #define SQ_V_MAC_LEGACY_F32            0x0000028e
18148 #define SQ_V_LSHLREV_B64               0x0000028f
18149 #define SQ_V_LSHRREV_B64               0x00000290
18150 #define SQ_V_ASHRREV_I64               0x00000291
18151 #define SQ_V_TRIG_PREOP_F64            0x00000292
18152 #define SQ_V_BFM_B32                   0x00000293
18153 #define SQ_V_CVT_PKNORM_I16_F32        0x00000294
18154 #define SQ_V_CVT_PKNORM_U16_F32        0x00000295
18155 #define SQ_V_CVT_PKRTZ_F16_F32         0x00000296
18156 #define SQ_V_CVT_PK_U16_U32            0x00000297
18157 #define SQ_V_CVT_PK_I16_I32            0x00000298
18158 #define SQ_V_CVT_PKNORM_I16_F16        0x00000299
18159 #define SQ_V_CVT_PKNORM_U16_F16        0x0000029a
18160 #define SQ_V_READLANE_REGRD_B32        0x0000029b
18161 #define SQ_V_ADD_I32                   0x0000029c
18162 #define SQ_V_SUB_I32                   0x0000029d
18163 #define SQ_V_ADD_I16                   0x0000029e
18164 #define SQ_V_SUB_I16                   0x0000029f
18165 #define SQ_V_PACK_B32_F16              0x000002a0
18166 
18167 /*
18168  * VALUE_SQ_SSRC_SPECIAL_LIT value
18169  */
18170 
18171 #define SQ_SRC_LITERAL                 0x000000ff
18172 
18173 /*
18174  * VALUE_SQ_DPP_CTRL value
18175  */
18176 
18177 #define SQ_DPP_QUAD_PERM               0x00000000
18178 #define SQ_DPP_ROW_SL1                 0x00000101
18179 #define SQ_DPP_ROW_SL2                 0x00000102
18180 #define SQ_DPP_ROW_SL3                 0x00000103
18181 #define SQ_DPP_ROW_SL4                 0x00000104
18182 #define SQ_DPP_ROW_SL5                 0x00000105
18183 #define SQ_DPP_ROW_SL6                 0x00000106
18184 #define SQ_DPP_ROW_SL7                 0x00000107
18185 #define SQ_DPP_ROW_SL8                 0x00000108
18186 #define SQ_DPP_ROW_SL9                 0x00000109
18187 #define SQ_DPP_ROW_SL10                0x0000010a
18188 #define SQ_DPP_ROW_SL11                0x0000010b
18189 #define SQ_DPP_ROW_SL12                0x0000010c
18190 #define SQ_DPP_ROW_SL13                0x0000010d
18191 #define SQ_DPP_ROW_SL14                0x0000010e
18192 #define SQ_DPP_ROW_SL15                0x0000010f
18193 #define SQ_DPP_ROW_SR1                 0x00000111
18194 #define SQ_DPP_ROW_SR2                 0x00000112
18195 #define SQ_DPP_ROW_SR3                 0x00000113
18196 #define SQ_DPP_ROW_SR4                 0x00000114
18197 #define SQ_DPP_ROW_SR5                 0x00000115
18198 #define SQ_DPP_ROW_SR6                 0x00000116
18199 #define SQ_DPP_ROW_SR7                 0x00000117
18200 #define SQ_DPP_ROW_SR8                 0x00000118
18201 #define SQ_DPP_ROW_SR9                 0x00000119
18202 #define SQ_DPP_ROW_SR10                0x0000011a
18203 #define SQ_DPP_ROW_SR11                0x0000011b
18204 #define SQ_DPP_ROW_SR12                0x0000011c
18205 #define SQ_DPP_ROW_SR13                0x0000011d
18206 #define SQ_DPP_ROW_SR14                0x0000011e
18207 #define SQ_DPP_ROW_SR15                0x0000011f
18208 #define SQ_DPP_ROW_RR1                 0x00000121
18209 #define SQ_DPP_ROW_RR2                 0x00000122
18210 #define SQ_DPP_ROW_RR3                 0x00000123
18211 #define SQ_DPP_ROW_RR4                 0x00000124
18212 #define SQ_DPP_ROW_RR5                 0x00000125
18213 #define SQ_DPP_ROW_RR6                 0x00000126
18214 #define SQ_DPP_ROW_RR7                 0x00000127
18215 #define SQ_DPP_ROW_RR8                 0x00000128
18216 #define SQ_DPP_ROW_RR9                 0x00000129
18217 #define SQ_DPP_ROW_RR10                0x0000012a
18218 #define SQ_DPP_ROW_RR11                0x0000012b
18219 #define SQ_DPP_ROW_RR12                0x0000012c
18220 #define SQ_DPP_ROW_RR13                0x0000012d
18221 #define SQ_DPP_ROW_RR14                0x0000012e
18222 #define SQ_DPP_ROW_RR15                0x0000012f
18223 #define SQ_DPP_WF_SL1                  0x00000130
18224 #define SQ_DPP_WF_RL1                  0x00000134
18225 #define SQ_DPP_WF_SR1                  0x00000138
18226 #define SQ_DPP_WF_RR1                  0x0000013c
18227 #define SQ_DPP_ROW_MIRROR              0x00000140
18228 #define SQ_DPP_ROW_HALF_MIRROR         0x00000141
18229 #define SQ_DPP_ROW_BCAST15             0x00000142
18230 #define SQ_DPP_ROW_BCAST31             0x00000143
18231 
18232 /*
18233  * VALUE_SQ_FLAT_SCRATCH_LOHI value
18234  */
18235 
18236 #define SQ_FLAT_SCRATCH_LO             0x00000066
18237 #define SQ_FLAT_SCRATCH_HI             0x00000067
18238 
18239 /*
18240  * VALUE_SQ_OP_VOP1 value
18241  */
18242 
18243 #define SQ_V_NOP                       0x00000000
18244 #define SQ_V_MOV_B32                   0x00000001
18245 #define SQ_V_READFIRSTLANE_B32         0x00000002
18246 #define SQ_V_CVT_I32_F64               0x00000003
18247 #define SQ_V_CVT_F64_I32               0x00000004
18248 #define SQ_V_CVT_F32_I32               0x00000005
18249 #define SQ_V_CVT_F32_U32               0x00000006
18250 #define SQ_V_CVT_U32_F32               0x00000007
18251 #define SQ_V_CVT_I32_F32               0x00000008
18252 #define SQ_V_MOV_FED_B32               0x00000009
18253 #define SQ_V_CVT_F16_F32               0x0000000a
18254 #define SQ_V_CVT_F32_F16               0x0000000b
18255 #define SQ_V_CVT_RPI_I32_F32           0x0000000c
18256 #define SQ_V_CVT_FLR_I32_F32           0x0000000d
18257 #define SQ_V_CVT_OFF_F32_I4            0x0000000e
18258 #define SQ_V_CVT_F32_F64               0x0000000f
18259 #define SQ_V_CVT_F64_F32               0x00000010
18260 #define SQ_V_CVT_F32_UBYTE0            0x00000011
18261 #define SQ_V_CVT_F32_UBYTE1            0x00000012
18262 #define SQ_V_CVT_F32_UBYTE2            0x00000013
18263 #define SQ_V_CVT_F32_UBYTE3            0x00000014
18264 #define SQ_V_CVT_U32_F64               0x00000015
18265 #define SQ_V_CVT_F64_U32               0x00000016
18266 #define SQ_V_TRUNC_F64                 0x00000017
18267 #define SQ_V_CEIL_F64                  0x00000018
18268 #define SQ_V_RNDNE_F64                 0x00000019
18269 #define SQ_V_FLOOR_F64                 0x0000001a
18270 #define SQ_V_FRACT_F32                 0x0000001b
18271 #define SQ_V_TRUNC_F32                 0x0000001c
18272 #define SQ_V_CEIL_F32                  0x0000001d
18273 #define SQ_V_RNDNE_F32                 0x0000001e
18274 #define SQ_V_FLOOR_F32                 0x0000001f
18275 #define SQ_V_EXP_F32                   0x00000020
18276 #define SQ_V_LOG_F32                   0x00000021
18277 #define SQ_V_RCP_F32                   0x00000022
18278 #define SQ_V_RCP_IFLAG_F32             0x00000023
18279 #define SQ_V_RSQ_F32                   0x00000024
18280 #define SQ_V_RCP_F64                   0x00000025
18281 #define SQ_V_RSQ_F64                   0x00000026
18282 #define SQ_V_SQRT_F32                  0x00000027
18283 #define SQ_V_SQRT_F64                  0x00000028
18284 #define SQ_V_SIN_F32                   0x00000029
18285 #define SQ_V_COS_F32                   0x0000002a
18286 #define SQ_V_NOT_B32                   0x0000002b
18287 #define SQ_V_BFREV_B32                 0x0000002c
18288 #define SQ_V_FFBH_U32                  0x0000002d
18289 #define SQ_V_FFBL_B32                  0x0000002e
18290 #define SQ_V_FFBH_I32                  0x0000002f
18291 #define SQ_V_FREXP_EXP_I32_F64         0x00000030
18292 #define SQ_V_FREXP_MANT_F64            0x00000031
18293 #define SQ_V_FRACT_F64                 0x00000032
18294 #define SQ_V_FREXP_EXP_I32_F32         0x00000033
18295 #define SQ_V_FREXP_MANT_F32            0x00000034
18296 #define SQ_V_CLREXCP                   0x00000035
18297 #define SQ_V_MOV_PRSV_B32              0x00000036
18298 #define SQ_V_CVT_F16_U16               0x00000039
18299 #define SQ_V_CVT_F16_I16               0x0000003a
18300 #define SQ_V_CVT_U16_F16               0x0000003b
18301 #define SQ_V_CVT_I16_F16               0x0000003c
18302 #define SQ_V_RCP_F16                   0x0000003d
18303 #define SQ_V_SQRT_F16                  0x0000003e
18304 #define SQ_V_RSQ_F16                   0x0000003f
18305 #define SQ_V_LOG_F16                   0x00000040
18306 #define SQ_V_EXP_F16                   0x00000041
18307 #define SQ_V_FREXP_MANT_F16            0x00000042
18308 #define SQ_V_FREXP_EXP_I16_F16         0x00000043
18309 #define SQ_V_FLOOR_F16                 0x00000044
18310 #define SQ_V_CEIL_F16                  0x00000045
18311 #define SQ_V_TRUNC_F16                 0x00000046
18312 #define SQ_V_RNDNE_F16                 0x00000047
18313 #define SQ_V_FRACT_F16                 0x00000048
18314 #define SQ_V_SIN_F16                   0x00000049
18315 #define SQ_V_COS_F16                   0x0000004a
18316 #define SQ_V_EXP_LEGACY_F32            0x0000004b
18317 #define SQ_V_LOG_LEGACY_F32            0x0000004c
18318 #define SQ_V_CVT_NORM_I16_F16          0x0000004d
18319 #define SQ_V_CVT_NORM_U16_F16          0x0000004e
18320 #define SQ_V_SAT_PK_U8_I16             0x0000004f
18321 #define SQ_V_WRITELANE_IMM32           0x00000050
18322 #define SQ_V_SWAP_B32                  0x00000051
18323 
18324 /*
18325  * VALUE_SQ_OP_FLAT value
18326  */
18327 
18328 #define SQ_FLAT_LOAD_UBYTE             0x00000010
18329 #define SQ_FLAT_LOAD_SBYTE             0x00000011
18330 #define SQ_FLAT_LOAD_USHORT            0x00000012
18331 #define SQ_FLAT_LOAD_SSHORT            0x00000013
18332 #define SQ_FLAT_LOAD_DWORD             0x00000014
18333 #define SQ_FLAT_LOAD_DWORDX2           0x00000015
18334 #define SQ_FLAT_LOAD_DWORDX3           0x00000016
18335 #define SQ_FLAT_LOAD_DWORDX4           0x00000017
18336 #define SQ_FLAT_STORE_BYTE             0x00000018
18337 #define SQ_FLAT_STORE_SHORT            0x0000001a
18338 #define SQ_FLAT_STORE_DWORD            0x0000001c
18339 #define SQ_FLAT_STORE_DWORDX2          0x0000001d
18340 #define SQ_FLAT_STORE_DWORDX3          0x0000001e
18341 #define SQ_FLAT_STORE_DWORDX4          0x0000001f
18342 #define SQ_FLAT_ATOMIC_SWAP            0x00000040
18343 #define SQ_FLAT_ATOMIC_CMPSWAP         0x00000041
18344 #define SQ_FLAT_ATOMIC_ADD             0x00000042
18345 #define SQ_FLAT_ATOMIC_SUB             0x00000043
18346 #define SQ_FLAT_ATOMIC_SMIN            0x00000044
18347 #define SQ_FLAT_ATOMIC_UMIN            0x00000045
18348 #define SQ_FLAT_ATOMIC_SMAX            0x00000046
18349 #define SQ_FLAT_ATOMIC_UMAX            0x00000047
18350 #define SQ_FLAT_ATOMIC_AND             0x00000048
18351 #define SQ_FLAT_ATOMIC_OR              0x00000049
18352 #define SQ_FLAT_ATOMIC_XOR             0x0000004a
18353 #define SQ_FLAT_ATOMIC_INC             0x0000004b
18354 #define SQ_FLAT_ATOMIC_DEC             0x0000004c
18355 #define SQ_FLAT_ATOMIC_SWAP_X2         0x00000060
18356 #define SQ_FLAT_ATOMIC_CMPSWAP_X2      0x00000061
18357 #define SQ_FLAT_ATOMIC_ADD_X2          0x00000062
18358 #define SQ_FLAT_ATOMIC_SUB_X2          0x00000063
18359 #define SQ_FLAT_ATOMIC_SMIN_X2         0x00000064
18360 #define SQ_FLAT_ATOMIC_UMIN_X2         0x00000065
18361 #define SQ_FLAT_ATOMIC_SMAX_X2         0x00000066
18362 #define SQ_FLAT_ATOMIC_UMAX_X2         0x00000067
18363 #define SQ_FLAT_ATOMIC_AND_X2          0x00000068
18364 #define SQ_FLAT_ATOMIC_OR_X2           0x00000069
18365 #define SQ_FLAT_ATOMIC_XOR_X2          0x0000006a
18366 #define SQ_FLAT_ATOMIC_INC_X2          0x0000006b
18367 #define SQ_FLAT_ATOMIC_DEC_X2          0x0000006c
18368 
18369 /*
18370  * VALUE_SQ_OP_DS value
18371  */
18372 
18373 #define SQ_DS_ADD_U32                  0x00000000
18374 #define SQ_DS_SUB_U32                  0x00000001
18375 #define SQ_DS_RSUB_U32                 0x00000002
18376 #define SQ_DS_INC_U32                  0x00000003
18377 #define SQ_DS_DEC_U32                  0x00000004
18378 #define SQ_DS_MIN_I32                  0x00000005
18379 #define SQ_DS_MAX_I32                  0x00000006
18380 #define SQ_DS_MIN_U32                  0x00000007
18381 #define SQ_DS_MAX_U32                  0x00000008
18382 #define SQ_DS_AND_B32                  0x00000009
18383 #define SQ_DS_OR_B32                   0x0000000a
18384 #define SQ_DS_XOR_B32                  0x0000000b
18385 #define SQ_DS_MSKOR_B32                0x0000000c
18386 #define SQ_DS_WRITE_B32                0x0000000d
18387 #define SQ_DS_WRITE2_B32               0x0000000e
18388 #define SQ_DS_WRITE2ST64_B32           0x0000000f
18389 #define SQ_DS_CMPST_B32                0x00000010
18390 #define SQ_DS_CMPST_F32                0x00000011
18391 #define SQ_DS_MIN_F32                  0x00000012
18392 #define SQ_DS_MAX_F32                  0x00000013
18393 #define SQ_DS_NOP                      0x00000014
18394 #define SQ_DS_ADD_F32                  0x00000015
18395 #define SQ_DS_WRITE_ADDTID_B32         0x0000001d
18396 #define SQ_DS_WRITE_B8                 0x0000001e
18397 #define SQ_DS_WRITE_B16                0x0000001f
18398 #define SQ_DS_ADD_RTN_U32              0x00000020
18399 #define SQ_DS_SUB_RTN_U32              0x00000021
18400 #define SQ_DS_RSUB_RTN_U32             0x00000022
18401 #define SQ_DS_INC_RTN_U32              0x00000023
18402 #define SQ_DS_DEC_RTN_U32              0x00000024
18403 #define SQ_DS_MIN_RTN_I32              0x00000025
18404 #define SQ_DS_MAX_RTN_I32              0x00000026
18405 #define SQ_DS_MIN_RTN_U32              0x00000027
18406 #define SQ_DS_MAX_RTN_U32              0x00000028
18407 #define SQ_DS_AND_RTN_B32              0x00000029
18408 #define SQ_DS_OR_RTN_B32               0x0000002a
18409 #define SQ_DS_XOR_RTN_B32              0x0000002b
18410 #define SQ_DS_MSKOR_RTN_B32            0x0000002c
18411 #define SQ_DS_WRXCHG_RTN_B32           0x0000002d
18412 #define SQ_DS_WRXCHG2_RTN_B32          0x0000002e
18413 #define SQ_DS_WRXCHG2ST64_RTN_B32      0x0000002f
18414 #define SQ_DS_CMPST_RTN_B32            0x00000030
18415 #define SQ_DS_CMPST_RTN_F32            0x00000031
18416 #define SQ_DS_MIN_RTN_F32              0x00000032
18417 #define SQ_DS_MAX_RTN_F32              0x00000033
18418 #define SQ_DS_WRAP_RTN_B32             0x00000034
18419 #define SQ_DS_ADD_RTN_F32              0x00000035
18420 #define SQ_DS_READ_B32                 0x00000036
18421 #define SQ_DS_READ2_B32                0x00000037
18422 #define SQ_DS_READ2ST64_B32            0x00000038
18423 #define SQ_DS_READ_I8                  0x00000039
18424 #define SQ_DS_READ_U8                  0x0000003a
18425 #define SQ_DS_READ_I16                 0x0000003b
18426 #define SQ_DS_READ_U16                 0x0000003c
18427 #define SQ_DS_SWIZZLE_B32              0x0000003d
18428 #define SQ_DS_PERMUTE_B32              0x0000003e
18429 #define SQ_DS_BPERMUTE_B32             0x0000003f
18430 #define SQ_DS_ADD_U64                  0x00000040
18431 #define SQ_DS_SUB_U64                  0x00000041
18432 #define SQ_DS_RSUB_U64                 0x00000042
18433 #define SQ_DS_INC_U64                  0x00000043
18434 #define SQ_DS_DEC_U64                  0x00000044
18435 #define SQ_DS_MIN_I64                  0x00000045
18436 #define SQ_DS_MAX_I64                  0x00000046
18437 #define SQ_DS_MIN_U64                  0x00000047
18438 #define SQ_DS_MAX_U64                  0x00000048
18439 #define SQ_DS_AND_B64                  0x00000049
18440 #define SQ_DS_OR_B64                   0x0000004a
18441 #define SQ_DS_XOR_B64                  0x0000004b
18442 #define SQ_DS_MSKOR_B64                0x0000004c
18443 #define SQ_DS_WRITE_B64                0x0000004d
18444 #define SQ_DS_WRITE2_B64               0x0000004e
18445 #define SQ_DS_WRITE2ST64_B64           0x0000004f
18446 #define SQ_DS_CMPST_B64                0x00000050
18447 #define SQ_DS_CMPST_F64                0x00000051
18448 #define SQ_DS_MIN_F64                  0x00000052
18449 #define SQ_DS_MAX_F64                  0x00000053
18450 #define SQ_DS_ADD_RTN_U64              0x00000060
18451 #define SQ_DS_SUB_RTN_U64              0x00000061
18452 #define SQ_DS_RSUB_RTN_U64             0x00000062
18453 #define SQ_DS_INC_RTN_U64              0x00000063
18454 #define SQ_DS_DEC_RTN_U64              0x00000064
18455 #define SQ_DS_MIN_RTN_I64              0x00000065
18456 #define SQ_DS_MAX_RTN_I64              0x00000066
18457 #define SQ_DS_MIN_RTN_U64              0x00000067
18458 #define SQ_DS_MAX_RTN_U64              0x00000068
18459 #define SQ_DS_AND_RTN_B64              0x00000069
18460 #define SQ_DS_OR_RTN_B64               0x0000006a
18461 #define SQ_DS_XOR_RTN_B64              0x0000006b
18462 #define SQ_DS_MSKOR_RTN_B64            0x0000006c
18463 #define SQ_DS_WRXCHG_RTN_B64           0x0000006d
18464 #define SQ_DS_WRXCHG2_RTN_B64          0x0000006e
18465 #define SQ_DS_WRXCHG2ST64_RTN_B64      0x0000006f
18466 #define SQ_DS_CMPST_RTN_B64            0x00000070
18467 #define SQ_DS_CMPST_RTN_F64            0x00000071
18468 #define SQ_DS_MIN_RTN_F64              0x00000072
18469 #define SQ_DS_MAX_RTN_F64              0x00000073
18470 #define SQ_DS_READ_B64                 0x00000076
18471 #define SQ_DS_READ2_B64                0x00000077
18472 #define SQ_DS_READ2ST64_B64            0x00000078
18473 #define SQ_DS_CONDXCHG32_RTN_B64       0x0000007e
18474 #define SQ_DS_ADD_SRC2_U32             0x00000080
18475 #define SQ_DS_SUB_SRC2_U32             0x00000081
18476 #define SQ_DS_RSUB_SRC2_U32            0x00000082
18477 #define SQ_DS_INC_SRC2_U32             0x00000083
18478 #define SQ_DS_DEC_SRC2_U32             0x00000084
18479 #define SQ_DS_MIN_SRC2_I32             0x00000085
18480 #define SQ_DS_MAX_SRC2_I32             0x00000086
18481 #define SQ_DS_MIN_SRC2_U32             0x00000087
18482 #define SQ_DS_MAX_SRC2_U32             0x00000088
18483 #define SQ_DS_AND_SRC2_B32             0x00000089
18484 #define SQ_DS_OR_SRC2_B32              0x0000008a
18485 #define SQ_DS_XOR_SRC2_B32             0x0000008b
18486 #define SQ_DS_WRITE_SRC2_B32           0x0000008d
18487 #define SQ_DS_MIN_SRC2_F32             0x00000092
18488 #define SQ_DS_MAX_SRC2_F32             0x00000093
18489 #define SQ_DS_ADD_SRC2_F32             0x00000095
18490 #define SQ_DS_GWS_SEMA_RELEASE_ALL     0x00000098
18491 #define SQ_DS_GWS_INIT                 0x00000099
18492 #define SQ_DS_GWS_SEMA_V               0x0000009a
18493 #define SQ_DS_GWS_SEMA_BR              0x0000009b
18494 #define SQ_DS_GWS_SEMA_P               0x0000009c
18495 #define SQ_DS_GWS_BARRIER              0x0000009d
18496 #define SQ_DS_READ_ADDTID_B32          0x000000b6
18497 #define SQ_DS_CONSUME                  0x000000bd
18498 #define SQ_DS_APPEND                   0x000000be
18499 #define SQ_DS_ORDERED_COUNT            0x000000bf
18500 #define SQ_DS_ADD_SRC2_U64             0x000000c0
18501 #define SQ_DS_SUB_SRC2_U64             0x000000c1
18502 #define SQ_DS_RSUB_SRC2_U64            0x000000c2
18503 #define SQ_DS_INC_SRC2_U64             0x000000c3
18504 #define SQ_DS_DEC_SRC2_U64             0x000000c4
18505 #define SQ_DS_MIN_SRC2_I64             0x000000c5
18506 #define SQ_DS_MAX_SRC2_I64             0x000000c6
18507 #define SQ_DS_MIN_SRC2_U64             0x000000c7
18508 #define SQ_DS_MAX_SRC2_U64             0x000000c8
18509 #define SQ_DS_AND_SRC2_B64             0x000000c9
18510 #define SQ_DS_OR_SRC2_B64              0x000000ca
18511 #define SQ_DS_XOR_SRC2_B64             0x000000cb
18512 #define SQ_DS_WRITE_SRC2_B64           0x000000cd
18513 #define SQ_DS_MIN_SRC2_F64             0x000000d2
18514 #define SQ_DS_MAX_SRC2_F64             0x000000d3
18515 #define SQ_DS_WRITE_B96                0x000000de
18516 #define SQ_DS_WRITE_B128               0x000000df
18517 #define SQ_DS_CONDXCHG32_RTN_B128      0x000000fd
18518 #define SQ_DS_READ_B96                 0x000000fe
18519 #define SQ_DS_READ_B128                0x000000ff
18520 
18521 /*
18522  * VALUE_SQ_OP_SMEM value
18523  */
18524 
18525 #define SQ_S_LOAD_DWORD                0x00000000
18526 #define SQ_S_LOAD_DWORDX2              0x00000001
18527 #define SQ_S_LOAD_DWORDX4              0x00000002
18528 #define SQ_S_LOAD_DWORDX8              0x00000003
18529 #define SQ_S_LOAD_DWORDX16             0x00000004
18530 #define SQ_S_SCRATCH_LOAD_DWORD        0x00000005
18531 #define SQ_S_SCRATCH_LOAD_DWORDX2      0x00000006
18532 #define SQ_S_SCRATCH_LOAD_DWORDX4      0x00000007
18533 #define SQ_S_BUFFER_LOAD_DWORD         0x00000008
18534 #define SQ_S_BUFFER_LOAD_DWORDX2       0x00000009
18535 #define SQ_S_BUFFER_LOAD_DWORDX4       0x0000000a
18536 #define SQ_S_BUFFER_LOAD_DWORDX8       0x0000000b
18537 #define SQ_S_BUFFER_LOAD_DWORDX16      0x0000000c
18538 #define SQ_S_STORE_DWORD               0x00000010
18539 #define SQ_S_STORE_DWORDX2             0x00000011
18540 #define SQ_S_STORE_DWORDX4             0x00000012
18541 #define SQ_S_SCRATCH_STORE_DWORD       0x00000015
18542 #define SQ_S_SCRATCH_STORE_DWORDX2     0x00000016
18543 #define SQ_S_SCRATCH_STORE_DWORDX4     0x00000017
18544 #define SQ_S_BUFFER_STORE_DWORD        0x00000018
18545 #define SQ_S_BUFFER_STORE_DWORDX2      0x00000019
18546 #define SQ_S_BUFFER_STORE_DWORDX4      0x0000001a
18547 #define SQ_S_DCACHE_INV                0x00000020
18548 #define SQ_S_DCACHE_WB                 0x00000021
18549 #define SQ_S_DCACHE_INV_VOL            0x00000022
18550 #define SQ_S_DCACHE_WB_VOL             0x00000023
18551 #define SQ_S_MEMTIME                   0x00000024
18552 #define SQ_S_MEMREALTIME               0x00000025
18553 #define SQ_S_ATC_PROBE                 0x00000026
18554 #define SQ_S_ATC_PROBE_BUFFER          0x00000027
18555 #define SQ_S_BUFFER_ATOMIC_SWAP        0x00000040
18556 #define SQ_S_BUFFER_ATOMIC_CMPSWAP     0x00000041
18557 #define SQ_S_BUFFER_ATOMIC_ADD         0x00000042
18558 #define SQ_S_BUFFER_ATOMIC_SUB         0x00000043
18559 #define SQ_S_BUFFER_ATOMIC_SMIN        0x00000044
18560 #define SQ_S_BUFFER_ATOMIC_UMIN        0x00000045
18561 #define SQ_S_BUFFER_ATOMIC_SMAX        0x00000046
18562 #define SQ_S_BUFFER_ATOMIC_UMAX        0x00000047
18563 #define SQ_S_BUFFER_ATOMIC_AND         0x00000048
18564 #define SQ_S_BUFFER_ATOMIC_OR          0x00000049
18565 #define SQ_S_BUFFER_ATOMIC_XOR         0x0000004a
18566 #define SQ_S_BUFFER_ATOMIC_INC         0x0000004b
18567 #define SQ_S_BUFFER_ATOMIC_DEC         0x0000004c
18568 #define SQ_S_BUFFER_ATOMIC_SWAP_X2     0x00000060
18569 #define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2  0x00000061
18570 #define SQ_S_BUFFER_ATOMIC_ADD_X2      0x00000062
18571 #define SQ_S_BUFFER_ATOMIC_SUB_X2      0x00000063
18572 #define SQ_S_BUFFER_ATOMIC_SMIN_X2     0x00000064
18573 #define SQ_S_BUFFER_ATOMIC_UMIN_X2     0x00000065
18574 #define SQ_S_BUFFER_ATOMIC_SMAX_X2     0x00000066
18575 #define SQ_S_BUFFER_ATOMIC_UMAX_X2     0x00000067
18576 #define SQ_S_BUFFER_ATOMIC_AND_X2      0x00000068
18577 #define SQ_S_BUFFER_ATOMIC_OR_X2       0x00000069
18578 #define SQ_S_BUFFER_ATOMIC_XOR_X2      0x0000006a
18579 #define SQ_S_BUFFER_ATOMIC_INC_X2      0x0000006b
18580 #define SQ_S_BUFFER_ATOMIC_DEC_X2      0x0000006c
18581 #define SQ_S_ATOMIC_SWAP               0x00000080
18582 #define SQ_S_ATOMIC_CMPSWAP            0x00000081
18583 #define SQ_S_ATOMIC_ADD                0x00000082
18584 #define SQ_S_ATOMIC_SUB                0x00000083
18585 #define SQ_S_ATOMIC_SMIN               0x00000084
18586 #define SQ_S_ATOMIC_UMIN               0x00000085
18587 #define SQ_S_ATOMIC_SMAX               0x00000086
18588 #define SQ_S_ATOMIC_UMAX               0x00000087
18589 #define SQ_S_ATOMIC_AND                0x00000088
18590 #define SQ_S_ATOMIC_OR                 0x00000089
18591 #define SQ_S_ATOMIC_XOR                0x0000008a
18592 #define SQ_S_ATOMIC_INC                0x0000008b
18593 #define SQ_S_ATOMIC_DEC                0x0000008c
18594 #define SQ_S_ATOMIC_SWAP_X2            0x000000a0
18595 #define SQ_S_ATOMIC_CMPSWAP_X2         0x000000a1
18596 #define SQ_S_ATOMIC_ADD_X2             0x000000a2
18597 #define SQ_S_ATOMIC_SUB_X2             0x000000a3
18598 #define SQ_S_ATOMIC_SMIN_X2            0x000000a4
18599 #define SQ_S_ATOMIC_UMIN_X2            0x000000a5
18600 #define SQ_S_ATOMIC_SMAX_X2            0x000000a6
18601 #define SQ_S_ATOMIC_UMAX_X2            0x000000a7
18602 #define SQ_S_ATOMIC_AND_X2             0x000000a8
18603 #define SQ_S_ATOMIC_OR_X2              0x000000a9
18604 #define SQ_S_ATOMIC_XOR_X2             0x000000aa
18605 #define SQ_S_ATOMIC_INC_X2             0x000000ab
18606 #define SQ_S_ATOMIC_DEC_X2             0x000000ac
18607 
18608 /*
18609  * VALUE_SQ_OP_VOP2 value
18610  */
18611 
18612 #define SQ_V_CNDMASK_B32               0x00000000
18613 #define SQ_V_ADD_F32                   0x00000001
18614 #define SQ_V_SUB_F32                   0x00000002
18615 #define SQ_V_SUBREV_F32                0x00000003
18616 #define SQ_V_MUL_LEGACY_F32            0x00000004
18617 #define SQ_V_MUL_F32                   0x00000005
18618 #define SQ_V_MUL_I32_I24               0x00000006
18619 #define SQ_V_MUL_HI_I32_I24            0x00000007
18620 #define SQ_V_MUL_U32_U24               0x00000008
18621 #define SQ_V_MUL_HI_U32_U24            0x00000009
18622 #define SQ_V_MIN_F32                   0x0000000a
18623 #define SQ_V_MAX_F32                   0x0000000b
18624 #define SQ_V_MIN_I32                   0x0000000c
18625 #define SQ_V_MAX_I32                   0x0000000d
18626 #define SQ_V_MIN_U32                   0x0000000e
18627 #define SQ_V_MAX_U32                   0x0000000f
18628 #define SQ_V_LSHRREV_B32               0x00000010
18629 #define SQ_V_ASHRREV_I32               0x00000011
18630 #define SQ_V_LSHLREV_B32               0x00000012
18631 #define SQ_V_AND_B32                   0x00000013
18632 #define SQ_V_OR_B32                    0x00000014
18633 #define SQ_V_XOR_B32                   0x00000015
18634 #define SQ_V_MAC_F32                   0x00000016
18635 #define SQ_V_MADMK_F32                 0x00000017
18636 #define SQ_V_MADAK_F32                 0x00000018
18637 #define SQ_V_ADD_CO_U32                0x00000019
18638 #define SQ_V_SUB_CO_U32                0x0000001a
18639 #define SQ_V_SUBREV_CO_U32             0x0000001b
18640 #define SQ_V_ADDC_CO_U32               0x0000001c
18641 #define SQ_V_SUBB_CO_U32               0x0000001d
18642 #define SQ_V_SUBBREV_CO_U32            0x0000001e
18643 #define SQ_V_ADD_F16                   0x0000001f
18644 #define SQ_V_SUB_F16                   0x00000020
18645 #define SQ_V_SUBREV_F16                0x00000021
18646 #define SQ_V_MUL_F16                   0x00000022
18647 #define SQ_V_MAC_F16                   0x00000023
18648 #define SQ_V_MADMK_F16                 0x00000024
18649 #define SQ_V_MADAK_F16                 0x00000025
18650 #define SQ_V_ADD_U16                   0x00000026
18651 #define SQ_V_SUB_U16                   0x00000027
18652 #define SQ_V_SUBREV_U16                0x00000028
18653 #define SQ_V_MUL_LO_U16                0x00000029
18654 #define SQ_V_LSHLREV_B16               0x0000002a
18655 #define SQ_V_LSHRREV_B16               0x0000002b
18656 #define SQ_V_ASHRREV_I16               0x0000002c
18657 #define SQ_V_MAX_F16                   0x0000002d
18658 #define SQ_V_MIN_F16                   0x0000002e
18659 #define SQ_V_MAX_U16                   0x0000002f
18660 #define SQ_V_MAX_I16                   0x00000030
18661 #define SQ_V_MIN_U16                   0x00000031
18662 #define SQ_V_MIN_I16                   0x00000032
18663 #define SQ_V_LDEXP_F16                 0x00000033
18664 #define SQ_V_ADD_U32                   0x00000034
18665 #define SQ_V_SUB_U32                   0x00000035
18666 #define SQ_V_SUBREV_U32                0x00000036
18667 
18668 /*
18669  * VALUE_SQ_SYSMSG_OP value
18670  */
18671 
18672 #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001
18673 #define SQ_SYSMSG_OP_REG_RD            0x00000002
18674 #define SQ_SYSMSG_OP_HOST_TRAP_ACK     0x00000003
18675 #define SQ_SYSMSG_OP_TTRACE_PC         0x00000004
18676 #define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005
18677 #define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006
18678 
18679 /*
18680  * VALUE_SQ_SSRC_SPECIAL_VCCZ value
18681  */
18682 
18683 #define SQ_SRC_VCCZ                    0x000000fb
18684 
18685 /*
18686  * VALUE_SQ_CHAN value
18687  */
18688 
18689 #define SQ_CHAN_X                      0x00000000
18690 #define SQ_CHAN_Y                      0x00000001
18691 #define SQ_CHAN_Z                      0x00000002
18692 #define SQ_CHAN_W                      0x00000003
18693 
18694 /*
18695  * VALUE_SQ_OP_SOPK value
18696  */
18697 
18698 #define SQ_S_MOVK_I32                  0x00000000
18699 #define SQ_S_CMOVK_I32                 0x00000001
18700 #define SQ_S_CMPK_EQ_I32               0x00000002
18701 #define SQ_S_CMPK_LG_I32               0x00000003
18702 #define SQ_S_CMPK_GT_I32               0x00000004
18703 #define SQ_S_CMPK_GE_I32               0x00000005
18704 #define SQ_S_CMPK_LT_I32               0x00000006
18705 #define SQ_S_CMPK_LE_I32               0x00000007
18706 #define SQ_S_CMPK_EQ_U32               0x00000008
18707 #define SQ_S_CMPK_LG_U32               0x00000009
18708 #define SQ_S_CMPK_GT_U32               0x0000000a
18709 #define SQ_S_CMPK_GE_U32               0x0000000b
18710 #define SQ_S_CMPK_LT_U32               0x0000000c
18711 #define SQ_S_CMPK_LE_U32               0x0000000d
18712 #define SQ_S_ADDK_I32                  0x0000000e
18713 #define SQ_S_MULK_I32                  0x0000000f
18714 #define SQ_S_CBRANCH_I_FORK            0x00000010
18715 #define SQ_S_GETREG_B32                0x00000011
18716 #define SQ_S_SETREG_B32                0x00000012
18717 #define SQ_S_GETREG_REGRD_B32          0x00000013
18718 #define SQ_S_SETREG_IMM32_B32          0x00000014
18719 #define SQ_S_CALL_B64                  0x00000015
18720 
18721 /*
18722  * VALUE_SQ_DPP_CTRL_L_1_15 value
18723  */
18724 
18725 #define SQ_L1                          0x00000001
18726 #define SQ_L2                          0x00000002
18727 #define SQ_L3                          0x00000003
18728 #define SQ_L4                          0x00000004
18729 #define SQ_L5                          0x00000005
18730 #define SQ_L6                          0x00000006
18731 #define SQ_L7                          0x00000007
18732 #define SQ_L8                          0x00000008
18733 #define SQ_L9                          0x00000009
18734 #define SQ_L10                         0x0000000a
18735 #define SQ_L11                         0x0000000b
18736 #define SQ_L12                         0x0000000c
18737 #define SQ_L13                         0x0000000d
18738 #define SQ_L14                         0x0000000e
18739 #define SQ_L15                         0x0000000f
18740 
18741 /*
18742  * VALUE_SQ_SGPR value
18743  */
18744 
18745 #define SQ_SGPR0                       0x00000000
18746 
18747 /*
18748  * VALUE_SQ_OP_VOP3P value
18749  */
18750 
18751 #define SQ_V_PK_MAD_I16                0x00000000
18752 #define SQ_V_PK_MUL_LO_U16             0x00000001
18753 #define SQ_V_PK_ADD_I16                0x00000002
18754 #define SQ_V_PK_SUB_I16                0x00000003
18755 #define SQ_V_PK_LSHLREV_B16            0x00000004
18756 #define SQ_V_PK_LSHRREV_B16            0x00000005
18757 #define SQ_V_PK_ASHRREV_I16            0x00000006
18758 #define SQ_V_PK_MAX_I16                0x00000007
18759 #define SQ_V_PK_MIN_I16                0x00000008
18760 #define SQ_V_PK_MAD_U16                0x00000009
18761 #define SQ_V_PK_ADD_U16                0x0000000a
18762 #define SQ_V_PK_SUB_U16                0x0000000b
18763 #define SQ_V_PK_MAX_U16                0x0000000c
18764 #define SQ_V_PK_MIN_U16                0x0000000d
18765 #define SQ_V_PK_MAD_F16                0x0000000e
18766 #define SQ_V_PK_ADD_F16                0x0000000f
18767 #define SQ_V_PK_MUL_F16                0x00000010
18768 #define SQ_V_PK_MIN_F16                0x00000011
18769 #define SQ_V_PK_MAX_F16                0x00000012
18770 #define SQ_V_MAD_MIX_F32               0x00000020
18771 #define SQ_V_MAD_MIXLO_F16             0x00000021
18772 #define SQ_V_MAD_MIXHI_F16             0x00000022
18773 
18774 /*
18775  * VALUE_SQ_OP_VINTRP value
18776  */
18777 
18778 #define SQ_V_INTERP_P1_F32             0x00000000
18779 #define SQ_V_INTERP_P2_F32             0x00000001
18780 #define SQ_V_INTERP_MOV_F32            0x00000002
18781 
18782 /*
18783  * VALUE_SQ_DPP_CTRL_R_1_15 value
18784  */
18785 
18786 #define SQ_R1                          0x00000001
18787 #define SQ_R2                          0x00000002
18788 #define SQ_R3                          0x00000003
18789 #define SQ_R4                          0x00000004
18790 #define SQ_R5                          0x00000005
18791 #define SQ_R6                          0x00000006
18792 #define SQ_R7                          0x00000007
18793 #define SQ_R8                          0x00000008
18794 #define SQ_R9                          0x00000009
18795 #define SQ_R10                         0x0000000a
18796 #define SQ_R11                         0x0000000b
18797 #define SQ_R12                         0x0000000c
18798 #define SQ_R13                         0x0000000d
18799 #define SQ_R14                         0x0000000e
18800 #define SQ_R15                         0x0000000f
18801 
18802 /*
18803  * VALUE_SQ_OP_SOP2 value
18804  */
18805 
18806 #define SQ_S_ADD_U32                   0x00000000
18807 #define SQ_S_SUB_U32                   0x00000001
18808 #define SQ_S_ADD_I32                   0x00000002
18809 #define SQ_S_SUB_I32                   0x00000003
18810 #define SQ_S_ADDC_U32                  0x00000004
18811 #define SQ_S_SUBB_U32                  0x00000005
18812 #define SQ_S_MIN_I32                   0x00000006
18813 #define SQ_S_MIN_U32                   0x00000007
18814 #define SQ_S_MAX_I32                   0x00000008
18815 #define SQ_S_MAX_U32                   0x00000009
18816 #define SQ_S_CSELECT_B32               0x0000000a
18817 #define SQ_S_CSELECT_B64               0x0000000b
18818 #define SQ_S_AND_B32                   0x0000000c
18819 #define SQ_S_AND_B64                   0x0000000d
18820 #define SQ_S_OR_B32                    0x0000000e
18821 #define SQ_S_OR_B64                    0x0000000f
18822 #define SQ_S_XOR_B32                   0x00000010
18823 #define SQ_S_XOR_B64                   0x00000011
18824 #define SQ_S_ANDN2_B32                 0x00000012
18825 #define SQ_S_ANDN2_B64                 0x00000013
18826 #define SQ_S_ORN2_B32                  0x00000014
18827 #define SQ_S_ORN2_B64                  0x00000015
18828 #define SQ_S_NAND_B32                  0x00000016
18829 #define SQ_S_NAND_B64                  0x00000017
18830 #define SQ_S_NOR_B32                   0x00000018
18831 #define SQ_S_NOR_B64                   0x00000019
18832 #define SQ_S_XNOR_B32                  0x0000001a
18833 #define SQ_S_XNOR_B64                  0x0000001b
18834 #define SQ_S_LSHL_B32                  0x0000001c
18835 #define SQ_S_LSHL_B64                  0x0000001d
18836 #define SQ_S_LSHR_B32                  0x0000001e
18837 #define SQ_S_LSHR_B64                  0x0000001f
18838 #define SQ_S_ASHR_I32                  0x00000020
18839 #define SQ_S_ASHR_I64                  0x00000021
18840 #define SQ_S_BFM_B32                   0x00000022
18841 #define SQ_S_BFM_B64                   0x00000023
18842 #define SQ_S_MUL_I32                   0x00000024
18843 #define SQ_S_BFE_U32                   0x00000025
18844 #define SQ_S_BFE_I32                   0x00000026
18845 #define SQ_S_BFE_U64                   0x00000027
18846 #define SQ_S_BFE_I64                   0x00000028
18847 #define SQ_S_CBRANCH_G_FORK            0x00000029
18848 #define SQ_S_ABSDIFF_I32               0x0000002a
18849 #define SQ_S_RFE_RESTORE_B64           0x0000002b
18850 #define SQ_S_MUL_HI_U32                0x0000002c
18851 #define SQ_S_MUL_HI_I32                0x0000002d
18852 #define SQ_S_LSHL1_ADD_U32             0x0000002e
18853 #define SQ_S_LSHL2_ADD_U32             0x0000002f
18854 #define SQ_S_LSHL3_ADD_U32             0x00000030
18855 #define SQ_S_LSHL4_ADD_U32             0x00000031
18856 #define SQ_S_PACK_LL_B32_B16           0x00000032
18857 #define SQ_S_PACK_LH_B32_B16           0x00000033
18858 #define SQ_S_PACK_HH_B32_B16           0x00000034
18859 
18860 /*
18861  * VALUE_SQ_SEG value
18862  */
18863 
18864 #define SQ_FLAT                        0x00000000
18865 #define SQ_SCRATCH                     0x00000001
18866 #define SQ_GLOBAL                      0x00000002
18867 
18868 /*
18869  * VALUE_SQ_SDST_EXEC value
18870  */
18871 
18872 #define SQ_EXEC_LO                     0x0000007e
18873 #define SQ_EXEC_HI                     0x0000007f
18874 
18875 /*
18876  * VALUE_SQ_SSRC_SPECIAL_NOLIT value
18877  */
18878 
18879 #define SQ_SRC_64_INT                  0x000000c0
18880 #define SQ_SRC_M_1_INT                 0x000000c1
18881 #define SQ_SRC_M_2_INT                 0x000000c2
18882 #define SQ_SRC_M_3_INT                 0x000000c3
18883 #define SQ_SRC_M_4_INT                 0x000000c4
18884 #define SQ_SRC_M_5_INT                 0x000000c5
18885 #define SQ_SRC_M_6_INT                 0x000000c6
18886 #define SQ_SRC_M_7_INT                 0x000000c7
18887 #define SQ_SRC_M_8_INT                 0x000000c8
18888 #define SQ_SRC_M_9_INT                 0x000000c9
18889 #define SQ_SRC_M_10_INT                0x000000ca
18890 #define SQ_SRC_M_11_INT                0x000000cb
18891 #define SQ_SRC_M_12_INT                0x000000cc
18892 #define SQ_SRC_M_13_INT                0x000000cd
18893 #define SQ_SRC_M_14_INT                0x000000ce
18894 #define SQ_SRC_M_15_INT                0x000000cf
18895 #define SQ_SRC_M_16_INT                0x000000d0
18896 #define SQ_SRC_0_5                     0x000000f0
18897 #define SQ_SRC_M_0_5                   0x000000f1
18898 #define SQ_SRC_1                       0x000000f2
18899 #define SQ_SRC_M_1                     0x000000f3
18900 #define SQ_SRC_2                       0x000000f4
18901 #define SQ_SRC_M_2                     0x000000f5
18902 #define SQ_SRC_4                       0x000000f6
18903 #define SQ_SRC_M_4                     0x000000f7
18904 #define SQ_SRC_INV_2PI                 0x000000f8
18905 
18906 /*
18907  * VALUE_SQ_VCC_LOHI value
18908  */
18909 
18910 #define SQ_VCC_LO                      0x0000006a
18911 #define SQ_VCC_HI                      0x0000006b
18912 
18913 /*
18914  * VALUE_SQ_TGT value
18915  */
18916 
18917 #define SQ_EXP_MRT0                    0x00000000
18918 #define SQ_EXP_MRTZ                    0x00000008
18919 #define SQ_EXP_NULL                    0x00000009
18920 #define SQ_EXP_POS0                    0x0000000c
18921 #define SQ_EXP_PARAM0                  0x00000020
18922 
18923 /*
18924  * VALUE_SQ_OP_SOPP value
18925  */
18926 
18927 #define SQ_S_NOP                       0x00000000
18928 #define SQ_S_ENDPGM                    0x00000001
18929 #define SQ_S_BRANCH                    0x00000002
18930 #define SQ_S_WAKEUP                    0x00000003
18931 #define SQ_S_CBRANCH_SCC0              0x00000004
18932 #define SQ_S_CBRANCH_SCC1              0x00000005
18933 #define SQ_S_CBRANCH_VCCZ              0x00000006
18934 #define SQ_S_CBRANCH_VCCNZ             0x00000007
18935 #define SQ_S_CBRANCH_EXECZ             0x00000008
18936 #define SQ_S_CBRANCH_EXECNZ            0x00000009
18937 #define SQ_S_BARRIER                   0x0000000a
18938 #define SQ_S_SETKILL                   0x0000000b
18939 #define SQ_S_WAITCNT                   0x0000000c
18940 #define SQ_S_SETHALT                   0x0000000d
18941 #define SQ_S_SLEEP                     0x0000000e
18942 #define SQ_S_SETPRIO                   0x0000000f
18943 #define SQ_S_SENDMSG                   0x00000010
18944 #define SQ_S_SENDMSGHALT               0x00000011
18945 #define SQ_S_TRAP                      0x00000012
18946 #define SQ_S_ICACHE_INV                0x00000013
18947 #define SQ_S_INCPERFLEVEL              0x00000014
18948 #define SQ_S_DECPERFLEVEL              0x00000015
18949 #define SQ_S_TTRACEDATA                0x00000016
18950 #define SQ_S_CBRANCH_CDBGSYS           0x00000017
18951 #define SQ_S_CBRANCH_CDBGUSER          0x00000018
18952 #define SQ_S_CBRANCH_CDBGSYS_OR_USER   0x00000019
18953 #define SQ_S_CBRANCH_CDBGSYS_AND_USER  0x0000001a
18954 #define SQ_S_ENDPGM_SAVED              0x0000001b
18955 #define SQ_S_SET_GPR_IDX_OFF           0x0000001c
18956 #define SQ_S_SET_GPR_IDX_MODE          0x0000001d
18957 #define SQ_S_ENDPGM_ORDERED_PS_DONE    0x0000001e
18958 
18959 /*
18960  * VALUE_SQ_OP_EXP value
18961  */
18962 
18963 #define SQ_EXP                         0x00000000
18964 
18965 /*
18966  * VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value
18967  */
18968 
18969 #define SQ_SRC_POPS_EXITING_WAVE_ID    0x000000ef
18970 
18971 /*
18972  * VALUE_SQ_XNACK_MASK_LOHI value
18973  */
18974 
18975 #define SQ_XNACK_MASK_LO               0x00000068
18976 #define SQ_XNACK_MASK_HI               0x00000069
18977 
18978 /*
18979  * VALUE_SQ_OMOD value
18980  */
18981 
18982 #define SQ_OMOD_OFF                    0x00000000
18983 #define SQ_OMOD_M2                     0x00000001
18984 #define SQ_OMOD_M4                     0x00000002
18985 #define SQ_OMOD_D2                     0x00000003
18986 
18987 /*
18988  * VALUE_SQ_SSRC_SPECIAL_EXECZ value
18989  */
18990 
18991 #define SQ_SRC_EXECZ                   0x000000fc
18992 
18993 /*
18994  * VALUE_SQ_COMPI value
18995  */
18996 
18997 #define SQ_F                           0x00000000
18998 #define SQ_LT                          0x00000001
18999 #define SQ_EQ                          0x00000002
19000 #define SQ_LE                          0x00000003
19001 #define SQ_GT                          0x00000004
19002 #define SQ_NE                          0x00000005
19003 #define SQ_GE                          0x00000006
19004 #define SQ_T                           0x00000007
19005 
19006 /*
19007  * VALUE_SQ_DPP_BOUND_CTRL value
19008  */
19009 
19010 #define SQ_DPP_BOUND_OFF               0x00000000
19011 #define SQ_DPP_BOUND_ZERO              0x00000001
19012 
19013 /*
19014  * VALUE_SQ_SDST_M0 value
19015  */
19016 
19017 #define SQ_M0                          0x0000007c
19018 
19019 /*
19020  * VALUE_SQ_MSG value
19021  */
19022 
19023 #define SQ_MSG_INTERRUPT               0x00000001
19024 #define SQ_MSG_GS                      0x00000002
19025 #define SQ_MSG_GS_DONE                 0x00000003
19026 #define SQ_MSG_SAVEWAVE                0x00000004
19027 #define SQ_MSG_STALL_WAVE_GEN          0x00000005
19028 #define SQ_MSG_HALT_WAVES              0x00000006
19029 #define SQ_MSG_ORDERED_PS_DONE         0x00000007
19030 #define SQ_MSG_EARLY_PRIM_DEALLOC      0x00000008
19031 #define SQ_MSG_GS_ALLOC_REQ            0x00000009
19032 #define SQ_MSG_SYSMSG                  0x0000000f
19033 
19034 /*
19035  * VALUE_SQ_PARAM value
19036  */
19037 
19038 #define SQ_PARAM_P10                   0x00000000
19039 #define SQ_PARAM_P20                   0x00000001
19040 #define SQ_PARAM_P0                    0x00000002
19041 
19042 /*
19043  * VALUE_SQ_OPU_VOP3 value
19044  */
19045 
19046 #define SQ_V_OPC_OFFSET                0x00000000
19047 #define SQ_V_OP2_OFFSET                0x00000100
19048 #define SQ_V_OP1_OFFSET                0x00000140
19049 #define SQ_V_INTRP_OFFSET              0x00000270
19050 #define SQ_V_OP3P_OFFSET               0x00000380
19051 
19052 /*
19053  * VALUE_SQ_SSRC_SPECIAL_SDWA value
19054  */
19055 
19056 #define SQ_SRC_SDWA                    0x000000f9
19057 
19058 /*
19059  * VALUE_SQ_SSRC_SPECIAL_APERTURE value
19060  */
19061 
19062 #define SQ_SRC_SHARED_BASE             0x000000eb
19063 #define SQ_SRC_SHARED_LIMIT            0x000000ec
19064 #define SQ_SRC_PRIVATE_BASE            0x000000ed
19065 #define SQ_SRC_PRIVATE_LIMIT           0x000000ee
19066 
19067 /*
19068  * VALUE_SQ_COMPF value
19069  */
19070 
19071 #define SQ_F                           0x00000000
19072 #define SQ_LT                          0x00000001
19073 #define SQ_EQ                          0x00000002
19074 #define SQ_LE                          0x00000003
19075 #define SQ_GT                          0x00000004
19076 #define SQ_LG                          0x00000005
19077 #define SQ_GE                          0x00000006
19078 #define SQ_O                           0x00000007
19079 #define SQ_U                           0x00000008
19080 #define SQ_NGE                         0x00000009
19081 #define SQ_NLG                         0x0000000a
19082 #define SQ_NGT                         0x0000000b
19083 #define SQ_NLE                         0x0000000c
19084 #define SQ_NEQ                         0x0000000d
19085 #define SQ_NLT                         0x0000000e
19086 #define SQ_TRU                         0x0000000f
19087 
19088 /*
19089  * VALUE_SQ_SDWA_UNUSED value
19090  */
19091 
19092 #define SQ_SDWA_UNUSED_PAD             0x00000000
19093 #define SQ_SDWA_UNUSED_SEXT            0x00000001
19094 #define SQ_SDWA_UNUSED_PRESERVE        0x00000002
19095 
19096 /*
19097  * VALUE_SQ_SSRC_SPECIAL_SCC value
19098  */
19099 
19100 #define SQ_SRC_SCC                     0x000000fd
19101 
19102 /*
19103  * VALUE_SQ_OP_VOPC value
19104  */
19105 
19106 #define SQ_V_CMP_CLASS_F32             0x00000010
19107 #define SQ_V_CMPX_CLASS_F32            0x00000011
19108 #define SQ_V_CMP_CLASS_F64             0x00000012
19109 #define SQ_V_CMPX_CLASS_F64            0x00000013
19110 #define SQ_V_CMP_CLASS_F16             0x00000014
19111 #define SQ_V_CMPX_CLASS_F16            0x00000015
19112 #define SQ_V_CMP_F_F16                 0x00000020
19113 #define SQ_V_CMP_LT_F16                0x00000021
19114 #define SQ_V_CMP_EQ_F16                0x00000022
19115 #define SQ_V_CMP_LE_F16                0x00000023
19116 #define SQ_V_CMP_GT_F16                0x00000024
19117 #define SQ_V_CMP_LG_F16                0x00000025
19118 #define SQ_V_CMP_GE_F16                0x00000026
19119 #define SQ_V_CMP_O_F16                 0x00000027
19120 #define SQ_V_CMP_U_F16                 0x00000028
19121 #define SQ_V_CMP_NGE_F16               0x00000029
19122 #define SQ_V_CMP_NLG_F16               0x0000002a
19123 #define SQ_V_CMP_NGT_F16               0x0000002b
19124 #define SQ_V_CMP_NLE_F16               0x0000002c
19125 #define SQ_V_CMP_NEQ_F16               0x0000002d
19126 #define SQ_V_CMP_NLT_F16               0x0000002e
19127 #define SQ_V_CMP_TRU_F16               0x0000002f
19128 #define SQ_V_CMPX_F_F16                0x00000030
19129 #define SQ_V_CMPX_LT_F16               0x00000031
19130 #define SQ_V_CMPX_EQ_F16               0x00000032
19131 #define SQ_V_CMPX_LE_F16               0x00000033
19132 #define SQ_V_CMPX_GT_F16               0x00000034
19133 #define SQ_V_CMPX_LG_F16               0x00000035
19134 #define SQ_V_CMPX_GE_F16               0x00000036
19135 #define SQ_V_CMPX_O_F16                0x00000037
19136 #define SQ_V_CMPX_U_F16                0x00000038
19137 #define SQ_V_CMPX_NGE_F16              0x00000039
19138 #define SQ_V_CMPX_NLG_F16              0x0000003a
19139 #define SQ_V_CMPX_NGT_F16              0x0000003b
19140 #define SQ_V_CMPX_NLE_F16              0x0000003c
19141 #define SQ_V_CMPX_NEQ_F16              0x0000003d
19142 #define SQ_V_CMPX_NLT_F16              0x0000003e
19143 #define SQ_V_CMPX_TRU_F16              0x0000003f
19144 #define SQ_V_CMP_F_F32                 0x00000040
19145 #define SQ_V_CMP_LT_F32                0x00000041
19146 #define SQ_V_CMP_EQ_F32                0x00000042
19147 #define SQ_V_CMP_LE_F32                0x00000043
19148 #define SQ_V_CMP_GT_F32                0x00000044
19149 #define SQ_V_CMP_LG_F32                0x00000045
19150 #define SQ_V_CMP_GE_F32                0x00000046
19151 #define SQ_V_CMP_O_F32                 0x00000047
19152 #define SQ_V_CMP_U_F32                 0x00000048
19153 #define SQ_V_CMP_NGE_F32               0x00000049
19154 #define SQ_V_CMP_NLG_F32               0x0000004a
19155 #define SQ_V_CMP_NGT_F32               0x0000004b
19156 #define SQ_V_CMP_NLE_F32               0x0000004c
19157 #define SQ_V_CMP_NEQ_F32               0x0000004d
19158 #define SQ_V_CMP_NLT_F32               0x0000004e
19159 #define SQ_V_CMP_TRU_F32               0x0000004f
19160 #define SQ_V_CMPX_F_F32                0x00000050
19161 #define SQ_V_CMPX_LT_F32               0x00000051
19162 #define SQ_V_CMPX_EQ_F32               0x00000052
19163 #define SQ_V_CMPX_LE_F32               0x00000053
19164 #define SQ_V_CMPX_GT_F32               0x00000054
19165 #define SQ_V_CMPX_LG_F32               0x00000055
19166 #define SQ_V_CMPX_GE_F32               0x00000056
19167 #define SQ_V_CMPX_O_F32                0x00000057
19168 #define SQ_V_CMPX_U_F32                0x00000058
19169 #define SQ_V_CMPX_NGE_F32              0x00000059
19170 #define SQ_V_CMPX_NLG_F32              0x0000005a
19171 #define SQ_V_CMPX_NGT_F32              0x0000005b
19172 #define SQ_V_CMPX_NLE_F32              0x0000005c
19173 #define SQ_V_CMPX_NEQ_F32              0x0000005d
19174 #define SQ_V_CMPX_NLT_F32              0x0000005e
19175 #define SQ_V_CMPX_TRU_F32              0x0000005f
19176 #define SQ_V_CMP_F_F64                 0x00000060
19177 #define SQ_V_CMP_LT_F64                0x00000061
19178 #define SQ_V_CMP_EQ_F64                0x00000062
19179 #define SQ_V_CMP_LE_F64                0x00000063
19180 #define SQ_V_CMP_GT_F64                0x00000064
19181 #define SQ_V_CMP_LG_F64                0x00000065
19182 #define SQ_V_CMP_GE_F64                0x00000066
19183 #define SQ_V_CMP_O_F64                 0x00000067
19184 #define SQ_V_CMP_U_F64                 0x00000068
19185 #define SQ_V_CMP_NGE_F64               0x00000069
19186 #define SQ_V_CMP_NLG_F64               0x0000006a
19187 #define SQ_V_CMP_NGT_F64               0x0000006b
19188 #define SQ_V_CMP_NLE_F64               0x0000006c
19189 #define SQ_V_CMP_NEQ_F64               0x0000006d
19190 #define SQ_V_CMP_NLT_F64               0x0000006e
19191 #define SQ_V_CMP_TRU_F64               0x0000006f
19192 #define SQ_V_CMPX_F_F64                0x00000070
19193 #define SQ_V_CMPX_LT_F64               0x00000071
19194 #define SQ_V_CMPX_EQ_F64               0x00000072
19195 #define SQ_V_CMPX_LE_F64               0x00000073
19196 #define SQ_V_CMPX_GT_F64               0x00000074
19197 #define SQ_V_CMPX_LG_F64               0x00000075
19198 #define SQ_V_CMPX_GE_F64               0x00000076
19199 #define SQ_V_CMPX_O_F64                0x00000077
19200 #define SQ_V_CMPX_U_F64                0x00000078
19201 #define SQ_V_CMPX_NGE_F64              0x00000079
19202 #define SQ_V_CMPX_NLG_F64              0x0000007a
19203 #define SQ_V_CMPX_NGT_F64              0x0000007b
19204 #define SQ_V_CMPX_NLE_F64              0x0000007c
19205 #define SQ_V_CMPX_NEQ_F64              0x0000007d
19206 #define SQ_V_CMPX_NLT_F64              0x0000007e
19207 #define SQ_V_CMPX_TRU_F64              0x0000007f
19208 #define SQ_V_CMP_F_I16                 0x000000a0
19209 #define SQ_V_CMP_LT_I16                0x000000a1
19210 #define SQ_V_CMP_EQ_I16                0x000000a2
19211 #define SQ_V_CMP_LE_I16                0x000000a3
19212 #define SQ_V_CMP_GT_I16                0x000000a4
19213 #define SQ_V_CMP_NE_I16                0x000000a5
19214 #define SQ_V_CMP_GE_I16                0x000000a6
19215 #define SQ_V_CMP_T_I16                 0x000000a7
19216 #define SQ_V_CMP_F_U16                 0x000000a8
19217 #define SQ_V_CMP_LT_U16                0x000000a9
19218 #define SQ_V_CMP_EQ_U16                0x000000aa
19219 #define SQ_V_CMP_LE_U16                0x000000ab
19220 #define SQ_V_CMP_GT_U16                0x000000ac
19221 #define SQ_V_CMP_NE_U16                0x000000ad
19222 #define SQ_V_CMP_GE_U16                0x000000ae
19223 #define SQ_V_CMP_T_U16                 0x000000af
19224 #define SQ_V_CMPX_F_I16                0x000000b0
19225 #define SQ_V_CMPX_LT_I16               0x000000b1
19226 #define SQ_V_CMPX_EQ_I16               0x000000b2
19227 #define SQ_V_CMPX_LE_I16               0x000000b3
19228 #define SQ_V_CMPX_GT_I16               0x000000b4
19229 #define SQ_V_CMPX_NE_I16               0x000000b5
19230 #define SQ_V_CMPX_GE_I16               0x000000b6
19231 #define SQ_V_CMPX_T_I16                0x000000b7
19232 #define SQ_V_CMPX_F_U16                0x000000b8
19233 #define SQ_V_CMPX_LT_U16               0x000000b9
19234 #define SQ_V_CMPX_EQ_U16               0x000000ba
19235 #define SQ_V_CMPX_LE_U16               0x000000bb
19236 #define SQ_V_CMPX_GT_U16               0x000000bc
19237 #define SQ_V_CMPX_NE_U16               0x000000bd
19238 #define SQ_V_CMPX_GE_U16               0x000000be
19239 #define SQ_V_CMPX_T_U16                0x000000bf
19240 #define SQ_V_CMP_F_I32                 0x000000c0
19241 #define SQ_V_CMP_LT_I32                0x000000c1
19242 #define SQ_V_CMP_EQ_I32                0x000000c2
19243 #define SQ_V_CMP_LE_I32                0x000000c3
19244 #define SQ_V_CMP_GT_I32                0x000000c4
19245 #define SQ_V_CMP_NE_I32                0x000000c5
19246 #define SQ_V_CMP_GE_I32                0x000000c6
19247 #define SQ_V_CMP_T_I32                 0x000000c7
19248 #define SQ_V_CMP_F_U32                 0x000000c8
19249 #define SQ_V_CMP_LT_U32                0x000000c9
19250 #define SQ_V_CMP_EQ_U32                0x000000ca
19251 #define SQ_V_CMP_LE_U32                0x000000cb
19252 #define SQ_V_CMP_GT_U32                0x000000cc
19253 #define SQ_V_CMP_NE_U32                0x000000cd
19254 #define SQ_V_CMP_GE_U32                0x000000ce
19255 #define SQ_V_CMP_T_U32                 0x000000cf
19256 #define SQ_V_CMPX_F_I32                0x000000d0
19257 #define SQ_V_CMPX_LT_I32               0x000000d1
19258 #define SQ_V_CMPX_EQ_I32               0x000000d2
19259 #define SQ_V_CMPX_LE_I32               0x000000d3
19260 #define SQ_V_CMPX_GT_I32               0x000000d4
19261 #define SQ_V_CMPX_NE_I32               0x000000d5
19262 #define SQ_V_CMPX_GE_I32               0x000000d6
19263 #define SQ_V_CMPX_T_I32                0x000000d7
19264 #define SQ_V_CMPX_F_U32                0x000000d8
19265 #define SQ_V_CMPX_LT_U32               0x000000d9
19266 #define SQ_V_CMPX_EQ_U32               0x000000da
19267 #define SQ_V_CMPX_LE_U32               0x000000db
19268 #define SQ_V_CMPX_GT_U32               0x000000dc
19269 #define SQ_V_CMPX_NE_U32               0x000000dd
19270 #define SQ_V_CMPX_GE_U32               0x000000de
19271 #define SQ_V_CMPX_T_U32                0x000000df
19272 #define SQ_V_CMP_F_I64                 0x000000e0
19273 #define SQ_V_CMP_LT_I64                0x000000e1
19274 #define SQ_V_CMP_EQ_I64                0x000000e2
19275 #define SQ_V_CMP_LE_I64                0x000000e3
19276 #define SQ_V_CMP_GT_I64                0x000000e4
19277 #define SQ_V_CMP_NE_I64                0x000000e5
19278 #define SQ_V_CMP_GE_I64                0x000000e6
19279 #define SQ_V_CMP_T_I64                 0x000000e7
19280 #define SQ_V_CMP_F_U64                 0x000000e8
19281 #define SQ_V_CMP_LT_U64                0x000000e9
19282 #define SQ_V_CMP_EQ_U64                0x000000ea
19283 #define SQ_V_CMP_LE_U64                0x000000eb
19284 #define SQ_V_CMP_GT_U64                0x000000ec
19285 #define SQ_V_CMP_NE_U64                0x000000ed
19286 #define SQ_V_CMP_GE_U64                0x000000ee
19287 #define SQ_V_CMP_T_U64                 0x000000ef
19288 #define SQ_V_CMPX_F_I64                0x000000f0
19289 #define SQ_V_CMPX_LT_I64               0x000000f1
19290 #define SQ_V_CMPX_EQ_I64               0x000000f2
19291 #define SQ_V_CMPX_LE_I64               0x000000f3
19292 #define SQ_V_CMPX_GT_I64               0x000000f4
19293 #define SQ_V_CMPX_NE_I64               0x000000f5
19294 #define SQ_V_CMPX_GE_I64               0x000000f6
19295 #define SQ_V_CMPX_T_I64                0x000000f7
19296 #define SQ_V_CMPX_F_U64                0x000000f8
19297 #define SQ_V_CMPX_LT_U64               0x000000f9
19298 #define SQ_V_CMPX_EQ_U64               0x000000fa
19299 #define SQ_V_CMPX_LE_U64               0x000000fb
19300 #define SQ_V_CMPX_GT_U64               0x000000fc
19301 #define SQ_V_CMPX_NE_U64               0x000000fd
19302 #define SQ_V_CMPX_GE_U64               0x000000fe
19303 #define SQ_V_CMPX_T_U64                0x000000ff
19304 
19305 /*
19306  * VALUE_SQ_GS_OP value
19307  */
19308 
19309 #define SQ_GS_OP_NOP                   0x00000000
19310 #define SQ_GS_OP_CUT                   0x00000001
19311 #define SQ_GS_OP_EMIT                  0x00000002
19312 #define SQ_GS_OP_EMIT_CUT              0x00000003
19313 
19314 /*
19315  * VALUE_SQ_SSRC_SPECIAL_LDS value
19316  */
19317 
19318 #define SQ_SRC_LDS_DIRECT              0x000000fe
19319 
19320 /*
19321  * VALUE_SQ_ATTR value
19322  */
19323 
19324 #define SQ_ATTR0                       0x00000000
19325 
19326 /*
19327  * VALUE_SQ_TGT_INTERNAL value
19328  */
19329 
19330 #define SQ_EXP_GDS0                    0x00000018
19331 
19332 /*
19333  * VALUE_SQ_OP_SOPC value
19334  */
19335 
19336 #define SQ_S_CMP_EQ_I32                0x00000000
19337 #define SQ_S_CMP_LG_I32                0x00000001
19338 #define SQ_S_CMP_GT_I32                0x00000002
19339 #define SQ_S_CMP_GE_I32                0x00000003
19340 #define SQ_S_CMP_LT_I32                0x00000004
19341 #define SQ_S_CMP_LE_I32                0x00000005
19342 #define SQ_S_CMP_EQ_U32                0x00000006
19343 #define SQ_S_CMP_LG_U32                0x00000007
19344 #define SQ_S_CMP_GT_U32                0x00000008
19345 #define SQ_S_CMP_GE_U32                0x00000009
19346 #define SQ_S_CMP_LT_U32                0x0000000a
19347 #define SQ_S_CMP_LE_U32                0x0000000b
19348 #define SQ_S_BITCMP0_B32               0x0000000c
19349 #define SQ_S_BITCMP1_B32               0x0000000d
19350 #define SQ_S_BITCMP0_B64               0x0000000e
19351 #define SQ_S_BITCMP1_B64               0x0000000f
19352 #define SQ_S_SETVSKIP                  0x00000010
19353 #define SQ_S_SET_GPR_IDX_ON            0x00000011
19354 #define SQ_S_CMP_EQ_U64                0x00000012
19355 #define SQ_S_CMP_LG_U64                0x00000013
19356 
19357 /*
19358  * VALUE_SQ_TRAP value
19359  */
19360 
19361 #define SQ_TTMP0                       0x0000006c
19362 #define SQ_TTMP1                       0x0000006d
19363 #define SQ_TTMP2                       0x0000006e
19364 #define SQ_TTMP3                       0x0000006f
19365 #define SQ_TTMP4                       0x00000070
19366 #define SQ_TTMP5                       0x00000071
19367 #define SQ_TTMP6                       0x00000072
19368 #define SQ_TTMP7                       0x00000073
19369 #define SQ_TTMP8                       0x00000074
19370 #define SQ_TTMP9                       0x00000075
19371 #define SQ_TTMP10                      0x00000076
19372 #define SQ_TTMP11                      0x00000077
19373 #define SQ_TTMP12                      0x00000078
19374 #define SQ_TTMP13                      0x00000079
19375 #define SQ_TTMP14                      0x0000007a
19376 #define SQ_TTMP15                      0x0000007b
19377 
19378 /*
19379  * VALUE_SQ_SRC_VGPR value
19380  */
19381 
19382 #define SQ_SRC_VGPR0                   0x00000100
19383 
19384 /*
19385  * VALUE_SQ_OP_MUBUF value
19386  */
19387 
19388 #define SQ_BUFFER_LOAD_FORMAT_X        0x00000000
19389 #define SQ_BUFFER_LOAD_FORMAT_XY       0x00000001
19390 #define SQ_BUFFER_LOAD_FORMAT_XYZ      0x00000002
19391 #define SQ_BUFFER_LOAD_FORMAT_XYZW     0x00000003
19392 #define SQ_BUFFER_STORE_FORMAT_X       0x00000004
19393 #define SQ_BUFFER_STORE_FORMAT_XY      0x00000005
19394 #define SQ_BUFFER_STORE_FORMAT_XYZ     0x00000006
19395 #define SQ_BUFFER_STORE_FORMAT_XYZW    0x00000007
19396 #define SQ_BUFFER_LOAD_FORMAT_D16_X    0x00000008
19397 #define SQ_BUFFER_LOAD_FORMAT_D16_XY   0x00000009
19398 #define SQ_BUFFER_LOAD_FORMAT_D16_XYZ  0x0000000a
19399 #define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
19400 #define SQ_BUFFER_STORE_FORMAT_D16_X   0x0000000c
19401 #define SQ_BUFFER_STORE_FORMAT_D16_XY  0x0000000d
19402 #define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
19403 #define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
19404 #define SQ_BUFFER_LOAD_UBYTE           0x00000010
19405 #define SQ_BUFFER_LOAD_SBYTE           0x00000011
19406 #define SQ_BUFFER_LOAD_USHORT          0x00000012
19407 #define SQ_BUFFER_LOAD_SSHORT          0x00000013
19408 #define SQ_BUFFER_LOAD_DWORD           0x00000014
19409 #define SQ_BUFFER_LOAD_DWORDX2         0x00000015
19410 #define SQ_BUFFER_LOAD_DWORDX3         0x00000016
19411 #define SQ_BUFFER_LOAD_DWORDX4         0x00000017
19412 #define SQ_BUFFER_STORE_BYTE           0x00000018
19413 #define SQ_BUFFER_STORE_SHORT          0x0000001a
19414 #define SQ_BUFFER_STORE_DWORD          0x0000001c
19415 #define SQ_BUFFER_STORE_DWORDX2        0x0000001d
19416 #define SQ_BUFFER_STORE_DWORDX3        0x0000001e
19417 #define SQ_BUFFER_STORE_DWORDX4        0x0000001f
19418 #define SQ_BUFFER_STORE_LDS_DWORD      0x0000003d
19419 #define SQ_BUFFER_WBINVL1              0x0000003e
19420 #define SQ_BUFFER_WBINVL1_VOL          0x0000003f
19421 #define SQ_BUFFER_ATOMIC_SWAP          0x00000040
19422 #define SQ_BUFFER_ATOMIC_CMPSWAP       0x00000041
19423 #define SQ_BUFFER_ATOMIC_ADD           0x00000042
19424 #define SQ_BUFFER_ATOMIC_SUB           0x00000043
19425 #define SQ_BUFFER_ATOMIC_SMIN          0x00000044
19426 #define SQ_BUFFER_ATOMIC_UMIN          0x00000045
19427 #define SQ_BUFFER_ATOMIC_SMAX          0x00000046
19428 #define SQ_BUFFER_ATOMIC_UMAX          0x00000047
19429 #define SQ_BUFFER_ATOMIC_AND           0x00000048
19430 #define SQ_BUFFER_ATOMIC_OR            0x00000049
19431 #define SQ_BUFFER_ATOMIC_XOR           0x0000004a
19432 #define SQ_BUFFER_ATOMIC_INC           0x0000004b
19433 #define SQ_BUFFER_ATOMIC_DEC           0x0000004c
19434 #define SQ_BUFFER_ATOMIC_SWAP_X2       0x00000060
19435 #define SQ_BUFFER_ATOMIC_CMPSWAP_X2    0x00000061
19436 #define SQ_BUFFER_ATOMIC_ADD_X2        0x00000062
19437 #define SQ_BUFFER_ATOMIC_SUB_X2        0x00000063
19438 #define SQ_BUFFER_ATOMIC_SMIN_X2       0x00000064
19439 #define SQ_BUFFER_ATOMIC_UMIN_X2       0x00000065
19440 #define SQ_BUFFER_ATOMIC_SMAX_X2       0x00000066
19441 #define SQ_BUFFER_ATOMIC_UMAX_X2       0x00000067
19442 #define SQ_BUFFER_ATOMIC_AND_X2        0x00000068
19443 #define SQ_BUFFER_ATOMIC_OR_X2         0x00000069
19444 #define SQ_BUFFER_ATOMIC_XOR_X2        0x0000006a
19445 #define SQ_BUFFER_ATOMIC_INC_X2        0x0000006b
19446 #define SQ_BUFFER_ATOMIC_DEC_X2        0x0000006c
19447 
19448 /*
19449  * VALUE_SQ_SDWA_SEL value
19450  */
19451 
19452 #define SQ_SDWA_BYTE_0                 0x00000000
19453 #define SQ_SDWA_BYTE_1                 0x00000001
19454 #define SQ_SDWA_BYTE_2                 0x00000002
19455 #define SQ_SDWA_BYTE_3                 0x00000003
19456 #define SQ_SDWA_WORD_0                 0x00000004
19457 #define SQ_SDWA_WORD_1                 0x00000005
19458 #define SQ_SDWA_DWORD                  0x00000006
19459 
19460 /*******************************************************
19461  * SX Enums
19462  *******************************************************/
19463 
19464 /*
19465  * SX_BLEND_OPT enum
19466  */
19467 
19468 typedef enum SX_BLEND_OPT {
19469 BLEND_OPT_PRESERVE_NONE_IGNORE_ALL       = 0x00000000,
19470 BLEND_OPT_PRESERVE_ALL_IGNORE_NONE       = 0x00000001,
19471 BLEND_OPT_PRESERVE_C1_IGNORE_C0          = 0x00000002,
19472 BLEND_OPT_PRESERVE_C0_IGNORE_C1          = 0x00000003,
19473 BLEND_OPT_PRESERVE_A1_IGNORE_A0          = 0x00000004,
19474 BLEND_OPT_PRESERVE_A0_IGNORE_A1          = 0x00000005,
19475 BLEND_OPT_PRESERVE_NONE_IGNORE_A0        = 0x00000006,
19476 BLEND_OPT_PRESERVE_NONE_IGNORE_NONE      = 0x00000007,
19477 } SX_BLEND_OPT;
19478 
19479 /*
19480  * SX_OPT_COMB_FCN enum
19481  */
19482 
19483 typedef enum SX_OPT_COMB_FCN {
19484 OPT_COMB_NONE                            = 0x00000000,
19485 OPT_COMB_ADD                             = 0x00000001,
19486 OPT_COMB_SUBTRACT                        = 0x00000002,
19487 OPT_COMB_MIN                             = 0x00000003,
19488 OPT_COMB_MAX                             = 0x00000004,
19489 OPT_COMB_REVSUBTRACT                     = 0x00000005,
19490 OPT_COMB_BLEND_DISABLED                  = 0x00000006,
19491 OPT_COMB_SAFE_ADD                        = 0x00000007,
19492 } SX_OPT_COMB_FCN;
19493 
19494 /*
19495  * SX_DOWNCONVERT_FORMAT enum
19496  */
19497 
19498 typedef enum SX_DOWNCONVERT_FORMAT {
19499 SX_RT_EXPORT_NO_CONVERSION               = 0x00000000,
19500 SX_RT_EXPORT_32_R                        = 0x00000001,
19501 SX_RT_EXPORT_32_A                        = 0x00000002,
19502 SX_RT_EXPORT_10_11_11                    = 0x00000003,
19503 SX_RT_EXPORT_2_10_10_10                  = 0x00000004,
19504 SX_RT_EXPORT_8_8_8_8                     = 0x00000005,
19505 SX_RT_EXPORT_5_6_5                       = 0x00000006,
19506 SX_RT_EXPORT_1_5_5_5                     = 0x00000007,
19507 SX_RT_EXPORT_4_4_4_4                     = 0x00000008,
19508 SX_RT_EXPORT_16_16_GR                    = 0x00000009,
19509 SX_RT_EXPORT_16_16_AR                    = 0x0000000a,
19510 } SX_DOWNCONVERT_FORMAT;
19511 
19512 /*
19513  * SX_PERFCOUNTER_VALS enum
19514  */
19515 
19516 typedef enum SX_PERFCOUNTER_VALS {
19517 SX_PERF_SEL_PA_IDLE_CYCLES               = 0x00000000,
19518 SX_PERF_SEL_PA_REQ                       = 0x00000001,
19519 SX_PERF_SEL_PA_POS                       = 0x00000002,
19520 SX_PERF_SEL_CLOCK                        = 0x00000003,
19521 SX_PERF_SEL_GATE_EN1                     = 0x00000004,
19522 SX_PERF_SEL_GATE_EN2                     = 0x00000005,
19523 SX_PERF_SEL_GATE_EN3                     = 0x00000006,
19524 SX_PERF_SEL_GATE_EN4                     = 0x00000007,
19525 SX_PERF_SEL_SH_POS_STARVE                = 0x00000008,
19526 SX_PERF_SEL_SH_COLOR_STARVE              = 0x00000009,
19527 SX_PERF_SEL_SH_POS_STALL                 = 0x0000000a,
19528 SX_PERF_SEL_SH_COLOR_STALL               = 0x0000000b,
19529 SX_PERF_SEL_DB0_PIXELS                   = 0x0000000c,
19530 SX_PERF_SEL_DB0_HALF_QUADS               = 0x0000000d,
19531 SX_PERF_SEL_DB0_PIXEL_STALL              = 0x0000000e,
19532 SX_PERF_SEL_DB0_PIXEL_IDLE               = 0x0000000f,
19533 SX_PERF_SEL_DB0_PRED_PIXELS              = 0x00000010,
19534 SX_PERF_SEL_DB1_PIXELS                   = 0x00000011,
19535 SX_PERF_SEL_DB1_HALF_QUADS               = 0x00000012,
19536 SX_PERF_SEL_DB1_PIXEL_STALL              = 0x00000013,
19537 SX_PERF_SEL_DB1_PIXEL_IDLE               = 0x00000014,
19538 SX_PERF_SEL_DB1_PRED_PIXELS              = 0x00000015,
19539 SX_PERF_SEL_DB2_PIXELS                   = 0x00000016,
19540 SX_PERF_SEL_DB2_HALF_QUADS               = 0x00000017,
19541 SX_PERF_SEL_DB2_PIXEL_STALL              = 0x00000018,
19542 SX_PERF_SEL_DB2_PIXEL_IDLE               = 0x00000019,
19543 SX_PERF_SEL_DB2_PRED_PIXELS              = 0x0000001a,
19544 SX_PERF_SEL_DB3_PIXELS                   = 0x0000001b,
19545 SX_PERF_SEL_DB3_HALF_QUADS               = 0x0000001c,
19546 SX_PERF_SEL_DB3_PIXEL_STALL              = 0x0000001d,
19547 SX_PERF_SEL_DB3_PIXEL_IDLE               = 0x0000001e,
19548 SX_PERF_SEL_DB3_PRED_PIXELS              = 0x0000001f,
19549 SX_PERF_SEL_COL_BUSY                     = 0x00000020,
19550 SX_PERF_SEL_POS_BUSY                     = 0x00000021,
19551 SX_PERF_SEL_DB0_A2M_DISCARD_QUADS        = 0x00000022,
19552 SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS        = 0x00000023,
19553 SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST        = 0x00000024,
19554 SX_PERF_SEL_DB0_MRT0_DISCARD_SRC         = 0x00000025,
19555 SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS        = 0x00000026,
19556 SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS        = 0x00000027,
19557 SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS        = 0x00000028,
19558 SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST        = 0x00000029,
19559 SX_PERF_SEL_DB0_MRT1_DISCARD_SRC         = 0x0000002a,
19560 SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS        = 0x0000002b,
19561 SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS        = 0x0000002c,
19562 SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS        = 0x0000002d,
19563 SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST        = 0x0000002e,
19564 SX_PERF_SEL_DB0_MRT2_DISCARD_SRC         = 0x0000002f,
19565 SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS        = 0x00000030,
19566 SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS        = 0x00000031,
19567 SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS        = 0x00000032,
19568 SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST        = 0x00000033,
19569 SX_PERF_SEL_DB0_MRT3_DISCARD_SRC         = 0x00000034,
19570 SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS        = 0x00000035,
19571 SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS        = 0x00000036,
19572 SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS        = 0x00000037,
19573 SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST        = 0x00000038,
19574 SX_PERF_SEL_DB0_MRT4_DISCARD_SRC         = 0x00000039,
19575 SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS        = 0x0000003a,
19576 SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS        = 0x0000003b,
19577 SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS        = 0x0000003c,
19578 SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST        = 0x0000003d,
19579 SX_PERF_SEL_DB0_MRT5_DISCARD_SRC         = 0x0000003e,
19580 SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS        = 0x0000003f,
19581 SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS        = 0x00000040,
19582 SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS        = 0x00000041,
19583 SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST        = 0x00000042,
19584 SX_PERF_SEL_DB0_MRT6_DISCARD_SRC         = 0x00000043,
19585 SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS        = 0x00000044,
19586 SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS        = 0x00000045,
19587 SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS        = 0x00000046,
19588 SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST        = 0x00000047,
19589 SX_PERF_SEL_DB0_MRT7_DISCARD_SRC         = 0x00000048,
19590 SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS        = 0x00000049,
19591 SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS        = 0x0000004a,
19592 SX_PERF_SEL_DB1_A2M_DISCARD_QUADS        = 0x0000004b,
19593 SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS        = 0x0000004c,
19594 SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST        = 0x0000004d,
19595 SX_PERF_SEL_DB1_MRT0_DISCARD_SRC         = 0x0000004e,
19596 SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS        = 0x0000004f,
19597 SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS        = 0x00000050,
19598 SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS        = 0x00000051,
19599 SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST        = 0x00000052,
19600 SX_PERF_SEL_DB1_MRT1_DISCARD_SRC         = 0x00000053,
19601 SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS        = 0x00000054,
19602 SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS        = 0x00000055,
19603 SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS        = 0x00000056,
19604 SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST        = 0x00000057,
19605 SX_PERF_SEL_DB1_MRT2_DISCARD_SRC         = 0x00000058,
19606 SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS        = 0x00000059,
19607 SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS        = 0x0000005a,
19608 SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS        = 0x0000005b,
19609 SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST        = 0x0000005c,
19610 SX_PERF_SEL_DB1_MRT3_DISCARD_SRC         = 0x0000005d,
19611 SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS        = 0x0000005e,
19612 SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS        = 0x0000005f,
19613 SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS        = 0x00000060,
19614 SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST        = 0x00000061,
19615 SX_PERF_SEL_DB1_MRT4_DISCARD_SRC         = 0x00000062,
19616 SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS        = 0x00000063,
19617 SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS        = 0x00000064,
19618 SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS        = 0x00000065,
19619 SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST        = 0x00000066,
19620 SX_PERF_SEL_DB1_MRT5_DISCARD_SRC         = 0x00000067,
19621 SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS        = 0x00000068,
19622 SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS        = 0x00000069,
19623 SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS        = 0x0000006a,
19624 SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST        = 0x0000006b,
19625 SX_PERF_SEL_DB1_MRT6_DISCARD_SRC         = 0x0000006c,
19626 SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS        = 0x0000006d,
19627 SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS        = 0x0000006e,
19628 SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS        = 0x0000006f,
19629 SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST        = 0x00000070,
19630 SX_PERF_SEL_DB1_MRT7_DISCARD_SRC         = 0x00000071,
19631 SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS        = 0x00000072,
19632 SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS        = 0x00000073,
19633 SX_PERF_SEL_DB2_A2M_DISCARD_QUADS        = 0x00000074,
19634 SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS        = 0x00000075,
19635 SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST        = 0x00000076,
19636 SX_PERF_SEL_DB2_MRT0_DISCARD_SRC         = 0x00000077,
19637 SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS        = 0x00000078,
19638 SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS        = 0x00000079,
19639 SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS        = 0x0000007a,
19640 SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST        = 0x0000007b,
19641 SX_PERF_SEL_DB2_MRT1_DISCARD_SRC         = 0x0000007c,
19642 SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS        = 0x0000007d,
19643 SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS        = 0x0000007e,
19644 SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS        = 0x0000007f,
19645 SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST        = 0x00000080,
19646 SX_PERF_SEL_DB2_MRT2_DISCARD_SRC         = 0x00000081,
19647 SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS        = 0x00000082,
19648 SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS        = 0x00000083,
19649 SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS        = 0x00000084,
19650 SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST        = 0x00000085,
19651 SX_PERF_SEL_DB2_MRT3_DISCARD_SRC         = 0x00000086,
19652 SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS        = 0x00000087,
19653 SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS        = 0x00000088,
19654 SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS        = 0x00000089,
19655 SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST        = 0x0000008a,
19656 SX_PERF_SEL_DB2_MRT4_DISCARD_SRC         = 0x0000008b,
19657 SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS        = 0x0000008c,
19658 SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS        = 0x0000008d,
19659 SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS        = 0x0000008e,
19660 SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST        = 0x0000008f,
19661 SX_PERF_SEL_DB2_MRT5_DISCARD_SRC         = 0x00000090,
19662 SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS        = 0x00000091,
19663 SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS        = 0x00000092,
19664 SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS        = 0x00000093,
19665 SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST        = 0x00000094,
19666 SX_PERF_SEL_DB2_MRT6_DISCARD_SRC         = 0x00000095,
19667 SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS        = 0x00000096,
19668 SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS        = 0x00000097,
19669 SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS        = 0x00000098,
19670 SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST        = 0x00000099,
19671 SX_PERF_SEL_DB2_MRT7_DISCARD_SRC         = 0x0000009a,
19672 SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS        = 0x0000009b,
19673 SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS        = 0x0000009c,
19674 SX_PERF_SEL_DB3_A2M_DISCARD_QUADS        = 0x0000009d,
19675 SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS        = 0x0000009e,
19676 SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST        = 0x0000009f,
19677 SX_PERF_SEL_DB3_MRT0_DISCARD_SRC         = 0x000000a0,
19678 SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS        = 0x000000a1,
19679 SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS        = 0x000000a2,
19680 SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS        = 0x000000a3,
19681 SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST        = 0x000000a4,
19682 SX_PERF_SEL_DB3_MRT1_DISCARD_SRC         = 0x000000a5,
19683 SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS        = 0x000000a6,
19684 SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS        = 0x000000a7,
19685 SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS        = 0x000000a8,
19686 SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST        = 0x000000a9,
19687 SX_PERF_SEL_DB3_MRT2_DISCARD_SRC         = 0x000000aa,
19688 SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS        = 0x000000ab,
19689 SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS        = 0x000000ac,
19690 SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS        = 0x000000ad,
19691 SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST        = 0x000000ae,
19692 SX_PERF_SEL_DB3_MRT3_DISCARD_SRC         = 0x000000af,
19693 SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS        = 0x000000b0,
19694 SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS        = 0x000000b1,
19695 SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS        = 0x000000b2,
19696 SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST        = 0x000000b3,
19697 SX_PERF_SEL_DB3_MRT4_DISCARD_SRC         = 0x000000b4,
19698 SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS        = 0x000000b5,
19699 SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS        = 0x000000b6,
19700 SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS        = 0x000000b7,
19701 SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST        = 0x000000b8,
19702 SX_PERF_SEL_DB3_MRT5_DISCARD_SRC         = 0x000000b9,
19703 SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS        = 0x000000ba,
19704 SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS        = 0x000000bb,
19705 SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS        = 0x000000bc,
19706 SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST        = 0x000000bd,
19707 SX_PERF_SEL_DB3_MRT6_DISCARD_SRC         = 0x000000be,
19708 SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS        = 0x000000bf,
19709 SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS        = 0x000000c0,
19710 SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS        = 0x000000c1,
19711 SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST        = 0x000000c2,
19712 SX_PERF_SEL_DB3_MRT7_DISCARD_SRC         = 0x000000c3,
19713 SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS        = 0x000000c4,
19714 SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS        = 0x000000c5,
19715 } SX_PERFCOUNTER_VALS;
19716 
19717 /*******************************************************
19718  * DB Enums
19719  *******************************************************/
19720 
19721 /*
19722  * ForceControl enum
19723  */
19724 
19725 typedef enum ForceControl {
19726 FORCE_OFF                                = 0x00000000,
19727 FORCE_ENABLE                             = 0x00000001,
19728 FORCE_DISABLE                            = 0x00000002,
19729 FORCE_RESERVED                           = 0x00000003,
19730 } ForceControl;
19731 
19732 /*
19733  * ZSamplePosition enum
19734  */
19735 
19736 typedef enum ZSamplePosition {
19737 Z_SAMPLE_CENTER                          = 0x00000000,
19738 Z_SAMPLE_CENTROID                        = 0x00000001,
19739 } ZSamplePosition;
19740 
19741 /*
19742  * ZOrder enum
19743  */
19744 
19745 typedef enum ZOrder {
19746 LATE_Z                                   = 0x00000000,
19747 EARLY_Z_THEN_LATE_Z                      = 0x00000001,
19748 RE_Z                                     = 0x00000002,
19749 EARLY_Z_THEN_RE_Z                        = 0x00000003,
19750 } ZOrder;
19751 
19752 /*
19753  * ZpassControl enum
19754  */
19755 
19756 typedef enum ZpassControl {
19757 ZPASS_DISABLE                            = 0x00000000,
19758 ZPASS_SAMPLES                            = 0x00000001,
19759 ZPASS_PIXELS                             = 0x00000002,
19760 } ZpassControl;
19761 
19762 /*
19763  * ZModeForce enum
19764  */
19765 
19766 typedef enum ZModeForce {
19767 NO_FORCE                                 = 0x00000000,
19768 FORCE_EARLY_Z                            = 0x00000001,
19769 FORCE_LATE_Z                             = 0x00000002,
19770 FORCE_RE_Z                               = 0x00000003,
19771 } ZModeForce;
19772 
19773 /*
19774  * ZLimitSumm enum
19775  */
19776 
19777 typedef enum ZLimitSumm {
19778 FORCE_SUMM_OFF                           = 0x00000000,
19779 FORCE_SUMM_MINZ                          = 0x00000001,
19780 FORCE_SUMM_MAXZ                          = 0x00000002,
19781 FORCE_SUMM_BOTH                          = 0x00000003,
19782 } ZLimitSumm;
19783 
19784 /*
19785  * CompareFrag enum
19786  */
19787 
19788 typedef enum CompareFrag {
19789 FRAG_NEVER                               = 0x00000000,
19790 FRAG_LESS                                = 0x00000001,
19791 FRAG_EQUAL                               = 0x00000002,
19792 FRAG_LEQUAL                              = 0x00000003,
19793 FRAG_GREATER                             = 0x00000004,
19794 FRAG_NOTEQUAL                            = 0x00000005,
19795 FRAG_GEQUAL                              = 0x00000006,
19796 FRAG_ALWAYS                              = 0x00000007,
19797 } CompareFrag;
19798 
19799 /*
19800  * StencilOp enum
19801  */
19802 
19803 typedef enum StencilOp {
19804 STENCIL_KEEP                             = 0x00000000,
19805 STENCIL_ZERO                             = 0x00000001,
19806 STENCIL_ONES                             = 0x00000002,
19807 STENCIL_REPLACE_TEST                     = 0x00000003,
19808 STENCIL_REPLACE_OP                       = 0x00000004,
19809 STENCIL_ADD_CLAMP                        = 0x00000005,
19810 STENCIL_SUB_CLAMP                        = 0x00000006,
19811 STENCIL_INVERT                           = 0x00000007,
19812 STENCIL_ADD_WRAP                         = 0x00000008,
19813 STENCIL_SUB_WRAP                         = 0x00000009,
19814 STENCIL_AND                              = 0x0000000a,
19815 STENCIL_OR                               = 0x0000000b,
19816 STENCIL_XOR                              = 0x0000000c,
19817 STENCIL_NAND                             = 0x0000000d,
19818 STENCIL_NOR                              = 0x0000000e,
19819 STENCIL_XNOR                             = 0x0000000f,
19820 } StencilOp;
19821 
19822 /*
19823  * ConservativeZExport enum
19824  */
19825 
19826 typedef enum ConservativeZExport {
19827 EXPORT_ANY_Z                             = 0x00000000,
19828 EXPORT_LESS_THAN_Z                       = 0x00000001,
19829 EXPORT_GREATER_THAN_Z                    = 0x00000002,
19830 EXPORT_RESERVED                          = 0x00000003,
19831 } ConservativeZExport;
19832 
19833 /*
19834  * DbPSLControl enum
19835  */
19836 
19837 typedef enum DbPSLControl {
19838 PSLC_AUTO                                = 0x00000000,
19839 PSLC_ON_HANG_ONLY                        = 0x00000001,
19840 PSLC_ASAP                                = 0x00000002,
19841 PSLC_COUNTDOWN                           = 0x00000003,
19842 } DbPSLControl;
19843 
19844 /*
19845  * DbPRTFaultBehavior enum
19846  */
19847 
19848 typedef enum DbPRTFaultBehavior {
19849 FAULT_ZERO                               = 0x00000000,
19850 FAULT_ONE                                = 0x00000001,
19851 FAULT_FAIL                               = 0x00000002,
19852 FAULT_PASS                               = 0x00000003,
19853 } DbPRTFaultBehavior;
19854 
19855 /*
19856  * PerfCounter_Vals enum
19857  */
19858 
19859 typedef enum PerfCounter_Vals {
19860 DB_PERF_SEL_SC_DB_tile_sends             = 0x00000000,
19861 DB_PERF_SEL_SC_DB_tile_busy              = 0x00000001,
19862 DB_PERF_SEL_SC_DB_tile_stalls            = 0x00000002,
19863 DB_PERF_SEL_SC_DB_tile_events            = 0x00000003,
19864 DB_PERF_SEL_SC_DB_tile_tiles             = 0x00000004,
19865 DB_PERF_SEL_SC_DB_tile_covered           = 0x00000005,
19866 DB_PERF_SEL_hiz_tc_read_starved          = 0x00000006,
19867 DB_PERF_SEL_hiz_tc_write_stall           = 0x00000007,
19868 DB_PERF_SEL_hiz_qtiles_culled            = 0x00000008,
19869 DB_PERF_SEL_his_qtiles_culled            = 0x00000009,
19870 DB_PERF_SEL_DB_SC_tile_sends             = 0x0000000a,
19871 DB_PERF_SEL_DB_SC_tile_busy              = 0x0000000b,
19872 DB_PERF_SEL_DB_SC_tile_stalls            = 0x0000000c,
19873 DB_PERF_SEL_DB_SC_tile_df_stalls         = 0x0000000d,
19874 DB_PERF_SEL_DB_SC_tile_tiles             = 0x0000000e,
19875 DB_PERF_SEL_DB_SC_tile_culled            = 0x0000000f,
19876 DB_PERF_SEL_DB_SC_tile_hier_kill         = 0x00000010,
19877 DB_PERF_SEL_DB_SC_tile_fast_ops          = 0x00000011,
19878 DB_PERF_SEL_DB_SC_tile_no_ops            = 0x00000012,
19879 DB_PERF_SEL_DB_SC_tile_tile_rate         = 0x00000013,
19880 DB_PERF_SEL_DB_SC_tile_ssaa_kill         = 0x00000014,
19881 DB_PERF_SEL_DB_SC_tile_fast_z_ops        = 0x00000015,
19882 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops  = 0x00000016,
19883 DB_PERF_SEL_SC_DB_quad_sends             = 0x00000017,
19884 DB_PERF_SEL_SC_DB_quad_busy              = 0x00000018,
19885 DB_PERF_SEL_SC_DB_quad_squads            = 0x00000019,
19886 DB_PERF_SEL_SC_DB_quad_tiles             = 0x0000001a,
19887 DB_PERF_SEL_SC_DB_quad_pixels            = 0x0000001b,
19888 DB_PERF_SEL_SC_DB_quad_killed_tiles      = 0x0000001c,
19889 DB_PERF_SEL_DB_SC_quad_sends             = 0x0000001d,
19890 DB_PERF_SEL_DB_SC_quad_busy              = 0x0000001e,
19891 DB_PERF_SEL_DB_SC_quad_stalls            = 0x0000001f,
19892 DB_PERF_SEL_DB_SC_quad_tiles             = 0x00000020,
19893 DB_PERF_SEL_DB_SC_quad_lit_quad          = 0x00000021,
19894 DB_PERF_SEL_DB_CB_tile_sends             = 0x00000022,
19895 DB_PERF_SEL_DB_CB_tile_busy              = 0x00000023,
19896 DB_PERF_SEL_DB_CB_tile_stalls            = 0x00000024,
19897 DB_PERF_SEL_SX_DB_quad_sends             = 0x00000025,
19898 DB_PERF_SEL_SX_DB_quad_busy              = 0x00000026,
19899 DB_PERF_SEL_SX_DB_quad_stalls            = 0x00000027,
19900 DB_PERF_SEL_SX_DB_quad_quads             = 0x00000028,
19901 DB_PERF_SEL_SX_DB_quad_pixels            = 0x00000029,
19902 DB_PERF_SEL_SX_DB_quad_exports           = 0x0000002a,
19903 DB_PERF_SEL_SH_quads_outstanding_sum     = 0x0000002b,
19904 DB_PERF_SEL_DB_CB_lquad_sends            = 0x0000002c,
19905 DB_PERF_SEL_DB_CB_lquad_busy             = 0x0000002d,
19906 DB_PERF_SEL_DB_CB_lquad_stalls           = 0x0000002e,
19907 DB_PERF_SEL_DB_CB_lquad_quads            = 0x0000002f,
19908 DB_PERF_SEL_tile_rd_sends                = 0x00000030,
19909 DB_PERF_SEL_mi_tile_rd_outstanding_sum   = 0x00000031,
19910 DB_PERF_SEL_quad_rd_sends                = 0x00000032,
19911 DB_PERF_SEL_quad_rd_busy                 = 0x00000033,
19912 DB_PERF_SEL_quad_rd_mi_stall             = 0x00000034,
19913 DB_PERF_SEL_quad_rd_rw_collision         = 0x00000035,
19914 DB_PERF_SEL_quad_rd_tag_stall            = 0x00000036,
19915 DB_PERF_SEL_quad_rd_32byte_reqs          = 0x00000037,
19916 DB_PERF_SEL_quad_rd_panic                = 0x00000038,
19917 DB_PERF_SEL_mi_quad_rd_outstanding_sum   = 0x00000039,
19918 DB_PERF_SEL_quad_rdret_sends             = 0x0000003a,
19919 DB_PERF_SEL_quad_rdret_busy              = 0x0000003b,
19920 DB_PERF_SEL_tile_wr_sends                = 0x0000003c,
19921 DB_PERF_SEL_tile_wr_acks                 = 0x0000003d,
19922 DB_PERF_SEL_mi_tile_wr_outstanding_sum   = 0x0000003e,
19923 DB_PERF_SEL_quad_wr_sends                = 0x0000003f,
19924 DB_PERF_SEL_quad_wr_busy                 = 0x00000040,
19925 DB_PERF_SEL_quad_wr_mi_stall             = 0x00000041,
19926 DB_PERF_SEL_quad_wr_coherency_stall      = 0x00000042,
19927 DB_PERF_SEL_quad_wr_acks                 = 0x00000043,
19928 DB_PERF_SEL_mi_quad_wr_outstanding_sum   = 0x00000044,
19929 DB_PERF_SEL_Tile_Cache_misses            = 0x00000045,
19930 DB_PERF_SEL_Tile_Cache_hits              = 0x00000046,
19931 DB_PERF_SEL_Tile_Cache_flushes           = 0x00000047,
19932 DB_PERF_SEL_Tile_Cache_surface_stall     = 0x00000048,
19933 DB_PERF_SEL_Tile_Cache_starves           = 0x00000049,
19934 DB_PERF_SEL_Tile_Cache_mem_return_starve  = 0x0000004a,
19935 DB_PERF_SEL_tcp_dispatcher_reads         = 0x0000004b,
19936 DB_PERF_SEL_tcp_prefetcher_reads         = 0x0000004c,
19937 DB_PERF_SEL_tcp_preloader_reads          = 0x0000004d,
19938 DB_PERF_SEL_tcp_dispatcher_flushes       = 0x0000004e,
19939 DB_PERF_SEL_tcp_prefetcher_flushes       = 0x0000004f,
19940 DB_PERF_SEL_tcp_preloader_flushes        = 0x00000050,
19941 DB_PERF_SEL_Depth_Tile_Cache_sends       = 0x00000051,
19942 DB_PERF_SEL_Depth_Tile_Cache_busy        = 0x00000052,
19943 DB_PERF_SEL_Depth_Tile_Cache_starves     = 0x00000053,
19944 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked  = 0x00000054,
19945 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall  = 0x00000055,
19946 DB_PERF_SEL_Depth_Tile_Cache_misses      = 0x00000056,
19947 DB_PERF_SEL_Depth_Tile_Cache_hits        = 0x00000057,
19948 DB_PERF_SEL_Depth_Tile_Cache_flushes     = 0x00000058,
19949 DB_PERF_SEL_Depth_Tile_Cache_noop_tile   = 0x00000059,
19950 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop  = 0x0000005a,
19951 DB_PERF_SEL_Depth_Tile_Cache_event       = 0x0000005b,
19952 DB_PERF_SEL_Depth_Tile_Cache_tile_frees  = 0x0000005c,
19953 DB_PERF_SEL_Depth_Tile_Cache_data_frees  = 0x0000005d,
19954 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve  = 0x0000005e,
19955 DB_PERF_SEL_Stencil_Cache_misses         = 0x0000005f,
19956 DB_PERF_SEL_Stencil_Cache_hits           = 0x00000060,
19957 DB_PERF_SEL_Stencil_Cache_flushes        = 0x00000061,
19958 DB_PERF_SEL_Stencil_Cache_starves        = 0x00000062,
19959 DB_PERF_SEL_Stencil_Cache_frees          = 0x00000063,
19960 DB_PERF_SEL_Z_Cache_separate_Z_misses    = 0x00000064,
19961 DB_PERF_SEL_Z_Cache_separate_Z_hits      = 0x00000065,
19962 DB_PERF_SEL_Z_Cache_separate_Z_flushes   = 0x00000066,
19963 DB_PERF_SEL_Z_Cache_separate_Z_starves   = 0x00000067,
19964 DB_PERF_SEL_Z_Cache_pmask_misses         = 0x00000068,
19965 DB_PERF_SEL_Z_Cache_pmask_hits           = 0x00000069,
19966 DB_PERF_SEL_Z_Cache_pmask_flushes        = 0x0000006a,
19967 DB_PERF_SEL_Z_Cache_pmask_starves        = 0x0000006b,
19968 DB_PERF_SEL_Z_Cache_frees                = 0x0000006c,
19969 DB_PERF_SEL_Plane_Cache_misses           = 0x0000006d,
19970 DB_PERF_SEL_Plane_Cache_hits             = 0x0000006e,
19971 DB_PERF_SEL_Plane_Cache_flushes          = 0x0000006f,
19972 DB_PERF_SEL_Plane_Cache_starves          = 0x00000070,
19973 DB_PERF_SEL_Plane_Cache_frees            = 0x00000071,
19974 DB_PERF_SEL_flush_expanded_stencil       = 0x00000072,
19975 DB_PERF_SEL_flush_compressed_stencil     = 0x00000073,
19976 DB_PERF_SEL_flush_single_stencil         = 0x00000074,
19977 DB_PERF_SEL_planes_flushed               = 0x00000075,
19978 DB_PERF_SEL_flush_1plane                 = 0x00000076,
19979 DB_PERF_SEL_flush_2plane                 = 0x00000077,
19980 DB_PERF_SEL_flush_3plane                 = 0x00000078,
19981 DB_PERF_SEL_flush_4plane                 = 0x00000079,
19982 DB_PERF_SEL_flush_5plane                 = 0x0000007a,
19983 DB_PERF_SEL_flush_6plane                 = 0x0000007b,
19984 DB_PERF_SEL_flush_7plane                 = 0x0000007c,
19985 DB_PERF_SEL_flush_8plane                 = 0x0000007d,
19986 DB_PERF_SEL_flush_9plane                 = 0x0000007e,
19987 DB_PERF_SEL_flush_10plane                = 0x0000007f,
19988 DB_PERF_SEL_flush_11plane                = 0x00000080,
19989 DB_PERF_SEL_flush_12plane                = 0x00000081,
19990 DB_PERF_SEL_flush_13plane                = 0x00000082,
19991 DB_PERF_SEL_flush_14plane                = 0x00000083,
19992 DB_PERF_SEL_flush_15plane                = 0x00000084,
19993 DB_PERF_SEL_flush_16plane                = 0x00000085,
19994 DB_PERF_SEL_flush_expanded_z             = 0x00000086,
19995 DB_PERF_SEL_earlyZ_waiting_for_postZ_done  = 0x00000087,
19996 DB_PERF_SEL_reZ_waiting_for_postZ_done   = 0x00000088,
19997 DB_PERF_SEL_dk_tile_sends                = 0x00000089,
19998 DB_PERF_SEL_dk_tile_busy                 = 0x0000008a,
19999 DB_PERF_SEL_dk_tile_quad_starves         = 0x0000008b,
20000 DB_PERF_SEL_dk_tile_stalls               = 0x0000008c,
20001 DB_PERF_SEL_dk_squad_sends               = 0x0000008d,
20002 DB_PERF_SEL_dk_squad_busy                = 0x0000008e,
20003 DB_PERF_SEL_dk_squad_stalls              = 0x0000008f,
20004 DB_PERF_SEL_Op_Pipe_Busy                 = 0x00000090,
20005 DB_PERF_SEL_Op_Pipe_MC_Read_stall        = 0x00000091,
20006 DB_PERF_SEL_qc_busy                      = 0x00000092,
20007 DB_PERF_SEL_qc_xfc                       = 0x00000093,
20008 DB_PERF_SEL_qc_conflicts                 = 0x00000094,
20009 DB_PERF_SEL_qc_full_stall                = 0x00000095,
20010 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ  = 0x00000096,
20011 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ  = 0x00000097,
20012 DB_PERF_SEL_tsc_insert_summarize_stall   = 0x00000098,
20013 DB_PERF_SEL_tl_busy                      = 0x00000099,
20014 DB_PERF_SEL_tl_dtc_read_starved          = 0x0000009a,
20015 DB_PERF_SEL_tl_z_fetch_stall             = 0x0000009b,
20016 DB_PERF_SEL_tl_stencil_stall             = 0x0000009c,
20017 DB_PERF_SEL_tl_z_decompress_stall        = 0x0000009d,
20018 DB_PERF_SEL_tl_stencil_locked_stall      = 0x0000009e,
20019 DB_PERF_SEL_tl_events                    = 0x0000009f,
20020 DB_PERF_SEL_tl_summarize_squads          = 0x000000a0,
20021 DB_PERF_SEL_tl_flush_expand_squads       = 0x000000a1,
20022 DB_PERF_SEL_tl_expand_squads             = 0x000000a2,
20023 DB_PERF_SEL_tl_preZ_squads               = 0x000000a3,
20024 DB_PERF_SEL_tl_postZ_squads              = 0x000000a4,
20025 DB_PERF_SEL_tl_preZ_noop_squads          = 0x000000a5,
20026 DB_PERF_SEL_tl_postZ_noop_squads         = 0x000000a6,
20027 DB_PERF_SEL_tl_tile_ops                  = 0x000000a7,
20028 DB_PERF_SEL_tl_in_xfc                    = 0x000000a8,
20029 DB_PERF_SEL_tl_in_single_stencil_expand_stall  = 0x000000a9,
20030 DB_PERF_SEL_tl_in_fast_z_stall           = 0x000000aa,
20031 DB_PERF_SEL_tl_out_xfc                   = 0x000000ab,
20032 DB_PERF_SEL_tl_out_squads                = 0x000000ac,
20033 DB_PERF_SEL_zf_plane_multicycle          = 0x000000ad,
20034 DB_PERF_SEL_PostZ_Samples_passing_Z      = 0x000000ae,
20035 DB_PERF_SEL_PostZ_Samples_failing_Z      = 0x000000af,
20036 DB_PERF_SEL_PostZ_Samples_failing_S      = 0x000000b0,
20037 DB_PERF_SEL_PreZ_Samples_passing_Z       = 0x000000b1,
20038 DB_PERF_SEL_PreZ_Samples_failing_Z       = 0x000000b2,
20039 DB_PERF_SEL_PreZ_Samples_failing_S       = 0x000000b3,
20040 DB_PERF_SEL_ts_tc_update_stall           = 0x000000b4,
20041 DB_PERF_SEL_sc_kick_start                = 0x000000b5,
20042 DB_PERF_SEL_sc_kick_end                  = 0x000000b6,
20043 DB_PERF_SEL_clock_reg_active             = 0x000000b7,
20044 DB_PERF_SEL_clock_main_active            = 0x000000b8,
20045 DB_PERF_SEL_clock_mem_export_active      = 0x000000b9,
20046 DB_PERF_SEL_esr_ps_out_busy              = 0x000000ba,
20047 DB_PERF_SEL_esr_ps_lqf_busy              = 0x000000bb,
20048 DB_PERF_SEL_esr_ps_lqf_stall             = 0x000000bc,
20049 DB_PERF_SEL_etr_out_send                 = 0x000000bd,
20050 DB_PERF_SEL_etr_out_busy                 = 0x000000be,
20051 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0x000000bf,
20052 DB_PERF_SEL_etr_out_cb_tile_stall        = 0x000000c0,
20053 DB_PERF_SEL_etr_out_esr_stall            = 0x000000c1,
20054 DB_PERF_SEL_esr_ps_sqq_busy              = 0x000000c2,
20055 DB_PERF_SEL_esr_ps_sqq_stall             = 0x000000c3,
20056 DB_PERF_SEL_esr_eot_fwd_busy             = 0x000000c4,
20057 DB_PERF_SEL_esr_eot_fwd_holding_squad    = 0x000000c5,
20058 DB_PERF_SEL_esr_eot_fwd_forward          = 0x000000c6,
20059 DB_PERF_SEL_esr_sqq_zi_busy              = 0x000000c7,
20060 DB_PERF_SEL_esr_sqq_zi_stall             = 0x000000c8,
20061 DB_PERF_SEL_postzl_sq_pt_busy            = 0x000000c9,
20062 DB_PERF_SEL_postzl_sq_pt_stall           = 0x000000ca,
20063 DB_PERF_SEL_postzl_se_busy               = 0x000000cb,
20064 DB_PERF_SEL_postzl_se_stall              = 0x000000cc,
20065 DB_PERF_SEL_postzl_partial_launch        = 0x000000cd,
20066 DB_PERF_SEL_postzl_full_launch           = 0x000000ce,
20067 DB_PERF_SEL_postzl_partial_waiting       = 0x000000cf,
20068 DB_PERF_SEL_postzl_tile_mem_stall        = 0x000000d0,
20069 DB_PERF_SEL_postzl_tile_init_stall       = 0x000000d1,
20070 DB_PEFF_SEL_prezl_tile_mem_stall         = 0x000000d2,
20071 DB_PERF_SEL_prezl_tile_init_stall        = 0x000000d3,
20072 DB_PERF_SEL_dtt_sm_clash_stall           = 0x000000d4,
20073 DB_PERF_SEL_dtt_sm_slot_stall            = 0x000000d5,
20074 DB_PERF_SEL_dtt_sm_miss_stall            = 0x000000d6,
20075 DB_PERF_SEL_mi_rdreq_busy                = 0x000000d7,
20076 DB_PERF_SEL_mi_rdreq_stall               = 0x000000d8,
20077 DB_PERF_SEL_mi_wrreq_busy                = 0x000000d9,
20078 DB_PERF_SEL_mi_wrreq_stall               = 0x000000da,
20079 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop  = 0x000000db,
20080 DB_PERF_SEL_dkg_tile_rate_tile           = 0x000000dc,
20081 DB_PERF_SEL_prezl_src_in_sends           = 0x000000dd,
20082 DB_PERF_SEL_prezl_src_in_stall           = 0x000000de,
20083 DB_PERF_SEL_prezl_src_in_squads          = 0x000000df,
20084 DB_PERF_SEL_prezl_src_in_squads_unrolled  = 0x000000e0,
20085 DB_PERF_SEL_prezl_src_in_tile_rate       = 0x000000e1,
20086 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled  = 0x000000e2,
20087 DB_PERF_SEL_prezl_src_out_stall          = 0x000000e3,
20088 DB_PERF_SEL_postzl_src_in_sends          = 0x000000e4,
20089 DB_PERF_SEL_postzl_src_in_stall          = 0x000000e5,
20090 DB_PERF_SEL_postzl_src_in_squads         = 0x000000e6,
20091 DB_PERF_SEL_postzl_src_in_squads_unrolled  = 0x000000e7,
20092 DB_PERF_SEL_postzl_src_in_tile_rate      = 0x000000e8,
20093 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled  = 0x000000e9,
20094 DB_PERF_SEL_postzl_src_out_stall         = 0x000000ea,
20095 DB_PERF_SEL_esr_ps_src_in_sends          = 0x000000eb,
20096 DB_PERF_SEL_esr_ps_src_in_stall          = 0x000000ec,
20097 DB_PERF_SEL_esr_ps_src_in_squads         = 0x000000ed,
20098 DB_PERF_SEL_esr_ps_src_in_squads_unrolled  = 0x000000ee,
20099 DB_PERF_SEL_esr_ps_src_in_tile_rate      = 0x000000ef,
20100 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled  = 0x000000f0,
20101 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate  = 0x000000f1,
20102 DB_PERF_SEL_esr_ps_src_out_stall         = 0x000000f2,
20103 DB_PERF_SEL_depth_bounds_qtiles_culled   = 0x000000f3,
20104 DB_PERF_SEL_PreZ_Samples_failing_DB      = 0x000000f4,
20105 DB_PERF_SEL_PostZ_Samples_failing_DB     = 0x000000f5,
20106 DB_PERF_SEL_flush_compressed             = 0x000000f6,
20107 DB_PERF_SEL_flush_plane_le4              = 0x000000f7,
20108 DB_PERF_SEL_tiles_z_fully_summarized     = 0x000000f8,
20109 DB_PERF_SEL_tiles_stencil_fully_summarized  = 0x000000f9,
20110 DB_PERF_SEL_tiles_z_clear_on_expclear    = 0x000000fa,
20111 DB_PERF_SEL_tiles_s_clear_on_expclear    = 0x000000fb,
20112 DB_PERF_SEL_tiles_decomp_on_expclear     = 0x000000fc,
20113 DB_PERF_SEL_tiles_compressed_to_decompressed  = 0x000000fd,
20114 DB_PERF_SEL_Op_Pipe_Prez_Busy            = 0x000000fe,
20115 DB_PERF_SEL_Op_Pipe_Postz_Busy           = 0x000000ff,
20116 DB_PERF_SEL_di_dt_stall                  = 0x00000100,
20117 DB_PERF_SEL_DB_SC_quad_double_quad       = 0x00000101,
20118 DB_PERF_SEL_SX_DB_quad_export_quads      = 0x00000102,
20119 DB_PERF_SEL_SX_DB_quad_double_format     = 0x00000103,
20120 DB_PERF_SEL_SX_DB_quad_fast_format       = 0x00000104,
20121 DB_PERF_SEL_SX_DB_quad_slow_format       = 0x00000105,
20122 DB_PERF_SEL_DB_CB_lquad_export_quads     = 0x00000106,
20123 DB_PERF_SEL_DB_CB_lquad_double_format    = 0x00000107,
20124 DB_PERF_SEL_DB_CB_lquad_fast_format      = 0x00000108,
20125 DB_PERF_SEL_DB_CB_lquad_slow_format      = 0x00000109,
20126 DB_PERF_SEL_CB_DB_rdreq_sends            = 0x0000010a,
20127 DB_PERF_SEL_CB_DB_rdreq_prt_sends        = 0x0000010b,
20128 DB_PERF_SEL_CB_DB_wrreq_sends            = 0x0000010c,
20129 DB_PERF_SEL_CB_DB_wrreq_prt_sends        = 0x0000010d,
20130 DB_PERF_SEL_DB_CB_rdret_ack              = 0x0000010e,
20131 DB_PERF_SEL_DB_CB_rdret_nack             = 0x0000010f,
20132 DB_PERF_SEL_DB_CB_wrret_ack              = 0x00000110,
20133 DB_PERF_SEL_DB_CB_wrret_nack             = 0x00000111,
20134 DB_PERF_SEL_DFSM_squads_in               = 0x00000112,
20135 DB_PERF_SEL_DFSM_full_cleared_squads_out  = 0x00000113,
20136 DB_PERF_SEL_DFSM_quads_in                = 0x00000114,
20137 DB_PERF_SEL_DFSM_fully_cleared_quads_out  = 0x00000115,
20138 DB_PERF_SEL_DFSM_lit_pixels_in           = 0x00000116,
20139 DB_PERF_SEL_DFSM_fully_cleared_pixels_out  = 0x00000117,
20140 DB_PERF_SEL_DFSM_lit_samples_in          = 0x00000118,
20141 DB_PERF_SEL_DFSM_lit_samples_out         = 0x00000119,
20142 DB_PERF_SEL_DFSM_cycles_above_watermark  = 0x0000011a,
20143 DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream  = 0x0000011b,
20144 DB_PERF_SEL_DFSM_stalled_by_downstream   = 0x0000011c,
20145 DB_PERF_SEL_DFSM_evicted_squads_above_watermark  = 0x0000011d,
20146 DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow  = 0x0000011e,
20147 DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO  = 0x0000011f,
20148 DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark  = 0x00000120,
20149 } PerfCounter_Vals;
20150 
20151 /*
20152  * RingCounterControl enum
20153  */
20154 
20155 typedef enum RingCounterControl {
20156 COUNTER_RING_SPLIT                       = 0x00000000,
20157 COUNTER_RING_0                           = 0x00000001,
20158 COUNTER_RING_1                           = 0x00000002,
20159 } RingCounterControl;
20160 
20161 /*
20162  * DbMemArbWatermarks enum
20163  */
20164 
20165 typedef enum DbMemArbWatermarks {
20166 TRANSFERRED_64_BYTES                     = 0x00000000,
20167 TRANSFERRED_128_BYTES                    = 0x00000001,
20168 TRANSFERRED_256_BYTES                    = 0x00000002,
20169 TRANSFERRED_512_BYTES                    = 0x00000003,
20170 TRANSFERRED_1024_BYTES                   = 0x00000004,
20171 TRANSFERRED_2048_BYTES                   = 0x00000005,
20172 TRANSFERRED_4096_BYTES                   = 0x00000006,
20173 TRANSFERRED_8192_BYTES                   = 0x00000007,
20174 } DbMemArbWatermarks;
20175 
20176 /*
20177  * DFSMFlushEvents enum
20178  */
20179 
20180 typedef enum DFSMFlushEvents {
20181 DB_FLUSH_AND_INV_DB_DATA_TS              = 0x00000000,
20182 DB_FLUSH_AND_INV_DB_META                 = 0x00000001,
20183 DB_CACHE_FLUSH                           = 0x00000002,
20184 DB_CACHE_FLUSH_TS                        = 0x00000003,
20185 DB_CACHE_FLUSH_AND_INV_EVENT             = 0x00000004,
20186 DB_CACHE_FLUSH_AND_INV_TS_EVENT          = 0x00000005,
20187 } DFSMFlushEvents;
20188 
20189 /*
20190  * PixelPipeCounterId enum
20191  */
20192 
20193 typedef enum PixelPipeCounterId {
20194 PIXEL_PIPE_OCCLUSION_COUNT_0             = 0x00000000,
20195 PIXEL_PIPE_OCCLUSION_COUNT_1             = 0x00000001,
20196 PIXEL_PIPE_OCCLUSION_COUNT_2             = 0x00000002,
20197 PIXEL_PIPE_OCCLUSION_COUNT_3             = 0x00000003,
20198 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0          = 0x00000004,
20199 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0          = 0x00000005,
20200 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1          = 0x00000006,
20201 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1          = 0x00000007,
20202 } PixelPipeCounterId;
20203 
20204 /*
20205  * PixelPipeStride enum
20206  */
20207 
20208 typedef enum PixelPipeStride {
20209 PIXEL_PIPE_STRIDE_32_BITS                = 0x00000000,
20210 PIXEL_PIPE_STRIDE_64_BITS                = 0x00000001,
20211 PIXEL_PIPE_STRIDE_128_BITS               = 0x00000002,
20212 PIXEL_PIPE_STRIDE_256_BITS               = 0x00000003,
20213 } PixelPipeStride;
20214 
20215 /*******************************************************
20216  * TA Enums
20217  *******************************************************/
20218 
20219 /*
20220  * TEX_BORDER_COLOR_TYPE enum
20221  */
20222 
20223 typedef enum TEX_BORDER_COLOR_TYPE {
20224 TEX_BorderColor_TransparentBlack         = 0x00000000,
20225 TEX_BorderColor_OpaqueBlack              = 0x00000001,
20226 TEX_BorderColor_OpaqueWhite              = 0x00000002,
20227 TEX_BorderColor_Register                 = 0x00000003,
20228 } TEX_BORDER_COLOR_TYPE;
20229 
20230 /*
20231  * TEX_CHROMA_KEY enum
20232  */
20233 
20234 typedef enum TEX_CHROMA_KEY {
20235 TEX_ChromaKey_Disabled                   = 0x00000000,
20236 TEX_ChromaKey_Kill                       = 0x00000001,
20237 TEX_ChromaKey_Blend                      = 0x00000002,
20238 TEX_ChromaKey_RESERVED_3                 = 0x00000003,
20239 } TEX_CHROMA_KEY;
20240 
20241 /*
20242  * TEX_CLAMP enum
20243  */
20244 
20245 typedef enum TEX_CLAMP {
20246 TEX_Clamp_Repeat                         = 0x00000000,
20247 TEX_Clamp_Mirror                         = 0x00000001,
20248 TEX_Clamp_ClampToLast                    = 0x00000002,
20249 TEX_Clamp_MirrorOnceToLast               = 0x00000003,
20250 TEX_Clamp_ClampHalfToBorder              = 0x00000004,
20251 TEX_Clamp_MirrorOnceHalfToBorder         = 0x00000005,
20252 TEX_Clamp_ClampToBorder                  = 0x00000006,
20253 TEX_Clamp_MirrorOnceToBorder             = 0x00000007,
20254 } TEX_CLAMP;
20255 
20256 /*
20257  * TEX_COORD_TYPE enum
20258  */
20259 
20260 typedef enum TEX_COORD_TYPE {
20261 TEX_CoordType_Unnormalized               = 0x00000000,
20262 TEX_CoordType_Normalized                 = 0x00000001,
20263 } TEX_COORD_TYPE;
20264 
20265 /*
20266  * TEX_DEPTH_COMPARE_FUNCTION enum
20267  */
20268 
20269 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
20270 TEX_DepthCompareFunction_Never           = 0x00000000,
20271 TEX_DepthCompareFunction_Less            = 0x00000001,
20272 TEX_DepthCompareFunction_Equal           = 0x00000002,
20273 TEX_DepthCompareFunction_LessEqual       = 0x00000003,
20274 TEX_DepthCompareFunction_Greater         = 0x00000004,
20275 TEX_DepthCompareFunction_NotEqual        = 0x00000005,
20276 TEX_DepthCompareFunction_GreaterEqual    = 0x00000006,
20277 TEX_DepthCompareFunction_Always          = 0x00000007,
20278 } TEX_DEPTH_COMPARE_FUNCTION;
20279 
20280 /*
20281  * TEX_DIM enum
20282  */
20283 
20284 typedef enum TEX_DIM {
20285 TEX_Dim_1D                               = 0x00000000,
20286 TEX_Dim_2D                               = 0x00000001,
20287 TEX_Dim_3D                               = 0x00000002,
20288 TEX_Dim_CubeMap                          = 0x00000003,
20289 TEX_Dim_1DArray                          = 0x00000004,
20290 TEX_Dim_2DArray                          = 0x00000005,
20291 TEX_Dim_2D_MSAA                          = 0x00000006,
20292 TEX_Dim_2DArray_MSAA                     = 0x00000007,
20293 } TEX_DIM;
20294 
20295 /*
20296  * TEX_FORMAT_COMP enum
20297  */
20298 
20299 typedef enum TEX_FORMAT_COMP {
20300 TEX_FormatComp_Unsigned                  = 0x00000000,
20301 TEX_FormatComp_Signed                    = 0x00000001,
20302 TEX_FormatComp_UnsignedBiased            = 0x00000002,
20303 TEX_FormatComp_RESERVED_3                = 0x00000003,
20304 } TEX_FORMAT_COMP;
20305 
20306 /*
20307  * TEX_MAX_ANISO_RATIO enum
20308  */
20309 
20310 typedef enum TEX_MAX_ANISO_RATIO {
20311 TEX_MaxAnisoRatio_1to1                   = 0x00000000,
20312 TEX_MaxAnisoRatio_2to1                   = 0x00000001,
20313 TEX_MaxAnisoRatio_4to1                   = 0x00000002,
20314 TEX_MaxAnisoRatio_8to1                   = 0x00000003,
20315 TEX_MaxAnisoRatio_16to1                  = 0x00000004,
20316 TEX_MaxAnisoRatio_RESERVED_5             = 0x00000005,
20317 TEX_MaxAnisoRatio_RESERVED_6             = 0x00000006,
20318 TEX_MaxAnisoRatio_RESERVED_7             = 0x00000007,
20319 } TEX_MAX_ANISO_RATIO;
20320 
20321 /*
20322  * TEX_MIP_FILTER enum
20323  */
20324 
20325 typedef enum TEX_MIP_FILTER {
20326 TEX_MipFilter_None                       = 0x00000000,
20327 TEX_MipFilter_Point                      = 0x00000001,
20328 TEX_MipFilter_Linear                     = 0x00000002,
20329 TEX_MipFilter_Point_Aniso_Adj            = 0x00000003,
20330 } TEX_MIP_FILTER;
20331 
20332 /*
20333  * TEX_REQUEST_SIZE enum
20334  */
20335 
20336 typedef enum TEX_REQUEST_SIZE {
20337 TEX_RequestSize_32B                      = 0x00000000,
20338 TEX_RequestSize_64B                      = 0x00000001,
20339 TEX_RequestSize_128B                     = 0x00000002,
20340 TEX_RequestSize_2X64B                    = 0x00000003,
20341 } TEX_REQUEST_SIZE;
20342 
20343 /*
20344  * TEX_SAMPLER_TYPE enum
20345  */
20346 
20347 typedef enum TEX_SAMPLER_TYPE {
20348 TEX_SamplerType_Invalid                  = 0x00000000,
20349 TEX_SamplerType_Valid                    = 0x00000001,
20350 } TEX_SAMPLER_TYPE;
20351 
20352 /*
20353  * TEX_XY_FILTER enum
20354  */
20355 
20356 typedef enum TEX_XY_FILTER {
20357 TEX_XYFilter_Point                       = 0x00000000,
20358 TEX_XYFilter_Linear                      = 0x00000001,
20359 TEX_XYFilter_AnisoPoint                  = 0x00000002,
20360 TEX_XYFilter_AnisoLinear                 = 0x00000003,
20361 } TEX_XY_FILTER;
20362 
20363 /*
20364  * TEX_Z_FILTER enum
20365  */
20366 
20367 typedef enum TEX_Z_FILTER {
20368 TEX_ZFilter_None                         = 0x00000000,
20369 TEX_ZFilter_Point                        = 0x00000001,
20370 TEX_ZFilter_Linear                       = 0x00000002,
20371 TEX_ZFilter_RESERVED_3                   = 0x00000003,
20372 } TEX_Z_FILTER;
20373 
20374 /*
20375  * VTX_CLAMP enum
20376  */
20377 
20378 typedef enum VTX_CLAMP {
20379 VTX_Clamp_ClampToZero                    = 0x00000000,
20380 VTX_Clamp_ClampToNAN                     = 0x00000001,
20381 } VTX_CLAMP;
20382 
20383 /*
20384  * VTX_FETCH_TYPE enum
20385  */
20386 
20387 typedef enum VTX_FETCH_TYPE {
20388 VTX_FetchType_VertexData                 = 0x00000000,
20389 VTX_FetchType_InstanceData               = 0x00000001,
20390 VTX_FetchType_NoIndexOffset              = 0x00000002,
20391 VTX_FetchType_RESERVED_3                 = 0x00000003,
20392 } VTX_FETCH_TYPE;
20393 
20394 /*
20395  * VTX_FORMAT_COMP_ALL enum
20396  */
20397 
20398 typedef enum VTX_FORMAT_COMP_ALL {
20399 VTX_FormatCompAll_Unsigned               = 0x00000000,
20400 VTX_FormatCompAll_Signed                 = 0x00000001,
20401 } VTX_FORMAT_COMP_ALL;
20402 
20403 /*
20404  * VTX_MEM_REQUEST_SIZE enum
20405  */
20406 
20407 typedef enum VTX_MEM_REQUEST_SIZE {
20408 VTX_MemRequestSize_32B                   = 0x00000000,
20409 VTX_MemRequestSize_64B                   = 0x00000001,
20410 } VTX_MEM_REQUEST_SIZE;
20411 
20412 /*
20413  * TVX_DATA_FORMAT enum
20414  */
20415 
20416 typedef enum TVX_DATA_FORMAT {
20417 TVX_FMT_INVALID                          = 0x00000000,
20418 TVX_FMT_8                                = 0x00000001,
20419 TVX_FMT_4_4                              = 0x00000002,
20420 TVX_FMT_3_3_2                            = 0x00000003,
20421 TVX_FMT_RESERVED_4                       = 0x00000004,
20422 TVX_FMT_16                               = 0x00000005,
20423 TVX_FMT_16_FLOAT                         = 0x00000006,
20424 TVX_FMT_8_8                              = 0x00000007,
20425 TVX_FMT_5_6_5                            = 0x00000008,
20426 TVX_FMT_6_5_5                            = 0x00000009,
20427 TVX_FMT_1_5_5_5                          = 0x0000000a,
20428 TVX_FMT_4_4_4_4                          = 0x0000000b,
20429 TVX_FMT_5_5_5_1                          = 0x0000000c,
20430 TVX_FMT_32                               = 0x0000000d,
20431 TVX_FMT_32_FLOAT                         = 0x0000000e,
20432 TVX_FMT_16_16                            = 0x0000000f,
20433 TVX_FMT_16_16_FLOAT                      = 0x00000010,
20434 TVX_FMT_8_24                             = 0x00000011,
20435 TVX_FMT_8_24_FLOAT                       = 0x00000012,
20436 TVX_FMT_24_8                             = 0x00000013,
20437 TVX_FMT_24_8_FLOAT                       = 0x00000014,
20438 TVX_FMT_10_11_11                         = 0x00000015,
20439 TVX_FMT_10_11_11_FLOAT                   = 0x00000016,
20440 TVX_FMT_11_11_10                         = 0x00000017,
20441 TVX_FMT_11_11_10_FLOAT                   = 0x00000018,
20442 TVX_FMT_2_10_10_10                       = 0x00000019,
20443 TVX_FMT_8_8_8_8                          = 0x0000001a,
20444 TVX_FMT_10_10_10_2                       = 0x0000001b,
20445 TVX_FMT_X24_8_32_FLOAT                   = 0x0000001c,
20446 TVX_FMT_32_32                            = 0x0000001d,
20447 TVX_FMT_32_32_FLOAT                      = 0x0000001e,
20448 TVX_FMT_16_16_16_16                      = 0x0000001f,
20449 TVX_FMT_16_16_16_16_FLOAT                = 0x00000020,
20450 TVX_FMT_RESERVED_33                      = 0x00000021,
20451 TVX_FMT_32_32_32_32                      = 0x00000022,
20452 TVX_FMT_32_32_32_32_FLOAT                = 0x00000023,
20453 TVX_FMT_RESERVED_36                      = 0x00000024,
20454 TVX_FMT_1                                = 0x00000025,
20455 TVX_FMT_1_REVERSED                       = 0x00000026,
20456 TVX_FMT_GB_GR                            = 0x00000027,
20457 TVX_FMT_BG_RG                            = 0x00000028,
20458 TVX_FMT_32_AS_8                          = 0x00000029,
20459 TVX_FMT_32_AS_8_8                        = 0x0000002a,
20460 TVX_FMT_5_9_9_9_SHAREDEXP                = 0x0000002b,
20461 TVX_FMT_8_8_8                            = 0x0000002c,
20462 TVX_FMT_16_16_16                         = 0x0000002d,
20463 TVX_FMT_16_16_16_FLOAT                   = 0x0000002e,
20464 TVX_FMT_32_32_32                         = 0x0000002f,
20465 TVX_FMT_32_32_32_FLOAT                   = 0x00000030,
20466 TVX_FMT_BC1                              = 0x00000031,
20467 TVX_FMT_BC2                              = 0x00000032,
20468 TVX_FMT_BC3                              = 0x00000033,
20469 TVX_FMT_BC4                              = 0x00000034,
20470 TVX_FMT_BC5                              = 0x00000035,
20471 TVX_FMT_APC0                             = 0x00000036,
20472 TVX_FMT_APC1                             = 0x00000037,
20473 TVX_FMT_APC2                             = 0x00000038,
20474 TVX_FMT_APC3                             = 0x00000039,
20475 TVX_FMT_APC4                             = 0x0000003a,
20476 TVX_FMT_APC5                             = 0x0000003b,
20477 TVX_FMT_APC6                             = 0x0000003c,
20478 TVX_FMT_APC7                             = 0x0000003d,
20479 TVX_FMT_CTX1                             = 0x0000003e,
20480 TVX_FMT_RESERVED_63                      = 0x0000003f,
20481 } TVX_DATA_FORMAT;
20482 
20483 /*
20484  * TVX_DST_SEL enum
20485  */
20486 
20487 typedef enum TVX_DST_SEL {
20488 TVX_DstSel_X                             = 0x00000000,
20489 TVX_DstSel_Y                             = 0x00000001,
20490 TVX_DstSel_Z                             = 0x00000002,
20491 TVX_DstSel_W                             = 0x00000003,
20492 TVX_DstSel_0f                            = 0x00000004,
20493 TVX_DstSel_1f                            = 0x00000005,
20494 TVX_DstSel_RESERVED_6                    = 0x00000006,
20495 TVX_DstSel_Mask                          = 0x00000007,
20496 } TVX_DST_SEL;
20497 
20498 /*
20499  * TVX_ENDIAN_SWAP enum
20500  */
20501 
20502 typedef enum TVX_ENDIAN_SWAP {
20503 TVX_EndianSwap_None                      = 0x00000000,
20504 TVX_EndianSwap_8in16                     = 0x00000001,
20505 TVX_EndianSwap_8in32                     = 0x00000002,
20506 TVX_EndianSwap_8in64                     = 0x00000003,
20507 } TVX_ENDIAN_SWAP;
20508 
20509 /*
20510  * TVX_INST enum
20511  */
20512 
20513 typedef enum TVX_INST {
20514 TVX_Inst_NormalVertexFetch               = 0x00000000,
20515 TVX_Inst_SemanticVertexFetch             = 0x00000001,
20516 TVX_Inst_RESERVED_2                      = 0x00000002,
20517 TVX_Inst_LD                              = 0x00000003,
20518 TVX_Inst_GetTextureResInfo               = 0x00000004,
20519 TVX_Inst_GetNumberOfSamples              = 0x00000005,
20520 TVX_Inst_GetLOD                          = 0x00000006,
20521 TVX_Inst_GetGradientsH                   = 0x00000007,
20522 TVX_Inst_GetGradientsV                   = 0x00000008,
20523 TVX_Inst_SetTextureOffsets               = 0x00000009,
20524 TVX_Inst_KeepGradients                   = 0x0000000a,
20525 TVX_Inst_SetGradientsH                   = 0x0000000b,
20526 TVX_Inst_SetGradientsV                   = 0x0000000c,
20527 TVX_Inst_Pass                            = 0x0000000d,
20528 TVX_Inst_GetBufferResInfo                = 0x0000000e,
20529 TVX_Inst_RESERVED_15                     = 0x0000000f,
20530 TVX_Inst_Sample                          = 0x00000010,
20531 TVX_Inst_Sample_L                        = 0x00000011,
20532 TVX_Inst_Sample_LB                       = 0x00000012,
20533 TVX_Inst_Sample_LZ                       = 0x00000013,
20534 TVX_Inst_Sample_G                        = 0x00000014,
20535 TVX_Inst_Gather4                         = 0x00000015,
20536 TVX_Inst_Sample_G_LB                     = 0x00000016,
20537 TVX_Inst_Gather4_O                       = 0x00000017,
20538 TVX_Inst_Sample_C                        = 0x00000018,
20539 TVX_Inst_Sample_C_L                      = 0x00000019,
20540 TVX_Inst_Sample_C_LB                     = 0x0000001a,
20541 TVX_Inst_Sample_C_LZ                     = 0x0000001b,
20542 TVX_Inst_Sample_C_G                      = 0x0000001c,
20543 TVX_Inst_Gather4_C                       = 0x0000001d,
20544 TVX_Inst_Sample_C_G_LB                   = 0x0000001e,
20545 TVX_Inst_Gather4_C_O                     = 0x0000001f,
20546 } TVX_INST;
20547 
20548 /*
20549  * TVX_NUM_FORMAT_ALL enum
20550  */
20551 
20552 typedef enum TVX_NUM_FORMAT_ALL {
20553 TVX_NumFormatAll_Norm                    = 0x00000000,
20554 TVX_NumFormatAll_Int                     = 0x00000001,
20555 TVX_NumFormatAll_Scaled                  = 0x00000002,
20556 TVX_NumFormatAll_RESERVED_3              = 0x00000003,
20557 } TVX_NUM_FORMAT_ALL;
20558 
20559 /*
20560  * TVX_SRC_SEL enum
20561  */
20562 
20563 typedef enum TVX_SRC_SEL {
20564 TVX_SrcSel_X                             = 0x00000000,
20565 TVX_SrcSel_Y                             = 0x00000001,
20566 TVX_SrcSel_Z                             = 0x00000002,
20567 TVX_SrcSel_W                             = 0x00000003,
20568 TVX_SrcSel_0f                            = 0x00000004,
20569 TVX_SrcSel_1f                            = 0x00000005,
20570 } TVX_SRC_SEL;
20571 
20572 /*
20573  * TVX_SRF_MODE_ALL enum
20574  */
20575 
20576 typedef enum TVX_SRF_MODE_ALL {
20577 TVX_SRFModeAll_ZCMO                      = 0x00000000,
20578 TVX_SRFModeAll_NZ                        = 0x00000001,
20579 } TVX_SRF_MODE_ALL;
20580 
20581 /*
20582  * TVX_TYPE enum
20583  */
20584 
20585 typedef enum TVX_TYPE {
20586 TVX_Type_InvalidTextureResource          = 0x00000000,
20587 TVX_Type_InvalidVertexBuffer             = 0x00000001,
20588 TVX_Type_ValidTextureResource            = 0x00000002,
20589 TVX_Type_ValidVertexBuffer               = 0x00000003,
20590 } TVX_TYPE;
20591 
20592 /*******************************************************
20593  * PA Enums
20594  *******************************************************/
20595 
20596 /*
20597  * SU_PERFCNT_SEL enum
20598  */
20599 
20600 typedef enum SU_PERFCNT_SEL {
20601 PERF_PAPC_PASX_REQ                       = 0x00000000,
20602 PERF_PAPC_PASX_DISABLE_PIPE              = 0x00000001,
20603 PERF_PAPC_PASX_FIRST_VECTOR              = 0x00000002,
20604 PERF_PAPC_PASX_SECOND_VECTOR             = 0x00000003,
20605 PERF_PAPC_PASX_FIRST_DEAD                = 0x00000004,
20606 PERF_PAPC_PASX_SECOND_DEAD               = 0x00000005,
20607 PERF_PAPC_PASX_VTX_KILL_DISCARD          = 0x00000006,
20608 PERF_PAPC_PASX_VTX_NAN_DISCARD           = 0x00000007,
20609 PERF_PAPC_PA_INPUT_PRIM                  = 0x00000008,
20610 PERF_PAPC_PA_INPUT_NULL_PRIM             = 0x00000009,
20611 PERF_PAPC_PA_INPUT_EVENT_FLAG            = 0x0000000a,
20612 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT       = 0x0000000b,
20613 PERF_PAPC_PA_INPUT_END_OF_PACKET         = 0x0000000c,
20614 PERF_PAPC_PA_INPUT_EXTENDED_EVENT        = 0x0000000d,
20615 PERF_PAPC_CLPR_CULL_PRIM                 = 0x0000000e,
20616 PERF_PAPC_CLPR_VVUCP_CULL_PRIM           = 0x0000000f,
20617 PERF_PAPC_CLPR_VV_CULL_PRIM              = 0x00000010,
20618 PERF_PAPC_CLPR_UCP_CULL_PRIM             = 0x00000011,
20619 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM        = 0x00000012,
20620 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM         = 0x00000013,
20621 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM         = 0x00000014,
20622 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM           = 0x00000015,
20623 PERF_PAPC_CLPR_VV_CLIP_PRIM              = 0x00000016,
20624 PERF_PAPC_CLPR_UCP_CLIP_PRIM             = 0x00000017,
20625 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE      = 0x00000018,
20626 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1          = 0x00000019,
20627 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2          = 0x0000001a,
20628 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3          = 0x0000001b,
20629 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4          = 0x0000001c,
20630 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8        = 0x0000001d,
20631 PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12       = 0x0000001e,
20632 PERF_PAPC_CLPR_CLIP_PLANE_NEAR           = 0x0000001f,
20633 PERF_PAPC_CLPR_CLIP_PLANE_FAR            = 0x00000020,
20634 PERF_PAPC_CLPR_CLIP_PLANE_LEFT           = 0x00000021,
20635 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT          = 0x00000022,
20636 PERF_PAPC_CLPR_CLIP_PLANE_TOP            = 0x00000023,
20637 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM         = 0x00000024,
20638 PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM        = 0x00000025,
20639 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM     = 0x00000026,
20640 PERF_PAPC_CLSM_NULL_PRIM                 = 0x00000027,
20641 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM      = 0x00000028,
20642 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM         = 0x00000029,
20643 PERF_PAPC_CLSM_OUT_PRIM_CNT_1            = 0x0000002a,
20644 PERF_PAPC_CLSM_OUT_PRIM_CNT_2            = 0x0000002b,
20645 PERF_PAPC_CLSM_OUT_PRIM_CNT_3            = 0x0000002c,
20646 PERF_PAPC_CLSM_OUT_PRIM_CNT_4            = 0x0000002d,
20647 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8          = 0x0000002e,
20648 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13         = 0x0000002f,
20649 PERF_PAPC_CLIPGA_VTE_KILL_PRIM           = 0x00000030,
20650 PERF_PAPC_SU_INPUT_PRIM                  = 0x00000031,
20651 PERF_PAPC_SU_INPUT_CLIP_PRIM             = 0x00000032,
20652 PERF_PAPC_SU_INPUT_NULL_PRIM             = 0x00000033,
20653 PERF_PAPC_SU_INPUT_PRIM_DUAL             = 0x00000034,
20654 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL        = 0x00000035,
20655 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM         = 0x00000036,
20656 PERF_PAPC_SU_BACK_FACE_CULL_PRIM         = 0x00000037,
20657 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM        = 0x00000038,
20658 PERF_PAPC_SU_POLYMODE_FACE_CULL          = 0x00000039,
20659 PERF_PAPC_SU_POLYMODE_BACK_CULL          = 0x0000003a,
20660 PERF_PAPC_SU_POLYMODE_FRONT_CULL         = 0x0000003b,
20661 PERF_PAPC_SU_POLYMODE_INVALID_FILL       = 0x0000003c,
20662 PERF_PAPC_SU_OUTPUT_PRIM                 = 0x0000003d,
20663 PERF_PAPC_SU_OUTPUT_CLIP_PRIM            = 0x0000003e,
20664 PERF_PAPC_SU_OUTPUT_NULL_PRIM            = 0x0000003f,
20665 PERF_PAPC_SU_OUTPUT_EVENT_FLAG           = 0x00000040,
20666 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT      = 0x00000041,
20667 PERF_PAPC_SU_OUTPUT_END_OF_PACKET        = 0x00000042,
20668 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE        = 0x00000043,
20669 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK        = 0x00000044,
20670 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT       = 0x00000045,
20671 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE      = 0x00000046,
20672 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK      = 0x00000047,
20673 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT     = 0x00000048,
20674 PERF_PAPC_SU_OUTPUT_PRIM_DUAL            = 0x00000049,
20675 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL       = 0x0000004a,
20676 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL        = 0x0000004b,
20677 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL   = 0x0000004c,
20678 PERF_PAPC_PASX_REQ_IDLE                  = 0x0000004d,
20679 PERF_PAPC_PASX_REQ_BUSY                  = 0x0000004e,
20680 PERF_PAPC_PASX_REQ_STALLED               = 0x0000004f,
20681 PERF_PAPC_PASX_REC_IDLE                  = 0x00000050,
20682 PERF_PAPC_PASX_REC_BUSY                  = 0x00000051,
20683 PERF_PAPC_PASX_REC_STARVED_SX            = 0x00000052,
20684 PERF_PAPC_PASX_REC_STALLED               = 0x00000053,
20685 PERF_PAPC_PASX_REC_STALLED_POS_MEM       = 0x00000054,
20686 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN      = 0x00000055,
20687 PERF_PAPC_CCGSM_IDLE                     = 0x00000056,
20688 PERF_PAPC_CCGSM_BUSY                     = 0x00000057,
20689 PERF_PAPC_CCGSM_STALLED                  = 0x00000058,
20690 PERF_PAPC_CLPRIM_IDLE                    = 0x00000059,
20691 PERF_PAPC_CLPRIM_BUSY                    = 0x0000005a,
20692 PERF_PAPC_CLPRIM_STALLED                 = 0x0000005b,
20693 PERF_PAPC_CLPRIM_STARVED_CCGSM           = 0x0000005c,
20694 PERF_PAPC_CLIPSM_IDLE                    = 0x0000005d,
20695 PERF_PAPC_CLIPSM_BUSY                    = 0x0000005e,
20696 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH     = 0x0000005f,
20697 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ       = 0x00000060,
20698 PERF_PAPC_CLIPSM_WAIT_CLIPGA             = 0x00000061,
20699 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP     = 0x00000062,
20700 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM         = 0x00000063,
20701 PERF_PAPC_CLIPGA_IDLE                    = 0x00000064,
20702 PERF_PAPC_CLIPGA_BUSY                    = 0x00000065,
20703 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP        = 0x00000066,
20704 PERF_PAPC_CLIPGA_STALLED                 = 0x00000067,
20705 PERF_PAPC_CLIP_IDLE                      = 0x00000068,
20706 PERF_PAPC_CLIP_BUSY                      = 0x00000069,
20707 PERF_PAPC_SU_IDLE                        = 0x0000006a,
20708 PERF_PAPC_SU_BUSY                        = 0x0000006b,
20709 PERF_PAPC_SU_STARVED_CLIP                = 0x0000006c,
20710 PERF_PAPC_SU_STALLED_SC                  = 0x0000006d,
20711 PERF_PAPC_CL_DYN_SCLK_VLD                = 0x0000006e,
20712 PERF_PAPC_SU_DYN_SCLK_VLD                = 0x0000006f,
20713 PERF_PAPC_PA_REG_SCLK_VLD                = 0x00000070,
20714 PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL  = 0x00000071,
20715 PERF_PAPC_PASX_SE0_REQ                   = 0x00000072,
20716 PERF_PAPC_PASX_SE1_REQ                   = 0x00000073,
20717 PERF_PAPC_PASX_SE0_FIRST_VECTOR          = 0x00000074,
20718 PERF_PAPC_PASX_SE0_SECOND_VECTOR         = 0x00000075,
20719 PERF_PAPC_PASX_SE1_FIRST_VECTOR          = 0x00000076,
20720 PERF_PAPC_PASX_SE1_SECOND_VECTOR         = 0x00000077,
20721 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL        = 0x00000078,
20722 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL        = 0x00000079,
20723 PERF_PAPC_SU_SE01_PRIM_FILTER_CULL       = 0x0000007a,
20724 PERF_PAPC_SU_SE0_OUTPUT_PRIM             = 0x0000007b,
20725 PERF_PAPC_SU_SE1_OUTPUT_PRIM             = 0x0000007c,
20726 PERF_PAPC_SU_SE01_OUTPUT_PRIM            = 0x0000007d,
20727 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM        = 0x0000007e,
20728 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM        = 0x0000007f,
20729 PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM       = 0x00000080,
20730 PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT  = 0x00000081,
20731 PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT  = 0x00000082,
20732 PERF_PAPC_SU_SE0_STALLED_SC              = 0x00000083,
20733 PERF_PAPC_SU_SE1_STALLED_SC              = 0x00000084,
20734 PERF_PAPC_SU_SE01_STALLED_SC             = 0x00000085,
20735 PERF_PAPC_CLSM_CLIPPING_PRIM             = 0x00000086,
20736 PERF_PAPC_SU_CULLED_PRIM                 = 0x00000087,
20737 PERF_PAPC_SU_OUTPUT_EOPG                 = 0x00000088,
20738 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL        = 0x00000089,
20739 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL        = 0x0000008a,
20740 PERF_PAPC_SU_SE2_OUTPUT_PRIM             = 0x0000008b,
20741 PERF_PAPC_SU_SE3_OUTPUT_PRIM             = 0x0000008c,
20742 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM        = 0x0000008d,
20743 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM        = 0x0000008e,
20744 PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET    = 0x0000008f,
20745 PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET    = 0x00000090,
20746 PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET    = 0x00000091,
20747 PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET    = 0x00000092,
20748 PERF_PAPC_SU_SE0_OUTPUT_EOPG             = 0x00000093,
20749 PERF_PAPC_SU_SE1_OUTPUT_EOPG             = 0x00000094,
20750 PERF_PAPC_SU_SE2_OUTPUT_EOPG             = 0x00000095,
20751 PERF_PAPC_SU_SE3_OUTPUT_EOPG             = 0x00000096,
20752 PERF_PAPC_SU_SE2_STALLED_SC              = 0x00000097,
20753 PERF_PAPC_SU_SE3_STALLED_SC              = 0x00000098,
20754 } SU_PERFCNT_SEL;
20755 
20756 /*
20757  * SC_PERFCNT_SEL enum
20758  */
20759 
20760 typedef enum SC_PERFCNT_SEL {
20761 SC_SRPS_WINDOW_VALID                     = 0x00000000,
20762 SC_PSSW_WINDOW_VALID                     = 0x00000001,
20763 SC_TPQZ_WINDOW_VALID                     = 0x00000002,
20764 SC_QZQP_WINDOW_VALID                     = 0x00000003,
20765 SC_TRPK_WINDOW_VALID                     = 0x00000004,
20766 SC_SRPS_WINDOW_VALID_BUSY                = 0x00000005,
20767 SC_PSSW_WINDOW_VALID_BUSY                = 0x00000006,
20768 SC_TPQZ_WINDOW_VALID_BUSY                = 0x00000007,
20769 SC_QZQP_WINDOW_VALID_BUSY                = 0x00000008,
20770 SC_TRPK_WINDOW_VALID_BUSY                = 0x00000009,
20771 SC_STARVED_BY_PA                         = 0x0000000a,
20772 SC_STALLED_BY_PRIMFIFO                   = 0x0000000b,
20773 SC_STALLED_BY_DB_TILE                    = 0x0000000c,
20774 SC_STARVED_BY_DB_TILE                    = 0x0000000d,
20775 SC_STALLED_BY_TILEORDERFIFO              = 0x0000000e,
20776 SC_STALLED_BY_TILEFIFO                   = 0x0000000f,
20777 SC_STALLED_BY_DB_QUAD                    = 0x00000010,
20778 SC_STARVED_BY_DB_QUAD                    = 0x00000011,
20779 SC_STALLED_BY_QUADFIFO                   = 0x00000012,
20780 SC_STALLED_BY_BCI                        = 0x00000013,
20781 SC_STALLED_BY_SPI                        = 0x00000014,
20782 SC_SCISSOR_DISCARD                       = 0x00000015,
20783 SC_BB_DISCARD                            = 0x00000016,
20784 SC_SUPERTILE_COUNT                       = 0x00000017,
20785 SC_SUPERTILE_PER_PRIM_H0                 = 0x00000018,
20786 SC_SUPERTILE_PER_PRIM_H1                 = 0x00000019,
20787 SC_SUPERTILE_PER_PRIM_H2                 = 0x0000001a,
20788 SC_SUPERTILE_PER_PRIM_H3                 = 0x0000001b,
20789 SC_SUPERTILE_PER_PRIM_H4                 = 0x0000001c,
20790 SC_SUPERTILE_PER_PRIM_H5                 = 0x0000001d,
20791 SC_SUPERTILE_PER_PRIM_H6                 = 0x0000001e,
20792 SC_SUPERTILE_PER_PRIM_H7                 = 0x0000001f,
20793 SC_SUPERTILE_PER_PRIM_H8                 = 0x00000020,
20794 SC_SUPERTILE_PER_PRIM_H9                 = 0x00000021,
20795 SC_SUPERTILE_PER_PRIM_H10                = 0x00000022,
20796 SC_SUPERTILE_PER_PRIM_H11                = 0x00000023,
20797 SC_SUPERTILE_PER_PRIM_H12                = 0x00000024,
20798 SC_SUPERTILE_PER_PRIM_H13                = 0x00000025,
20799 SC_SUPERTILE_PER_PRIM_H14                = 0x00000026,
20800 SC_SUPERTILE_PER_PRIM_H15                = 0x00000027,
20801 SC_SUPERTILE_PER_PRIM_H16                = 0x00000028,
20802 SC_TILE_PER_PRIM_H0                      = 0x00000029,
20803 SC_TILE_PER_PRIM_H1                      = 0x0000002a,
20804 SC_TILE_PER_PRIM_H2                      = 0x0000002b,
20805 SC_TILE_PER_PRIM_H3                      = 0x0000002c,
20806 SC_TILE_PER_PRIM_H4                      = 0x0000002d,
20807 SC_TILE_PER_PRIM_H5                      = 0x0000002e,
20808 SC_TILE_PER_PRIM_H6                      = 0x0000002f,
20809 SC_TILE_PER_PRIM_H7                      = 0x00000030,
20810 SC_TILE_PER_PRIM_H8                      = 0x00000031,
20811 SC_TILE_PER_PRIM_H9                      = 0x00000032,
20812 SC_TILE_PER_PRIM_H10                     = 0x00000033,
20813 SC_TILE_PER_PRIM_H11                     = 0x00000034,
20814 SC_TILE_PER_PRIM_H12                     = 0x00000035,
20815 SC_TILE_PER_PRIM_H13                     = 0x00000036,
20816 SC_TILE_PER_PRIM_H14                     = 0x00000037,
20817 SC_TILE_PER_PRIM_H15                     = 0x00000038,
20818 SC_TILE_PER_PRIM_H16                     = 0x00000039,
20819 SC_TILE_PER_SUPERTILE_H0                 = 0x0000003a,
20820 SC_TILE_PER_SUPERTILE_H1                 = 0x0000003b,
20821 SC_TILE_PER_SUPERTILE_H2                 = 0x0000003c,
20822 SC_TILE_PER_SUPERTILE_H3                 = 0x0000003d,
20823 SC_TILE_PER_SUPERTILE_H4                 = 0x0000003e,
20824 SC_TILE_PER_SUPERTILE_H5                 = 0x0000003f,
20825 SC_TILE_PER_SUPERTILE_H6                 = 0x00000040,
20826 SC_TILE_PER_SUPERTILE_H7                 = 0x00000041,
20827 SC_TILE_PER_SUPERTILE_H8                 = 0x00000042,
20828 SC_TILE_PER_SUPERTILE_H9                 = 0x00000043,
20829 SC_TILE_PER_SUPERTILE_H10                = 0x00000044,
20830 SC_TILE_PER_SUPERTILE_H11                = 0x00000045,
20831 SC_TILE_PER_SUPERTILE_H12                = 0x00000046,
20832 SC_TILE_PER_SUPERTILE_H13                = 0x00000047,
20833 SC_TILE_PER_SUPERTILE_H14                = 0x00000048,
20834 SC_TILE_PER_SUPERTILE_H15                = 0x00000049,
20835 SC_TILE_PER_SUPERTILE_H16                = 0x0000004a,
20836 SC_TILE_PICKED_H1                        = 0x0000004b,
20837 SC_TILE_PICKED_H2                        = 0x0000004c,
20838 SC_TILE_PICKED_H3                        = 0x0000004d,
20839 SC_TILE_PICKED_H4                        = 0x0000004e,
20840 SC_QZ0_MULTI_GPU_TILE_DISCARD            = 0x0000004f,
20841 SC_QZ1_MULTI_GPU_TILE_DISCARD            = 0x00000050,
20842 SC_QZ2_MULTI_GPU_TILE_DISCARD            = 0x00000051,
20843 SC_QZ3_MULTI_GPU_TILE_DISCARD            = 0x00000052,
20844 SC_QZ0_TILE_COUNT                        = 0x00000053,
20845 SC_QZ1_TILE_COUNT                        = 0x00000054,
20846 SC_QZ2_TILE_COUNT                        = 0x00000055,
20847 SC_QZ3_TILE_COUNT                        = 0x00000056,
20848 SC_QZ0_TILE_COVERED_COUNT                = 0x00000057,
20849 SC_QZ1_TILE_COVERED_COUNT                = 0x00000058,
20850 SC_QZ2_TILE_COVERED_COUNT                = 0x00000059,
20851 SC_QZ3_TILE_COVERED_COUNT                = 0x0000005a,
20852 SC_QZ0_TILE_NOT_COVERED_COUNT            = 0x0000005b,
20853 SC_QZ1_TILE_NOT_COVERED_COUNT            = 0x0000005c,
20854 SC_QZ2_TILE_NOT_COVERED_COUNT            = 0x0000005d,
20855 SC_QZ3_TILE_NOT_COVERED_COUNT            = 0x0000005e,
20856 SC_QZ0_QUAD_PER_TILE_H0                  = 0x0000005f,
20857 SC_QZ0_QUAD_PER_TILE_H1                  = 0x00000060,
20858 SC_QZ0_QUAD_PER_TILE_H2                  = 0x00000061,
20859 SC_QZ0_QUAD_PER_TILE_H3                  = 0x00000062,
20860 SC_QZ0_QUAD_PER_TILE_H4                  = 0x00000063,
20861 SC_QZ0_QUAD_PER_TILE_H5                  = 0x00000064,
20862 SC_QZ0_QUAD_PER_TILE_H6                  = 0x00000065,
20863 SC_QZ0_QUAD_PER_TILE_H7                  = 0x00000066,
20864 SC_QZ0_QUAD_PER_TILE_H8                  = 0x00000067,
20865 SC_QZ0_QUAD_PER_TILE_H9                  = 0x00000068,
20866 SC_QZ0_QUAD_PER_TILE_H10                 = 0x00000069,
20867 SC_QZ0_QUAD_PER_TILE_H11                 = 0x0000006a,
20868 SC_QZ0_QUAD_PER_TILE_H12                 = 0x0000006b,
20869 SC_QZ0_QUAD_PER_TILE_H13                 = 0x0000006c,
20870 SC_QZ0_QUAD_PER_TILE_H14                 = 0x0000006d,
20871 SC_QZ0_QUAD_PER_TILE_H15                 = 0x0000006e,
20872 SC_QZ0_QUAD_PER_TILE_H16                 = 0x0000006f,
20873 SC_QZ1_QUAD_PER_TILE_H0                  = 0x00000070,
20874 SC_QZ1_QUAD_PER_TILE_H1                  = 0x00000071,
20875 SC_QZ1_QUAD_PER_TILE_H2                  = 0x00000072,
20876 SC_QZ1_QUAD_PER_TILE_H3                  = 0x00000073,
20877 SC_QZ1_QUAD_PER_TILE_H4                  = 0x00000074,
20878 SC_QZ1_QUAD_PER_TILE_H5                  = 0x00000075,
20879 SC_QZ1_QUAD_PER_TILE_H6                  = 0x00000076,
20880 SC_QZ1_QUAD_PER_TILE_H7                  = 0x00000077,
20881 SC_QZ1_QUAD_PER_TILE_H8                  = 0x00000078,
20882 SC_QZ1_QUAD_PER_TILE_H9                  = 0x00000079,
20883 SC_QZ1_QUAD_PER_TILE_H10                 = 0x0000007a,
20884 SC_QZ1_QUAD_PER_TILE_H11                 = 0x0000007b,
20885 SC_QZ1_QUAD_PER_TILE_H12                 = 0x0000007c,
20886 SC_QZ1_QUAD_PER_TILE_H13                 = 0x0000007d,
20887 SC_QZ1_QUAD_PER_TILE_H14                 = 0x0000007e,
20888 SC_QZ1_QUAD_PER_TILE_H15                 = 0x0000007f,
20889 SC_QZ1_QUAD_PER_TILE_H16                 = 0x00000080,
20890 SC_QZ2_QUAD_PER_TILE_H0                  = 0x00000081,
20891 SC_QZ2_QUAD_PER_TILE_H1                  = 0x00000082,
20892 SC_QZ2_QUAD_PER_TILE_H2                  = 0x00000083,
20893 SC_QZ2_QUAD_PER_TILE_H3                  = 0x00000084,
20894 SC_QZ2_QUAD_PER_TILE_H4                  = 0x00000085,
20895 SC_QZ2_QUAD_PER_TILE_H5                  = 0x00000086,
20896 SC_QZ2_QUAD_PER_TILE_H6                  = 0x00000087,
20897 SC_QZ2_QUAD_PER_TILE_H7                  = 0x00000088,
20898 SC_QZ2_QUAD_PER_TILE_H8                  = 0x00000089,
20899 SC_QZ2_QUAD_PER_TILE_H9                  = 0x0000008a,
20900 SC_QZ2_QUAD_PER_TILE_H10                 = 0x0000008b,
20901 SC_QZ2_QUAD_PER_TILE_H11                 = 0x0000008c,
20902 SC_QZ2_QUAD_PER_TILE_H12                 = 0x0000008d,
20903 SC_QZ2_QUAD_PER_TILE_H13                 = 0x0000008e,
20904 SC_QZ2_QUAD_PER_TILE_H14                 = 0x0000008f,
20905 SC_QZ2_QUAD_PER_TILE_H15                 = 0x00000090,
20906 SC_QZ2_QUAD_PER_TILE_H16                 = 0x00000091,
20907 SC_QZ3_QUAD_PER_TILE_H0                  = 0x00000092,
20908 SC_QZ3_QUAD_PER_TILE_H1                  = 0x00000093,
20909 SC_QZ3_QUAD_PER_TILE_H2                  = 0x00000094,
20910 SC_QZ3_QUAD_PER_TILE_H3                  = 0x00000095,
20911 SC_QZ3_QUAD_PER_TILE_H4                  = 0x00000096,
20912 SC_QZ3_QUAD_PER_TILE_H5                  = 0x00000097,
20913 SC_QZ3_QUAD_PER_TILE_H6                  = 0x00000098,
20914 SC_QZ3_QUAD_PER_TILE_H7                  = 0x00000099,
20915 SC_QZ3_QUAD_PER_TILE_H8                  = 0x0000009a,
20916 SC_QZ3_QUAD_PER_TILE_H9                  = 0x0000009b,
20917 SC_QZ3_QUAD_PER_TILE_H10                 = 0x0000009c,
20918 SC_QZ3_QUAD_PER_TILE_H11                 = 0x0000009d,
20919 SC_QZ3_QUAD_PER_TILE_H12                 = 0x0000009e,
20920 SC_QZ3_QUAD_PER_TILE_H13                 = 0x0000009f,
20921 SC_QZ3_QUAD_PER_TILE_H14                 = 0x000000a0,
20922 SC_QZ3_QUAD_PER_TILE_H15                 = 0x000000a1,
20923 SC_QZ3_QUAD_PER_TILE_H16                 = 0x000000a2,
20924 SC_QZ0_QUAD_COUNT                        = 0x000000a3,
20925 SC_QZ1_QUAD_COUNT                        = 0x000000a4,
20926 SC_QZ2_QUAD_COUNT                        = 0x000000a5,
20927 SC_QZ3_QUAD_COUNT                        = 0x000000a6,
20928 SC_P0_HIZ_TILE_COUNT                     = 0x000000a7,
20929 SC_P1_HIZ_TILE_COUNT                     = 0x000000a8,
20930 SC_P2_HIZ_TILE_COUNT                     = 0x000000a9,
20931 SC_P3_HIZ_TILE_COUNT                     = 0x000000aa,
20932 SC_P0_HIZ_QUAD_PER_TILE_H0               = 0x000000ab,
20933 SC_P0_HIZ_QUAD_PER_TILE_H1               = 0x000000ac,
20934 SC_P0_HIZ_QUAD_PER_TILE_H2               = 0x000000ad,
20935 SC_P0_HIZ_QUAD_PER_TILE_H3               = 0x000000ae,
20936 SC_P0_HIZ_QUAD_PER_TILE_H4               = 0x000000af,
20937 SC_P0_HIZ_QUAD_PER_TILE_H5               = 0x000000b0,
20938 SC_P0_HIZ_QUAD_PER_TILE_H6               = 0x000000b1,
20939 SC_P0_HIZ_QUAD_PER_TILE_H7               = 0x000000b2,
20940 SC_P0_HIZ_QUAD_PER_TILE_H8               = 0x000000b3,
20941 SC_P0_HIZ_QUAD_PER_TILE_H9               = 0x000000b4,
20942 SC_P0_HIZ_QUAD_PER_TILE_H10              = 0x000000b5,
20943 SC_P0_HIZ_QUAD_PER_TILE_H11              = 0x000000b6,
20944 SC_P0_HIZ_QUAD_PER_TILE_H12              = 0x000000b7,
20945 SC_P0_HIZ_QUAD_PER_TILE_H13              = 0x000000b8,
20946 SC_P0_HIZ_QUAD_PER_TILE_H14              = 0x000000b9,
20947 SC_P0_HIZ_QUAD_PER_TILE_H15              = 0x000000ba,
20948 SC_P0_HIZ_QUAD_PER_TILE_H16              = 0x000000bb,
20949 SC_P1_HIZ_QUAD_PER_TILE_H0               = 0x000000bc,
20950 SC_P1_HIZ_QUAD_PER_TILE_H1               = 0x000000bd,
20951 SC_P1_HIZ_QUAD_PER_TILE_H2               = 0x000000be,
20952 SC_P1_HIZ_QUAD_PER_TILE_H3               = 0x000000bf,
20953 SC_P1_HIZ_QUAD_PER_TILE_H4               = 0x000000c0,
20954 SC_P1_HIZ_QUAD_PER_TILE_H5               = 0x000000c1,
20955 SC_P1_HIZ_QUAD_PER_TILE_H6               = 0x000000c2,
20956 SC_P1_HIZ_QUAD_PER_TILE_H7               = 0x000000c3,
20957 SC_P1_HIZ_QUAD_PER_TILE_H8               = 0x000000c4,
20958 SC_P1_HIZ_QUAD_PER_TILE_H9               = 0x000000c5,
20959 SC_P1_HIZ_QUAD_PER_TILE_H10              = 0x000000c6,
20960 SC_P1_HIZ_QUAD_PER_TILE_H11              = 0x000000c7,
20961 SC_P1_HIZ_QUAD_PER_TILE_H12              = 0x000000c8,
20962 SC_P1_HIZ_QUAD_PER_TILE_H13              = 0x000000c9,
20963 SC_P1_HIZ_QUAD_PER_TILE_H14              = 0x000000ca,
20964 SC_P1_HIZ_QUAD_PER_TILE_H15              = 0x000000cb,
20965 SC_P1_HIZ_QUAD_PER_TILE_H16              = 0x000000cc,
20966 SC_P2_HIZ_QUAD_PER_TILE_H0               = 0x000000cd,
20967 SC_P2_HIZ_QUAD_PER_TILE_H1               = 0x000000ce,
20968 SC_P2_HIZ_QUAD_PER_TILE_H2               = 0x000000cf,
20969 SC_P2_HIZ_QUAD_PER_TILE_H3               = 0x000000d0,
20970 SC_P2_HIZ_QUAD_PER_TILE_H4               = 0x000000d1,
20971 SC_P2_HIZ_QUAD_PER_TILE_H5               = 0x000000d2,
20972 SC_P2_HIZ_QUAD_PER_TILE_H6               = 0x000000d3,
20973 SC_P2_HIZ_QUAD_PER_TILE_H7               = 0x000000d4,
20974 SC_P2_HIZ_QUAD_PER_TILE_H8               = 0x000000d5,
20975 SC_P2_HIZ_QUAD_PER_TILE_H9               = 0x000000d6,
20976 SC_P2_HIZ_QUAD_PER_TILE_H10              = 0x000000d7,
20977 SC_P2_HIZ_QUAD_PER_TILE_H11              = 0x000000d8,
20978 SC_P2_HIZ_QUAD_PER_TILE_H12              = 0x000000d9,
20979 SC_P2_HIZ_QUAD_PER_TILE_H13              = 0x000000da,
20980 SC_P2_HIZ_QUAD_PER_TILE_H14              = 0x000000db,
20981 SC_P2_HIZ_QUAD_PER_TILE_H15              = 0x000000dc,
20982 SC_P2_HIZ_QUAD_PER_TILE_H16              = 0x000000dd,
20983 SC_P3_HIZ_QUAD_PER_TILE_H0               = 0x000000de,
20984 SC_P3_HIZ_QUAD_PER_TILE_H1               = 0x000000df,
20985 SC_P3_HIZ_QUAD_PER_TILE_H2               = 0x000000e0,
20986 SC_P3_HIZ_QUAD_PER_TILE_H3               = 0x000000e1,
20987 SC_P3_HIZ_QUAD_PER_TILE_H4               = 0x000000e2,
20988 SC_P3_HIZ_QUAD_PER_TILE_H5               = 0x000000e3,
20989 SC_P3_HIZ_QUAD_PER_TILE_H6               = 0x000000e4,
20990 SC_P3_HIZ_QUAD_PER_TILE_H7               = 0x000000e5,
20991 SC_P3_HIZ_QUAD_PER_TILE_H8               = 0x000000e6,
20992 SC_P3_HIZ_QUAD_PER_TILE_H9               = 0x000000e7,
20993 SC_P3_HIZ_QUAD_PER_TILE_H10              = 0x000000e8,
20994 SC_P3_HIZ_QUAD_PER_TILE_H11              = 0x000000e9,
20995 SC_P3_HIZ_QUAD_PER_TILE_H12              = 0x000000ea,
20996 SC_P3_HIZ_QUAD_PER_TILE_H13              = 0x000000eb,
20997 SC_P3_HIZ_QUAD_PER_TILE_H14              = 0x000000ec,
20998 SC_P3_HIZ_QUAD_PER_TILE_H15              = 0x000000ed,
20999 SC_P3_HIZ_QUAD_PER_TILE_H16              = 0x000000ee,
21000 SC_P0_HIZ_QUAD_COUNT                     = 0x000000ef,
21001 SC_P1_HIZ_QUAD_COUNT                     = 0x000000f0,
21002 SC_P2_HIZ_QUAD_COUNT                     = 0x000000f1,
21003 SC_P3_HIZ_QUAD_COUNT                     = 0x000000f2,
21004 SC_P0_DETAIL_QUAD_COUNT                  = 0x000000f3,
21005 SC_P1_DETAIL_QUAD_COUNT                  = 0x000000f4,
21006 SC_P2_DETAIL_QUAD_COUNT                  = 0x000000f5,
21007 SC_P3_DETAIL_QUAD_COUNT                  = 0x000000f6,
21008 SC_P0_DETAIL_QUAD_WITH_1_PIX             = 0x000000f7,
21009 SC_P0_DETAIL_QUAD_WITH_2_PIX             = 0x000000f8,
21010 SC_P0_DETAIL_QUAD_WITH_3_PIX             = 0x000000f9,
21011 SC_P0_DETAIL_QUAD_WITH_4_PIX             = 0x000000fa,
21012 SC_P1_DETAIL_QUAD_WITH_1_PIX             = 0x000000fb,
21013 SC_P1_DETAIL_QUAD_WITH_2_PIX             = 0x000000fc,
21014 SC_P1_DETAIL_QUAD_WITH_3_PIX             = 0x000000fd,
21015 SC_P1_DETAIL_QUAD_WITH_4_PIX             = 0x000000fe,
21016 SC_P2_DETAIL_QUAD_WITH_1_PIX             = 0x000000ff,
21017 SC_P2_DETAIL_QUAD_WITH_2_PIX             = 0x00000100,
21018 SC_P2_DETAIL_QUAD_WITH_3_PIX             = 0x00000101,
21019 SC_P2_DETAIL_QUAD_WITH_4_PIX             = 0x00000102,
21020 SC_P3_DETAIL_QUAD_WITH_1_PIX             = 0x00000103,
21021 SC_P3_DETAIL_QUAD_WITH_2_PIX             = 0x00000104,
21022 SC_P3_DETAIL_QUAD_WITH_3_PIX             = 0x00000105,
21023 SC_P3_DETAIL_QUAD_WITH_4_PIX             = 0x00000106,
21024 SC_EARLYZ_QUAD_COUNT                     = 0x00000107,
21025 SC_EARLYZ_QUAD_WITH_1_PIX                = 0x00000108,
21026 SC_EARLYZ_QUAD_WITH_2_PIX                = 0x00000109,
21027 SC_EARLYZ_QUAD_WITH_3_PIX                = 0x0000010a,
21028 SC_EARLYZ_QUAD_WITH_4_PIX                = 0x0000010b,
21029 SC_PKR_QUAD_PER_ROW_H1                   = 0x0000010c,
21030 SC_PKR_QUAD_PER_ROW_H2                   = 0x0000010d,
21031 SC_PKR_4X2_QUAD_SPLIT                    = 0x0000010e,
21032 SC_PKR_4X2_FILL_QUAD                     = 0x0000010f,
21033 SC_PKR_END_OF_VECTOR                     = 0x00000110,
21034 SC_PKR_CONTROL_XFER                      = 0x00000111,
21035 SC_PKR_DBHANG_FORCE_EOV                  = 0x00000112,
21036 SC_REG_SCLK_BUSY                         = 0x00000113,
21037 SC_GRP0_DYN_SCLK_BUSY                    = 0x00000114,
21038 SC_GRP1_DYN_SCLK_BUSY                    = 0x00000115,
21039 SC_GRP2_DYN_SCLK_BUSY                    = 0x00000116,
21040 SC_GRP3_DYN_SCLK_BUSY                    = 0x00000117,
21041 SC_GRP4_DYN_SCLK_BUSY                    = 0x00000118,
21042 SC_PA0_SC_DATA_FIFO_RD                   = 0x00000119,
21043 SC_PA0_SC_DATA_FIFO_WE                   = 0x0000011a,
21044 SC_PA1_SC_DATA_FIFO_RD                   = 0x0000011b,
21045 SC_PA1_SC_DATA_FIFO_WE                   = 0x0000011c,
21046 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES   = 0x0000011d,
21047 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES           = 0x0000011e,
21048 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM      = 0x0000011f,
21049 SC_PS_ARB_STALLED_FROM_BELOW             = 0x00000120,
21050 SC_PS_ARB_STARVED_FROM_ABOVE             = 0x00000121,
21051 SC_PS_ARB_SC_BUSY                        = 0x00000122,
21052 SC_PS_ARB_PA_SC_BUSY                     = 0x00000123,
21053 SC_PA2_SC_DATA_FIFO_RD                   = 0x00000124,
21054 SC_PA2_SC_DATA_FIFO_WE                   = 0x00000125,
21055 SC_PA3_SC_DATA_FIFO_RD                   = 0x00000126,
21056 SC_PA3_SC_DATA_FIFO_WE                   = 0x00000127,
21057 SC_PA_SC_DEALLOC_0_0_WE                  = 0x00000128,
21058 SC_PA_SC_DEALLOC_0_1_WE                  = 0x00000129,
21059 SC_PA_SC_DEALLOC_1_0_WE                  = 0x0000012a,
21060 SC_PA_SC_DEALLOC_1_1_WE                  = 0x0000012b,
21061 SC_PA_SC_DEALLOC_2_0_WE                  = 0x0000012c,
21062 SC_PA_SC_DEALLOC_2_1_WE                  = 0x0000012d,
21063 SC_PA_SC_DEALLOC_3_0_WE                  = 0x0000012e,
21064 SC_PA_SC_DEALLOC_3_1_WE                  = 0x0000012f,
21065 SC_PA0_SC_EOP_WE                         = 0x00000130,
21066 SC_PA0_SC_EOPG_WE                        = 0x00000131,
21067 SC_PA0_SC_EVENT_WE                       = 0x00000132,
21068 SC_PA1_SC_EOP_WE                         = 0x00000133,
21069 SC_PA1_SC_EOPG_WE                        = 0x00000134,
21070 SC_PA1_SC_EVENT_WE                       = 0x00000135,
21071 SC_PA2_SC_EOP_WE                         = 0x00000136,
21072 SC_PA2_SC_EOPG_WE                        = 0x00000137,
21073 SC_PA2_SC_EVENT_WE                       = 0x00000138,
21074 SC_PA3_SC_EOP_WE                         = 0x00000139,
21075 SC_PA3_SC_EOPG_WE                        = 0x0000013a,
21076 SC_PA3_SC_EVENT_WE                       = 0x0000013b,
21077 SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO  = 0x0000013c,
21078 SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH          = 0x0000013d,
21079 SC_PS_ARB_NULL_PRIM_BUBBLE_POP           = 0x0000013e,
21080 SC_PS_ARB_EOP_POP_SYNC_POP               = 0x0000013f,
21081 SC_PS_ARB_EVENT_SYNC_POP                 = 0x00000140,
21082 SC_SC_PS_ENG_MULTICYCLE_BUBBLE           = 0x00000141,
21083 SC_PA0_SC_FPOV_WE                        = 0x00000142,
21084 SC_PA1_SC_FPOV_WE                        = 0x00000143,
21085 SC_PA2_SC_FPOV_WE                        = 0x00000144,
21086 SC_PA3_SC_FPOV_WE                        = 0x00000145,
21087 SC_PA0_SC_LPOV_WE                        = 0x00000146,
21088 SC_PA1_SC_LPOV_WE                        = 0x00000147,
21089 SC_PA2_SC_LPOV_WE                        = 0x00000148,
21090 SC_PA3_SC_LPOV_WE                        = 0x00000149,
21091 SC_SC_SPI_DEALLOC_0_0                    = 0x0000014a,
21092 SC_SC_SPI_DEALLOC_0_1                    = 0x0000014b,
21093 SC_SC_SPI_DEALLOC_0_2                    = 0x0000014c,
21094 SC_SC_SPI_DEALLOC_1_0                    = 0x0000014d,
21095 SC_SC_SPI_DEALLOC_1_1                    = 0x0000014e,
21096 SC_SC_SPI_DEALLOC_1_2                    = 0x0000014f,
21097 SC_SC_SPI_DEALLOC_2_0                    = 0x00000150,
21098 SC_SC_SPI_DEALLOC_2_1                    = 0x00000151,
21099 SC_SC_SPI_DEALLOC_2_2                    = 0x00000152,
21100 SC_SC_SPI_DEALLOC_3_0                    = 0x00000153,
21101 SC_SC_SPI_DEALLOC_3_1                    = 0x00000154,
21102 SC_SC_SPI_DEALLOC_3_2                    = 0x00000155,
21103 SC_SC_SPI_FPOV_0                         = 0x00000156,
21104 SC_SC_SPI_FPOV_1                         = 0x00000157,
21105 SC_SC_SPI_FPOV_2                         = 0x00000158,
21106 SC_SC_SPI_FPOV_3                         = 0x00000159,
21107 SC_SC_SPI_EVENT                          = 0x0000015a,
21108 SC_PS_TS_EVENT_FIFO_PUSH                 = 0x0000015b,
21109 SC_PS_TS_EVENT_FIFO_POP                  = 0x0000015c,
21110 SC_PS_CTX_DONE_FIFO_PUSH                 = 0x0000015d,
21111 SC_PS_CTX_DONE_FIFO_POP                  = 0x0000015e,
21112 SC_MULTICYCLE_BUBBLE_FREEZE              = 0x0000015f,
21113 SC_EOP_SYNC_WINDOW                       = 0x00000160,
21114 SC_PA0_SC_NULL_WE                        = 0x00000161,
21115 SC_PA0_SC_NULL_DEALLOC_WE                = 0x00000162,
21116 SC_PA0_SC_DATA_FIFO_EOPG_RD              = 0x00000163,
21117 SC_PA0_SC_DATA_FIFO_EOP_RD               = 0x00000164,
21118 SC_PA0_SC_DEALLOC_0_RD                   = 0x00000165,
21119 SC_PA0_SC_DEALLOC_1_RD                   = 0x00000166,
21120 SC_PA1_SC_DATA_FIFO_EOPG_RD              = 0x00000167,
21121 SC_PA1_SC_DATA_FIFO_EOP_RD               = 0x00000168,
21122 SC_PA1_SC_DEALLOC_0_RD                   = 0x00000169,
21123 SC_PA1_SC_DEALLOC_1_RD                   = 0x0000016a,
21124 SC_PA1_SC_NULL_WE                        = 0x0000016b,
21125 SC_PA1_SC_NULL_DEALLOC_WE                = 0x0000016c,
21126 SC_PA2_SC_DATA_FIFO_EOPG_RD              = 0x0000016d,
21127 SC_PA2_SC_DATA_FIFO_EOP_RD               = 0x0000016e,
21128 SC_PA2_SC_DEALLOC_0_RD                   = 0x0000016f,
21129 SC_PA2_SC_DEALLOC_1_RD                   = 0x00000170,
21130 SC_PA2_SC_NULL_WE                        = 0x00000171,
21131 SC_PA2_SC_NULL_DEALLOC_WE                = 0x00000172,
21132 SC_PA3_SC_DATA_FIFO_EOPG_RD              = 0x00000173,
21133 SC_PA3_SC_DATA_FIFO_EOP_RD               = 0x00000174,
21134 SC_PA3_SC_DEALLOC_0_RD                   = 0x00000175,
21135 SC_PA3_SC_DEALLOC_1_RD                   = 0x00000176,
21136 SC_PA3_SC_NULL_WE                        = 0x00000177,
21137 SC_PA3_SC_NULL_DEALLOC_WE                = 0x00000178,
21138 SC_PS_PA0_SC_FIFO_EMPTY                  = 0x00000179,
21139 SC_PS_PA0_SC_FIFO_FULL                   = 0x0000017a,
21140 SC_PA0_PS_DATA_SEND                      = 0x0000017b,
21141 SC_PS_PA1_SC_FIFO_EMPTY                  = 0x0000017c,
21142 SC_PS_PA1_SC_FIFO_FULL                   = 0x0000017d,
21143 SC_PA1_PS_DATA_SEND                      = 0x0000017e,
21144 SC_PS_PA2_SC_FIFO_EMPTY                  = 0x0000017f,
21145 SC_PS_PA2_SC_FIFO_FULL                   = 0x00000180,
21146 SC_PA2_PS_DATA_SEND                      = 0x00000181,
21147 SC_PS_PA3_SC_FIFO_EMPTY                  = 0x00000182,
21148 SC_PS_PA3_SC_FIFO_FULL                   = 0x00000183,
21149 SC_PA3_PS_DATA_SEND                      = 0x00000184,
21150 SC_BUSY_PROCESSING_MULTICYCLE_PRIM       = 0x00000185,
21151 SC_BUSY_CNT_NOT_ZERO                     = 0x00000186,
21152 SC_BM_BUSY                               = 0x00000187,
21153 SC_BACKEND_BUSY                          = 0x00000188,
21154 SC_SCF_SCB_INTERFACE_BUSY                = 0x00000189,
21155 SC_SCB_BUSY                              = 0x0000018a,
21156 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY  = 0x0000018b,
21157 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL  = 0x0000018c,
21158 SC_PBB_BIN_HIST_NUM_PRIMS                = 0x0000018d,
21159 SC_PBB_BATCH_HIST_NUM_PRIMS              = 0x0000018e,
21160 SC_PBB_BIN_HIST_NUM_CONTEXTS             = 0x0000018f,
21161 SC_PBB_BATCH_HIST_NUM_CONTEXTS           = 0x00000190,
21162 SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES    = 0x00000191,
21163 SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES  = 0x00000192,
21164 SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS     = 0x00000193,
21165 SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS  = 0x00000194,
21166 SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM      = 0x00000195,
21167 SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW    = 0x00000196,
21168 SC_PBB_BUSY                              = 0x00000197,
21169 SC_PBB_BUSY_AND_RTR                      = 0x00000198,
21170 SC_PBB_STALLS_PA_DUE_TO_NO_TILES         = 0x00000199,
21171 SC_PBB_NUM_BINS                          = 0x0000019a,
21172 SC_PBB_END_OF_BIN                        = 0x0000019b,
21173 SC_PBB_END_OF_BATCH                      = 0x0000019c,
21174 SC_PBB_PRIMBIN_PROCESSED                 = 0x0000019d,
21175 SC_PBB_PRIM_ADDED_TO_BATCH               = 0x0000019e,
21176 SC_PBB_NONBINNED_PRIM                    = 0x0000019f,
21177 SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB       = 0x000001a0,
21178 SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB       = 0x000001a1,
21179 SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION  = 0x000001a2,
21180 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW  = 0x000001a3,
21181 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN  = 0x000001a4,
21182 SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE  = 0x000001a5,
21183 SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE  = 0x000001a6,
21184 SC_PBB_BATCH_BREAK_DUE_TO_PRIM           = 0x000001a7,
21185 SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE     = 0x000001a8,
21186 SC_PBB_BATCH_BREAK_DUE_TO_EVENT          = 0x000001a9,
21187 SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT     = 0x000001aa,
21188 SC_POPS_INTRA_WAVE_OVERLAPS              = 0x000001ab,
21189 SC_POPS_FORCE_EOV                        = 0x000001ac,
21190 SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE  = 0x000001ad,
21191 SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE  = 0x000001ae,
21192 } SC_PERFCNT_SEL;
21193 
21194 /*
21195  * SePairXsel enum
21196  */
21197 
21198 typedef enum SePairXsel {
21199 RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE   = 0x00000000,
21200 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE  = 0x00000001,
21201 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE  = 0x00000002,
21202 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE  = 0x00000003,
21203 RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE  = 0x00000004,
21204 } SePairXsel;
21205 
21206 /*
21207  * SePairYsel enum
21208  */
21209 
21210 typedef enum SePairYsel {
21211 RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE   = 0x00000000,
21212 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE  = 0x00000001,
21213 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE  = 0x00000002,
21214 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE  = 0x00000003,
21215 RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE  = 0x00000004,
21216 } SePairYsel;
21217 
21218 /*
21219  * SePairMap enum
21220  */
21221 
21222 typedef enum SePairMap {
21223 RASTER_CONFIG_SE_PAIR_MAP_0              = 0x00000000,
21224 RASTER_CONFIG_SE_PAIR_MAP_1              = 0x00000001,
21225 RASTER_CONFIG_SE_PAIR_MAP_2              = 0x00000002,
21226 RASTER_CONFIG_SE_PAIR_MAP_3              = 0x00000003,
21227 } SePairMap;
21228 
21229 /*
21230  * SeXsel enum
21231  */
21232 
21233 typedef enum SeXsel {
21234 RASTER_CONFIG_SE_XSEL_8_WIDE_TILE        = 0x00000000,
21235 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE       = 0x00000001,
21236 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE       = 0x00000002,
21237 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE       = 0x00000003,
21238 RASTER_CONFIG_SE_XSEL_128_WIDE_TILE      = 0x00000004,
21239 } SeXsel;
21240 
21241 /*
21242  * SeYsel enum
21243  */
21244 
21245 typedef enum SeYsel {
21246 RASTER_CONFIG_SE_YSEL_8_WIDE_TILE        = 0x00000000,
21247 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE       = 0x00000001,
21248 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE       = 0x00000002,
21249 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE       = 0x00000003,
21250 RASTER_CONFIG_SE_YSEL_128_WIDE_TILE      = 0x00000004,
21251 } SeYsel;
21252 
21253 /*
21254  * SeMap enum
21255  */
21256 
21257 typedef enum SeMap {
21258 RASTER_CONFIG_SE_MAP_0                   = 0x00000000,
21259 RASTER_CONFIG_SE_MAP_1                   = 0x00000001,
21260 RASTER_CONFIG_SE_MAP_2                   = 0x00000002,
21261 RASTER_CONFIG_SE_MAP_3                   = 0x00000003,
21262 } SeMap;
21263 
21264 /*
21265  * ScXsel enum
21266  */
21267 
21268 typedef enum ScXsel {
21269 RASTER_CONFIG_SC_XSEL_8_WIDE_TILE        = 0x00000000,
21270 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE       = 0x00000001,
21271 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE       = 0x00000002,
21272 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE       = 0x00000003,
21273 } ScXsel;
21274 
21275 /*
21276  * ScYsel enum
21277  */
21278 
21279 typedef enum ScYsel {
21280 RASTER_CONFIG_SC_YSEL_8_WIDE_TILE        = 0x00000000,
21281 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE       = 0x00000001,
21282 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE       = 0x00000002,
21283 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE       = 0x00000003,
21284 } ScYsel;
21285 
21286 /*
21287  * ScMap enum
21288  */
21289 
21290 typedef enum ScMap {
21291 RASTER_CONFIG_SC_MAP_0                   = 0x00000000,
21292 RASTER_CONFIG_SC_MAP_1                   = 0x00000001,
21293 RASTER_CONFIG_SC_MAP_2                   = 0x00000002,
21294 RASTER_CONFIG_SC_MAP_3                   = 0x00000003,
21295 } ScMap;
21296 
21297 /*
21298  * PkrXsel2 enum
21299  */
21300 
21301 typedef enum PkrXsel2 {
21302 RASTER_CONFIG_PKR_XSEL2_0                = 0x00000000,
21303 RASTER_CONFIG_PKR_XSEL2_1                = 0x00000001,
21304 RASTER_CONFIG_PKR_XSEL2_2                = 0x00000002,
21305 RASTER_CONFIG_PKR_XSEL2_3                = 0x00000003,
21306 } PkrXsel2;
21307 
21308 /*
21309  * PkrXsel enum
21310  */
21311 
21312 typedef enum PkrXsel {
21313 RASTER_CONFIG_PKR_XSEL_0                 = 0x00000000,
21314 RASTER_CONFIG_PKR_XSEL_1                 = 0x00000001,
21315 RASTER_CONFIG_PKR_XSEL_2                 = 0x00000002,
21316 RASTER_CONFIG_PKR_XSEL_3                 = 0x00000003,
21317 } PkrXsel;
21318 
21319 /*
21320  * PkrYsel enum
21321  */
21322 
21323 typedef enum PkrYsel {
21324 RASTER_CONFIG_PKR_YSEL_0                 = 0x00000000,
21325 RASTER_CONFIG_PKR_YSEL_1                 = 0x00000001,
21326 RASTER_CONFIG_PKR_YSEL_2                 = 0x00000002,
21327 RASTER_CONFIG_PKR_YSEL_3                 = 0x00000003,
21328 } PkrYsel;
21329 
21330 /*
21331  * PkrMap enum
21332  */
21333 
21334 typedef enum PkrMap {
21335 RASTER_CONFIG_PKR_MAP_0                  = 0x00000000,
21336 RASTER_CONFIG_PKR_MAP_1                  = 0x00000001,
21337 RASTER_CONFIG_PKR_MAP_2                  = 0x00000002,
21338 RASTER_CONFIG_PKR_MAP_3                  = 0x00000003,
21339 } PkrMap;
21340 
21341 /*
21342  * RbXsel enum
21343  */
21344 
21345 typedef enum RbXsel {
21346 RASTER_CONFIG_RB_XSEL_0                  = 0x00000000,
21347 RASTER_CONFIG_RB_XSEL_1                  = 0x00000001,
21348 } RbXsel;
21349 
21350 /*
21351  * RbYsel enum
21352  */
21353 
21354 typedef enum RbYsel {
21355 RASTER_CONFIG_RB_YSEL_0                  = 0x00000000,
21356 RASTER_CONFIG_RB_YSEL_1                  = 0x00000001,
21357 } RbYsel;
21358 
21359 /*
21360  * RbXsel2 enum
21361  */
21362 
21363 typedef enum RbXsel2 {
21364 RASTER_CONFIG_RB_XSEL2_0                 = 0x00000000,
21365 RASTER_CONFIG_RB_XSEL2_1                 = 0x00000001,
21366 RASTER_CONFIG_RB_XSEL2_2                 = 0x00000002,
21367 RASTER_CONFIG_RB_XSEL2_3                 = 0x00000003,
21368 } RbXsel2;
21369 
21370 /*
21371  * RbMap enum
21372  */
21373 
21374 typedef enum RbMap {
21375 RASTER_CONFIG_RB_MAP_0                   = 0x00000000,
21376 RASTER_CONFIG_RB_MAP_1                   = 0x00000001,
21377 RASTER_CONFIG_RB_MAP_2                   = 0x00000002,
21378 RASTER_CONFIG_RB_MAP_3                   = 0x00000003,
21379 } RbMap;
21380 
21381 /*
21382  * BinningMode enum
21383  */
21384 
21385 typedef enum BinningMode {
21386 BINNING_ALLOWED                          = 0x00000000,
21387 FORCE_BINNING_ON                         = 0x00000001,
21388 DISABLE_BINNING_USE_NEW_SC               = 0x00000002,
21389 DISABLE_BINNING_USE_LEGACY_SC            = 0x00000003,
21390 } BinningMode;
21391 
21392 /*
21393  * BinEventCntl enum
21394  */
21395 
21396 typedef enum BinEventCntl {
21397 BINNER_BREAK_BATCH                       = 0x00000000,
21398 BINNER_PIPELINE                          = 0x00000001,
21399 BINNER_DROP_ASSERT                       = 0x00000002,
21400 } BinEventCntl;
21401 
21402 /*
21403  * CovToShaderSel enum
21404  */
21405 
21406 typedef enum CovToShaderSel {
21407 INPUT_COVERAGE                           = 0x00000000,
21408 INPUT_INNER_COVERAGE                     = 0x00000001,
21409 INPUT_DEPTH_COVERAGE                     = 0x00000002,
21410 #ifndef __NetBSD__		/* XXX @!#&* */
21411 RAW                                      = 0x00000003,
21412 #endif
21413 } CovToShaderSel;
21414 
21415 /*******************************************************
21416  * RMI Enums
21417  *******************************************************/
21418 
21419 /*
21420  * RMIPerfSel enum
21421  */
21422 
21423 typedef enum RMIPerfSel {
21424 RMI_PERF_SEL_NONE                        = 0x00000000,
21425 RMI_PERF_SEL_BUSY                        = 0x00000001,
21426 RMI_PERF_SEL_REG_CLK_VLD                 = 0x00000002,
21427 RMI_PERF_SEL_DYN_CLK_CMN_VLD             = 0x00000003,
21428 RMI_PERF_SEL_DYN_CLK_RB_VLD              = 0x00000004,
21429 RMI_PERF_SEL_DYN_CLK_PERF_VLD            = 0x00000005,
21430 RMI_PERF_SEL_PERF_WINDOW                 = 0x00000006,
21431 RMI_PERF_SEL_EVENT_SEND                  = 0x00000007,
21432 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008,
21433 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009,
21434 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a,
21435 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b,
21436 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c,
21437 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d,
21438 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e,
21439 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f,
21440 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010,
21441 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011,
21442 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012,
21443 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013,
21444 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014,
21445 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015,
21446 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016,
21447 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017,
21448 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018,
21449 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019,
21450 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a,
21451 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b,
21452 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c,
21453 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d,
21454 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e,
21455 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f,
21456 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020,
21457 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021,
21458 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022,
21459 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023,
21460 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024,
21461 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025,
21462 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026,
21463 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027,
21464 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028,
21465 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029,
21466 RMI_PERF_SEL_UTCL1_TRANSLATION_MISS      = 0x0000002a,
21467 RMI_PERF_SEL_UTCL1_PERMISSION_MISS       = 0x0000002b,
21468 RMI_PERF_SEL_UTCL1_REQUEST               = 0x0000002c,
21469 RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX    = 0x0000002d,
21470 RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT    = 0x0000002e,
21471 RMI_PERF_SEL_UTCL1_LFIFO_FULL            = 0x0000002f,
21472 RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES   = 0x00000030,
21473 RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x00000031,
21474 RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL   = 0x00000032,
21475 RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL         = 0x00000033,
21476 RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS      = 0x00000034,
21477 RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID        = 0x00000035,
21478 RMI_PERF_SEL_RB_RMI_WRREQ_BUSY           = 0x00000036,
21479 RMI_PERF_SEL_RB_RMI_WRREQ_CID0           = 0x00000037,
21480 RMI_PERF_SEL_RB_RMI_WRREQ_CID1           = 0x00000038,
21481 RMI_PERF_SEL_RB_RMI_WRREQ_CID2           = 0x00000039,
21482 RMI_PERF_SEL_RB_RMI_WRREQ_CID3           = 0x0000003a,
21483 RMI_PERF_SEL_RB_RMI_WRREQ_CID4           = 0x0000003b,
21484 RMI_PERF_SEL_RB_RMI_WRREQ_CID5           = 0x0000003c,
21485 RMI_PERF_SEL_RB_RMI_WRREQ_CID6           = 0x0000003d,
21486 RMI_PERF_SEL_RB_RMI_WRREQ_CID7           = 0x0000003e,
21487 RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 0x0000003f,
21488 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000040,
21489 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000041,
21490 RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY      = 0x00000042,
21491 RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID  = 0x00000043,
21492 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0     = 0x00000044,
21493 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1     = 0x00000045,
21494 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2     = 0x00000046,
21495 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3     = 0x00000047,
21496 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4     = 0x00000048,
21497 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5     = 0x00000049,
21498 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6     = 0x0000004a,
21499 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7     = 0x0000004b,
21500 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0    = 0x0000004c,
21501 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1    = 0x0000004d,
21502 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2    = 0x0000004e,
21503 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3    = 0x0000004f,
21504 RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID     = 0x00000050,
21505 RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID        = 0x00000051,
21506 RMI_PERF_SEL_RB_RMI_RDREQ_BUSY           = 0x00000052,
21507 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0        = 0x00000053,
21508 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1        = 0x00000054,
21509 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2        = 0x00000055,
21510 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3        = 0x00000056,
21511 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4        = 0x00000057,
21512 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5        = 0x00000058,
21513 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6        = 0x00000059,
21514 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7        = 0x0000005a,
21515 RMI_PERF_SEL_RB_RMI_RDREQ_CID0           = 0x0000005b,
21516 RMI_PERF_SEL_RB_RMI_RDREQ_CID1           = 0x0000005c,
21517 RMI_PERF_SEL_RB_RMI_RDREQ_CID2           = 0x0000005d,
21518 RMI_PERF_SEL_RB_RMI_RDREQ_CID3           = 0x0000005e,
21519 RMI_PERF_SEL_RB_RMI_RDREQ_CID4           = 0x0000005f,
21520 RMI_PERF_SEL_RB_RMI_RDREQ_CID5           = 0x00000060,
21521 RMI_PERF_SEL_RB_RMI_RDREQ_CID6           = 0x00000061,
21522 RMI_PERF_SEL_RB_RMI_RDREQ_CID7           = 0x00000062,
21523 RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000063,
21524 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000064,
21525 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000065,
21526 RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY      = 0x00000066,
21527 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000067,
21528 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0  = 0x00000068,
21529 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1  = 0x00000069,
21530 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2  = 0x0000006a,
21531 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3  = 0x0000006b,
21532 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4  = 0x0000006c,
21533 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5  = 0x0000006d,
21534 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6  = 0x0000006e,
21535 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7  = 0x0000006f,
21536 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000070,
21537 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000071,
21538 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000072,
21539 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000073,
21540 RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID        = 0x00000074,
21541 RMI_PERF_SEL_RMI_TC_REQ_BUSY             = 0x00000075,
21542 RMI_PERF_SEL_RMI_TC_WRREQ_CID0           = 0x00000076,
21543 RMI_PERF_SEL_RMI_TC_WRREQ_CID1           = 0x00000077,
21544 RMI_PERF_SEL_RMI_TC_WRREQ_CID2           = 0x00000078,
21545 RMI_PERF_SEL_RMI_TC_WRREQ_CID3           = 0x00000079,
21546 RMI_PERF_SEL_RMI_TC_WRREQ_CID4           = 0x0000007a,
21547 RMI_PERF_SEL_RMI_TC_WRREQ_CID5           = 0x0000007b,
21548 RMI_PERF_SEL_RMI_TC_WRREQ_CID6           = 0x0000007c,
21549 RMI_PERF_SEL_RMI_TC_WRREQ_CID7           = 0x0000007d,
21550 RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000007e,
21551 RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID  = 0x0000007f,
21552 RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID        = 0x00000080,
21553 RMI_PERF_SEL_RMI_TC_RDREQ_CID0           = 0x00000081,
21554 RMI_PERF_SEL_RMI_TC_RDREQ_CID1           = 0x00000082,
21555 RMI_PERF_SEL_RMI_TC_RDREQ_CID2           = 0x00000083,
21556 RMI_PERF_SEL_RMI_TC_RDREQ_CID3           = 0x00000084,
21557 RMI_PERF_SEL_RMI_TC_RDREQ_CID4           = 0x00000085,
21558 RMI_PERF_SEL_RMI_TC_RDREQ_CID5           = 0x00000086,
21559 RMI_PERF_SEL_RMI_TC_RDREQ_CID6           = 0x00000087,
21560 RMI_PERF_SEL_RMI_TC_RDREQ_CID7           = 0x00000088,
21561 RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000089,
21562 RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID  = 0x0000008a,
21563 RMI_PERF_SEL_UTCL1_BUSY                  = 0x0000008b,
21564 RMI_PERF_SEL_RMI_UTC_REQ                 = 0x0000008c,
21565 RMI_PERF_SEL_RMI_UTC_BUSY                = 0x0000008d,
21566 RMI_PERF_SEL_UTCL1_UTCL2_REQ             = 0x0000008e,
21567 RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY     = 0x0000008f,
21568 RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT       = 0x00000090,
21569 RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT       = 0x00000091,
21570 RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x00000092,
21571 RMI_PERF_SEL_XNACK_FIFO_NUM_USED         = 0x00000093,
21572 RMI_PERF_SEL_LAT_FIFO_NUM_USED           = 0x00000094,
21573 RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ       = 0x00000095,
21574 RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ    = 0x00000096,
21575 RMI_PERF_SEL_XNACK_FIFO_FULL             = 0x00000097,
21576 RMI_PERF_SEL_XNACK_FIFO_BUSY             = 0x00000098,
21577 RMI_PERF_SEL_LAT_FIFO_FULL               = 0x00000099,
21578 RMI_PERF_SEL_SKID_FIFO_DEPTH             = 0x0000009a,
21579 RMI_PERF_SEL_TCIW_INFLIGHT_COUNT         = 0x0000009b,
21580 RMI_PERF_SEL_PRT_FIFO_NUM_USED           = 0x0000009c,
21581 RMI_PERF_SEL_PRT_FIFO_REQ                = 0x0000009d,
21582 RMI_PERF_SEL_PRT_FIFO_BUSY               = 0x0000009e,
21583 RMI_PERF_SEL_TCIW_REQ                    = 0x0000009f,
21584 RMI_PERF_SEL_TCIW_BUSY                   = 0x000000a0,
21585 RMI_PERF_SEL_SKID_FIFO_REQ               = 0x000000a1,
21586 RMI_PERF_SEL_SKID_FIFO_BUSY              = 0x000000a2,
21587 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0  = 0x000000a3,
21588 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1  = 0x000000a4,
21589 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2  = 0x000000a5,
21590 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3  = 0x000000a6,
21591 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR       = 0x000000a7,
21592 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR      = 0x000000a8,
21593 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB      = 0x000000a9,
21594 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB     = 0x000000aa,
21595 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000ab,
21596 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000ac,
21597 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000ad,
21598 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000ae,
21599 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000af,
21600 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000b0,
21601 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000b1,
21602 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000b2,
21603 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000b3,
21604 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000b4,
21605 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000b5,
21606 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000b6,
21607 RMI_PERF_SEL_POP_DEMUX_RTS_RTR           = 0x000000b7,
21608 RMI_PERF_SEL_POP_DEMUX_RTSB_RTR          = 0x000000b8,
21609 RMI_PERF_SEL_POP_DEMUX_RTS_RTRB          = 0x000000b9,
21610 RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB         = 0x000000ba,
21611 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR        = 0x000000bb,
21612 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR       = 0x000000bc,
21613 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB       = 0x000000bd,
21614 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB      = 0x000000be,
21615 RMI_PERF_SEL_UTC_POP_RTS_RTR             = 0x000000bf,
21616 RMI_PERF_SEL_UTC_POP_RTSB_RTR            = 0x000000c0,
21617 RMI_PERF_SEL_UTC_POP_RTS_RTRB            = 0x000000c1,
21618 RMI_PERF_SEL_UTC_POP_RTSB_RTRB           = 0x000000c2,
21619 RMI_PERF_SEL_POP_XNACK_RTS_RTR           = 0x000000c3,
21620 RMI_PERF_SEL_POP_XNACK_RTSB_RTR          = 0x000000c4,
21621 RMI_PERF_SEL_POP_XNACK_RTS_RTRB          = 0x000000c5,
21622 RMI_PERF_SEL_POP_XNACK_RTSB_RTRB         = 0x000000c6,
21623 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR      = 0x000000c7,
21624 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR     = 0x000000c8,
21625 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB     = 0x000000c9,
21626 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB    = 0x000000ca,
21627 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000cb,
21628 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000cc,
21629 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000cd,
21630 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000ce,
21631 RMI_PERF_SEL_SKID_FIFO_IN_RTS            = 0x000000cf,
21632 RMI_PERF_SEL_SKID_FIFO_IN_RTSB           = 0x000000d0,
21633 RMI_PERF_SEL_SKID_FIFO_OUT_RTS           = 0x000000d1,
21634 RMI_PERF_SEL_SKID_FIFO_OUT_RTSB          = 0x000000d2,
21635 RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR  = 0x000000d3,
21636 RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000d4,
21637 RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR   = 0x000000d5,
21638 RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR   = 0x000000d6,
21639 RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR    = 0x000000d7,
21640 RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR    = 0x000000d8,
21641 RMI_PERF_SEL_REORDER_FIFO_REQ            = 0x000000d9,
21642 RMI_PERF_SEL_REORDER_FIFO_BUSY           = 0x000000da,
21643 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID  = 0x000000db,
21644 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0     = 0x000000dc,
21645 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1     = 0x000000dd,
21646 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2     = 0x000000de,
21647 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3     = 0x000000df,
21648 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4     = 0x000000e0,
21649 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5     = 0x000000e1,
21650 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6     = 0x000000e2,
21651 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7     = 0x000000e3,
21652 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0    = 0x000000e4,
21653 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1    = 0x000000e5,
21654 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2    = 0x000000e6,
21655 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3    = 0x000000e7,
21656 } RMIPerfSel;
21657 
21658 /*******************************************************
21659  * IH Enums
21660  *******************************************************/
21661 
21662 /*
21663  * IH_PERF_SEL enum
21664  */
21665 
21666 typedef enum IH_PERF_SEL {
21667 IH_PERF_SEL_CYCLE                        = 0x00000000,
21668 IH_PERF_SEL_IDLE                         = 0x00000001,
21669 IH_PERF_SEL_INPUT_IDLE                   = 0x00000002,
21670 IH_PERF_SEL_BUFFER_IDLE                  = 0x00000003,
21671 IH_PERF_SEL_RB0_FULL                     = 0x00000004,
21672 IH_PERF_SEL_RB0_OVERFLOW                 = 0x00000005,
21673 IH_PERF_SEL_RB0_WPTR_WRITEBACK           = 0x00000006,
21674 IH_PERF_SEL_RB0_WPTR_WRAP                = 0x00000007,
21675 IH_PERF_SEL_RB0_RPTR_WRAP                = 0x00000008,
21676 IH_PERF_SEL_MC_WR_IDLE                   = 0x00000009,
21677 IH_PERF_SEL_MC_WR_COUNT                  = 0x0000000a,
21678 IH_PERF_SEL_MC_WR_STALL                  = 0x0000000b,
21679 IH_PERF_SEL_MC_WR_CLEAN_PENDING          = 0x0000000c,
21680 IH_PERF_SEL_MC_WR_CLEAN_STALL            = 0x0000000d,
21681 IH_PERF_SEL_BIF_LINE0_RISING             = 0x0000000e,
21682 IH_PERF_SEL_BIF_LINE0_FALLING            = 0x0000000f,
21683 IH_PERF_SEL_RB1_FULL                     = 0x00000010,
21684 IH_PERF_SEL_RB1_OVERFLOW                 = 0x00000011,
21685 Reserved18                               = 0x00000012,
21686 IH_PERF_SEL_RB1_WPTR_WRAP                = 0x00000013,
21687 IH_PERF_SEL_RB1_RPTR_WRAP                = 0x00000014,
21688 IH_PERF_SEL_RB2_FULL                     = 0x00000015,
21689 IH_PERF_SEL_RB2_OVERFLOW                 = 0x00000016,
21690 Reserved23                               = 0x00000017,
21691 IH_PERF_SEL_RB2_WPTR_WRAP                = 0x00000018,
21692 IH_PERF_SEL_RB2_RPTR_WRAP                = 0x00000019,
21693 Reserved26                               = 0x0000001a,
21694 Reserved27                               = 0x0000001b,
21695 Reserved28                               = 0x0000001c,
21696 Reserved29                               = 0x0000001d,
21697 IH_PERF_SEL_RB0_FULL_VF0                 = 0x0000001e,
21698 IH_PERF_SEL_RB0_FULL_VF1                 = 0x0000001f,
21699 IH_PERF_SEL_RB0_FULL_VF2                 = 0x00000020,
21700 IH_PERF_SEL_RB0_FULL_VF3                 = 0x00000021,
21701 IH_PERF_SEL_RB0_FULL_VF4                 = 0x00000022,
21702 IH_PERF_SEL_RB0_FULL_VF5                 = 0x00000023,
21703 IH_PERF_SEL_RB0_FULL_VF6                 = 0x00000024,
21704 IH_PERF_SEL_RB0_FULL_VF7                 = 0x00000025,
21705 IH_PERF_SEL_RB0_FULL_VF8                 = 0x00000026,
21706 IH_PERF_SEL_RB0_FULL_VF9                 = 0x00000027,
21707 IH_PERF_SEL_RB0_FULL_VF10                = 0x00000028,
21708 IH_PERF_SEL_RB0_FULL_VF11                = 0x00000029,
21709 IH_PERF_SEL_RB0_FULL_VF12                = 0x0000002a,
21710 IH_PERF_SEL_RB0_FULL_VF13                = 0x0000002b,
21711 IH_PERF_SEL_RB0_FULL_VF14                = 0x0000002c,
21712 IH_PERF_SEL_RB0_FULL_VF15                = 0x0000002d,
21713 IH_PERF_SEL_RB0_OVERFLOW_VF0             = 0x0000002e,
21714 IH_PERF_SEL_RB0_OVERFLOW_VF1             = 0x0000002f,
21715 IH_PERF_SEL_RB0_OVERFLOW_VF2             = 0x00000030,
21716 IH_PERF_SEL_RB0_OVERFLOW_VF3             = 0x00000031,
21717 IH_PERF_SEL_RB0_OVERFLOW_VF4             = 0x00000032,
21718 IH_PERF_SEL_RB0_OVERFLOW_VF5             = 0x00000033,
21719 IH_PERF_SEL_RB0_OVERFLOW_VF6             = 0x00000034,
21720 IH_PERF_SEL_RB0_OVERFLOW_VF7             = 0x00000035,
21721 IH_PERF_SEL_RB0_OVERFLOW_VF8             = 0x00000036,
21722 IH_PERF_SEL_RB0_OVERFLOW_VF9             = 0x00000037,
21723 IH_PERF_SEL_RB0_OVERFLOW_VF10            = 0x00000038,
21724 IH_PERF_SEL_RB0_OVERFLOW_VF11            = 0x00000039,
21725 IH_PERF_SEL_RB0_OVERFLOW_VF12            = 0x0000003a,
21726 IH_PERF_SEL_RB0_OVERFLOW_VF13            = 0x0000003b,
21727 IH_PERF_SEL_RB0_OVERFLOW_VF14            = 0x0000003c,
21728 IH_PERF_SEL_RB0_OVERFLOW_VF15            = 0x0000003d,
21729 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0       = 0x0000003e,
21730 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1       = 0x0000003f,
21731 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2       = 0x00000040,
21732 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3       = 0x00000041,
21733 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4       = 0x00000042,
21734 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5       = 0x00000043,
21735 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6       = 0x00000044,
21736 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7       = 0x00000045,
21737 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8       = 0x00000046,
21738 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9       = 0x00000047,
21739 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10      = 0x00000048,
21740 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11      = 0x00000049,
21741 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12      = 0x0000004a,
21742 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13      = 0x0000004b,
21743 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14      = 0x0000004c,
21744 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15      = 0x0000004d,
21745 IH_PERF_SEL_RB0_WPTR_WRAP_VF0            = 0x0000004e,
21746 IH_PERF_SEL_RB0_WPTR_WRAP_VF1            = 0x0000004f,
21747 IH_PERF_SEL_RB0_WPTR_WRAP_VF2            = 0x00000050,
21748 IH_PERF_SEL_RB0_WPTR_WRAP_VF3            = 0x00000051,
21749 IH_PERF_SEL_RB0_WPTR_WRAP_VF4            = 0x00000052,
21750 IH_PERF_SEL_RB0_WPTR_WRAP_VF5            = 0x00000053,
21751 IH_PERF_SEL_RB0_WPTR_WRAP_VF6            = 0x00000054,
21752 IH_PERF_SEL_RB0_WPTR_WRAP_VF7            = 0x00000055,
21753 IH_PERF_SEL_RB0_WPTR_WRAP_VF8            = 0x00000056,
21754 IH_PERF_SEL_RB0_WPTR_WRAP_VF9            = 0x00000057,
21755 IH_PERF_SEL_RB0_WPTR_WRAP_VF10           = 0x00000058,
21756 IH_PERF_SEL_RB0_WPTR_WRAP_VF11           = 0x00000059,
21757 IH_PERF_SEL_RB0_WPTR_WRAP_VF12           = 0x0000005a,
21758 IH_PERF_SEL_RB0_WPTR_WRAP_VF13           = 0x0000005b,
21759 IH_PERF_SEL_RB0_WPTR_WRAP_VF14           = 0x0000005c,
21760 IH_PERF_SEL_RB0_WPTR_WRAP_VF15           = 0x0000005d,
21761 IH_PERF_SEL_RB0_RPTR_WRAP_VF0            = 0x0000005e,
21762 IH_PERF_SEL_RB0_RPTR_WRAP_VF1            = 0x0000005f,
21763 IH_PERF_SEL_RB0_RPTR_WRAP_VF2            = 0x00000060,
21764 IH_PERF_SEL_RB0_RPTR_WRAP_VF3            = 0x00000061,
21765 IH_PERF_SEL_RB0_RPTR_WRAP_VF4            = 0x00000062,
21766 IH_PERF_SEL_RB0_RPTR_WRAP_VF5            = 0x00000063,
21767 IH_PERF_SEL_RB0_RPTR_WRAP_VF6            = 0x00000064,
21768 IH_PERF_SEL_RB0_RPTR_WRAP_VF7            = 0x00000065,
21769 IH_PERF_SEL_RB0_RPTR_WRAP_VF8            = 0x00000066,
21770 IH_PERF_SEL_RB0_RPTR_WRAP_VF9            = 0x00000067,
21771 IH_PERF_SEL_RB0_RPTR_WRAP_VF10           = 0x00000068,
21772 IH_PERF_SEL_RB0_RPTR_WRAP_VF11           = 0x00000069,
21773 IH_PERF_SEL_RB0_RPTR_WRAP_VF12           = 0x0000006a,
21774 IH_PERF_SEL_RB0_RPTR_WRAP_VF13           = 0x0000006b,
21775 IH_PERF_SEL_RB0_RPTR_WRAP_VF14           = 0x0000006c,
21776 IH_PERF_SEL_RB0_RPTR_WRAP_VF15           = 0x0000006d,
21777 IH_PERF_SEL_BIF_LINE0_RISING_VF0         = 0x0000006e,
21778 IH_PERF_SEL_BIF_LINE0_RISING_VF1         = 0x0000006f,
21779 IH_PERF_SEL_BIF_LINE0_RISING_VF2         = 0x00000070,
21780 IH_PERF_SEL_BIF_LINE0_RISING_VF3         = 0x00000071,
21781 IH_PERF_SEL_BIF_LINE0_RISING_VF4         = 0x00000072,
21782 IH_PERF_SEL_BIF_LINE0_RISING_VF5         = 0x00000073,
21783 IH_PERF_SEL_BIF_LINE0_RISING_VF6         = 0x00000074,
21784 IH_PERF_SEL_BIF_LINE0_RISING_VF7         = 0x00000075,
21785 IH_PERF_SEL_BIF_LINE0_RISING_VF8         = 0x00000076,
21786 IH_PERF_SEL_BIF_LINE0_RISING_VF9         = 0x00000077,
21787 IH_PERF_SEL_BIF_LINE0_RISING_VF10        = 0x00000078,
21788 IH_PERF_SEL_BIF_LINE0_RISING_VF11        = 0x00000079,
21789 IH_PERF_SEL_BIF_LINE0_RISING_VF12        = 0x0000007a,
21790 IH_PERF_SEL_BIF_LINE0_RISING_VF13        = 0x0000007b,
21791 IH_PERF_SEL_BIF_LINE0_RISING_VF14        = 0x0000007c,
21792 IH_PERF_SEL_BIF_LINE0_RISING_VF15        = 0x0000007d,
21793 IH_PERF_SEL_BIF_LINE0_FALLING_VF0        = 0x0000007e,
21794 IH_PERF_SEL_BIF_LINE0_FALLING_VF1        = 0x0000007f,
21795 IH_PERF_SEL_BIF_LINE0_FALLING_VF2        = 0x00000080,
21796 IH_PERF_SEL_BIF_LINE0_FALLING_VF3        = 0x00000081,
21797 IH_PERF_SEL_BIF_LINE0_FALLING_VF4        = 0x00000082,
21798 IH_PERF_SEL_BIF_LINE0_FALLING_VF5        = 0x00000083,
21799 IH_PERF_SEL_BIF_LINE0_FALLING_VF6        = 0x00000084,
21800 IH_PERF_SEL_BIF_LINE0_FALLING_VF7        = 0x00000085,
21801 IH_PERF_SEL_BIF_LINE0_FALLING_VF8        = 0x00000086,
21802 IH_PERF_SEL_BIF_LINE0_FALLING_VF9        = 0x00000087,
21803 IH_PERF_SEL_BIF_LINE0_FALLING_VF10       = 0x00000088,
21804 IH_PERF_SEL_BIF_LINE0_FALLING_VF11       = 0x00000089,
21805 IH_PERF_SEL_BIF_LINE0_FALLING_VF12       = 0x0000008a,
21806 IH_PERF_SEL_BIF_LINE0_FALLING_VF13       = 0x0000008b,
21807 IH_PERF_SEL_BIF_LINE0_FALLING_VF14       = 0x0000008c,
21808 IH_PERF_SEL_BIF_LINE0_FALLING_VF15       = 0x0000008d,
21809 Reserved142                              = 0x0000008e,
21810 Reserved143                              = 0x0000008f,
21811 Reserved144                              = 0x00000090,
21812 Reserved145                              = 0x00000091,
21813 Reserved146                              = 0x00000092,
21814 Reserved147                              = 0x00000093,
21815 Reserved148                              = 0x00000094,
21816 Reserved149                              = 0x00000095,
21817 IH_PERF_SEL_CLIENT0_INT                  = 0x00000096,
21818 IH_PERF_SEL_CLIENT1_INT                  = 0x00000097,
21819 IH_PERF_SEL_CLIENT2_INT                  = 0x00000098,
21820 IH_PERF_SEL_CLIENT3_INT                  = 0x00000099,
21821 IH_PERF_SEL_CLIENT4_INT                  = 0x0000009a,
21822 IH_PERF_SEL_CLIENT5_INT                  = 0x0000009b,
21823 IH_PERF_SEL_CLIENT6_INT                  = 0x0000009c,
21824 IH_PERF_SEL_CLIENT7_INT                  = 0x0000009d,
21825 IH_PERF_SEL_CLIENT8_INT                  = 0x0000009e,
21826 IH_PERF_SEL_CLIENT9_INT                  = 0x0000009f,
21827 IH_PERF_SEL_CLIENT10_INT                 = 0x000000a0,
21828 IH_PERF_SEL_CLIENT11_INT                 = 0x000000a1,
21829 IH_PERF_SEL_CLIENT12_INT                 = 0x000000a2,
21830 IH_PERF_SEL_CLIENT13_INT                 = 0x000000a3,
21831 IH_PERF_SEL_CLIENT14_INT                 = 0x000000a4,
21832 IH_PERF_SEL_CLIENT15_INT                 = 0x000000a5,
21833 IH_PERF_SEL_CLIENT16_INT                 = 0x000000a6,
21834 IH_PERF_SEL_CLIENT17_INT                 = 0x000000a7,
21835 IH_PERF_SEL_CLIENT18_INT                 = 0x000000a8,
21836 IH_PERF_SEL_CLIENT19_INT                 = 0x000000a9,
21837 IH_PERF_SEL_CLIENT20_INT                 = 0x000000aa,
21838 IH_PERF_SEL_CLIENT21_INT                 = 0x000000ab,
21839 IH_PERF_SEL_CLIENT22_INT                 = 0x000000ac,
21840 IH_PERF_SEL_CLIENT23_INT                 = 0x000000ad,
21841 IH_PERF_SEL_CLIENT24_INT                 = 0x000000ae,
21842 IH_PERF_SEL_CLIENT25_INT                 = 0x000000af,
21843 IH_PERF_SEL_CLIENT26_INT                 = 0x000000b0,
21844 IH_PERF_SEL_CLIENT27_INT                 = 0x000000b1,
21845 IH_PERF_SEL_CLIENT28_INT                 = 0x000000b2,
21846 IH_PERF_SEL_CLIENT29_INT                 = 0x000000b3,
21847 IH_PERF_SEL_CLIENT30_INT                 = 0x000000b4,
21848 IH_PERF_SEL_CLIENT31_INT                 = 0x000000b5,
21849 Reserved182                              = 0x000000b6,
21850 Reserved183                              = 0x000000b7,
21851 Reserved184                              = 0x000000b8,
21852 Reserved185                              = 0x000000b9,
21853 Reserved186                              = 0x000000ba,
21854 Reserved187                              = 0x000000bb,
21855 Reserved188                              = 0x000000bc,
21856 Reserved189                              = 0x000000bd,
21857 Reserved190                              = 0x000000be,
21858 Reserved191                              = 0x000000bf,
21859 Reserved192                              = 0x000000c0,
21860 Reserved193                              = 0x000000c1,
21861 Reserved194                              = 0x000000c2,
21862 Reserved195                              = 0x000000c3,
21863 Reserved196                              = 0x000000c4,
21864 Reserved197                              = 0x000000c5,
21865 Reserved198                              = 0x000000c6,
21866 Reserved199                              = 0x000000c7,
21867 Reserved200                              = 0x000000c8,
21868 Reserved201                              = 0x000000c9,
21869 Reserved202                              = 0x000000ca,
21870 Reserved203                              = 0x000000cb,
21871 Reserved204                              = 0x000000cc,
21872 Reserved205                              = 0x000000cd,
21873 Reserved206                              = 0x000000ce,
21874 Reserved207                              = 0x000000cf,
21875 Reserved208                              = 0x000000d0,
21876 Reserved209                              = 0x000000d1,
21877 Reserved210                              = 0x000000d2,
21878 Reserved211                              = 0x000000d3,
21879 Reserved212                              = 0x000000d4,
21880 Reserved213                              = 0x000000d5,
21881 Reserved214                              = 0x000000d6,
21882 Reserved215                              = 0x000000d7,
21883 Reserved216                              = 0x000000d8,
21884 Reserved217                              = 0x000000d9,
21885 Reserved218                              = 0x000000da,
21886 Reserved219                              = 0x000000db,
21887 IH_PERF_SEL_RB1_FULL_VF0                 = 0x000000dc,
21888 IH_PERF_SEL_RB1_FULL_VF1                 = 0x000000dd,
21889 IH_PERF_SEL_RB1_FULL_VF2                 = 0x000000de,
21890 IH_PERF_SEL_RB1_FULL_VF3                 = 0x000000df,
21891 IH_PERF_SEL_RB1_FULL_VF4                 = 0x000000e0,
21892 IH_PERF_SEL_RB1_FULL_VF5                 = 0x000000e1,
21893 IH_PERF_SEL_RB1_FULL_VF6                 = 0x000000e2,
21894 IH_PERF_SEL_RB1_FULL_VF7                 = 0x000000e3,
21895 IH_PERF_SEL_RB1_FULL_VF8                 = 0x000000e4,
21896 IH_PERF_SEL_RB1_FULL_VF9                 = 0x000000e5,
21897 IH_PERF_SEL_RB1_FULL_VF10                = 0x000000e6,
21898 IH_PERF_SEL_RB1_FULL_VF11                = 0x000000e7,
21899 IH_PERF_SEL_RB1_FULL_VF12                = 0x000000e8,
21900 IH_PERF_SEL_RB1_FULL_VF13                = 0x000000e9,
21901 IH_PERF_SEL_RB1_FULL_VF14                = 0x000000ea,
21902 IH_PERF_SEL_RB1_FULL_VF15                = 0x000000eb,
21903 IH_PERF_SEL_RB1_OVERFLOW_VF0             = 0x000000ec,
21904 IH_PERF_SEL_RB1_OVERFLOW_VF1             = 0x000000ed,
21905 IH_PERF_SEL_RB1_OVERFLOW_VF2             = 0x000000ee,
21906 IH_PERF_SEL_RB1_OVERFLOW_VF3             = 0x000000ef,
21907 IH_PERF_SEL_RB1_OVERFLOW_VF4             = 0x000000f0,
21908 IH_PERF_SEL_RB1_OVERFLOW_VF5             = 0x000000f1,
21909 IH_PERF_SEL_RB1_OVERFLOW_VF6             = 0x000000f2,
21910 IH_PERF_SEL_RB1_OVERFLOW_VF7             = 0x000000f3,
21911 IH_PERF_SEL_RB1_OVERFLOW_VF8             = 0x000000f4,
21912 IH_PERF_SEL_RB1_OVERFLOW_VF9             = 0x000000f5,
21913 IH_PERF_SEL_RB1_OVERFLOW_VF10            = 0x000000f6,
21914 IH_PERF_SEL_RB1_OVERFLOW_VF11            = 0x000000f7,
21915 IH_PERF_SEL_RB1_OVERFLOW_VF12            = 0x000000f8,
21916 IH_PERF_SEL_RB1_OVERFLOW_VF13            = 0x000000f9,
21917 IH_PERF_SEL_RB1_OVERFLOW_VF14            = 0x000000fa,
21918 IH_PERF_SEL_RB1_OVERFLOW_VF15            = 0x000000fb,
21919 Reserved252                              = 0x000000fc,
21920 Reserved253                              = 0x000000fd,
21921 Reserved254                              = 0x000000fe,
21922 Reserved255                              = 0x000000ff,
21923 Reserved256                              = 0x00000100,
21924 Reserved257                              = 0x00000101,
21925 Reserved258                              = 0x00000102,
21926 Reserved259                              = 0x00000103,
21927 Reserved260                              = 0x00000104,
21928 Reserved261                              = 0x00000105,
21929 Reserved262                              = 0x00000106,
21930 Reserved263                              = 0x00000107,
21931 Reserved264                              = 0x00000108,
21932 Reserved265                              = 0x00000109,
21933 Reserved266                              = 0x0000010a,
21934 Reserved267                              = 0x0000010b,
21935 IH_PERF_SEL_RB1_WPTR_WRAP_VF0            = 0x0000010c,
21936 IH_PERF_SEL_RB1_WPTR_WRAP_VF1            = 0x0000010d,
21937 IH_PERF_SEL_RB1_WPTR_WRAP_VF2            = 0x0000010e,
21938 IH_PERF_SEL_RB1_WPTR_WRAP_VF3            = 0x0000010f,
21939 IH_PERF_SEL_RB1_WPTR_WRAP_VF4            = 0x00000110,
21940 IH_PERF_SEL_RB1_WPTR_WRAP_VF5            = 0x00000111,
21941 IH_PERF_SEL_RB1_WPTR_WRAP_VF6            = 0x00000112,
21942 IH_PERF_SEL_RB1_WPTR_WRAP_VF7            = 0x00000113,
21943 IH_PERF_SEL_RB1_WPTR_WRAP_VF8            = 0x00000114,
21944 IH_PERF_SEL_RB1_WPTR_WRAP_VF9            = 0x00000115,
21945 IH_PERF_SEL_RB1_WPTR_WRAP_VF10           = 0x00000116,
21946 IH_PERF_SEL_RB1_WPTR_WRAP_VF11           = 0x00000117,
21947 IH_PERF_SEL_RB1_WPTR_WRAP_VF12           = 0x00000118,
21948 IH_PERF_SEL_RB1_WPTR_WRAP_VF13           = 0x00000119,
21949 IH_PERF_SEL_RB1_WPTR_WRAP_VF14           = 0x0000011a,
21950 IH_PERF_SEL_RB1_WPTR_WRAP_VF15           = 0x0000011b,
21951 IH_PERF_SEL_RB1_RPTR_WRAP_VF0            = 0x0000011c,
21952 IH_PERF_SEL_RB1_RPTR_WRAP_VF1            = 0x0000011d,
21953 IH_PERF_SEL_RB1_RPTR_WRAP_VF2            = 0x0000011e,
21954 IH_PERF_SEL_RB1_RPTR_WRAP_VF3            = 0x0000011f,
21955 IH_PERF_SEL_RB1_RPTR_WRAP_VF4            = 0x00000120,
21956 IH_PERF_SEL_RB1_RPTR_WRAP_VF5            = 0x00000121,
21957 IH_PERF_SEL_RB1_RPTR_WRAP_VF6            = 0x00000122,
21958 IH_PERF_SEL_RB1_RPTR_WRAP_VF7            = 0x00000123,
21959 IH_PERF_SEL_RB1_RPTR_WRAP_VF8            = 0x00000124,
21960 IH_PERF_SEL_RB1_RPTR_WRAP_VF9            = 0x00000125,
21961 IH_PERF_SEL_RB1_RPTR_WRAP_VF10           = 0x00000126,
21962 IH_PERF_SEL_RB1_RPTR_WRAP_VF11           = 0x00000127,
21963 IH_PERF_SEL_RB1_RPTR_WRAP_VF12           = 0x00000128,
21964 IH_PERF_SEL_RB1_RPTR_WRAP_VF13           = 0x00000129,
21965 IH_PERF_SEL_RB1_RPTR_WRAP_VF14           = 0x0000012a,
21966 IH_PERF_SEL_RB1_RPTR_WRAP_VF15           = 0x0000012b,
21967 Reserved300                              = 0x0000012c,
21968 Reserved301                              = 0x0000012d,
21969 Reserved302                              = 0x0000012e,
21970 Reserved303                              = 0x0000012f,
21971 Reserved304                              = 0x00000130,
21972 Reserved305                              = 0x00000131,
21973 Reserved306                              = 0x00000132,
21974 Reserved307                              = 0x00000133,
21975 Reserved308                              = 0x00000134,
21976 Reserved309                              = 0x00000135,
21977 Reserved310                              = 0x00000136,
21978 Reserved311                              = 0x00000137,
21979 Reserved312                              = 0x00000138,
21980 Reserved313                              = 0x00000139,
21981 Reserved314                              = 0x0000013a,
21982 Reserved315                              = 0x0000013b,
21983 Reserved316                              = 0x0000013c,
21984 Reserved317                              = 0x0000013d,
21985 Reserved318                              = 0x0000013e,
21986 Reserved319                              = 0x0000013f,
21987 Reserved320                              = 0x00000140,
21988 Reserved321                              = 0x00000141,
21989 Reserved322                              = 0x00000142,
21990 Reserved323                              = 0x00000143,
21991 Reserved324                              = 0x00000144,
21992 Reserved325                              = 0x00000145,
21993 Reserved326                              = 0x00000146,
21994 Reserved327                              = 0x00000147,
21995 Reserved328                              = 0x00000148,
21996 Reserved329                              = 0x00000149,
21997 Reserved330                              = 0x0000014a,
21998 Reserved331                              = 0x0000014b,
21999 IH_PERF_SEL_RB2_FULL_VF0                 = 0x0000014c,
22000 IH_PERF_SEL_RB2_FULL_VF1                 = 0x0000014d,
22001 IH_PERF_SEL_RB2_FULL_VF2                 = 0x0000014e,
22002 IH_PERF_SEL_RB2_FULL_VF3                 = 0x0000014f,
22003 IH_PERF_SEL_RB2_FULL_VF4                 = 0x00000150,
22004 IH_PERF_SEL_RB2_FULL_VF5                 = 0x00000151,
22005 IH_PERF_SEL_RB2_FULL_VF6                 = 0x00000152,
22006 IH_PERF_SEL_RB2_FULL_VF7                 = 0x00000153,
22007 IH_PERF_SEL_RB2_FULL_VF8                 = 0x00000154,
22008 IH_PERF_SEL_RB2_FULL_VF9                 = 0x00000155,
22009 IH_PERF_SEL_RB2_FULL_VF10                = 0x00000156,
22010 IH_PERF_SEL_RB2_FULL_VF11                = 0x00000157,
22011 IH_PERF_SEL_RB2_FULL_VF12                = 0x00000158,
22012 IH_PERF_SEL_RB2_FULL_VF13                = 0x00000159,
22013 IH_PERF_SEL_RB2_FULL_VF14                = 0x0000015a,
22014 IH_PERF_SEL_RB2_FULL_VF15                = 0x0000015b,
22015 IH_PERF_SEL_RB2_OVERFLOW_VF0             = 0x0000015c,
22016 IH_PERF_SEL_RB2_OVERFLOW_VF1             = 0x0000015d,
22017 IH_PERF_SEL_RB2_OVERFLOW_VF2             = 0x0000015e,
22018 IH_PERF_SEL_RB2_OVERFLOW_VF3             = 0x0000015f,
22019 IH_PERF_SEL_RB2_OVERFLOW_VF4             = 0x00000160,
22020 IH_PERF_SEL_RB2_OVERFLOW_VF5             = 0x00000161,
22021 IH_PERF_SEL_RB2_OVERFLOW_VF6             = 0x00000162,
22022 IH_PERF_SEL_RB2_OVERFLOW_VF7             = 0x00000163,
22023 IH_PERF_SEL_RB2_OVERFLOW_VF8             = 0x00000164,
22024 IH_PERF_SEL_RB2_OVERFLOW_VF9             = 0x00000165,
22025 IH_PERF_SEL_RB2_OVERFLOW_VF10            = 0x00000166,
22026 IH_PERF_SEL_RB2_OVERFLOW_VF11            = 0x00000167,
22027 IH_PERF_SEL_RB2_OVERFLOW_VF12            = 0x00000168,
22028 IH_PERF_SEL_RB2_OVERFLOW_VF13            = 0x00000169,
22029 IH_PERF_SEL_RB2_OVERFLOW_VF14            = 0x0000016a,
22030 IH_PERF_SEL_RB2_OVERFLOW_VF15            = 0x0000016b,
22031 Reserved364                              = 0x0000016c,
22032 Reserved365                              = 0x0000016d,
22033 Reserved366                              = 0x0000016e,
22034 Reserved367                              = 0x0000016f,
22035 Reserved368                              = 0x00000170,
22036 Reserved369                              = 0x00000171,
22037 Reserved370                              = 0x00000172,
22038 Reserved371                              = 0x00000173,
22039 Reserved372                              = 0x00000174,
22040 Reserved373                              = 0x00000175,
22041 Reserved374                              = 0x00000176,
22042 Reserved375                              = 0x00000177,
22043 Reserved376                              = 0x00000178,
22044 Reserved377                              = 0x00000179,
22045 Reserved378                              = 0x0000017a,
22046 Reserved379                              = 0x0000017b,
22047 IH_PERF_SEL_RB2_WPTR_WRAP_VF0            = 0x0000017c,
22048 IH_PERF_SEL_RB2_WPTR_WRAP_VF1            = 0x0000017d,
22049 IH_PERF_SEL_RB2_WPTR_WRAP_VF2            = 0x0000017e,
22050 IH_PERF_SEL_RB2_WPTR_WRAP_VF3            = 0x0000017f,
22051 IH_PERF_SEL_RB2_WPTR_WRAP_VF4            = 0x00000180,
22052 IH_PERF_SEL_RB2_WPTR_WRAP_VF5            = 0x00000181,
22053 IH_PERF_SEL_RB2_WPTR_WRAP_VF6            = 0x00000182,
22054 IH_PERF_SEL_RB2_WPTR_WRAP_VF7            = 0x00000183,
22055 IH_PERF_SEL_RB2_WPTR_WRAP_VF8            = 0x00000184,
22056 IH_PERF_SEL_RB2_WPTR_WRAP_VF9            = 0x00000185,
22057 IH_PERF_SEL_RB2_WPTR_WRAP_VF10           = 0x00000186,
22058 IH_PERF_SEL_RB2_WPTR_WRAP_VF11           = 0x00000187,
22059 IH_PERF_SEL_RB2_WPTR_WRAP_VF12           = 0x00000188,
22060 IH_PERF_SEL_RB2_WPTR_WRAP_VF13           = 0x00000189,
22061 IH_PERF_SEL_RB2_WPTR_WRAP_VF14           = 0x0000018a,
22062 IH_PERF_SEL_RB2_WPTR_WRAP_VF15           = 0x0000018b,
22063 IH_PERF_SEL_RB2_RPTR_WRAP_VF0            = 0x0000018c,
22064 IH_PERF_SEL_RB2_RPTR_WRAP_VF1            = 0x0000018d,
22065 IH_PERF_SEL_RB2_RPTR_WRAP_VF2            = 0x0000018e,
22066 IH_PERF_SEL_RB2_RPTR_WRAP_VF3            = 0x0000018f,
22067 IH_PERF_SEL_RB2_RPTR_WRAP_VF4            = 0x00000190,
22068 IH_PERF_SEL_RB2_RPTR_WRAP_VF5            = 0x00000191,
22069 IH_PERF_SEL_RB2_RPTR_WRAP_VF6            = 0x00000192,
22070 IH_PERF_SEL_RB2_RPTR_WRAP_VF7            = 0x00000193,
22071 IH_PERF_SEL_RB2_RPTR_WRAP_VF8            = 0x00000194,
22072 IH_PERF_SEL_RB2_RPTR_WRAP_VF9            = 0x00000195,
22073 IH_PERF_SEL_RB2_RPTR_WRAP_VF10           = 0x00000196,
22074 IH_PERF_SEL_RB2_RPTR_WRAP_VF11           = 0x00000197,
22075 IH_PERF_SEL_RB2_RPTR_WRAP_VF12           = 0x00000198,
22076 IH_PERF_SEL_RB2_RPTR_WRAP_VF13           = 0x00000199,
22077 IH_PERF_SEL_RB2_RPTR_WRAP_VF14           = 0x0000019a,
22078 IH_PERF_SEL_RB2_RPTR_WRAP_VF15           = 0x0000019b,
22079 Reserved412                              = 0x0000019c,
22080 Reserved413                              = 0x0000019d,
22081 Reserved414                              = 0x0000019e,
22082 Reserved415                              = 0x0000019f,
22083 Reserved416                              = 0x000001a0,
22084 Reserved417                              = 0x000001a1,
22085 Reserved418                              = 0x000001a2,
22086 Reserved419                              = 0x000001a3,
22087 Reserved420                              = 0x000001a4,
22088 Reserved421                              = 0x000001a5,
22089 Reserved422                              = 0x000001a6,
22090 Reserved423                              = 0x000001a7,
22091 Reserved424                              = 0x000001a8,
22092 Reserved425                              = 0x000001a9,
22093 Reserved426                              = 0x000001aa,
22094 Reserved427                              = 0x000001ab,
22095 Reserved428                              = 0x000001ac,
22096 Reserved429                              = 0x000001ad,
22097 Reserved430                              = 0x000001ae,
22098 Reserved431                              = 0x000001af,
22099 Reserved432                              = 0x000001b0,
22100 Reserved433                              = 0x000001b1,
22101 Reserved434                              = 0x000001b2,
22102 Reserved435                              = 0x000001b3,
22103 Reserved436                              = 0x000001b4,
22104 Reserved437                              = 0x000001b5,
22105 Reserved438                              = 0x000001b6,
22106 Reserved439                              = 0x000001b7,
22107 Reserved440                              = 0x000001b8,
22108 Reserved441                              = 0x000001b9,
22109 Reserved442                              = 0x000001ba,
22110 Reserved443                              = 0x000001bb,
22111 Reserved444                              = 0x000001bc,
22112 Reserved445                              = 0x000001bd,
22113 Reserved446                              = 0x000001be,
22114 Reserved447                              = 0x000001bf,
22115 Reserved448                              = 0x000001c0,
22116 Reserved449                              = 0x000001c1,
22117 Reserved450                              = 0x000001c2,
22118 Reserved451                              = 0x000001c3,
22119 Reserved452                              = 0x000001c4,
22120 Reserved453                              = 0x000001c5,
22121 Reserved454                              = 0x000001c6,
22122 Reserved455                              = 0x000001c7,
22123 Reserved456                              = 0x000001c8,
22124 Reserved457                              = 0x000001c9,
22125 Reserved458                              = 0x000001ca,
22126 Reserved459                              = 0x000001cb,
22127 Reserved460                              = 0x000001cc,
22128 Reserved461                              = 0x000001cd,
22129 Reserved462                              = 0x000001ce,
22130 Reserved463                              = 0x000001cf,
22131 Reserved464                              = 0x000001d0,
22132 Reserved465                              = 0x000001d1,
22133 Reserved466                              = 0x000001d2,
22134 Reserved467                              = 0x000001d3,
22135 Reserved468                              = 0x000001d4,
22136 Reserved469                              = 0x000001d5,
22137 Reserved470                              = 0x000001d6,
22138 Reserved471                              = 0x000001d7,
22139 Reserved472                              = 0x000001d8,
22140 Reserved473                              = 0x000001d9,
22141 Reserved474                              = 0x000001da,
22142 Reserved475                              = 0x000001db,
22143 Reserved476                              = 0x000001dc,
22144 Reserved477                              = 0x000001dd,
22145 Reserved478                              = 0x000001de,
22146 Reserved479                              = 0x000001df,
22147 Reserved480                              = 0x000001e0,
22148 Reserved481                              = 0x000001e1,
22149 Reserved482                              = 0x000001e2,
22150 Reserved483                              = 0x000001e3,
22151 Reserved484                              = 0x000001e4,
22152 Reserved485                              = 0x000001e5,
22153 Reserved486                              = 0x000001e6,
22154 Reserved487                              = 0x000001e7,
22155 Reserved488                              = 0x000001e8,
22156 Reserved489                              = 0x000001e9,
22157 Reserved490                              = 0x000001ea,
22158 Reserved491                              = 0x000001eb,
22159 Reserved492                              = 0x000001ec,
22160 Reserved493                              = 0x000001ed,
22161 Reserved494                              = 0x000001ee,
22162 Reserved495                              = 0x000001ef,
22163 Reserved496                              = 0x000001f0,
22164 Reserved497                              = 0x000001f1,
22165 Reserved498                              = 0x000001f2,
22166 Reserved499                              = 0x000001f3,
22167 Reserved500                              = 0x000001f4,
22168 Reserved501                              = 0x000001f5,
22169 Reserved502                              = 0x000001f6,
22170 Reserved503                              = 0x000001f7,
22171 Reserved504                              = 0x000001f8,
22172 Reserved505                              = 0x000001f9,
22173 Reserved506                              = 0x000001fa,
22174 Reserved507                              = 0x000001fb,
22175 Reserved508                              = 0x000001fc,
22176 Reserved509                              = 0x000001fd,
22177 Reserved510                              = 0x000001fe,
22178 Reserved511                              = 0x000001ff,
22179 } IH_PERF_SEL;
22180 
22181 /*******************************************************
22182  * SEM Enums
22183  *******************************************************/
22184 
22185 /*
22186  * SEM_PERF_SEL enum
22187  */
22188 
22189 typedef enum SEM_PERF_SEL {
22190 SEM_PERF_SEL_CYCLE                       = 0x00000000,
22191 SEM_PERF_SEL_IDLE                        = 0x00000001,
22192 SEM_PERF_SEL_SDMA0_REQ_SIGNAL            = 0x00000002,
22193 SEM_PERF_SEL_SDMA1_REQ_SIGNAL            = 0x00000003,
22194 SEM_PERF_SEL_UVD_REQ_SIGNAL              = 0x00000004,
22195 SEM_PERF_SEL_VCE0_REQ_SIGNAL             = 0x00000005,
22196 SEM_PERF_SEL_ACP_REQ_SIGNAL              = 0x00000006,
22197 SEM_PERF_SEL_ISP_REQ_SIGNAL              = 0x00000007,
22198 SEM_PERF_SEL_VCE1_REQ_SIGNAL             = 0x00000008,
22199 SEM_PERF_SEL_VP8_REQ_SIGNAL              = 0x00000009,
22200 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL           = 0x0000000a,
22201 SEM_PERF_SEL_CPG_E1_REQ_SIGNAL           = 0x0000000b,
22202 SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL     = 0x0000000c,
22203 SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL     = 0x0000000d,
22204 SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL     = 0x0000000e,
22205 SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL     = 0x0000000f,
22206 SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL     = 0x00000010,
22207 SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL     = 0x00000011,
22208 SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL     = 0x00000012,
22209 SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL     = 0x00000013,
22210 SEM_PERF_SEL_SDMA0_REQ_WAIT              = 0x00000014,
22211 SEM_PERF_SEL_SDMA1_REQ_WAIT              = 0x00000015,
22212 SEM_PERF_SEL_UVD_REQ_WAIT                = 0x00000016,
22213 SEM_PERF_SEL_VCE0_REQ_WAIT               = 0x00000017,
22214 SEM_PERF_SEL_ACP_REQ_WAIT                = 0x00000018,
22215 SEM_PERF_SEL_ISP_REQ_WAIT                = 0x00000019,
22216 SEM_PERF_SEL_VCE1_REQ_WAIT               = 0x0000001a,
22217 SEM_PERF_SEL_VP8_REQ_WAIT                = 0x0000001b,
22218 SEM_PERF_SEL_CPG_E0_REQ_WAIT             = 0x0000001c,
22219 SEM_PERF_SEL_CPG_E1_REQ_WAIT             = 0x0000001d,
22220 SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT       = 0x0000001e,
22221 SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT       = 0x0000001f,
22222 SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT       = 0x00000020,
22223 SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT       = 0x00000021,
22224 SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT       = 0x00000022,
22225 SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT       = 0x00000023,
22226 SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT       = 0x00000024,
22227 SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT       = 0x00000025,
22228 SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT       = 0x00000026,
22229 SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT       = 0x00000027,
22230 SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT       = 0x00000028,
22231 SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT       = 0x00000029,
22232 SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT       = 0x0000002a,
22233 SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT       = 0x0000002b,
22234 SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT       = 0x0000002c,
22235 SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT       = 0x0000002d,
22236 SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT       = 0x0000002e,
22237 SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT       = 0x0000002f,
22238 SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT      = 0x00000030,
22239 SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT      = 0x00000031,
22240 SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT      = 0x00000032,
22241 SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT      = 0x00000033,
22242 SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT      = 0x00000034,
22243 SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT      = 0x00000035,
22244 SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT      = 0x00000036,
22245 SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT      = 0x00000037,
22246 SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT      = 0x00000038,
22247 SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT      = 0x00000039,
22248 SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT      = 0x0000003a,
22249 SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT      = 0x0000003b,
22250 SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT      = 0x0000003c,
22251 SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT      = 0x0000003d,
22252 SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT      = 0x0000003e,
22253 SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT      = 0x0000003f,
22254 SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT      = 0x00000040,
22255 SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT      = 0x00000041,
22256 SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT      = 0x00000042,
22257 SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT      = 0x00000043,
22258 SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT      = 0x00000044,
22259 SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT      = 0x00000045,
22260 SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT       = 0x00000046,
22261 SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT       = 0x00000047,
22262 SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT       = 0x00000048,
22263 SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT       = 0x00000049,
22264 SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT       = 0x0000004a,
22265 SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT       = 0x0000004b,
22266 SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT       = 0x0000004c,
22267 SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT       = 0x0000004d,
22268 SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT       = 0x0000004e,
22269 SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT       = 0x0000004f,
22270 SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT      = 0x00000050,
22271 SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT      = 0x00000051,
22272 SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT      = 0x00000052,
22273 SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT      = 0x00000053,
22274 SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT      = 0x00000054,
22275 SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT      = 0x00000055,
22276 SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT      = 0x00000056,
22277 SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT      = 0x00000057,
22278 SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT      = 0x00000058,
22279 SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT      = 0x00000059,
22280 SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT      = 0x0000005a,
22281 SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT      = 0x0000005b,
22282 SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT      = 0x0000005c,
22283 SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT      = 0x0000005d,
22284 SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT      = 0x0000005e,
22285 SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT      = 0x0000005f,
22286 SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT      = 0x00000060,
22287 SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT      = 0x00000061,
22288 SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT      = 0x00000062,
22289 SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT      = 0x00000063,
22290 SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT      = 0x00000064,
22291 SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT      = 0x00000065,
22292 SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT      = 0x00000066,
22293 SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT      = 0x00000067,
22294 SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT      = 0x00000068,
22295 SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT      = 0x00000069,
22296 SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT      = 0x0000006a,
22297 SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT      = 0x0000006b,
22298 SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT      = 0x0000006c,
22299 SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT      = 0x0000006d,
22300 SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT      = 0x0000006e,
22301 SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT      = 0x0000006f,
22302 SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT     = 0x00000070,
22303 SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT     = 0x00000071,
22304 SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT     = 0x00000072,
22305 SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT     = 0x00000073,
22306 SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT     = 0x00000074,
22307 SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT     = 0x00000075,
22308 SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT     = 0x00000076,
22309 SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT     = 0x00000077,
22310 SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT     = 0x00000078,
22311 SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT     = 0x00000079,
22312 SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT     = 0x0000007a,
22313 SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT     = 0x0000007b,
22314 SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT     = 0x0000007c,
22315 SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT     = 0x0000007d,
22316 SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT     = 0x0000007e,
22317 SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT     = 0x0000007f,
22318 SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT     = 0x00000080,
22319 SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT     = 0x00000081,
22320 SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT     = 0x00000082,
22321 SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT     = 0x00000083,
22322 SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT     = 0x00000084,
22323 SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT     = 0x00000085,
22324 SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT      = 0x00000086,
22325 SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT      = 0x00000087,
22326 SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT      = 0x00000088,
22327 SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT      = 0x00000089,
22328 SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT      = 0x0000008a,
22329 SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT      = 0x0000008b,
22330 SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT      = 0x0000008c,
22331 SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT      = 0x0000008d,
22332 SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT      = 0x0000008e,
22333 SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT      = 0x0000008f,
22334 SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT     = 0x00000090,
22335 SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT     = 0x00000091,
22336 SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT     = 0x00000092,
22337 SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT     = 0x00000093,
22338 SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT     = 0x00000094,
22339 SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT     = 0x00000095,
22340 SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT     = 0x00000096,
22341 SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT     = 0x00000097,
22342 SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT     = 0x00000098,
22343 SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT     = 0x00000099,
22344 SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT     = 0x0000009a,
22345 SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT     = 0x0000009b,
22346 SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT     = 0x0000009c,
22347 SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT     = 0x0000009d,
22348 SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT     = 0x0000009e,
22349 SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT     = 0x0000009f,
22350 SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT     = 0x000000a0,
22351 SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT     = 0x000000a1,
22352 SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT     = 0x000000a2,
22353 SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT     = 0x000000a3,
22354 SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT     = 0x000000a4,
22355 SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT     = 0x000000a5,
22356 SEM_PERF_SEL_MC_RD_REQ                   = 0x000000a6,
22357 SEM_PERF_SEL_MC_RD_RET                   = 0x000000a7,
22358 SEM_PERF_SEL_MC_WR_REQ                   = 0x000000a8,
22359 SEM_PERF_SEL_MC_WR_RET                   = 0x000000a9,
22360 SEM_PERF_SEL_ATC_REQ                     = 0x000000aa,
22361 SEM_PERF_SEL_ATC_RET                     = 0x000000ab,
22362 SEM_PERF_SEL_ATC_XNACK                   = 0x000000ac,
22363 SEM_PERF_SEL_ATC_INVALIDATION            = 0x000000ad,
22364 } SEM_PERF_SEL;
22365 
22366 /*******************************************************
22367  * SDMA Enums
22368  *******************************************************/
22369 
22370 /*
22371  * SDMA_PERF_SEL enum
22372  */
22373 
22374 typedef enum SDMA_PERF_SEL {
22375 SDMA_PERF_SEL_CYCLE                      = 0x00000000,
22376 SDMA_PERF_SEL_IDLE                       = 0x00000001,
22377 SDMA_PERF_SEL_REG_IDLE                   = 0x00000002,
22378 SDMA_PERF_SEL_RB_EMPTY                   = 0x00000003,
22379 SDMA_PERF_SEL_RB_FULL                    = 0x00000004,
22380 SDMA_PERF_SEL_RB_WPTR_WRAP               = 0x00000005,
22381 SDMA_PERF_SEL_RB_RPTR_WRAP               = 0x00000006,
22382 SDMA_PERF_SEL_RB_WPTR_POLL_READ          = 0x00000007,
22383 SDMA_PERF_SEL_RB_RPTR_WB                 = 0x00000008,
22384 SDMA_PERF_SEL_RB_CMD_IDLE                = 0x00000009,
22385 SDMA_PERF_SEL_RB_CMD_FULL                = 0x0000000a,
22386 SDMA_PERF_SEL_IB_CMD_IDLE                = 0x0000000b,
22387 SDMA_PERF_SEL_IB_CMD_FULL                = 0x0000000c,
22388 SDMA_PERF_SEL_EX_IDLE                    = 0x0000000d,
22389 SDMA_PERF_SEL_SRBM_REG_SEND              = 0x0000000e,
22390 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE  = 0x0000000f,
22391 SDMA_PERF_SEL_MC_WR_IDLE                 = 0x00000010,
22392 SDMA_PERF_SEL_MC_WR_COUNT                = 0x00000011,
22393 SDMA_PERF_SEL_MC_RD_IDLE                 = 0x00000012,
22394 SDMA_PERF_SEL_MC_RD_COUNT                = 0x00000013,
22395 SDMA_PERF_SEL_MC_RD_RET_STALL            = 0x00000014,
22396 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE         = 0x00000015,
22397 SDMA_PERF_SEL_SEM_IDLE                   = 0x00000018,
22398 SDMA_PERF_SEL_SEM_REQ_STALL              = 0x00000019,
22399 SDMA_PERF_SEL_SEM_REQ_COUNT              = 0x0000001a,
22400 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE        = 0x0000001b,
22401 SDMA_PERF_SEL_SEM_RESP_FAIL              = 0x0000001c,
22402 SDMA_PERF_SEL_SEM_RESP_PASS              = 0x0000001d,
22403 SDMA_PERF_SEL_INT_IDLE                   = 0x0000001e,
22404 SDMA_PERF_SEL_INT_REQ_STALL              = 0x0000001f,
22405 SDMA_PERF_SEL_INT_REQ_COUNT              = 0x00000020,
22406 SDMA_PERF_SEL_INT_RESP_ACCEPTED          = 0x00000021,
22407 SDMA_PERF_SEL_INT_RESP_RETRY             = 0x00000022,
22408 SDMA_PERF_SEL_NUM_PACKET                 = 0x00000023,
22409 SDMA_PERF_SEL_CE_WREQ_IDLE               = 0x00000025,
22410 SDMA_PERF_SEL_CE_WR_IDLE                 = 0x00000026,
22411 SDMA_PERF_SEL_CE_SPLIT_IDLE              = 0x00000027,
22412 SDMA_PERF_SEL_CE_RREQ_IDLE               = 0x00000028,
22413 SDMA_PERF_SEL_CE_OUT_IDLE                = 0x00000029,
22414 SDMA_PERF_SEL_CE_IN_IDLE                 = 0x0000002a,
22415 SDMA_PERF_SEL_CE_DST_IDLE                = 0x0000002b,
22416 SDMA_PERF_SEL_CE_AFIFO_FULL              = 0x0000002e,
22417 SDMA_PERF_SEL_CE_INFO_FULL               = 0x00000031,
22418 SDMA_PERF_SEL_CE_INFO1_FULL              = 0x00000032,
22419 SDMA_PERF_SEL_CE_RD_STALL                = 0x00000033,
22420 SDMA_PERF_SEL_CE_WR_STALL                = 0x00000034,
22421 SDMA_PERF_SEL_GFX_SELECT                 = 0x00000035,
22422 SDMA_PERF_SEL_RLC0_SELECT                = 0x00000036,
22423 SDMA_PERF_SEL_RLC1_SELECT                = 0x00000037,
22424 SDMA_PERF_SEL_PAGE_SELECT                = 0x00000038,
22425 SDMA_PERF_SEL_CTX_CHANGE                 = 0x00000039,
22426 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED         = 0x0000003a,
22427 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION       = 0x0000003b,
22428 SDMA_PERF_SEL_DOORBELL                   = 0x0000003c,
22429 SDMA_PERF_SEL_RD_BA_RTR                  = 0x0000003d,
22430 SDMA_PERF_SEL_WR_BA_RTR                  = 0x0000003e,
22431 SDMA_PERF_SEL_F32_L1_WR_VLD              = 0x0000003f,
22432 SDMA_PERF_SEL_CE_L1_WR_VLD               = 0x00000040,
22433 SDMA_PERF_SEL_CE_L1_STALL                = 0x00000041,
22434 SDMA_PERF_SEL_SDMA_INVACK_NFLUSH         = 0x00000042,
22435 SDMA_PERF_SEL_SDMA_INVACK_FLUSH          = 0x00000043,
22436 SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH        = 0x00000044,
22437 SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH         = 0x00000045,
22438 SDMA_PERF_SEL_ATCL2_RET_XNACK            = 0x00000046,
22439 SDMA_PERF_SEL_ATCL2_RET_ACK              = 0x00000047,
22440 SDMA_PERF_SEL_ATCL2_FREE                 = 0x00000048,
22441 SDMA_PERF_SEL_SDMA_ATCL2_SEND            = 0x00000049,
22442 SDMA_PERF_SEL_DMA_L1_WR_SEND             = 0x0000004a,
22443 SDMA_PERF_SEL_DMA_L1_RD_SEND             = 0x0000004b,
22444 SDMA_PERF_SEL_DMA_MC_WR_SEND             = 0x0000004c,
22445 SDMA_PERF_SEL_DMA_MC_RD_SEND             = 0x0000004d,
22446 SDMA_PERF_SEL_L1_WR_FIFO_IDLE            = 0x0000004e,
22447 SDMA_PERF_SEL_L1_RD_FIFO_IDLE            = 0x0000004f,
22448 SDMA_PERF_SEL_L1_WRL2_IDLE               = 0x00000050,
22449 SDMA_PERF_SEL_L1_RDL2_IDLE               = 0x00000051,
22450 SDMA_PERF_SEL_L1_WRMC_IDLE               = 0x00000052,
22451 SDMA_PERF_SEL_L1_RDMC_IDLE               = 0x00000053,
22452 SDMA_PERF_SEL_L1_WR_INV_IDLE             = 0x00000054,
22453 SDMA_PERF_SEL_L1_RD_INV_IDLE             = 0x00000055,
22454 SDMA_PERF_SEL_L1_WR_INV_EN               = 0x00000056,
22455 SDMA_PERF_SEL_L1_RD_INV_EN               = 0x00000057,
22456 SDMA_PERF_SEL_L1_WR_WAIT_INVADR          = 0x00000058,
22457 SDMA_PERF_SEL_L1_RD_WAIT_INVADR          = 0x00000059,
22458 SDMA_PERF_SEL_IS_INVREQ_ADDR_WR          = 0x0000005a,
22459 SDMA_PERF_SEL_IS_INVREQ_ADDR_RD          = 0x0000005b,
22460 SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT        = 0x0000005c,
22461 SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT        = 0x0000005d,
22462 SDMA_PERF_SEL_L1_INV_MIDDLE              = 0x0000005e,
22463 SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER    = 0x000000fe,
22464 SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER    = 0x000000ff,
22465 } SDMA_PERF_SEL;
22466 
22467 /*******************************************************
22468  * SMUIO Enums
22469  *******************************************************/
22470 
22471 /*
22472  * ROM_SIGNATURE value
22473  */
22474 
22475 #define ROM_SIGNATURE                  0x0000aa55
22476 
22477 /*******************************************************
22478  * XDMA_CMN Enums
22479  *******************************************************/
22480 
22481 /*
22482  * ENUM_XDMA_LOCAL_SW_MODE enum
22483  */
22484 
22485 typedef enum ENUM_XDMA_LOCAL_SW_MODE {
22486 XDMA_LOCAL_SW_MODE_SW_256B_D             = 0x00000002,
22487 XDMA_LOCAL_SW_MODE_SW_64KB_D             = 0x0000000a,
22488 XDMA_LOCAL_SW_MODE_SW_64KB_D_X           = 0x0000001a,
22489 } ENUM_XDMA_LOCAL_SW_MODE;
22490 
22491 /*******************************************************
22492  * XDMA_SLV Enums
22493  *******************************************************/
22494 
22495 /*
22496  * ENUM_XDMA_SLV_ALPHA_POSITION enum
22497  */
22498 
22499 typedef enum ENUM_XDMA_SLV_ALPHA_POSITION {
22500 XDMA_SLV_ALPHA_POSITION_7_0              = 0x00000000,
22501 XDMA_SLV_ALPHA_POSITION_15_8             = 0x00000001,
22502 XDMA_SLV_ALPHA_POSITION_23_16            = 0x00000002,
22503 XDMA_SLV_ALPHA_POSITION_31_24            = 0x00000003,
22504 } ENUM_XDMA_SLV_ALPHA_POSITION;
22505 
22506 /*******************************************************
22507  * XDMA_MSTR Enums
22508  *******************************************************/
22509 
22510 /*
22511  * ENUM_XDMA_MSTR_ALPHA_POSITION enum
22512  */
22513 
22514 typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION {
22515 XDMA_MSTR_ALPHA_POSITION_7_0             = 0x00000000,
22516 XDMA_MSTR_ALPHA_POSITION_15_8            = 0x00000001,
22517 XDMA_MSTR_ALPHA_POSITION_23_16           = 0x00000002,
22518 XDMA_MSTR_ALPHA_POSITION_31_24           = 0x00000003,
22519 } ENUM_XDMA_MSTR_ALPHA_POSITION;
22520 
22521 /*
22522  * ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum
22523  */
22524 
22525 typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL {
22526 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0      = 0x00000000,
22527 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1      = 0x00000001,
22528 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2      = 0x00000002,
22529 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3      = 0x00000003,
22530 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4      = 0x00000004,
22531 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5      = 0x00000005,
22532 } ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL;
22533 
22534 
22535 #endif /*_vega10_ENUM_HEADER*/
22536 
22537