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Searched refs:REGWRITE_2 (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/arch/hpcmips/stand/lcboot/
H A Di28f128.c65 REGWRITE_2(base, 0, 0x98); in i28f128_probe()
79 REGWRITE_2(base, 0, 0xff); in i28f128_probe()
88 REGWRITE_2(addr, 0, I28F128_BLK_ERASE_1ST); in block_erase()
89 REGWRITE_2(addr, 0, I28F128_BLK_ERASE_2ND); in block_erase()
95 REGWRITE_2(addr, 0, I28F128_CLEAR_STATUS); in block_erase()
96 REGWRITE_2(addr, 0, I28F128_RESET); in block_erase()
108 REGWRITE_2(addr, 0, I28F128_WORDBYTE_PROG); in word_program()
109 REGWRITE_2(addr, 0, data); in word_program()
115 REGWRITE_2(addr, 0, I28F128_CLEAR_STATUS); in word_program()
116 REGWRITE_2(addr, 0, I28F128_RESET); in word_program()
[all …]
H A Dmain.c188 REGWRITE_2(VRETIMEH, 0, 0); in init_devices()
189 REGWRITE_2(VRETIMEM, 0, 0); in init_devices()
190 REGWRITE_2(VRETIMEL, 0, 0); in init_devices()
213 REGWRITE_2(VR4181_ISABRG_ADDR, ISABRGCTL, 0x0003); in init_devices()
214 REGWRITE_2(VR4181_ISABRG_ADDR, XISACTL, 0x0401); in init_devices()
224 REGWRITE_2(VR4181_CMU_ADDR, 0, CMUMASK_SIU | CMUMASK_AIU); in init_devices()
242 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PIOD_L_REG_W, 0xffff); in init_devices()
243 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE0_REG_W, in init_devices()
256 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE1_REG_W, GP8_GPO); in init_devices()
268 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE2_REG_W, in init_devices()
[all …]
H A Dif_cs.c75 #define CS_WRITE_2(off, val) REGWRITE_2(CS_IO_BASE, (off), (val))
77 (REGWRITE_2(CS_IO_BASE, PORT_PKTPG_PTR, (off)), \
80 (REGWRITE_2(CS_IO_BASE, PORT_PKTPG_PTR, (off)), \
81 REGWRITE_2(CS_IO_BASE, PORT_PKTPG_DATA, (val)))
H A Dextern.h86 #define REGWRITE_2(base, off, val) \ macro
103 #define bus_space_write_2(iot, ioh, off, val) REGWRITE_2((ioh), (off), (val))