Home
last modified time | relevance | path

Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 32) sorted by relevance

12

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_mxgpu_ai.c235 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()
288 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
H A Damdgpu_mxgpu_nv.c237 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_nv_set_mailbox_ack_irq()
293 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_nv_set_mailbox_rcv_irq()
H A Damdgpu_irq.h45 AMDGPU_IRQ_STATE_ENABLE, enumerator
H A Damdgpu_mxgpu_vi.c510 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()
540 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
H A Damdgpu_nbio_v7_4.c381 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()
417 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
H A Damdgpu_si_dma.c606 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
622 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
H A Damdgpu_irq.c498 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
H A Damdgpu_gmc_v9_0.c239 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_ecc_interrupt_state()
288 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()
H A Damdgpu_sdma_v2_4.c1025 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
1041 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
H A Damdgpu_vce_v2_0.c529 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
H A Damdgpu_cik_sdma.c1131 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1147 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
H A Damdgpu_sdma_v3_0.c1359 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
1375 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
H A Damdgpu_gfx_v9_0.c5384 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()
5387 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()
5436 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()
5454 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()
5457 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
5473 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()
5476 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()
5507 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_cp_ecc_error_state()
H A Damdgpu_gfx_v6_0.c3251 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()
3280 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()
3314 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()
3339 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
H A Damdgpu_gmc_v10_0.c109 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
H A Damdgpu_vce_v3_0.c713 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
H A Damdgpu_gmc_v6_0.c1084 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
H A Damdgpu_gfx_v10_0.c4841 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v10_0_set_gfx_eop_interrupt_state()
4894 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v10_0_set_compute_eop_interrupt_state()
4989 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v10_0_set_priv_reg_fault_state()
4992 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v10_0_set_priv_reg_fault_state()
5008 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v10_0_set_priv_inst_fault_state()
5011 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v10_0_set_priv_inst_fault_state()
H A Damdgpu_dce_v8_0.c2904 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()
2955 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vline_interrupt_state()
2983 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_hpd_interrupt_state()
H A Damdgpu_gfx_v7_0.c4722 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()
4773 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_compute_eop_interrupt_state()
4796 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_reg_fault_state()
4821 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_inst_fault_state()
H A Damdgpu_dce_v10_0.c2993 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()
3022 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vline_interrupt_state()
3051 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_hpd_irq_state()
H A Damdgpu_dce_v11_0.c3119 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()
3148 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vline_interrupt_state()
3177 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_hpd_irq_state()
H A Damdgpu_sdma_v4_0.c2014 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_trap_irq_state()
2099 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_ecc_irq_state()
H A Damdgpu_vce_v4_0.c1024 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v4_0_set_interrupt_state()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_irq.c604 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()
635 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()

12