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Searched refs:vs12 (Results 1 – 11 of 11) sorted by relevance

/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dppc64-acc-regalloc.ll37 ; CHECK-NEXT: xxlxor vs12, vs12, vs12
52 ; CHECK-NEXT: xvmaddadp vs12, vs0, vs12
58 ; CHECK-NEXT: xxlor vs14, vs12, vs12
59 ; CHECK-NEXT: xxlor vs12, v2, v2
102 ; CHECK-NEXT: stxv vs12, 48(0)
129 ; TRACKLIVE-NEXT: xxlxor vs12, vs12, vs12
144 ; TRACKLIVE-NEXT: xvmaddadp vs12, vs0, vs12
150 ; TRACKLIVE-NEXT: xxlor vs14, vs12, vs12
151 ; TRACKLIVE-NEXT: xxlor vs12, v2, v2
194 ; TRACKLIVE-NEXT: stxv vs12, 48(0)
H A Dvector-reduce-fadd.ll2270 ; PWR9LE-NEXT: lxv vs12, 336(r1)
2336 ; PWR9LE-NEXT: xxswapd v2, vs12
2342 ; PWR9LE-NEXT: xxswapd vs12, vs10
2388 ; PWR9BE-NEXT: lxv vs12, 352(r1)
2456 ; PWR9BE-NEXT: xxswapd vs12, vs12
2508 ; PWR10LE-NEXT: lxv vs12, 336(r1)
2574 ; PWR10LE-NEXT: xxswapd v2, vs12
2580 ; PWR10LE-NEXT: xxswapd vs12, vs10
2626 ; PWR10BE-NEXT: lxv vs12, 35
[all...]
H A Dmma-intrinsics.ll404 ; CHECK-NEXT: lxv vs12, 64(r7)
411 ; CHECK-NEXT: xvf32gernp acc0, vs12, vs13
453 ; CHECK-BE-NEXT: lxv vs12, 64(r7)
460 ; CHECK-BE-NEXT: xvf32gernp acc0, vs12, vs13
H A Dspill-vec-pair.ll157 …~{vs2},~{vs3},~{vs4},~{vs5},~{vs6},~{vs7},~{vs8},~{vs9},~{vs10},~{vs11},~{vs12},~{vs13},~{vs14},~{…
H A Dvec_conv_fp64_to_i16_elts.ll301 ; CHECK-P8-NEXT: lxvd2x vs12, r4, r6
325 ; CHECK-P8-NEXT: xxswapd v2, vs12
848 ; CHECK-P8-NEXT: lxvd2x vs12, r4, r6
872 ; CHECK-P8-NEXT: xxswapd v2, vs12
H A Dvec_conv_fp64_to_i8_elts.ll315 ; CHECK-P8-NEXT: lxvd2x vs12, r3, r4
347 ; CHECK-P8-NEXT: xxswapd v2, vs12
870 ; CHECK-P8-NEXT: lxvd2x vs12, r3, r4
902 ; CHECK-P8-NEXT: xxswapd v2, vs12
H A Dvector-lrint.ll2368 ; BE-NEXT: lxvd2x vs12, 0, r3
2382 ; BE-NEXT: stxvd2x vs12, r30, r3
3512 ; FAST-NEXT: xxmrghd v5, vs12, vs11
3546 ; FAST-NEXT: xxmrghd v10, vs12, vs11
3548 ; FAST-NEXT: xxswapd vs12, v0
3578 ; FAST-NEXT: stxvd2x vs12, r30, r3
H A Dvector-llrint.ll2357 ; BE-NEXT: lxvd2x vs12, 0, r3
2371 ; BE-NEXT: stxvd2x vs12, r30, r3
3501 ; FAST-NEXT: xxmrghd v5, vs12, vs11
3535 ; FAST-NEXT: xxmrghd v10, vs12, vs11
3537 ; FAST-NEXT: xxswapd vs12, v0
3567 ; FAST-NEXT: stxvd2x vs12, r30, r3
/llvm-project/llvm/test/CodeGen/RISCV/rvv/
H A Dundef-earlyclobber-chain.ll79 %vs12.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 1)
80 %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
88 %vs12.i.i.i.2 = add <vscale x 1 x i16> %v15.2, splat (i16 1)
89 %v18.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i.2, i64 1)
132 %vs12.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 1)
133 %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
H A Dvrgatherei16-subreg-liveness.ll12 define internal void @foo(<vscale x 1 x i16> %v15, <vscale x 1 x i16> %0, <vscale x 1 x i16> %vs12.i.i.i, <vscale x 1 x i16> %1, <vscale x 8 x i8> %v37) {
53 %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h221 DEFINE_VSX(vs12, LLDB_INVALID_REGNUM), \
406 uint32_t vs12[4]; member