xref: /llvm-project/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll (revision 706e1975400b3f30bd406b694bb711a7c7dbe1c4) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
3; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
4; RUN:    | FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
6; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
7; RUN:     -enable-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
8
9%0 = type <{ double }>
10%1 = type <{ double }>
11
12define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2) local_unnamed_addr {
13; CHECK-LABEL: acc_regalloc:
14; CHECK:       # %bb.0: # %bb
15; CHECK-NEXT:    lwz r3, 0(r3)
16; CHECK-NEXT:    lxv v4, 0(0)
17; CHECK-NEXT:    xxlxor v0, v0, v0
18; CHECK-NEXT:    xxlxor v1, v1, v1
19; CHECK-NEXT:    xxlxor v2, v2, v2
20; CHECK-NEXT:    li r6, 1
21; CHECK-NEXT:    li r4, 16
22; CHECK-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
23; CHECK-NEXT:    stfd f15, -136(r1) # 8-byte Folded Spill
24; CHECK-NEXT:    extswsli r3, r3, 3
25; CHECK-NEXT:    xvmaddadp v1, v4, v1
26; CHECK-NEXT:    lxvdsx v5, 0, r3
27; CHECK-NEXT:    xvmaddadp v0, v5, v0
28; CHECK-NEXT:    .p2align 4
29; CHECK-NEXT:  .LBB0_1: # %bb9
30; CHECK-NEXT:    #
31; CHECK-NEXT:    addi r6, r6, 2
32; CHECK-NEXT:    lxv vs0, 16(0)
33; CHECK-NEXT:    lxv vs1, -64(r5)
34; CHECK-NEXT:    xxlxor vs7, vs7, vs7
35; CHECK-NEXT:    xxlor vs3, v0, v0
36; CHECK-NEXT:    xxlxor vs2, vs2, vs2
37; CHECK-NEXT:    xxlxor vs12, vs12, vs12
38; CHECK-NEXT:    mulld r6, r6, r3
39; CHECK-NEXT:    xxlor vs10, v2, v2
40; CHECK-NEXT:    xxlor vs4, v2, v2
41; CHECK-NEXT:    xxlor vs8, vs10, vs10
42; CHECK-NEXT:    xxlor vs10, v1, v1
43; CHECK-NEXT:    xvmaddadp vs7, vs0, v5
44; CHECK-NEXT:    xvmuldp vs6, vs0, v2
45; CHECK-NEXT:    lxv vs0, -16(r5)
46; CHECK-NEXT:    xvmaddadp vs3, vs1, v2
47; CHECK-NEXT:    xvmaddadp vs2, vs1, vs2
48; CHECK-NEXT:    lxvdsx v6, r6, r4
49; CHECK-NEXT:    li r6, 0
50; CHECK-NEXT:    xvmaddadp vs7, v2, v2
51; CHECK-NEXT:    xvmaddadp vs6, v2, v2
52; CHECK-NEXT:    xvmaddadp vs12, vs0, vs12
53; CHECK-NEXT:    xvmuldp v3, vs1, v6
54; CHECK-NEXT:    xvmuldp vs11, v4, v6
55; CHECK-NEXT:    xvmuldp vs13, vs0, v6
56; CHECK-NEXT:    xvmuldp vs5, v6, v2
57; CHECK-NEXT:    xxlor vs0, v2, v2
58; CHECK-NEXT:    xxlor vs14, vs12, vs12
59; CHECK-NEXT:    xxlor vs12, v2, v2
60; CHECK-NEXT:    xxlor vs1, v3, v3
61; CHECK-NEXT:    xxlor vs9, vs11, vs11
62; CHECK-NEXT:    xxlor vs15, vs13, vs13
63; CHECK-NEXT:    xxmtacc acc1
64; CHECK-NEXT:    xxmtacc acc0
65; CHECK-NEXT:    xxmtacc acc2
66; CHECK-NEXT:    xxmtacc acc3
67; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
68; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
69; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
70; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
71; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
72; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
73; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
74; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
75; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
76; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
77; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
78; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
79; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
80; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
81; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
82; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
83; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
84; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
85; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
86; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
87; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
88; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
89; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
90; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
91; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
92; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
93; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
94; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
95; CHECK-NEXT:    xxmfacc acc0
96; CHECK-NEXT:    xxmfacc acc1
97; CHECK-NEXT:    xxmfacc acc2
98; CHECK-NEXT:    xxmfacc acc3
99; CHECK-NEXT:    stxv vs1, 0(r3)
100; CHECK-NEXT:    stxv vs9, 32(r3)
101; CHECK-NEXT:    stxv vs4, 16(0)
102; CHECK-NEXT:    stxv vs12, 48(0)
103; CHECK-NEXT:    b .LBB0_1
104;
105; TRACKLIVE-LABEL: acc_regalloc:
106; TRACKLIVE:       # %bb.0: # %bb
107; TRACKLIVE-NEXT:    lwz r3, 0(r3)
108; TRACKLIVE-NEXT:    lxv v4, 0(0)
109; TRACKLIVE-NEXT:    xxlxor v0, v0, v0
110; TRACKLIVE-NEXT:    xxlxor v1, v1, v1
111; TRACKLIVE-NEXT:    xxlxor v2, v2, v2
112; TRACKLIVE-NEXT:    li r6, 1
113; TRACKLIVE-NEXT:    li r4, 16
114; TRACKLIVE-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
115; TRACKLIVE-NEXT:    stfd f15, -136(r1) # 8-byte Folded Spill
116; TRACKLIVE-NEXT:    extswsli r3, r3, 3
117; TRACKLIVE-NEXT:    xvmaddadp v1, v4, v1
118; TRACKLIVE-NEXT:    lxvdsx v5, 0, r3
119; TRACKLIVE-NEXT:    xvmaddadp v0, v5, v0
120; TRACKLIVE-NEXT:    .p2align 4
121; TRACKLIVE-NEXT:  .LBB0_1: # %bb9
122; TRACKLIVE-NEXT:    #
123; TRACKLIVE-NEXT:    addi r6, r6, 2
124; TRACKLIVE-NEXT:    lxv vs0, 16(0)
125; TRACKLIVE-NEXT:    lxv vs1, -64(r5)
126; TRACKLIVE-NEXT:    xxlxor vs7, vs7, vs7
127; TRACKLIVE-NEXT:    xxlor vs3, v0, v0
128; TRACKLIVE-NEXT:    xxlxor vs2, vs2, vs2
129; TRACKLIVE-NEXT:    xxlxor vs12, vs12, vs12
130; TRACKLIVE-NEXT:    mulld r6, r6, r3
131; TRACKLIVE-NEXT:    xxlor vs10, v2, v2
132; TRACKLIVE-NEXT:    xxlor vs4, v2, v2
133; TRACKLIVE-NEXT:    xxlor vs8, vs10, vs10
134; TRACKLIVE-NEXT:    xxlor vs10, v1, v1
135; TRACKLIVE-NEXT:    xvmaddadp vs7, vs0, v5
136; TRACKLIVE-NEXT:    xvmuldp vs6, vs0, v2
137; TRACKLIVE-NEXT:    lxv vs0, -16(r5)
138; TRACKLIVE-NEXT:    xvmaddadp vs3, vs1, v2
139; TRACKLIVE-NEXT:    xvmaddadp vs2, vs1, vs2
140; TRACKLIVE-NEXT:    lxvdsx v6, r6, r4
141; TRACKLIVE-NEXT:    li r6, 0
142; TRACKLIVE-NEXT:    xvmaddadp vs7, v2, v2
143; TRACKLIVE-NEXT:    xvmaddadp vs6, v2, v2
144; TRACKLIVE-NEXT:    xvmaddadp vs12, vs0, vs12
145; TRACKLIVE-NEXT:    xvmuldp v3, vs1, v6
146; TRACKLIVE-NEXT:    xvmuldp vs11, v4, v6
147; TRACKLIVE-NEXT:    xvmuldp vs13, vs0, v6
148; TRACKLIVE-NEXT:    xvmuldp vs5, v6, v2
149; TRACKLIVE-NEXT:    xxlor vs0, v2, v2
150; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12
151; TRACKLIVE-NEXT:    xxlor vs12, v2, v2
152; TRACKLIVE-NEXT:    xxlor vs1, v3, v3
153; TRACKLIVE-NEXT:    xxlor vs9, vs11, vs11
154; TRACKLIVE-NEXT:    xxlor vs15, vs13, vs13
155; TRACKLIVE-NEXT:    xxmtacc acc1
156; TRACKLIVE-NEXT:    xxmtacc acc0
157; TRACKLIVE-NEXT:    xxmtacc acc2
158; TRACKLIVE-NEXT:    xxmtacc acc3
159; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
160; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
161; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
162; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
163; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
164; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
165; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
166; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
167; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
168; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
169; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
170; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
171; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
172; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
173; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
174; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
175; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
176; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
177; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
178; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
179; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
180; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
181; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
182; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
183; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
184; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
185; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
186; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
187; TRACKLIVE-NEXT:    xxmfacc acc0
188; TRACKLIVE-NEXT:    xxmfacc acc1
189; TRACKLIVE-NEXT:    xxmfacc acc2
190; TRACKLIVE-NEXT:    xxmfacc acc3
191; TRACKLIVE-NEXT:    stxv vs1, 0(r3)
192; TRACKLIVE-NEXT:    stxv vs9, 32(r3)
193; TRACKLIVE-NEXT:    stxv vs4, 16(0)
194; TRACKLIVE-NEXT:    stxv vs12, 48(0)
195; TRACKLIVE-NEXT:    b .LBB0_1
196bb:
197  %i = load i32, ptr %arg, align 4
198  %i3 = sext i32 %i to i64
199  %i4 = shl nsw i64 %i3, 3
200  %i6 = getelementptr i8, ptr %arg1, i64 undef
201  %i7 = getelementptr [0 x %1], ptr %arg2, i64 0, i64 -8
202  %i8 = getelementptr i8, ptr %i6, i64 undef
203  br label %bb9
204
205bb9:                                              ; preds = %bb95, %bb
206  %i10 = phi i64 [ 1, %bb ], [ 0, %bb95 ]
207  %i11 = getelementptr %1, ptr null, i64 2
208  %i13 = load <2 x double>, ptr %i11, align 1
209  %i14 = add nuw nsw i64 %i10, 2
210  %i15 = getelementptr inbounds %1, ptr %i7, i64 undef
211  %i17 = load <2 x double>, ptr %i15, align 1
212  %i18 = load <2 x double>, ptr null, align 1
213  %i19 = getelementptr %1, ptr %i15, i64 6
214  %i21 = load <2 x double>, ptr %i19, align 1
215  %i22 = load i64, ptr undef, align 8
216  %i23 = insertelement <2 x i64> poison, i64 %i22, i32 0
217  %i24 = bitcast <2 x i64> %i23 to <2 x double>
218  %i25 = shufflevector <2 x double> %i24, <2 x double> undef, <2 x i32> zeroinitializer
219  %i26 = mul i64 %i14, %i4
220  %i27 = getelementptr i8, ptr null, i64 %i26
221  %i29 = getelementptr i8, ptr %i27, i64 16
222  %i31 = load i64, ptr %i29, align 8
223  %i32 = insertelement <2 x i64> poison, i64 %i31, i32 0
224  %i33 = bitcast <2 x i64> %i32 to <2 x double>
225  %i34 = shufflevector <2 x double> %i33, <2 x double> undef, <2 x i32> zeroinitializer
226  %i35 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> %i25, <2 x double> zeroinitializer)
227  %i36 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i13, <2 x double> %i25, <2 x double> zeroinitializer)
228  %i37 = fmul contract <2 x double> %i13, zeroinitializer
229  %i38 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i17, <2 x double> zeroinitializer, <2 x double> %i35)
230  %i39 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> %i36)
231  %i40 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i17, <2 x double> zeroinitializer, <2 x double> zeroinitializer)
232  %i41 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> %i37)
233  %i42 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i18, <2 x double> zeroinitializer, <2 x double> zeroinitializer)
234  %i43 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i21, <2 x double> zeroinitializer, <2 x double> zeroinitializer)
235  %i44 = fmul contract <2 x double> %i17, %i34
236  %i45 = fmul contract <2 x double> zeroinitializer, %i34
237  %i46 = fmul contract <2 x double> %i18, %i34
238  %i47 = fmul contract <2 x double> %i21, %i34
239  %i48 = bitcast <2 x double> %i44 to <16 x i8>
240  %i49 = bitcast <2 x double> %i40 to <16 x i8>
241  %i50 = bitcast <2 x double> %i38 to <16 x i8>
242  %i51 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i48, <16 x i8> %i49, <16 x i8> %i50)
243  %i52 = bitcast <2 x double> %i45 to <16 x i8>
244  %i53 = bitcast <2 x double> %i41 to <16 x i8>
245  %i54 = bitcast <2 x double> %i39 to <16 x i8>
246  %i55 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i52, <16 x i8> %i53, <16 x i8> %i54)
247  %i56 = bitcast <2 x double> %i46 to <16 x i8>
248  %i57 = bitcast <2 x double> %i42 to <16 x i8>
249  %i58 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i56, <16 x i8> %i57, <16 x i8> %i56)
250  %i59 = bitcast <2 x double> %i47 to <16 x i8>
251  %i60 = bitcast <2 x double> %i43 to <16 x i8>
252  %i61 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i59, <16 x i8> %i60, <16 x i8> %i59)
253  %i62 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i51, <256 x i1> undef, <16 x i8> undef)
254  %i63 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i55, <256 x i1> undef, <16 x i8> undef)
255  %i64 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i58, <256 x i1> undef, <16 x i8> undef)
256  %i65 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i61, <256 x i1> undef, <16 x i8> undef)
257  %i66 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i62, <256 x i1> undef, <16 x i8> undef)
258  %i67 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i63, <256 x i1> undef, <16 x i8> undef)
259  %i68 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i64, <256 x i1> undef, <16 x i8> undef)
260  %i69 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i65, <256 x i1> undef, <16 x i8> undef)
261  %i70 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i66, <256 x i1> undef, <16 x i8> undef)
262  %i71 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i67, <256 x i1> undef, <16 x i8> undef)
263  %i72 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i68, <256 x i1> undef, <16 x i8> undef)
264  %i73 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i69, <256 x i1> undef, <16 x i8> undef)
265  %i74 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i70, <256 x i1> undef, <16 x i8> undef)
266  %i75 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i71, <256 x i1> undef, <16 x i8> undef)
267  %i76 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i72, <256 x i1> undef, <16 x i8> undef)
268  %i77 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i73, <256 x i1> undef, <16 x i8> undef)
269  %i78 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i74, <256 x i1> undef, <16 x i8> undef)
270  %i79 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i75, <256 x i1> undef, <16 x i8> undef)
271  %i80 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i76, <256 x i1> undef, <16 x i8> undef)
272  %i81 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i77, <256 x i1> undef, <16 x i8> undef)
273  br label %bb82
274
275bb82:                                             ; preds = %bb82, %bb9
276  %i83 = phi <512 x i1> [ %i94, %bb82 ], [ %i81, %bb9 ]
277  %i84 = phi <512 x i1> [ %i93, %bb82 ], [ %i80, %bb9 ]
278  %i85 = phi <512 x i1> [ %i92, %bb82 ], [ %i79, %bb9 ]
279  %i86 = phi <512 x i1> [ %i91, %bb82 ], [ %i78, %bb9 ]
280  %i87 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i86, <256 x i1> undef, <16 x i8> undef)
281  %i88 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i85, <256 x i1> undef, <16 x i8> undef)
282  %i89 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i84, <256 x i1> undef, <16 x i8> undef)
283  %i90 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i83, <256 x i1> undef, <16 x i8> undef)
284  %i91 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i87, <256 x i1> undef, <16 x i8> undef)
285  %i92 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i88, <256 x i1> undef, <16 x i8> undef)
286  %i93 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i89, <256 x i1> undef, <16 x i8> undef)
287  %i94 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i90, <256 x i1> undef, <16 x i8> undef)
288  br i1 undef, label %bb95, label %bb82
289
290bb95:                                             ; preds = %bb82
291  %i96 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i91)
292  %i97 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i96, 2
293  %i98 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i92)
294  %i99 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i98, 3
295  %i100 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i93)
296  %i101 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i100, 2
297  %i102 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i94)
298  %i103 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i102, 3
299  %i104 = getelementptr inbounds i8, ptr %i8, i64 undef
300  store <16 x i8> %i97, ptr %i104, align 1
301  %i106 = getelementptr i8, ptr %i104, i64 32
302  store <16 x i8> %i101, ptr %i106, align 1
303  %i108 = getelementptr i8, ptr null, i64 16
304  store <16 x i8> %i99, ptr %i108, align 1
305  %i110 = getelementptr i8, ptr null, i64 48
306  store <16 x i8> %i103, ptr %i110, align 1
307  br label %bb9
308}
309
310declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
311declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
312declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
313declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
314
315