1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix NOSUBREG 3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -enable-subreg-liveness=true | FileCheck %s --check-prefix SUBREG 4 5; This test checks that vrgatherei16 instructions are correctly 6; register-allocated. The LMUL=1 destination register groups may not overlap 7; with the EMUL=2 source vector register groups. 8 9; FIXME: enabling subregister liveness results in incorrect register 10; allocation! 11 12define internal void @foo(<vscale x 1 x i16> %v15, <vscale x 1 x i16> %0, <vscale x 1 x i16> %vs12.i.i.i, <vscale x 1 x i16> %1, <vscale x 8 x i8> %v37) { 13; NOSUBREG-LABEL: foo: 14; NOSUBREG: # %bb.0: # %loopIR.preheader.i.i 15; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma 16; NOSUBREG-NEXT: vmv.v.i v9, 0 17; NOSUBREG-NEXT: vsetvli zero, zero, e16, m2, ta, ma 18; NOSUBREG-NEXT: vmv.v.i v14, 0 19; NOSUBREG-NEXT: vmv1r.v v8, v9 20; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma 21; NOSUBREG-NEXT: vrgatherei16.vv v8, v9, v14 22; NOSUBREG-NEXT: .LBB0_1: # %loopIR3.i.i 23; NOSUBREG-NEXT: # =>This Inner Loop Header: Depth=1 24; NOSUBREG-NEXT: vl1r.v v9, (zero) 25; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma 26; NOSUBREG-NEXT: vmv1r.v v13, v12 27; NOSUBREG-NEXT: vrgatherei16.vv v13, v9, v10 28; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma 29; NOSUBREG-NEXT: vand.vv v9, v8, v13 30; NOSUBREG-NEXT: vs1r.v v9, (zero) 31; NOSUBREG-NEXT: j .LBB0_1 32; 33; SUBREG-LABEL: foo: 34; SUBREG: # %bb.0: # %loopIR.preheader.i.i 35; SUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma 36; SUBREG-NEXT: vmv.v.i v9, 0 37; SUBREG-NEXT: vsetvli zero, zero, e16, m2, ta, ma 38; SUBREG-NEXT: vmv.v.i v14, 0 39; SUBREG-NEXT: vmv1r.v v8, v9 40; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma 41; SUBREG-NEXT: vrgatherei16.vv v8, v9, v14 42; SUBREG-NEXT: .LBB0_1: # %loopIR3.i.i 43; SUBREG-NEXT: # =>This Inner Loop Header: Depth=1 44; SUBREG-NEXT: vl1r.v v9, (zero) 45; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma 46; SUBREG-NEXT: vmv1r.v v13, v12 47; SUBREG-NEXT: vrgatherei16.vv v13, v9, v10 48; SUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma 49; SUBREG-NEXT: vand.vv v9, v8, v13 50; SUBREG-NEXT: vs1r.v v9, (zero) 51; SUBREG-NEXT: j .LBB0_1 52loopIR.preheader.i.i: 53 %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0) 54 br label %loopIR3.i.i 55 56loopIR3.i.i: ; preds = %loopIR3.i.i, %loopIR.preheader.i.i 57 %v376 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8 58 %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i16> zeroinitializer, i64 4) 59 %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> %v37, <vscale x 8 x i8> %v376, <vscale x 8 x i16> %v18, i64 4) 60 %v42 = and <vscale x 8 x i8> %v38, %v40 61 store <vscale x 8 x i8> %v42, ptr addrspace(1) null, align 4 62 br label %loopIR3.i.i 63} 64 65; Function Attrs: nocallback nofree nosync nounwind readnone willreturn 66declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16>, <vscale x 1 x i16>, i64 immarg) #0 67 68; Function Attrs: nounwind readnone 69declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i16>, i64) #1 70 71attributes #0 = { nocallback nofree nosync nounwind readnone willreturn } 72attributes #1 = { nounwind readnone } 73