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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td290 def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
291 (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
294 def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
295 (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
408 def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
409 (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
410 def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
411 (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
412 def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
413 (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Require
[all...]
H A DHexagonMapAsm2IntrinV62.gen.td17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
20 IntRegsLow8:$src3),
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
39 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
40 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
42 HvxVR:$src3),
43 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
54 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
55 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
[all …]
H A DHexagonIntrinsicsV60.td171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
175 IntRegs:$src3),
176 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
184 IntRegs:$src3),
185 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
[all …]
H A DHexagonIntrinsics.td145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
207 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
208 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
212 HvxVR:$src3),
213 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
310 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
311 (MI HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>,
315 u3_0ImmPred:$src3),
317 u3_0ImmPred:$src3)>,
[all...]
/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAMX.td67 opaquemem:$src3), []>;
71 opaquemem:$src3), []>;
74 GR16:$src2, opaquemem:$src3,
102 (ins TILE:$src1, TILE:$src2, TILE:$src3),
103 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
106 (ins TILE:$src1, TILE:$src2, TILE:$src3),
107 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
110 (ins TILE:$src1, TILE:$src2, TILE:$src3),
[all...]
H A DX86InstrXOP.td172 (ins VR128:$src1, VR128:$src2, VR128:$src3),
174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
176 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP, VVVV,
179 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
184 VR128:$src3))]>, XOP, VVVV, Sched<[sched.Folded, sched.ReadAfterFold]>;
218 (v8i16 VR128:$src3))),
219 (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>;
221 (v4i32 VR128:$src3))),
222 (VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
[all …]
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
52 (MemFrag addr:$src3))))]>,
61 (ins RC:$src1, RC:$src2, RC:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrSSE.td2076 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2078 (i8 timm:$src3))))], d>,
2082 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2084 (i8 timm:$src3))))], d>,
2090 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2094 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2098 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[all...]
H A DX86InstrFragmentsSIMD.td219 def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3),
220 [(X86strict_cmpp node:$src1, node:$src2, node:$src3),
221 (X86cmpp node:$src1, node:$src2, node:$src3)]>;
239 def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3),
240 [(X86strict_cmpm node:$src1, node:$src2, node:$src3),
241 (X86cmpm node:$src1, node:$src2, node:$src3)]>;
568 def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3),
569 [(X86strict_Fnmadd node:$src1, node:$src2, node:$src3),
570 (X86Fnmadd node:$src1, node:$src2, node:$src3)]>;
573 def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3),
[all...]
H A DX86InstrAVX512.td380 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
382 "$src3, $src2, $src1", "$src1, $src2, $src3",
383 (vinsert_insert:$src3 (To.VT To.RC:$src1),
386 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
392 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
394 "$src3, $src2, $src1", "$src1, $src2, $src3",
395 (vinsert_insert:$src3 (To.VT To.RC:$src1),
398 (vinsert_for_mask:$src3 (T
[all...]
H A DX86InstrMMX.td111 (ins VR64:$src1, VR64:$src2, u8imm:$src3),
112 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
113 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
116 (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
119 (i8 timm:$src3)))]>,
522 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
523 "pinsrw\t{$src3,
[all...]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
41 : EXPCommon<0, ps.done, "exp$tgt $src0, $src1, $src2, $src3"
49 : EXPCommon<ps.row, ps.done, name#"$tgt $src0, $src1, $src2, $src3"
143 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
146 ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
152 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
155 ExpSrc2:$src2, ExpSrc3:$src3, 0, 0, timm:$en)
/llvm-project/clang/test/SemaOpenCL/
H A Dqueue_t_overload.cl6 void kernel ker(__local char *src1, __local float *src2, __global int *src3) {
10 foo(q, src3); // expected-error {{no matching function for call to 'foo'}}
11 foo(1, src3); // expected-error {{no matching function for call to 'foo'}}
H A Devent_t_overload.cl6 void kernel ker(__local char *src1, __local float *src2, __global int *src3) {
10 foo(evt, src3); // expected-error {{no matching function for call to 'foo'}}
/llvm-project/flang/test/Evaluate/
H A Dtest_folding.py74 src3 = "" variable
113 src3 += f"{m.string}\n"
115 for passed_results, line in enumerate(src3.split("\n")):
/llvm-project/llvm/test/TableGen/
H A Dusevalname.td19 def rri : Instr<[(set RC:$dst, (shufp:$src3
23 // CHECK: shufp:src3
H A DGlobalISelEmitter.td
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.alignbyte.ll7 define amdgpu_kernel void @v_alignbyte_b32(ptr addrspace(1) %out, i32 %src1, i32 %src2, i32 %src3) …
8 %val = call i32 @llvm.amdgcn.alignbyte(i32 %src1, i32 %src2, i32 %src3) #0
H A Dllvm.amdgcn.perm.ll8 define amdgpu_ps void @v_perm_b32_v_v_v(i32 %src1, i32 %src2, i32 %src3, ptr addrspace(1) %out) #1 {
9 %val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 %src3) #0
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dmve-fmas.ll6 define arm_aapcs_vfpcc <8 x half> @vfma16_v1(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
46 %0 = fmul <8 x half> %src2, %src3
51 define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
91 %0 = fmul <8 x half> %src2, %src3
96 define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
136 %0 = fmul <8 x half> %src2, %src3
182 %src3 = fptrunc float %src3o to half
183 %i = insertelement <8 x half> undef, half %src3, i32 0
239 %src3 = fptrunc float %src3o to half
240 %i = insertelement <8 x half> undef, half %src3, i3
[all...]
/llvm-project/libc/test/src/__support/File/
H A Dfile_test.cpp198 MemoryView src3("hello\n file\0longer for an \n overflow", 37), in TEST()
200 EXPECT_MEM_EQ(src3, dst_full_final); in TEST()
207 EXPECT_MEM_EQ(src3, dst_line_final); in TEST()
208 EXPECT_MEM_EQ(src3, dst_full_final); in TEST()
268 MemoryView src3(initial_content, READ_SIZE), dst3(read_data, READ_SIZE); in TEST()
269 EXPECT_MEM_EQ(src3, dst3); in TEST() local
414 MemoryView src3(data, sizeof(data)), in TEST()
416 EXPECT_MEM_EQ(src3, dst3); in TEST()
199 MemoryView src3("hello\n file\0longer for an \n overflow", 37), TEST() local
415 MemoryView src3(data, sizeof(data)), TEST() local
/llvm-project/lldb/test/API/tools/lldb-dap/step/
H A DTestDAP_step.py59 (src3, line3) = self.get_source_and_line(threadId=tid)
62 self.assertEqual(src1, src3, "verify step in source")
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dbranch-hint.ll105 define void @branch_hint_6(i32 %src1, i32 %src2, i32 %src3) {
119 %cmp4 = icmp eq i32 %src3, 1
/llvm-project/mlir/test/mlir-vulkan-runner/
H A Dvector-deinterleave.mlir
/llvm-project/llvm/test/CodeGen/X86/
H A Dwindows-seh-EHa-PreserveCFG.ll9 %src3 = getelementptr inbounds float, ptr %src, i64 3
10 %tmp3 = load float, ptr %src3

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