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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6 |
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331f22af |
| 10-May-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Remove unnecessary predicates from aliases. NFC. (#91602)
So long as the target of the alias is predicated with HasImageInsts or
similar, the alias itself does not need this predicate.
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fe0b7983 |
| 09-May-2024 |
Joe Nash <joseph.nash@amd.com> |
[AMDGPU] Create AMDGPUMnemonicAlias tablegen class (#89288)
AMDGPUMnemonicAlias is a MnemonicAlias that inherits from
GCNPredicateControl, so that we can set predicates on the alias the same
way a
[AMDGPU] Create AMDGPUMnemonicAlias tablegen class (#89288)
AMDGPUMnemonicAlias is a MnemonicAlias that inherits from
GCNPredicateControl, so that we can set predicates on the alias the same
way as Instructions.
Use AssemblerPredicate instead of Requires on aliases
NFC.
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Revision tags: llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1 |
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4119042d |
| 07-Mar-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Simplify EXP Real instruction definitions. NFC.
Pass the Pseudo (instead of its name) into EXP_Real_Row and
EXP_Real_ComprVM since it is already available in all subclasses.
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ee1bcf74 |
| 06-Mar-2024 |
Changpeng Fang <changpeng.fang@amd.com> |
AMDGPI: Rename HasExpOrExportInsts to HasExportInsts. NFC (#84252)
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d6c52c1e |
| 05-Mar-2024 |
Changpeng Fang <changpeng.fang@amd.com> |
AMDGPU: Define HasExpOrExportInsts for export instruction definitions. (#84083)
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Revision tags: llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3 |
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9c06b079 |
| 14-Feb-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Refactor export instruction definitions. NFC. (#81738)
Using multiclasses for the Real instruction definitions has a couple of
benefits:
- It avoids repeating information that was already
[AMDGPU] Refactor export instruction definitions. NFC. (#81738)
Using multiclasses for the Real instruction definitions has a couple of
benefits:
- It avoids repeating information that was already specified when
defining the corresponding pseudo, like the row and done bits.
- It allows commoning up the Real definitions for architectures which
are mostly the same, like GFX11 and GFX12.
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Revision tags: llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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7a259634 |
| 09-Jan-2024 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Flip the default value of maybeAtomic. NFCI. (#75220)
In practice maybeAtomic = 0 is used to prevent SIMemoryLegalizer from
interfering with instructions that are mayLoad or mayStore but l
[AMDGPU] Flip the default value of maybeAtomic. NFCI. (#75220)
In practice maybeAtomic = 0 is used to prevent SIMemoryLegalizer from
interfering with instructions that are mayLoad or mayStore but lack
MachineMemOperands. These instructions should be the exception not the
rule, so this patch sets maybeAtomic = 1 by default and only overrides
it to 0 where necessary.
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44ff904d |
| 07-Dec-2023 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Add VEXPORT encoding for GFX12 (#74615)
In GFX12 the exp instruction is renamed to export, but exp is still
accepted as an alias.
Co-authored-by: Mateja Marjanovic <mateja.marjanovic@am
[AMDGPU] Add VEXPORT encoding for GFX12 (#74615)
In GFX12 the exp instruction is renamed to export, but exp is still
accepted as an alias.
Co-authored-by: Mateja Marjanovic <mateja.marjanovic@amd.com>
show more ...
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6 |
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445a483b |
| 13-Jun-2022 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Add new GFX11 intrinsic llvm.amdgcn.exp.row
Differential Revision: https://reviews.llvm.org/D127671
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Revision tags: llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2 |
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1a51ab76 |
| 25-Apr-2022 |
Joe Nash <Joseph.Nash@amd.com> |
[AMDGPU] gfx11 export instructions
Contributors:
Jay Foad <jay.foad@amd.com>
Dmitry Preobrazhensky <d-pre@mail.ru>
Patch 10/N for upstreaming of AMDGPU gfx11 architecture.
Depends on D125822
Revi
[AMDGPU] gfx11 export instructions
Contributors:
Jay Foad <jay.foad@amd.com>
Dmitry Preobrazhensky <d-pre@mail.ru>
Patch 10/N for upstreaming of AMDGPU gfx11 architecture.
Depends on D125822
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D125824
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b4231ac4 |
| 21-Apr-2022 |
Dmitry Preobrazhensky <d-pre@mail.ru> |
[AMDGPU][GFX90A+] Disabled ds_ordered_count and exp
Differential Revision: https://reviews.llvm.org/D124087
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Revision tags: llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1 |
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f23c4c6f |
| 11-Nov-2020 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Separate out real exp instructions by subtarget. NFC.
Differential Revision: https://reviews.llvm.org/D91247
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2b33ea69 |
| 11-Nov-2020 |
Jay Foad <jay.foad@amd.com> |
[AMDGPU] Split exp instructions out into their own tablegen file. NFC.
Differential Revision: https://reviews.llvm.org/D91246
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