Lines Matching refs:src3

6 define arm_aapcs_vfpcc <8 x half> @vfma16_v1(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
46   %0 = fmul <8 x half> %src2, %src3
51 define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
91   %0 = fmul <8 x half> %src2, %src3
96 define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
136   %0 = fmul <8 x half> %src2, %src3
182   %src3 = fptrunc float %src3o to half
183   %i = insertelement <8 x half> undef, half %src3, i32 0
239   %src3 = fptrunc float %src3o to half
240   %i = insertelement <8 x half> undef, half %src3, i32 0
247 define arm_aapcs_vfpcc <4 x float> @vfma32_v1(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
267   %0 = fmul <4 x float> %src2, %src3
272 define arm_aapcs_vfpcc <4 x float> @vfma32_v2(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
292   %0 = fmul <4 x float> %src2, %src3
297 define arm_aapcs_vfpcc <4 x float> @vfms32(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
317   %0 = fmul <4 x float> %src2, %src3
322 define arm_aapcs_vfpcc <4 x float> @vfmar32(<4 x float> %src1, <4 x float> %src2, float %src3) {
344   %i = insertelement <4 x float> undef, float %src3, i32 0
351 define arm_aapcs_vfpcc <4 x float> @vfmas32(<4 x float> %src1, <4 x float> %src2, float %src3) {
377   %i = insertelement <4 x float> undef, float %src3, i32 0
387 define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
477   %0 = fmul <8 x half> %src2, %src3
484 define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
574   %0 = fmul <8 x half> %src2, %src3
581 define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
671   %0 = fmul <8 x half> %src2, %src3
770   %src3 = fptrunc float %src3o to half
771   %i = insertelement <8 x half> undef, half %src3, i32 0
870   %src3 = fptrunc float %src3o to half
871   %i = insertelement <8 x half> undef, half %src3, i32 0
880 define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
926   %0 = fmul <4 x float> %src2, %src3
933 define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
979   %0 = fmul <4 x float> %src2, %src3
986 define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
1032   %0 = fmul <4 x float> %src2, %src3
1039 define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float> %src2, float %src3) {
1088   %i = insertelement <4 x float> undef, float %src3, i32 0
1097 define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float> %src2, float %src3) {
1144   %i = insertelement <4 x float> undef, float %src3, i32 0