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/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.h145 bool ConditionPassed(const uint32_t opcode);
147 uint32_t CurrentCond(const uint32_t opcode);
301 const uint32_t opcode,
310 static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode,
313 static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode,
317 bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding);
320 bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding);
323 bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding);
326 bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding);
329 bool EmulateMOVLowHigh(const uint32_t opcode, const ARMEncoding encoding);
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H A DEmulateInstructionARM.cpp891 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode, in EmulatePUSH() argument
921 if (ConditionPassed(opcode)) { in EmulatePUSH()
930 registers = Bits32(opcode, 7, 0); in EmulatePUSH()
932 if (Bit32(opcode, 8)) in EmulatePUSH()
940 registers = Bits32(opcode, 15, 0) & ~0xa000; in EmulatePUSH()
946 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
953 registers = Bits32(opcode, 15, 0); in EmulatePUSH()
959 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
1014 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode, in EmulatePOP() argument
1037 if (ConditionPassed(opcode)) { in EmulatePOP()
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/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td46 class IForm<bits<4> opcode, DestMode ad, bit bw, SourceMode as, int size,
54 let Inst{15-12} = opcode;
63 class IForm8<bits<4> opcode, DestMode dest, SourceMode src, int size,
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
67 class I8rr<bits<4> opcode,
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
73 class I8ri<bits<4> opcode,
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
82 class I8rc<bits<4> opcode,
91 let Inst{15-12} = opcode;
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/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalizer-info-validation.mir17 # DEBUG: G_ADD (opcode [[ADD_OPC:[0-9]+]]): 1 type index, 0 imm indices
21 # DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices
22 # DEBUG-NEXT: .. opcode [[SUB_OPC]] is aliased to [[ADD_OPC]]
26 # DEBUG-NEXT: G_MUL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
30 # DEBUG-NEXT: G_SDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices
34 # DEBUG-NEXT: G_UDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices
35 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
39 # DEBUG-NEXT: G_SREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
43 # DEBUG-NEXT: G_UREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
44 # DEBUG-NEXT: .. opcode {{[
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/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
22 let Inst{0-5} = opcode;
129 class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr,
131 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp;
134 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
136 : I<opcode, OOL, IOL, asmstr, itin> {
146 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
147 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
163 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
165 : BForm<opcode, a
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/llvm-project/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h55 static inline uint32_t DecodeImmShiftThumb(const uint32_t opcode, in DecodeImmShiftThumb() argument
57 return DecodeImmShift(Bits32(opcode, 5, 4), in DecodeImmShiftThumb()
58 Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6), in DecodeImmShiftThumb()
64 static inline uint32_t DecodeImmShiftARM(const uint32_t opcode, in DecodeImmShiftARM() argument
66 return DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); in DecodeImmShiftARM()
280 static inline uint32_t ARMExpandImm_C(uint32_t opcode, uint32_t carry_in, in ARMExpandImm_C() argument
283 uint32_t imm = bits(opcode, 7, 0); // immediate value in ARMExpandImm_C()
284 uint32_t amt = 2 * bits(opcode, 11, 8); // rotate amount in ARMExpandImm_C()
295 static inline uint32_t ARMExpandImm(uint32_t opcode) { in ARMExpandImm() argument
300 return ARMExpandImm_C(opcode, carry_in, carry_out); in ARMExpandImm()
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/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
34 let Inst{1-0} = opcode;
41 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
51 let Inst{1-0} = opcode;
57 class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
67 let Inst{1-0} = opcode;
70 class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
78 let Inst{1-0} = opcode;
84 class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
93 let Inst{1-0} = opcode;
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H A DRISCVInstrFormats.td115 // The following opcode names match those given in Table 19.1 in the
116 // RISC-V User-level ISA specification ("RISC-V base opcode map").
333 class RVInstRBase<bits<3> funct3, RISCVOpcode opcode, dag outs,
344 let Inst{6-0} = opcode.Value;
347 class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
349 : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
354 RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
356 : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
362 class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
375 let Inst{6-0} = opcode
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/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td41 // MemKey identifies a targe reg-mem opcode, while MemType can be either
43 // its corresponding target opcode. See comment at MemFoldPseudo.
2332 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2334 : InstRRE<opcode, (outs cls:$R1), (ins),
2340 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2341 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2344 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
2345 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2350 class StoreInherentS<string mnemonic, bits<16> opcode,
2352 : InstS<opcode, (out
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/llvm-project/lldb/source/Plugins/Instruction/PPC64/
H A DEmulateInstructionPPC64.cpp136 EmulateInstructionPPC64::GetOpcodeForInstruction(uint32_t opcode) { in GetOpcodeForInstruction() argument
153 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value) in GetOpcodeForInstruction()
160 const uint32_t opcode = m_opcode.GetOpcode32(); in EvaluateInstruction() local
162 Opcode *opcode_data = GetOpcodeForInstruction(opcode); in EvaluateInstruction()
181 success = (this->*opcode_data->callback)(opcode); in EvaluateInstruction()
203 bool EmulateInstructionPPC64::EmulateMFSPR(uint32_t opcode) { in EmulateMFSPR() argument
204 uint32_t rt = Bits32(opcode, 25, 21); in EmulateMFSPR()
205 uint32_t spr = Bits32(opcode, 20, 11); in EmulateMFSPR()
228 bool EmulateInstructionPPC64::EmulateLD(uint32_t opcode) { in EmulateLD() argument
229 uint32_t rt = Bits32(opcode, 25, 21); in EmulateLD()
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H A DEmulateInstructionPPC64.h74 bool (EmulateInstructionPPC64::*callback)(uint32_t opcode);
80 Opcode *GetOpcodeForInstruction(uint32_t opcode);
82 bool EmulateMFSPR(uint32_t opcode);
83 bool EmulateLD(uint32_t opcode);
84 bool EmulateSTD(uint32_t opcode);
85 bool EmulateOR(uint32_t opcode);
86 bool EmulateADDI(uint32_t opcode);
/llvm-project/llvm/test/tools/llvm-exegesis/X86/latency/
H A Dlatency-LEA64_32r.s1 …benchmark-phase=assemble-measured-code -opcode-name=LEA64_32r -repetition-mode=duplicate -max-conf…
2 …benchmark-phase=assemble-measured-code -opcode-name=LEA64_32r -repetition-mode=duplicate -max-conf…
4 … --benchmark-phase=assemble-measured-code -opcode-name=LEA64_32r -repetition-mode=loop -max-config…
5 … --benchmark-phase=assemble-measured-code -opcode-name=LEA64_32r -repetition-mode=loop -max-config…
8 …benchmark-phase=assemble-measured-code -opcode-name=LEA64_32r -repetition-mode=duplicate -max-conf…
9 …benchmark-phase=assemble-measured-code -opcode-name=LEA64_32r -repetition-mode=duplicate -max-conf…
12 … --benchmark-phase=assemble-measured-code -opcode-name=LEA64_32r -repetition-mode=loop -max-config…
13 … --benchmark-phase=assemble-measured-code -opcode-name=LEA64_32r -repetition-mode=loop -max-config…
H A Ddump-object-to-disk.s1 …own -mcpu=x86-64 -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=ADDPSrr -repe…
2 …own -mcpu=x86-64 -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=ADDPSrr -repe…
3 …own -mcpu=x86-64 -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=ADDPSrr -repe…
4 …own -mcpu=x86-64 -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=ADDPSrr -repe…
5 …own -mcpu=x86-64 -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=ADDPSrr -repe…
6 …own -mcpu=x86-64 -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=ADDPSrr -repe…
8 …cpu=x86-64 -mode=latency --benchmark-phase=prepare-and-assemble-snippet -opcode-name=ADDPSrr -repe…
9 …cpu=x86-64 -mode=latency --benchmark-phase=prepare-and-assemble-snippet -opcode-name=ADDPSrr -repe…
10 …cpu=x86-64 -mode=latency --benchmark-phase=prepare-and-assemble-snippet -opcode-name=ADDPSrr -repe…
11 …cpu=x86-64 -mode=latency --benchmark-phase=prepare-and-assemble-snippet -opcode-name=ADDPSrr -repe…
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/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp184 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) { in GetOpcodeForInstruction() argument
366 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value) in GetOpcodeForInstruction()
390 const uint32_t opcode = m_opcode.GetOpcode32(); in EvaluateInstruction() local
391 Opcode *opcode_data = GetOpcodeForInstruction(opcode); in EvaluateInstruction()
416 success = (this->*opcode_data->callback)(opcode); in EvaluateInstruction()
580 bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) { in EmulateADDSUBImm() argument
616 const uint32_t sf = Bit32(opcode, 31); in EmulateADDSUBImm()
617 const uint32_t op = Bit32(opcode, 30); in EmulateADDSUBImm()
618 const uint32_t S = Bit32(opcode, 29); in EmulateADDSUBImm()
619 const uint32_t shift = Bits32(opcode, 23, 22); in EmulateADDSUBImm()
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H A DEmulateInstructionARM64.h161 bool (EmulateInstructionARM64::*callback)(const uint32_t opcode);
165 static Opcode *GetOpcodeForInstruction(const uint32_t opcode);
175 bool EmulateADDSUBImm(const uint32_t opcode);
177 template <AddrMode a_mode> bool EmulateLDPSTP(const uint32_t opcode);
179 template <AddrMode a_mode> bool EmulateLDRSTRImm(const uint32_t opcode);
181 bool EmulateB(const uint32_t opcode);
183 bool EmulateBcond(const uint32_t opcode);
185 bool EmulateCBZ(const uint32_t opcode);
187 bool EmulateTBZ(const uint32_t opcode);
/llvm-project/llvm/test/tools/llvm-objdump/MachO/
H A Dbad-bind.test2 …object (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB bad library ordinal: 355 (max 1) for opcode at: 0x0)
5 …ect (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB malformed uleb128, extends past end for opcode at: 0x0)
8 …ormed object (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB uleb128 too big for uint64 for opcode at: 0x0)
11 …ormed object (for BIND_OPCODE_SET_DYLIB_SPECIAL_IMM unknown special ordinal: -5 for opcode at: 0x0)
14 …(for BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM symbol name extends past opcodes for opcode at: 0x2)
17 …: truncated or malformed object (for BIND_OPCODE_SET_TYPE_IMM bad bind type: 5 for opcode at: 0x14)
20 …ed object (for BIND_OPCODE_SET_ADDEND_SLEB malformed sleb128, extends past end for opcode at: 0x14)
23 …d object (for BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB bad segIndex (too large) for opcode at: 0x15)
26 …object (for BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB bad offset, not in section for opcode at: 0x15)
29 … or malformed object (for BIND_OPCODE_ADD_ADDR_ULEB bad offset, not in section for opcode at: 0x17)
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/llvm-project/llvm/include/llvm/IR/
H A DInstruction.def25 #define HANDLE_TERM_INST(num, opcode, Class)
27 #define HANDLE_TERM_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
39 #define HANDLE_UNARY_INST(num, opcode, instclass)
41 #define HANDLE_UNARY_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
53 #define HANDLE_BINARY_INST(num, opcode, instclass)
55 #define HANDLE_BINARY_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
67 #define HANDLE_MEMORY_INST(num, opcode, Class)
69 #define HANDLE_MEMORY_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
81 #define HANDLE_CAST_INST(num, opcode, Class)
83 #define HANDLE_CAST_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
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/llvm-project/mlir/unittests/Dialect/SPIRV/
H A DSerializationTest.cpp100 /// Handles a SPIR-V instruction with the given `opcode` and `operand`.
102 using HandleFn = llvm::function_ref<bool(spirv::Opcode opcode,
116 spirv::Opcode opcode = in scanInstruction() local
120 if (handleFn(opcode, operands)) in scanInstruction()
144 auto hasBlockDecoration = [](spirv::Opcode opcode, in TEST_F()
146 return opcode == spirv::Opcode::OpDecorate && operands.size() == 2 && in TEST_F()
162 auto countBlockDecoration = [&count](spirv::Opcode opcode, in TEST_F() argument
164 if (opcode == spirv::Opcode::OpDecorate && operands.size() == 2 && in TEST_F()
188 auto hasSignlessVal = [&](spirv::Opcode opcode, ArrayRef<uint32_t> operands) { in TEST_F() argument
189 return opcode in TEST_F()
163 __anon93dba63e0202(spirv::Opcode opcode, ArrayRef<uint32_t> operands) TEST_F() argument
194 __anon93dba63e0402(spirv::Opcode opcode, ArrayRef<uint32_t> operands) TEST_F() argument
209 __anon93dba63e0502(spirv::Opcode opcode, ArrayRef<uint32_t> operands) TEST_F() argument
225 __anon93dba63e0602(spirv::Opcode opcode, ArrayRef<uint32_t> operands) TEST_F() argument
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/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrFormats.td12 // opcode - operation code.
20 // <opcode | I13 | xd>
33 // <opcode | xj | xd>
45 // <opcode | rj | xd>
57 // <opcode | xj | cd>
70 // <opcode | I1 | xj | xd>
85 // <opcode | I2 | xj | xd>
99 // <opcode | I2 | rj | xd>
113 // <opcode | I2 | xj | rd>
128 // <opcode | I3 | xj | xd>
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H A DLoongArchLSXInstrFormats.td12 // opcode - operation code.
20 // <opcode | I13 | vd>
33 // <opcode | vj | vd>
45 // <opcode | rj | vd>
57 // <opcode | vj | cd>
70 // <opcode | I1 | vj | vd>
84 // <opcode | I1 | rj | vd>
98 // <opcode | I1 | vj | rd>
113 // <opcode | I2 | vj | vd>
127 // <opcode | I2 | rj | vd>
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H A DLoongArchLBTInstrFormats.td12 // opcode - operation code.
26 // <opcode | rj>
37 // <opcode | I3 | rj>
50 // <opcode | I4 | rj>
63 // <opcode | I4 | rd>
76 // <opcode | I5 | rj>
89 // <opcode | rd | I5 | I4>
104 // <opcode | rd | I5 | I8>
119 // <opcode | I6 | rj>
132 // <opcode | I8 | rd>
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/llvm-project/llvm/test/TableGen/
H A DSlice.td15 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
17 bits<8> Opcode = opcode;
65 multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
66 def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
69 def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
74 multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
75 def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
78 def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
83 multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> :
84 scalar<opcode, asmstr, patterns>,
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H A Dcast.td21 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
23 bits<8> Opcode = opcode;
72 multiclass arith<bits<8> opcode, string asmstr, string Intr> {
73 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
77 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
84 class IntInst<bits<8> opcode, string asmstr, Intrinsic Intr> :
85 Inst<opcode,(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
90 multiclass arith_int<bits<8> opcode, string asmstr, string Intr> {
91 def PS_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_ps"))>;
93 def PD_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_pd"))>;
/llvm-project/lldb/test/Shell/SymbolFile/DWARF/x86/
H A Ddwarf5-line-strp.s103 .byte 0 # opcode: 0x1 has 0 args
104 .byte 0x1 # opcode: 0x2 has 1 args
105 .byte 0x1 # opcode: 0x3 has 1 args
106 .byte 0x1 # opcode: 0x4 has 1 args
107 .byte 0x1 # opcode: 0x5 has 1 args
108 .byte 0 # opcode: 0x6 has 0 args
109 .byte 0 # opcode: 0x7 has 0 args
110 .byte 0 # opcode: 0x8 has 0 args
111 .byte 0x1 # opcode: 0x9 has 1 args
112 .byte 0 # opcode: 0xa has 0 args
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/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp24 // 2. Read the opcode, and determine what kind of opcode it is. The
30 // 3. Depending on the opcode type, look in one of four ClassDecision structures
31 // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which
32 // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get
52 // the main opcode. This is orthogonal from its meaning (an GPR or an XMM
107 // given a particular opcode.
112 // Specifies which opcode->instruction tables to look at given
124 uint8_t opcode, uint8_ in decode() argument
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