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Searched refs:getRegClass (Results 1 – 25 of 227) sorted by relevance

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/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp
/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
H A DInitUndef.cpp151 const TargetRegisterClass *TargetRegClass = MRI->getRegClass(Reg); in handleSubReg()
205 const TargetRegisterClass *TargetRegClass = MRI->getRegClass(MO.getReg()); in fixupIllOperand()
229 TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF); in processBasicBlock()
H A DPeepholeOptimizer.cpp812 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
823 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in insertPHI()
909 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in getNextRewritableSource()
937 RC = MRI->getRegClass(UseMI->getOperand(0).getReg());
1023 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in ExtractSubregRewriter()
1085 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
1115 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in getNextRewritableSource()
1280 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
1426 MRI->getRegClass(DstReg) == MRI->getRegClass(Re in foldImmediate()
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H A DRegAllocFast.cpp475 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
575 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
633 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in reload()
899 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtReg()
990 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtRegUndef()
1096 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in defineVirtReg()
1311 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in findAndSortDefOperandIndexes()
1314 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in findAndSortDefOperandIndexes()
1325 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in findAndSortDefOperandIndexes()
1378 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg in isTiedToNotUndef()
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H A DDetectDeadLanes.cpp73 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy()
170 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
289 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
447 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput()
H A DRegAllocBase.cpp108 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
126 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); in allocatePhysRegs()
H A DModuloSchedule.cpp553 const TargetRegisterClass *RC = MRI.getRegClass(Def); in generateExistingPhis()
692 const TargetRegisterClass *RC = MRI.getRegClass(Def); in generatePhis()
828 SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def)); in splitLifetimes()
1042 const TargetRegisterClass *RC = MRI.getRegClass(reg); in updateInstruction()
1191 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1195 Register SplitReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1247 MRI.getRegClass(MI.getOperand(0).getReg())); in EliminateDeadPhis()
1446 LoopReg = phi(LoopReg, *DefaultI++, MRI.getRegClass(Reg)); in remapUse()
1454 auto RC = MRI.getRegClass(Reg); in remapUse()
1499 MRI.constrainRegClass(R, MRI.getRegClass(*InitRe in phi()
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/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp67 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
149 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
H A DWebAssemblyExplicitLocals.cpp311 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); in runOnMachineFunction()
344 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
416 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
452 typeForRegClass(MRI.getRegClass(Reg))); in runOnMachineFunction()
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp261 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
326 const TargetRegisterClass *RC = MRI->getRegClass(DstReg); in visitINSERT()
549 TII->getRegClass(TII->get(Opcode.first), 0, TRI, *MF); in splitTwoPartImm()
551 TII->getRegClass(TII->get(Opcode.first), 1, TRI, *MF); in splitTwoPartImm()
555 : TII->getRegClass(TII->get(Opcode.second), 0, TRI, *MF); in splitTwoPartImm()
559 : TII->getRegClass(TII->get(Opcode.second), 1, TRI, *MF); in splitTwoPartImm()
575 MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg)); in visitINSviGPR()
619 if (MRI->getRegClass(SrcMI->getOperand(1).getReg()) == in is64bitDefwithZeroHigh64bit()
647 const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg()); in visitINSvi64lane()
696 MRI->constrainRegClass(NewDef, MRI->getRegClass(OldDe in runOnMachineFunction()
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/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
271 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
515 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
516 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
532 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
538 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
636 MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg())); in runOnInstruction()
H A DARMRegisterBankInfo.cpp147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp129 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
130 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
171 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
210 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getSubRegIndex()
213 return getRegClass(Ty, RegBank); in getSubRegIndex()
262 RC = getRegClass(Ty, RB); in selectDebugInstr()
293 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
323 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
810 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
811 const TargetRegisterClass *SrcRC = getRegClass(SrcT in selectTruncOrPtrToInt()
172 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { getRegClass() function in X86InstructionSelector
202 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, getRegClass() function in X86InstructionSelector
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/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp127 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
128 MRI.getRegClass(AddendSrcReg)) in processBlock()
133 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
233 MRI.getRegClass(OldFMAReg))) in processBlock()
/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp80 unsigned RegClassID = MRI->getRegClass(Reg)->getID(); in INITIALIZE_PASS_DEPENDENCY()
179 unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs(); in INITIALIZE_PASS_DEPENDENCY()
244 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R));
H A DX86FastPreTileConfig.cpp125 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
206 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
221 const TargetRegisterClass &RC = *MRI->getRegClass(OrigReg); in reload()
272 unsigned RegClassID = MRI->getRegClass(Reg)->getID(); in isTileDef()
/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNPreRAOptimizations.cpp91 bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg)); in processReg()
113 bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg)); in processReg()
231 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in runOnMachineFunction()
H A DSIFixSGPRCopies.cpp208 ? MRI.getRegClass(SrcReg)
215 ? MRI.getRegClass(DstReg)
259 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
283 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
671 const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg()); in runOnMachineFunction()
829 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes); in processPHINode()
866 MRI->getRegClass(MaybeVGPRConstMO.getReg()); in tryMoveVGPRConstToSGPR()
888 TRI->hasVectorRegisters(MRI->getRegClass(SrcReg))) { in lowerSpecialCase()
924 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in analyzeVGPRToSGPRCopy()
H A DGCNRewritePartialRegUses.cpp208 auto *RC = TRI->getRegClass(ClassID); in getAllocatableAndAlignedRegClassMask()
269 auto *RC = TRI->getRegClass(ClassID); in getRegClassWithShiftedSubregs()
405 return TII->getRegClass(TII->get(MI->getOpcode()), MI->getOperandNo(&MO), TRI, in getOperandRegClass()
416 auto *RC = MRI->getRegClass(Reg); in rewriteReg()
/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp865 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) in printRangePrefetchAlias()
867 &MRI.getRegClass(AArch64::GPR64RegClassID)); in printRangePrefetchAlias()
1672 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || in printVectorList()
1673 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || in printVectorList()
1674 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) || in printVectorList()
1675 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) || in printVectorList()
1676 MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) in printVectorList()
1678 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || in printVectorList()
1679 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || in printVectorList()
1680 MRI.getRegClass(AArch6 in printVectorList()
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/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h315 unsigned getRegClass() const { return Bitfield::get<RegClass>(Storage); } in getRegClass() function
377 if (!getRegClass()) in hasRegClassConstraint()
379 RC = getRegClass() - 1; in hasRegClassConstraint()
403 assert(getRegClass() == 0 && "Register class already set"); in setRegClass()
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp140 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
335 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
434 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
478 if (MRI->getRegClass(DR.R) != PredRC) in eliminatePredCopies()
480 if (MRI->getRegClass(SR.R) != PredRC) in eliminatePredCopies()
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp133 TII->getRegClass(II, i + II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
158 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
205 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
234 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
338 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
412 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF)) in AddOperand()
475 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
541 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
598 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
639 TRI->getAllocatableClass(TRI->getRegClass(DstRCId in EmitCopyToRegClassNode()
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