| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 33 cl::desc("Use TargetSchedModel for latency lookup"));
42 bool TargetSchedModel::hasInstrSchedModel() const {
46 bool TargetSchedModel::hasInstrItineraries() const {
50 void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo) {
72 bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI,
83 bool TargetSchedModel::mustEndGroup(const MachineInstr *MI,
94 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
119 const MCSchedClassDesc *TargetSchedModel::
172 unsigned TargetSchedModel::computeOperandLatency(
239 TargetSchedModel
[all...] |
| H A D | MachineTraceMetrics.cpp | 139 for (TargetSchedModel::ProcResIter in getResources()
935 const TargetSchedModel &SchedModel, in updatePhysDepsUpwards()
992 const TargetSchedModel &SchedModel, in addLiveIns()
1273 for (TargetSchedModel::ProcResIter in getResourceLength()
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| H A D | MachineScheduler.cpp | 1011 for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), in dumpScheduleTraceTopDown()
1093 for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), in dumpScheduleTraceBottomUp()
2279 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { in reset()
2288 for (TargetSchedModel::ProcResIter in init()
2301 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) { in init()
2740 for (TargetSchedModel::ProcResIter in bumpNode()
2754 for (TargetSchedModel::ProcResIter in bumpNode()
2971 const TargetSchedModel *SchedModel) {
2976 for (TargetSchedModel::ProcResIter in initResourceDelta()
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| H A D | VLIWMachineScheduler.cpp | 66 const TargetSchedModel *SM) in VLIWResourceModel()
303 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in initialize()
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | VLIWMachineScheduler.h | 40 const TargetSchedModel *SchedModel;
50 VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM);
129 const TargetSchedModel *SchedModel = nullptr;
158 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) { in init()
212 const TargetSchedModel *SchedModel = nullptr;
246 const TargetSchedModel *SchedModel) const;
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| H A D | TargetSubtargetInfo.h | 54 class TargetSchedModel; variable
147 const TargetSchedModel *SchedModel) const { in resolveSchedClass()
253 const TargetSchedModel *SchedModel) const { in getCriticalPathRCs()
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| H A D | TargetSchedule.h | 30 class TargetSchedModel {
49 TargetSchedModel() : SchedModel(MCSchedModel::Default) {} in TargetSchedModel() function
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| H A D | MachineScheduler.h | 620 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
851 const TargetSchedModel *SchedModel = nullptr;
962 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
1074 /// scheduling candidates based on TargetSchedModel making it easy to implement
1171 const TargetSchedModel *SchedModel);
1176 const TargetSchedModel *SchedModel = nullptr;
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| H A D | ScheduleDAGInstrs.h | 120 /// TargetSchedModel provides an interface to the machine model.
121 TargetSchedModel SchedModel;
277 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
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| H A D | MachineTraceMetrics.h | 103 TargetSchedModel SchedModel;
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| H A D | TargetInstrInfo.h | 65 class TargetSchedModel;
1829 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1839 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
64 class TargetSchedModel; global() variable
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.h | 48 const TargetSchedModel *SchedModel;
111 const TargetSchedModel *SM) in SystemZHazardRecognizer()
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| H A D | SystemZHazardRecognizer.cpp | 175 for (TargetSchedModel::ProcResIter in dumpSU()
296 for (TargetSchedModel::ProcResIter in EmitInstruction()
400 for (TargetSchedModel::ProcResIter in resourcesCost()
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| H A D | SystemZMachineScheduler.h | 36 TargetSchedModel SchedModel;
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.h | 35 const TargetSchedModel *SchedModel) const override;
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| H A D | HexagonMachineScheduler.cpp | 41 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in createVLIWResourceModel()
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| H A D | HexagonSubtarget.h | 327 const TargetSchedModel *SchedModel) const override; in getHVXElementTypes()
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNHazardRecognizer.h | 49 const TargetSchedModel &TSchedModel;
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| H A D | GCNSchedStrategy.h | 369 const TargetSchedModel &SM);
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| H A D | AMDGPUInsertDelayAlu.cpp | 33 const TargetSchedModel *SchedModel;
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 35 TargetSchedModel SchedModel;
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| H A D | AArch64Schedule.td | 10 // const MachineInstr *MI and const TargetSchedModel *SchedModel
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| H A D | AArch64Subtarget.h | 343 const TargetSchedModel *SchedModel) const override; in swiftAsyncContextIsDynamicallySet()
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86PadShortFunction.cpp | 91 TargetSchedModel TSM;
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 473 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
478 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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