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Searched refs:SchedModel (Results 1 – 25 of 133) sorted by relevance

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/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp43 return EnableSchedModel && SchedModel.hasInstrSchedModel(); in hasInstrSchedModel()
52 SchedModel = TSInfo->getSchedModel(); in init()
56 unsigned NumRes = SchedModel.getNumProcResourceKinds(); in init()
58 ResourceLCM = SchedModel.IssueWidth; in init()
60 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits; in init()
64 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
66 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits; in init()
123 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
134 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
177 const unsigned DefaultDefLatency = TII->defaultDefLatency(SchedModel, *DefM in computeOperandLatency()
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H A DMachineScheduler.cpp995 if (!SchedModel.hasInstrSchedModel())
1011 for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), in dumpScheduleTraceTopDown()
1012 PE = SchedModel.getWriteProcResEnd(SC); in dumpScheduleTraceTopDown()
1044 make_range(SchedModel.getWriteProcResBegin(SC), in dumpScheduleTraceTopDown()
1045 SchedModel.getWriteProcResEnd(SC))); in dumpScheduleTraceTopDown()
1058 SchedModel.getResourceName(PI.ProcResourceIdx); in dumpScheduleTraceTopDown()
1076 if (!SchedModel.hasInstrSchedModel()) in dumpScheduleTraceTopDown()
1093 for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), in dumpScheduleTraceBottomUp()
1094 PE = SchedModel.getWriteProcResEnd(SC); in dumpScheduleTraceBottomUp()
1125 make_range(SchedModel in dumpScheduleTraceBottomUp()
2282 init(ScheduleDAGMI * DAG,const TargetSchedModel * SchedModel) init() argument
2974 initResourceDelta(const ScheduleDAGMI * DAG,const TargetSchedModel * SchedModel) initResourceDelta() argument
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H A DMachineTraceMetrics.cpp82 SchedModel.init(&ST); in releaseMemory()
85 SchedModel.getNumProcResourceKinds()); in releaseMemory()
122 unsigned PRKinds = SchedModel.getNumProcResourceKinds(); in getResources()
133 if (!SchedModel.hasInstrSchedModel()) in getResources()
135 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI); in getResources()
140 PI = SchedModel.getWriteProcResBegin(SC), in getResources()
141 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) { in getResources()
152 PRCycles[K] * SchedModel.getResourceFactor(K);
161 unsigned PRKinds = SchedModel.getNumProcResourceKinds(); in Ensemble()
173 unsigned PRKinds = MTM.SchedModel
907 updatePhysDepsUpwards(const MachineInstr & MI,unsigned Height,SparseSet<LiveRegUnit> & RegUnits,const TargetSchedModel & SchedModel,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) updatePhysDepsUpwards() argument
964 pushDepHeight(const DataDep & Dep,const MachineInstr & UseMI,unsigned UseHeight,MIHeightMap & Heights,const TargetSchedModel & SchedModel,const TargetInstrInfo * TII) pushDepHeight() argument
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H A DVLIWMachineScheduler.cpp67 : TII(STI.getInstrInfo()), SchedModel(SM) { in VLIWResourceModel()
74 Packet.reserve(SchedModel->getIssueWidth()); in VLIWResourceModel()
156 Packet.size() >= SchedModel->getIssueWidth()) { in reserveResources()
272 SchedModel = DAG->getSchedModel(); in initialize()
274 Top.init(DAG, SchedModel); in initialize()
275 Bot.init(DAG, SchedModel); in initialize()
303 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in initialize()
304 return new VLIWResourceModel(STI, SchedModel);
362 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
363 if (IssueCount + uops > SchedModel in checkHazard()
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H A DScheduleDAGInstrs.cpp124 SchedModel.init(&ST); in ScheduleDAGInstrs()
281 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
286 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOpIdx, Dep, &SchedModel); in addPhysRegDataDeps()
325 SchedModel.computeOutputLatency(MI, OperIdx, DefInstr)); in addPhysRegDeps()
328 &SchedModel); in addPhysRegDeps()
456 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use, in addVRegDefDeps()
459 &SchedModel); in addVRegDefDeps()
501 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
589 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr()); in initSUnits()
599 if (SchedModel in initSUnits()
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H A DEarlyIfConversion.cpp767 MCSchedModel SchedModel;
928 unsigned CritLimit = SchedModel.MispredictPenalty/2; in shouldConvertIf()
1101 SchedModel = STI.getSchedModel(); in runOnMachineFunction()
1159 TargetSchedModel SchedModel; in shouldConvertIf()
1211 unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);
1225 unsigned NumCycles = SchedModel.computeInstrLatency(&I, false); in runOnMachineFunction()
1231 unsigned NumCycles = SchedModel.computeInstrLatency(&I, false); in runOnMachineFunction()
1267 SchedModel.init(&STI);
763 MCSchedModel SchedModel; global() member in __anondae13cb90311::EarlyIfConverter
1116 TargetSchedModel SchedModel; global() member in __anondae13cb90b11::EarlyIfPredicator
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h33 MCSchedModel SchedModel; variable
49 TargetSchedModel() : SchedModel(MCSchedModel::Default) {} in TargetSchedModel()
74 const MCSchedModel *getMCSchedModel() const { return &SchedModel; } in getMCSchedModel()
95 unsigned getProcessorID() const { return SchedModel.getProcessorID(); } in getProcessorID()
98 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
113 return SchedModel.getNumProcResourceKinds(); in getNumProcResourceKinds()
118 return SchedModel.getProcResource(PIdx); in getProcResource()
125 return SchedModel.getProcResource(PIdx)->Name; in getResourceName()
160 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } in getMicroOpBufferSize()
165 return SchedModel.getProcResource(PIdx)->BufferSize; in getResourceBufferSize()
H A DVLIWMachineScheduler.h40 const TargetSchedModel *SchedModel; variable
129 const TargetSchedModel *SchedModel = nullptr; member
160 SchedModel = smodel; in init()
169 CriticalPathLength = BBSize / SchedModel->getIssueWidth(); in init()
212 const TargetSchedModel *SchedModel = nullptr; variable
246 const TargetSchedModel *SchedModel) const;
H A DScheduleDAGInstrs.h121 TargetSchedModel SchedModel;
277 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
281 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in IsReachable()
282 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
120 TargetSchedModel SchedModel; global() variable
H A DMachineScheduler.h620 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
851 const TargetSchedModel *SchedModel = nullptr;
997 return RetiredMOps * SchedModel->getMicroOpFactor(); in getExecutedCount()
1005 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
1028 return SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin &&
1029 !SchedModel->getProcResource(PIdx)->BufferSize;
1171 const TargetSchedModel *SchedModel);
1176 const TargetSchedModel *SchedModel = nullptr;
842 const TargetSchedModel *SchedModel = nullptr; global() variable
1167 const TargetSchedModel *SchedModel = nullptr; global() variable
H A DTargetSubtargetInfo.h147 const TargetSchedModel *SchedModel) const { in resolveSchedClass()
253 const TargetSchedModel *SchedModel) const { in getCriticalPathRCs()
146 resolveSchedClass(unsigned SchedClass,const MachineInstr * MI,const TargetSchedModel * SchedModel) resolveSchedClass() argument
242 adjustSchedDependency(SUnit * Def,int DefOpIdx,SUnit * Use,int UseOpIdx,SDep & Dep,const TargetSchedModel * SchedModel) adjustSchedDependency() argument
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp152 for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i) in nextGroup()
176 PI = SchedModel->getWriteProcResBegin(SC), in dumpSU()
177 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { in dumpSU()
179 *SchedModel->getProcResource(PI->ProcResourceIdx); in dumpSU()
226 for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i) in dumpProcResourceCounters()
236 for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i) in dumpProcResourceCounters()
238 dbgs() << SchedModel->getProcResource(i)->Name in dumpProcResourceCounters()
244 << SchedModel->getProcResource(CriticalResourceIdx)->Name in dumpProcResourceCounters()
260 ProcResourceCounters.assign(SchedModel->getNumProcResourceKinds(), 0); in clearProcResCounters()
297 PI = SchedModel->getWriteProcResBegin(SC), in EmitInstruction()
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H A DSystemZHazardRecognizer.h48 const TargetSchedModel *SchedModel; variable
112 : TII(tii), SchedModel(SM) { in SystemZHazardRecognizer()
122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel()) in getSchedClass()
123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp35 TargetSchedModel SchedModel; member in __anonb6bec6d80111::AArch64StorePairSuppress
88 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldAddSTPToBlock()
92 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx2); in shouldAddSTPToBlock()
141 SchedModel.init(&ST); in runOnMachineFunction()
147 if (!SchedModel.hasInstrSchedModel()) { in runOnMachineFunction()
H A DAArch64SIMDInstrOpt.cpp72 TargetSchedModel SchedModel; member
223 std::string Subtarget = std::string(SchedModel.getSubtargetInfo()->getCPU()); in shouldReplaceInst()
231 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldReplaceInst()
243 SCDescRepl = SchedModel.getMCSchedModel()->getSchedClassDesc( in shouldReplaceInst()
255 ReplCost += SchedModel.computeInstrLatency(IDesc->getOpcode()); in shouldReplaceInst()
257 if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost) in shouldReplaceInst()
294 std::string(SchedModel.getSubtargetInfo()->getCPU()); in shouldExitEarly()
706 SchedModel.init(&ST); in runOnMachineFunction()
707 if (!SchedModel.hasInstrSchedModel()) in runOnMachineFunction()
H A DAArch64SchedKryo.td41 let SchedModel = KryoModel in {
60 let SchedModel = KryoModel in {
141 } // SchedModel = KryoModel
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSISchedule.td15 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
215 let SchedModel = SIFullSpeedModel in {
231 } // End SchedModel = SIFullSpeedModel
233 let SchedModel = SIQuarterSpeedModel in {
253 } // End SchedModel = SIQuarterSpeedModel
255 let SchedModel = SIDPFullSpeedModel in {
277 } // End SchedModel = SIDPFullSpeedModel
279 let SchedModel = SIDPGFX940FullSpeedModel in {
311 } // End SchedModel = SIDPGFX940FullSpeedModel
314 let SchedModel
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H A DAMDGPUInsertDelayAlu.cpp33 const TargetSchedModel *SchedModel; member in __anona99e5d4a0111::AMDGPUInsertDelayAlu
390 unsigned Latency = SchedModel->computeOperandLatency( in runOnMachineBasicBlock()
432 SchedModel = &SII->getSchedModel(); in runOnMachineFunction()
/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td185 // SchedModel ties these units to a processor for any stand-alone defs
192 SchedMachineModel SchedModel = ?;
202 SchedMachineModel SchedModel = ?;
240 // SchedModel silences warnings but is ignored.
244 SchedMachineModel SchedModel = ?;
249 // SchedModel ties these resources to a processor.
274 SchedMachineModel SchedModel = ?;
316 // type at the same time. This class is unaware of its SchedModel so
323 // SchedModel ties these resources to a processor.
330 SchedMachineModel SchedModel = ?;
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/llvm-project/llvm/test/TableGen/
H A DInvalidMCSchedClassDesc.td23 let SchedModel = SchedModel_A in {
32 let SchedModel = SchedModel_B in {
40 let SchedModel = SchedModel_C in {
/llvm-project/llvm/unittests/Target/AArch64/
H A DAArch64SVESchedPseudoTest.cpp61 MCSchedModel SchedModel = STI->getSchedModel(); in runSVEPseudoTestForCPU() local
80 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCClass); in runSVEPseudoTestForCPU()
85 SchedModel.getSchedClassDesc(SCClassOrig); in runSVEPseudoTestForCPU()
/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h112 MCSchedModel SchedModel =
123 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F), in InstrItineraryData()
124 Itineraries(SchedModel.InstrItineraries) {} in InstrItineraryData()
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp41 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in createVLIWResourceModel()
42 return new HexagonVLIWResourceModel(STI, SchedModel); in createVLIWResourceModel()
/llvm-project/llvm/lib/MC/
H A DMCSubtargetInfo.cpp344 assert(CPUEntry->SchedModel && "Missing processor SchedModel value"); in getEnabledProcessorFeatures()
345 return *CPUEntry->SchedModel; in getEnabledProcessorFeatures()
350 const MCSchedModel &SchedModel = getSchedModelForCPU(CPU); in getCacheSize()
351 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); in getCacheSize()
330 const MCSchedModel &SchedModel = getSchedModelForCPU(CPU); getInstrItineraryForCPU() local
/llvm-project/llvm/tools/llvm-exegesis/lib/
H A DSchedClassResolution.cpp279 const auto &SchedModel = STI.getSchedModel(); in findProcResIdx() local
280 for (int I = 0, E = SchedModel.getNumProcResourceKinds(); I < E; ++I) { in findProcResIdx()
281 if (NameOrId == SchedModel.getProcResource(I)->Name) in findProcResIdx()

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