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Searched refs:ProcResource (Results 1 – 25 of 77) sorted by relevance

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/llvm-project/llvm/tools/llvm-mca/Views/
H A DResourcePressureView.cpp29 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in ResourcePressureView() local
30 unsigned NumUnits = ProcResource.NumUnits; in ResourcePressureView()
32 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in ResourcePressureView()
36 R2VIndex += ProcResource.NumUnits; in ResourcePressureView()
73 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printColumnNames() local
74 unsigned NumUnits = ProcResource.NumUnits; in printColumnNames()
76 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printColumnNames()
112 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printResourcePressurePerIter() local
113 unsigned NumUnits = ProcResource.NumUnits; in printResourcePressurePerIter()
115 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printResourcePressurePerIter()
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H A DSchedulerStatistics.cpp140 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printSchedulerUsage() local
141 if (ProcResource.BufferSize <= 0) in printSchedulerUsage()
146 double AlmostFullThreshold = (double)(ProcResource.BufferSize * 4) / 5; in printSchedulerUsage()
150 FOS << ProcResource.Name; in printSchedulerUsage()
159 BU.MaxUsedSlots == static_cast<unsigned>(ProcResource.BufferSize)) in printSchedulerUsage()
165 FOS << ProcResource.BufferSize << '\n'; in printSchedulerUsage()
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td39 def FalkorUnitB : ProcResource<1>; // Branch
40 def FalkorUnitLD : ProcResource<1>; // Load pipe
41 def FalkorUnitSD : ProcResource<1>; // Store data
42 def FalkorUnitST : ProcResource<1>; // Store pipe
43 def FalkorUnitX : ProcResource<1>; // Complex arithmetic
44 def FalkorUnitY : ProcResource<1>; // Simple arithmetic
45 def FalkorUnitZ : ProcResource<1>; // Simple arithmetic
47 def FalkorUnitVSD : ProcResource<1>; // Vector store data
48 def FalkorUnitVX : ProcResource<1>; // Vector X-pipe
49 def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe
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H A DAArch64SchedExynosM5.td38 def M5UnitA : ProcResource<2>; // Simple integer
39 def M5UnitC : ProcResource<2>; // Simple and complex integer
41 def M5UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
42 def M5UnitE : ProcResource<2>; // Simple 32-bit integer
44 def M5UnitF : ProcResource<2>; // CRC (inside C)
45 def M5UnitB : ProcResource<1>; // Branch
46 def M5UnitL0 : ProcResource<1>; // Load
47 def M5UnitS0 : ProcResource<1>; // Store
48 def M5PipeLS : ProcResource<1>; // Load/Store
50 def M5UnitL1 : ProcResource<1>;
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H A DAArch64SchedExynosM3.td39 def M3UnitA : ProcResource<2>; // Simple integer
40 def M3UnitC : ProcResource<2>; // Simple and complex integer
41 def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
42 def M3UnitB : ProcResource<2>; // Branch
43 def M3UnitL : ProcResource<2>; // Load
44 def M3UnitS : ProcResource<1>; // Store
45 def M3PipeF0 : ProcResource<1>; // FP #0
47 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
48 def M3UnitFADD0 : ProcResource<1>; // Simple FP
49 def M3UnitFCVT0 : ProcResource<1>; // FP conversion
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H A DAArch64SchedExynosM4.td38 def M4UnitA : ProcResource<2>; // Simple integer
39 def M4UnitC : ProcResource<2>; // Simple and complex integer
41 def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
43 def M4UnitE : ProcResource<1>; // CRC (inside C0)
44 def M4UnitB : ProcResource<2>; // Branch
45 def M4UnitL0 : ProcResource<1>; // Load
46 def M4UnitS0 : ProcResource<1>; // Store
47 def M4PipeLS : ProcResource<1>; // Load/Store
49 def M4UnitL1 : ProcResource<1>;
50 def M4UnitS1 : ProcResource<1>;
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H A DAArch64SchedKryo.td42 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops
43 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops
44 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops
45 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops
54 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops
55 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
H A DAArch64SchedA53.td39 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
42 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
43 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
44 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
45 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
46 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
47 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
48 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSyntacoreSCR3.td
H A DRISCVSchedSyntacoreSCR1.td33 def SCR1_ALU : ProcResource<1>;
34 def SCR1_LSU : ProcResource<1>;
35 def SCR1_MUL : ProcResource<1>;
36 def SCR1_DIV : ProcResource<1>;
37 def SCR1_CFU : ProcResource<1>;
H A DRISCVSchedRocket.td29 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
33 def RocketUnitALU : ProcResource<1>; // Int ALU
34 def RocketUnitIMul : ProcResource<1>; // Int Multiply
35 def RocketUnitMem : ProcResource<1>; // Load/Store
36 def RocketUnitB : ProcResource<1>; // Branch
38 def RocketUnitFPALU : ProcResource<1>; // FP ALU
42 def RocketUnitIDiv : ProcResource<1>; // Int Division
43 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
H A DRISCVSchedXiangShanNanHu.td34 def XS2ALU : ProcResource<4>;
35 def XS2MDU : ProcResource<2>;
36 def XS2MISC : ProcResource<1>;
38 def XS2FMAC : ProcResource<4>;
39 def XS2FMISC : ProcResource<2>;
42 def XS2LD : ProcResource<2>;
43 def XS2ST : ProcResource<2>;
H A DRISCVSchedSiFiveP400.td139 def SiFiveP400IEXQ0 : ProcResource<1>;
140 def SiFiveP400IEXQ1 : ProcResource<1>;
141 def SiFiveP400IEXQ2 : ProcResource<1>;
142 def SiFiveP400FEXQ0 : ProcResource<1>;
143 def SiFiveP400Load : ProcResource<1>;
144 def SiFiveP400Store : ProcResource<1>;
151 def SiFiveP400Div : ProcResource<1>;
155 def SiFiveP400FloatDiv : ProcResource<1>;
158 def SiFiveP400VEXQ0 : ProcResource<1>;
159 def SiFiveP400VLD : ProcResource<
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/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td56 def DISPx02 : ProcResource<2>;
57 def DISPx13 : ProcResource<2>;
60 def DISPxab : ProcResource<2>;
62 def DISPb01 : ProcResource<2>;
76 def IP_AGEN : ProcResource<4>;
77 def IP_EXEC : ProcResource<4>;
78 def IP_EXECE : ProcResource<2> {
82 def IP_EXECO : ProcResource<2> {
89 def ALU : ProcResource<4>;
90 def ALUE : ProcResource<2> {
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H A DPPCScheduleP8.td30 def P8_LU_LS_FX : ProcResource<6>;
31 def P8_LU_LS : ProcResource<4> { let Super = P8_LU_LS_FX; }
32 def P8_LS : ProcResource<2> { let Super = P8_LU_LS; }
33 def P8_LU : ProcResource<2> { let Super = P8_LU_LS; }
34 def P8_FX : ProcResource<2> { let Super = P8_LU_LS_FX; }
35 def P8_DFU : ProcResource<1>;
36 def P8_BR : ProcResource<1> { let BufferSize = 16; }
37 def P8_CY : ProcResource<1>;
38 def P8_CRL : ProcResource<1>;
39 def P8_VMX : ProcResource<2>;
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H A DPPCScheduleP10.td42 def P10_BF : ProcResource<4>; // Four Binary Floating Point pipelines.
43 def P10_BR : ProcResource<2>; // Two Branch pipelines.
44 def P10_CY : ProcResource<4>; // Four Crypto pipelines.
45 def P10_DF : ProcResource<1>; // One Decimal Floating Point pipelines.
46 def P10_DV : ProcResource<2>; // Two Fixed-point divide (DIV) pipelines.
47 def P10_DX : ProcResource<2>; // Two 128-bit fixed-point and BCD pipelines.
48 def P10_FX : ProcResource<4>; // Four ALU pipelines.
49 def P10_LD : ProcResource<2>; // Two Load pipelines.
50 def P10_MM : ProcResource<2>; // Two 512-bit SIMD matrix multiply engine pipelines.
51 def P10_PM : ProcResource<4>; // Four 128-bit permute (PM) pipelines.
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H A DPPCScheduleP7.td37 def P7_LSU_FXU: ProcResource<4>;
38 def P7_LSU: ProcResource<2> {
41 def P7_FXU: ProcResource<2> {
45 def P7_FPU: ProcResource<4>;
47 def P7_ScalarFPU: ProcResource<2> {
50 def P7_VectorFPU: ProcResource<2> {
54 def P7_VMX: ProcResource<1>;
55 def P7_VPM: ProcResource<1> {
59 def P7_VXS: ProcResource<1> {
62 def P7_DFU: ProcResource<
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/llvm-project/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp34 const MCProcResourceDesc &ProcResource = *SM.getProcResource(Index); in execute() local
35 unsigned NumUnits = ProcResource.NumUnits; in execute()
36 if (!ProcResource.SubUnitsIdxBegin) { in execute()
50 unsigned SubUnitIdx = ProcResource.SubUnitsIdxBegin[I1]; in execute()
/llvm-project/llvm/tools/llvm-mca/
H A DPipelinePrinter.cpp86 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in getJSONTargetInfo() local
87 unsigned NumUnits = ProcResource.NumUnits; in getJSONTargetInfo()
88 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in getJSONTargetInfo()
92 std::string ResourceName = ProcResource.Name; in getJSONTargetInfo()
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSISchedule.td104 def HWBranch : ProcResource<1> {
107 def HWExport : ProcResource<1> {
110 def HWLGKM : ProcResource<1> {
113 def HWSALU : ProcResource<1> {
116 def HWVMEM : ProcResource<1> {
119 def HWVALU : ProcResource<1> {
122 def HWTransVALU : ProcResource<1> { // Transcendental VALU
125 def HWRC : ProcResource<1> { // Register destination cache
128 def HWXDL : ProcResource<1> { // MFMA CU
/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM85.td39 def M85UnitLoadL : ProcResource<1> { let BufferSize = 0; }
40 def M85UnitLoadH : ProcResource<1> { let BufferSize = 0; }
42 def M85UnitStoreL : ProcResource<1> { let BufferSize = 0; }
43 def M85UnitStoreH : ProcResource<1> { let BufferSize = 0; }
45 def M85UnitALU : ProcResource<2> { let BufferSize = 0; }
46 def M85UnitShift1 : ProcResource<1> { let BufferSize = 0; }
47 def M85UnitShift2 : ProcResource<1> { let BufferSize = 0; }
48 def M85UnitMAC : ProcResource<1> { let BufferSize = 0; }
49 def M85UnitBranch : ProcResource<1> { let BufferSize = 0; }
50 def M85UnitVFPAL : ProcResource<
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H A DARMScheduleM7.td38 def M7UnitLoadL : ProcResource<1> { let BufferSize = 0; }
39 def M7UnitLoadH : ProcResource<1> { let BufferSize = 0; }
41 def M7UnitStore : ProcResource<1> { let BufferSize = 0; }
42 def M7UnitALU : ProcResource<2>;
43 def M7UnitShift1 : ProcResource<1> { let BufferSize = 0; }
44 def M7UnitShift2 : ProcResource<1> { let BufferSize = 0; }
45 def M7UnitMAC : ProcResource<1> { let BufferSize = 0; }
46 def M7UnitBranch : ProcResource<1> { let BufferSize = 0; }
47 def M7UnitVFP : ProcResource<1> { let BufferSize = 0; }
48 def M7UnitVPortL : ProcResource<
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/llvm-project/llvm/test/TableGen/
H A DAcquireAtCycle.td21 def ResX0 : ProcResource<1>; // X0
22 def ResX1 : ProcResource<1>; // X1
23 def ResX2 : ProcResource<1>; // X2
/llvm-project/llvm/include/llvm/Target/
H A DTargetPfmCounters.td21 // Issue counters can be tied to a ProcResource
24 // The name of the ProcResource on which uops are issued. This is used by
27 // ProcResource.
/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td32 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
33 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
47 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
48 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
49 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
50 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
52 def P5600AL2Div : ProcResource<1>;
54 def P5600CTISTD : ProcResource<1>;
231 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
232 def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; }
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