1// RUN: llvm-tblgen -gen-subtarget -DCORRECT -I %p/../../include %s 2>&1 | \ 2// RUN: FileCheck %s --check-prefix=CORRECT 3 4// RUN: not llvm-tblgen -gen-subtarget -DWRONG_SIZE -I %p/../../include %s 2>&1 | \ 5// RUN: FileCheck %s --check-prefix=WRONG_SIZE 6 7// RUN: not llvm-tblgen -gen-subtarget -DWRONG_VALUE -I %p/../../include %s 2>&1 | \ 8// RUN: FileCheck %s --check-prefix=WRONG_VALUE 9 10// RUN: not llvm-tblgen -gen-subtarget -DNEGATIVE_INVALID -I %p/../../include %s 2>&1 | \ 11// RUN: FileCheck %s --check-prefix=NEGATIVE_INVALID 12 13// Make sure that AcquireAtCycle in WriteRes is used to generate the 14// correct data. 15 16include "llvm/Target/Target.td" 17 18def MyTarget : Target; 19 20let BufferSize = 0 in { 21def ResX0 : ProcResource<1>; // X0 22def ResX1 : ProcResource<1>; // X1 23def ResX2 : ProcResource<1>; // X2 24} 25 26let OutOperandList = (outs), InOperandList = (ins) in { 27 def Inst_A : Instruction; 28 def Inst_B : Instruction; 29} 30 31let CompleteModel = 0 in { 32 def SchedModel_A: SchedMachineModel; 33} 34 35def WriteInst_A : SchedWrite; 36def WriteInst_B : SchedWrite; 37 38let SchedModel = SchedModel_A in { 39// Check the generated data when there are no semantic issues. 40#ifdef CORRECT 41// CORRECT-LABEL: llvm::MCWriteProcResEntry MyTargetWriteProcResTable[] = { 42// CORRECT-NEXT: { 0, 0, 0 }, // Invalid 43def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> { 44// CORRECT-NEXT: { 1, 2, 0}, // #1 45// CORRECT-NEXT: { 2, 4, 1}, // #2 46// CORRECT-NEXT: { 3, 3, 2}, // #3 47 let ReleaseAtCycles = [2, 4, 3]; 48 let AcquireAtCycles = [0, 1, 2]; 49} 50def : WriteRes<WriteInst_B, [ResX2]> { 51// If unspecified, AcquireAtCycle is set to 0. 52// CORRECT-NEXT: { 3, 1, 0} // #4 53 let ReleaseAtCycles = [1]; 54} 55#endif // CORRECT 56 57#ifdef WRONG_SIZE 58// WRONG_SIZE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(AcquireAtCycles) != size(ProcResources): 2 vs 3 59def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> { 60 let ReleaseAtCycles = [2, 4, 3]; 61 let AcquireAtCycles = [0, 1]; 62} 63#endif 64 65#ifdef WRONG_VALUE 66// WRONG_VALUE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: AcquireAtCycles < ReleaseAtCycles must hold 67def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> { 68 let ReleaseAtCycles = [2, 4, 3]; 69 let AcquireAtCycles = [0, 1, 8]; 70} 71#endif 72 73#ifdef NEGATIVE_INVALID 74// NEGATIVE_INVALID: AcquireAtCycle.td:[[@LINE+1]]:1: error: Invalid value: AcquireAtCycle must be a non-negative value. 75def : WriteRes<WriteInst_A, [ResX0]> { 76 let ReleaseAtCycles = [2]; 77 let AcquireAtCycles = [-1]; 78} 79#endif 80 81def : InstRW<[WriteInst_A], (instrs Inst_A)>; 82def : InstRW<[WriteInst_B], (instrs Inst_B)>; 83} 84 85def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>; 86 87