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Searched refs:NewOpcode (Results 1 – 25 of 50) sorted by relevance

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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp84 int NewOpcode = 0; in InvertAndChangeJumpTarget()
87 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
90 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
93 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
96 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
102 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
85 int NewOpcode = 0; InvertAndChangeJumpTarget() local
H A DHexagonGenMemAbsolute.cpp65 static bool isValidIndexedLoad(int &Opcode, int &NewOpcode);
66 static bool isValidIndexedStore(int &Opcode, int &NewOpcode);
H A DHexagonVLIWPacketizer.cpp462 int NewOpcode; in promoteToDotNew() local
464 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
466 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
467 MI.setDesc(HII->get(NewOpcode)); in promoteToDotNew()
472 int NewOpcode = HII->getDotOldOp(MI); in demoteToDotOld() local
473 MI.setDesc(HII->get(NewOpcode)); in demoteToDotOld()
891 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) : in canPromoteToDotNew() local
893 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp64 unsigned &NewOpcode) {
79 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode()); in findVCMPToFoldIntoVPST()
80 if (NewOpcode == 0) in findVCMPToFoldIntoVPST()
272 unsigned NewOpcode; in InsertVPTBlocks()
274 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) { in InsertVPTBlocks()
276 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode)); in InsertVPTBlocks()
67 findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,const TargetRegisterInfo * TRI,unsigned & NewOpcode) findVCMPToFoldIntoVPST() argument
275 unsigned NewOpcode; InsertVPTBlocks() local
/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp133 int NewOpcode; in InsertSPImmInst()
135 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
136 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
141 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
142 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
148 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
149 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
138 int NewOpcode; InsertSPImmInst() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp395 unsigned NewOpcode = AMDGPU::getMIMGOpcode(Info->BaseOpcode, NewEncoding, in shrinkMIMG()
397 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
431 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; in shrinkMadFma()
448 NewOpcode = AMDGPU::V_MADAK_F32; in shrinkMadFma()
451 NewOpcode = AMDGPU::V_FMAAK_F32; in shrinkMadFma()
454 NewOpcode = AMDGPU::V_MADAK_F16; in shrinkMadFma()
459 NewOpcode = ST->hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_fake16 in shrinkMadFma()
478 NewOpcode = AMDGPU::V_MADMK_F32; in shrinkMadFma()
481 NewOpcode = AMDGPU::V_FMAMK_F32; in shrinkMadFma()
484 NewOpcode in shrinkMadFma()
385 unsigned NewOpcode = AMDGPU::getMIMGOpcode(Info->BaseOpcode, NewEncoding, shrinkMIMG() local
421 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; shrinkMadFma() local
[all...]
H A DGCNCreateVOPD.cpp73 int NewOpcode = in doReplace()
76 assert(NewOpcode != -1 && in doReplace() local
80 FirstMI->getDebugLoc(), SII->get(NewOpcode)) in doReplace()
H A DR600MachineCFGStructurizer.cpp200 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
202 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
204 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
205 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
208 MachineBasicBlock::iterator I, int NewOpcode,
435 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
437 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
444 int NewOpcode, in insertInstrBefore() argument
447 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
457 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
469 insertCondBranchBefore(MachineBasicBlock::iterator I,int NewOpcode,const DebugLoc & DL) insertCondBranchBefore() argument
482 insertCondBranchBefore(MachineBasicBlock * blk,MachineBasicBlock::iterator I,int NewOpcode,int RegNum,const DebugLoc & DL) insertCondBranchBefore() argument
[all...]
H A DAMDGPUPostLegalizerCombiner.cpp114 bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
407 auto [LoadMI, NewOpcode] = MatchData; in applyCombineSignExtendInReg()
408 LoadMI->setDesc(TII.get(NewOpcode)); in applyCombineSignExtendInReg()
418 MachineInstr &MI, unsigned &NewOpcode) const { in matchCombine_s_mul_u64()
426 NewOpcode = AMDGPU::G_AMDGPU_S_MUL_U64_U32; in matchCombine_s_mul_u64()
432 NewOpcode = AMDGPU::G_AMDGPU_S_MUL_I64_I32; in matchCombine_s_mul_u64()
H A DSIWholeQuadMode.cpp757 unsigned NewOpcode = 0; in splitBlock()
760 NewOpcode = AMDGPU::S_AND_B32_term; in splitBlock()
763 NewOpcode = AMDGPU::S_AND_B64_term; in splitBlock()
766 NewOpcode = AMDGPU::S_MOV_B32_term; in splitBlock()
769 NewOpcode = AMDGPU::S_MOV_B64_term; in splitBlock()
774 if (NewOpcode) in splitBlock()
775 TermMI->setDesc(TII->get(NewOpcode)); in splitBlock()
754 unsigned NewOpcode = 0; splitBlock() local
H A DSIOptimizeExecMasking.cpp597 const int NewOpcode = AMDGPU::getVCMPXOpFromVCMP(VCmp.getOpcode()); in optimizeVCMPSaveExecSequence()
599 if (NewOpcode == -1) in optimizeVCMPSaveExecSequence()
619 VCmp.getDebugLoc(), TII->get(NewOpcode)); in optimizeVCMPSaveExecSequence()
578 const int NewOpcode = AMDGPU::getVCMPXOpFromVCMP(VCmp.getOpcode()); optimizeVCMPSaveExecSequence() local
H A DSIInstrInfo.cpp2589 unsigned NewOpcode = -1; in reMaterialize()
2591 NewOpcode = AMDGPU::S_LOAD_DWORDX8_IMM; in reMaterialize()
2593 NewOpcode = AMDGPU::S_LOAD_DWORDX4_IMM; in reMaterialize()
2597 const MCInstrDesc &TID = get(NewOpcode); in reMaterialize()
7162 unsigned NewOpcode = getVALUOp(Inst); in moveToVALUImpl()
7168 NewOpcode = AMDGPU::V_ADD_U64_PSEUDO; in moveToVALUImpl()
7171 NewOpcode = AMDGPU::V_SUB_U64_PSEUDO; in moveToVALUImpl()
7274 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; in moveToVALUImpl()
7280 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; in moveToVALUImpl()
7286 NewOpcode in moveToVALUImpl()
2604 unsigned NewOpcode = -1; reMaterialize() local
6974 unsigned NewOpcode = getVALUOp(Inst); moveToVALUImpl() local
[all...]
/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp524 unsigned NewOpcode = AluI->getOpcode(); in optLEAALU() local
525 NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
530 NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
588 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
594 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
599 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
612 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
616 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
619 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
623 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
[all …]
/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
263 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
264 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
266 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
451 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
469 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp173 int NewOpcode = -1; in encodeInstruction() local
176 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
177 if (NewOpcode == -1) in encodeInstruction()
178 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
181 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
184 if (NewOpcode == -1) in encodeInstruction()
185 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
187 if (NewOpcode != -1) { in encodeInstruction()
191 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp225 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex()
230 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode), in eliminateFrameIndex()
228 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); eliminateFrameIndex() local
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp68 // each having the opcode given by NewOpcode. in splitMove()
70 unsigned NewOpcode) const { in splitMove()
96 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
97 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
144 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc()
145 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
146 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
1091 unsigned NewOpcode; in convertToThreeAddress()
1093 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
1096 NewOpcode in convertToThreeAddress()
143 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); splitAdjDynAlloc() local
1090 unsigned NewOpcode; convertToThreeAddress() local
[all...]
H A DSystemZFrameLowering.cpp714 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
718 if (!NewOpcode) { in emitEpilogue()
723 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
724 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
727 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
717 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); emitEpilogue() local
H A DSystemZInstrInfo.h189 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1652 std::string NewOpcode; in ParseOperand()
1654 NewOpcode = std::string(Name); in ParseOperand()
1655 NewOpcode += '+'; in ParseOperand()
1656 Name = NewOpcode;
1659 NewOpcode = std::string(Name); in ParseInstruction()
1660 NewOpcode += '-'; in ParseInstruction()
1661 Name = NewOpcode; in ParseInstruction()
1667 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1675 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1663 std::string NewOpcode; ParseInstruction() local
/llvm-project/clang-tools-extra/clang-tidy/readability/
H A DSimplifyBooleanExprCheck.cpp986 auto NewOpcode = getDemorganFlippedOperator(Inner->getOpcode()); in reportDeMorgan() local
987 if (shouldRemoveParens(Parent, NewOpcode, Parens)) { in reportDeMorgan()
996 if (flipDemorganSide(Fixes, Context, Inner->getLHS(), NewOpcode) || in reportDeMorgan()
997 flipDemorganSide(Fixes, Context, Inner->getRHS(), NewOpcode)) in reportDeMorgan()
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp1730 unsigned NewOpcode = 0u; in eliminateFrameIndex()
1778 NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex()
1779 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
1798 if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) { in eliminateFrameIndex()
1804 MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ)); in eliminateFrameIndex()
1734 unsigned NewOpcode = 0u; eliminateFrameIndex() local
H A DPPCISelDAGToDAG.cpp7404 unsigned NewOpcode; in PeepholePPC64ZExt()
7408 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; in PeepholePPC64ZExt()
7409 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
7410 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
7411 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
7412 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
7413 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
7414 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
7415 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; in PeepholePPC64ZExt()
7416 case PPC::CNTLZW: NewOpcode in PeepholePPC64ZExt()
7405 unsigned NewOpcode; PeepholePPC64ZExt() local
[all...]
/llvm-project/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp562 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch()
563 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); in replaceWithCompactBranch() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp565 int NewOpcode; in expand_DestructiveOp()
567 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1) in expand_DestructiveOp()
568 Opcode = NewOpcode; in expand_DestructiveOp()
570 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1) in expand_DestructiveOp()
571 Opcode = NewOpcode; in expand_DestructiveOp()
563 int NewOpcode; expand_DestructiveOp() local

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