[PowerPC] Remove unused includes (NFC) (#116163)

Identified with misc-include-cleaner.

Reland "[PowerPC] Add error for incorrect use of memory operands (#114277)" (#115958)

Commit 93589057830b2c3c35500ee8cac25c717a1e98f9 was reverted because it
caused a failure with test `lld :: ELF/

Reland "[PowerPC] Add error for incorrect use of memory operands (#114277)" (#115958)

Commit 93589057830b2c3c35500ee8cac25c717a1e98f9 was reverted because it
caused a failure with test `lld :: ELF/ppc64-local-exec-tls.s`. This
relands the commit with a fix for the test.

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Revert "[PowerPC] Add error for incorrect use of memory operands (#114277)"

This commit broke a test on a couple bots
lld :: ELF/ppc64-local-exec-tls.s

This reverts commit 93589057830b2c3c35500ee8c

Revert "[PowerPC] Add error for incorrect use of memory operands (#114277)"

This commit broke a test on a couple bots
lld :: ELF/ppc64-local-exec-tls.s

This reverts commit 93589057830b2c3c35500ee8cac25c717a1e98f9.

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[PowerPC] Add error for incorrect use of memory operands (#114277)

If an instruction doesn't support memory operands, but one is provided,
an error should be raised. And conversely, if an instructi

[PowerPC] Add error for incorrect use of memory operands (#114277)

If an instruction doesn't support memory operands, but one is provided,
an error should be raised. And conversely, if an instruction requires a
memory operand, but none is given, an error should be raised.

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NFC: Make isPPC64 const and use member initializer

[NFC][PowerPC] Use tablegen's MatchRegisterName() (#111553)

Use PPC `MatchRegisterName()` that is auto generated by table gen.

[PowerPC] Update matchRegisterName() to return MCRegister instead of bool (#111186)

Initial patch to start using TableGen's auto generated function
`MatchRegisterName()`.

Update `PPCAsmParser::m

[PowerPC] Update matchRegisterName() to return MCRegister instead of bool (#111186)

Initial patch to start using TableGen's auto generated function
`MatchRegisterName()`.

Update `PPCAsmParser::matchRegisterName()` implementation to align more
with tablegen's auto generated function.

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[NFC] Update function names in MCTargetAsmParser.h (#108643)

Update function names to adhere to LLVM coding standard.

[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)

S.substr(N) is simpler than S.slice(N, StringRef::npos) and
S.slice(N, S.size()). Also, substr is probably better recognizable
t

[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)

S.substr(N) is simpler than S.slice(N, StringRef::npos) and
S.slice(N, S.size()). Also, substr is probably better recognizable
than slice thanks to std::string_view::substr.

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[MC] Make `MCParsedAsmOperand::getReg()` return `MCRegister` (#86444)

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.

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[PowerPC] Add a set of extended mnemonics that are missing from Power 10. (#73003)

This patch adds the majority of the missing extended mnemonics that were
introduced in Power 10.

The only exten

[PowerPC] Add a set of extended mnemonics that are missing from Power 10. (#73003)

This patch adds the majority of the missing extended mnemonics that were
introduced in Power 10.

The only extended mnemonics that were not added are related to the plq
and pstq instructions. These will be added in a separate patch as the
instructions themselves would also have to be added.

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[MC] Change tryParseRegister to return ParseStatus (NFC)

This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variab

[MC] Change tryParseRegister to return ParseStatus (NFC)

This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variables to just Reg
(a leftover from the days when RegNo had 'unsigned' type).

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[PPC32] Parse bl __tls_get_addr(x@tlsgd)@plt+32768

PPC32 -fpic/-fPIC generates `bl __tls_get_addr(x@tlsgd)@PLT` or
`bl __tls_get_addr(x@tlsgd)@PLT+32768`.
`powerpc-linux-gnu-gcc -fPIC` generates `bl

[PPC32] Parse bl __tls_get_addr(x@tlsgd)@plt+32768

PPC32 -fpic/-fPIC generates `bl __tls_get_addr(x@tlsgd)@PLT` or
`bl __tls_get_addr(x@tlsgd)@PLT+32768`.
`powerpc-linux-gnu-gcc -fPIC` generates `bl __tls_get_addr+32668(x@tlsgd)@plt`.

These expressions can be parsed by GNU assembler but not by the integrated
assembler. Add the support.

Differential Revision: https://reviews.llvm.org/D153206

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PPCAsmParser: Use parseOptionalToken

to simplify code near __tls_get_addr parsing.

[llvm] Migrate {starts,ends}with_insensitive to {starts,ends}_with_insensitive (NFC)

This patch migrates uses of StringRef::{starts,ends}with_insensitive
to StringRef::{starts,ends}_with_insensitive

[llvm] Migrate {starts,ends}with_insensitive to {starts,ends}_with_insensitive (NFC)

This patch migrates uses of StringRef::{starts,ends}with_insensitive
to StringRef::{starts,ends}_with_insensitive so that we can use names
similar to those used in std::string_view. I'm planning to deprecate
StringRef::{starts,ends}with_insensitive once the migration is
complete across the code base.

Differential Revision: https://reviews.llvm.org/D150426

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[PowerPC] Implement DFP add and sub instructions.

Add the following Decimal Floating Point (DFP) instructions for PowerPC.
dadd, daddq, dsub, dsubq

In order to add these instructions a new register

[PowerPC] Implement DFP add and sub instructions.

Add the following Decimal Floating Point (DFP) instructions for PowerPC.
dadd, daddq, dsub, dsubq

In order to add these instructions a new register class for a pair
of floating point registers is added.

This patch is only to allow the user to specify the instructions in
assembly. There is no scheduling or patterns for the instructions.

Reviewed By: amyk

Differential Revision: https://reviews.llvm.org/D148597

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Simplify with hasFeature. NFC

Use llvm::has_single_bit<uint32_t> (NFC)

This patch replaces isPowerOf2_32 with llvm::has_single_bit<uint32_t>
where the argument is wider than uint32_t.

[Target] Use llvm::count{l,r}_{zero,one} (NFC)

[MC] Use `MCRegister` instead of `unsigned` in `MCTargetAsmParser`

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D140273

[Alignment][NFC] Use Align in MCStreamer::emitValueToAlignment

Differential Revision: https://reviews.llvm.org/D138674

[PowerPC] Add new DMR register classes to Future CPU.

A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) a

[PowerPC] Add new DMR register classes to Future CPU.

A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits
long. These regsiters can also be used in consecutive pairs which leads to a
register that is 2048 bits.

This patch also adds 7 new instructions that use these registers. More
instructions will be added in future patches.

Reviewed By: amyk, saghir

Differential Revision: https://reviews.llvm.org/D136366

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[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC

With C++17 there is no Clang pedantic warning or MSVC C5051.

[PowerPC] Allow absolute expressions in relocations

The Linux kernel build uses absolute expressions suffixed with @lo/@ha
relocations. This currently doesn't work for DS/DQ form instructions and
th

[PowerPC] Allow absolute expressions in relocations

The Linux kernel build uses absolute expressions suffixed with @lo/@ha
relocations. This currently doesn't work for DS/DQ form instructions and
there is no reason for it not to. It also works with GAS.
This patch allows this as long as the value is a multiple of 4/16
for DS/DQ form.

Differential revision: https://reviews.llvm.org/D115419

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