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Searched refs:ctrl (Results 1 – 25 of 49) sorted by relevance

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/dpdk/drivers/net/enic/base/
H A Dvnic_intr.c11 intr->ctrl = NULL; in vnic_intr_free()
20 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); in vnic_intr_alloc()
21 if (!intr->ctrl) { in vnic_intr_alloc()
33 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); in vnic_intr_init()
34 iowrite32(mask_on_assertion, &intr->ctrl->mask_on_assertion); in vnic_intr_init()
35 iowrite32(0, &intr->ctrl->int_credits); in vnic_intr_init()
42 coalescing_timer), &intr->ctrl->coalescing_timer); in vnic_intr_coalescing_timer_set()
47 iowrite32(0, &intr->ctrl->int_credits); in vnic_intr_clean()
H A Dvnic_intr.h36 struct vnic_intr_ctrl __iomem *ctrl; /* memory-mapped */ member
41 iowrite32(0, &intr->ctrl->mask); in vnic_intr_unmask()
46 iowrite32(1, &intr->ctrl->mask); in vnic_intr_mask()
51 return ioread32(&intr->ctrl->mask); in vnic_intr_masked()
64 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); in vnic_intr_return_credits()
69 return ioread32(&intr->ctrl->int_credits); in vnic_intr_credits()
/dpdk/drivers/raw/ifpga/base/
H A Dopae_spi.c11 u64 ctrl = 0; in nios_spi_indirect_read() local
15 ctrl = NIOS_SPI_RD | ((u64)reg << 32); in nios_spi_indirect_read()
16 opae_writeq(ctrl, dev->regs + NIOS_SPI_CTRL); in nios_spi_indirect_read()
31 u64 ctrl = 0; in nios_spi_indirect_write() local
35 ctrl |= NIOS_SPI_WR | (u64)reg << 32; in nios_spi_indirect_write()
36 ctrl |= value & NIOS_SPI_WRITE_DATA; in nios_spi_indirect_write()
38 opae_writeq(ctrl, dev->regs + NIOS_SPI_CTRL); in nios_spi_indirect_write()
50 u64 ctrl; in spi_indirect_write() local
54 ctrl = CTRL_W | (reg >> 2); in spi_indirect_write()
55 opae_writeq(ctrl, dev->regs + SPI_CTRL); in spi_indirect_write()
[all …]
H A Dopae_i2c.c136 u64 ctrl; in i2c_indirect_write() local
138 ctrl = I2C_CTRL_W | (reg >> 2); in i2c_indirect_write()
141 opae_writeq(ctrl, dev->base + I2C_CTRL); in i2c_indirect_write()
147 u64 ctrl; in i2c_indirect_read() local
150 ctrl = I2C_CTRL_R | (reg >> 2); in i2c_indirect_read()
151 opae_writeq(ctrl, dev->base + I2C_CTRL); in i2c_indirect_read()
/dpdk/drivers/net/pfe/
H A Dpfe_hif_lib.h80 u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */ member
90 #define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \ argument
92 #define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \ argument
125 u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ member
131 u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ member
/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_api_cmd.c176 u64 ctrl; in prepare_cell_ctrl() local
180 ctrl = be64_to_cpu(*cell_ctrl); in prepare_cell_ctrl()
181 ctrl = HINIC_API_CMD_CELL_CTRL_CLEAR(ctrl, CELL_LEN) & in prepare_cell_ctrl()
182 HINIC_API_CMD_CELL_CTRL_CLEAR(ctrl, RD_DMA_ATTR_OFF) & in prepare_cell_ctrl()
183 HINIC_API_CMD_CELL_CTRL_CLEAR(ctrl, WR_DMA_ATTR_OFF) & in prepare_cell_ctrl()
184 HINIC_API_CMD_CELL_CTRL_CLEAR(ctrl, XOR_CHKSUM); in prepare_cell_ctrl()
186 ctrl |= HINIC_API_CMD_CELL_CTRL_SET(SIZE_8BYTES(cell_len), CELL_LEN) | in prepare_cell_ctrl()
190 chksum = xor_chksum_set(&ctrl); in prepare_cell_ctrl()
192 ctrl |= HINIC_API_CMD_CELL_CTRL_SET(chksum, XOR_CHKSUM); in prepare_cell_ctrl()
195 *cell_ctrl = cpu_to_be64(ctrl); in prepare_cell_ctrl()
[all …]
H A Dhinic_pmd_cmdq.c285 struct hinic_ctrl *ctrl; in cmdq_prepare_wqe_ctrl() local
295 ctrl = &wqe_lcmd->ctrl; in cmdq_prepare_wqe_ctrl()
301 ctrl = &wqe_scmd->ctrl; in cmdq_prepare_wqe_ctrl()
305 ctrl->ctrl_info = CMDQ_CTRL_SET(prod_idx, PI) | in cmdq_prepare_wqe_ctrl()
401 struct hinic_ctrl *ctrl; in clear_wqe_complete_bit() local
409 ctrl = &wqe_lcmd->ctrl; in clear_wqe_complete_bit()
413 ctrl = &wqe_scmd->ctrl; in clear_wqe_complete_bit()
417 ctrl->ctrl_info = 0; in clear_wqe_complete_bit()
717 struct hinic_ctrl *ctrl; in hinic_cmdq_poll_msg() local
742 ctrl = &wqe_lcmd->ctrl; in hinic_cmdq_poll_msg()
[all …]
H A Dhinic_pmd_cmdq.h125 struct hinic_ctrl ctrl; member
133 struct hinic_ctrl ctrl; member
/dpdk/drivers/net/mlx5/hws/
H A Dmlx5dr_pat_arg.c314 struct mlx5dr_send_engine_post_ctrl ctrl; in mlx5dr_arg_decapl3_write() local
320 ctrl = mlx5dr_send_engine_post_start(queue); in mlx5dr_arg_decapl3_write()
321 mlx5dr_send_engine_post_req_wqe(&ctrl, (void *)&wqe_ctrl, &wqe_len); in mlx5dr_arg_decapl3_write()
323 mlx5dr_send_engine_post_req_wqe(&ctrl, (void *)&wqe_arg, &wqe_len); in mlx5dr_arg_decapl3_write()
326 mlx5dr_send_engine_post_end(&ctrl, &send_attr); in mlx5dr_arg_decapl3_write()
337 struct mlx5dr_send_engine_post_ctrl ctrl; in mlx5dr_arg_write() local
349 ctrl = mlx5dr_send_engine_post_start(queue); in mlx5dr_arg_write()
350 mlx5dr_send_engine_post_req_wqe(&ctrl, (void *)&wqe_ctrl, &wqe_len); in mlx5dr_arg_write()
352 mlx5dr_send_engine_post_req_wqe(&ctrl, (void *)&wqe_arg, &wqe_len); in mlx5dr_arg_write()
355 mlx5dr_send_engine_post_end(&ctrl, &send_attr); in mlx5dr_arg_write()
[all …]
H A Dmlx5dr_send.h240 void mlx5dr_send_engine_post_req_wqe(struct mlx5dr_send_engine_post_ctrl *ctrl,
243 void mlx5dr_send_engine_post_end(struct mlx5dr_send_engine_post_ctrl *ctrl,
/dpdk/drivers/net/mlx4/
H A Dmlx4_rxtx.c468 volatile struct mlx4_wqe_ctrl_seg *ctrl) in mlx4_tx_burst_fill_tso_dsegs() argument
479 ((volatile uint8_t *)ctrl + tinfo->wqe_size); in mlx4_tx_burst_fill_tso_dsegs()
606 volatile struct mlx4_wqe_ctrl_seg *ctrl) in mlx4_tx_burst_fill_tso_hdr() argument
609 (volatile struct mlx4_wqe_lso_seg *)(ctrl + 1); in mlx4_tx_burst_fill_tso_hdr()
684 volatile struct mlx4_wqe_ctrl_seg *ctrl) in mlx4_tx_burst_tso() argument
697 dseg = mlx4_tx_burst_fill_tso_hdr(buf, txq, &tinfo, ctrl); in mlx4_tx_burst_tso()
703 ctrl_next = mlx4_tx_burst_fill_tso_dsegs(buf, txq, &tinfo, dseg, ctrl); in mlx4_tx_burst_tso()
717 ctrl->fence_size = tinfo.fence_size; in mlx4_tx_burst_tso()
740 volatile struct mlx4_wqe_ctrl_seg *ctrl) in mlx4_tx_burst_segs() argument
750 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1); in mlx4_tx_burst_segs()
[all …]
/dpdk/drivers/net/ark/
H A Dark_pktdir.c25 inst->regs->ctrl = ARK_PKT_DIR_INIT_VAL; /* POR state */ in ark_pktdir_init()
41 inst->regs->ctrl = v; in ark_pktdir_setup()
48 return inst->regs->ctrl; in ark_pktdir_status()
/dpdk/drivers/net/virtio/
H A Dvirtio_ethdev.c150 struct virtio_pmd_ctrl ctrl; in virtio_set_multiple_queues_rss() local
163 ctrl.hdr.class = VIRTIO_NET_CTRL_MQ; in virtio_set_multiple_queues_rss()
164 ctrl.hdr.cmd = VIRTIO_NET_CTRL_MQ_RSS_CONFIG; in virtio_set_multiple_queues_rss()
165 memcpy(ctrl.data, &rss, sizeof(rss)); in virtio_set_multiple_queues_rss()
169 ret = virtio_send_command(hw->cvq, &ctrl, &dlen, 1); in virtio_set_multiple_queues_rss()
182 struct virtio_pmd_ctrl ctrl; in virtio_set_multiple_queues_auto() local
186 ctrl.hdr.class = VIRTIO_NET_CTRL_MQ; in virtio_set_multiple_queues_auto()
187 ctrl.hdr.cmd = VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET; in virtio_set_multiple_queues_auto()
188 memcpy(ctrl.data, &nb_queues, sizeof(uint16_t)); in virtio_set_multiple_queues_auto()
192 ret = virtio_send_command(hw->cvq, &ctrl, &dlen, 1); in virtio_set_multiple_queues_auto()
[all …]
/dpdk/drivers/net/ngbe/base/
H A Dngbe_phy_yt.c425 u16 ctrl = 0; in ngbe_reset_phy_yt() local
434 ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &ctrl); in ngbe_reset_phy_yt()
435 if (ctrl & YT_CHIP_MODE_MASK) { in ngbe_reset_phy_yt()
437 status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl); in ngbe_reset_phy_yt()
439 ctrl |= YT_BCR_RESET; in ngbe_reset_phy_yt()
440 status = hw->phy.write_reg(hw, YT_BCR, 0, ctrl); in ngbe_reset_phy_yt()
443 status = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl); in ngbe_reset_phy_yt()
444 if (!(ctrl & YT_BCR_RESET)) in ngbe_reset_phy_yt()
450 status = ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &ctrl); in ngbe_reset_phy_yt()
452 ctrl |= YT_BCR_RESET; in ngbe_reset_phy_yt()
[all …]
/dpdk/doc/guides/vdpadevs/features/
H A Ddefault.ini21 ctrl vq =
22 ctrl rx =
/dpdk/drivers/net/ena/base/ena_defs/
H A Dena_eth_io_defs.h182 uint8_t ctrl; member
754 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK; in get_ena_eth_io_rx_desc_phase()
759 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK; in set_ena_eth_io_rx_desc_phase()
764 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT; in get_ena_eth_io_rx_desc_first()
769 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK; in set_ena_eth_io_rx_desc_first()
774 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT; in get_ena_eth_io_rx_desc_last()
779 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK; in set_ena_eth_io_rx_desc_last()
784 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT; in get_ena_eth_io_rx_desc_comp_req()
789 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; in set_ena_eth_io_rx_desc_comp_req()
/dpdk/drivers/net/mlx5/linux/
H A Dmlx5_verbs.c51 return mlx5_glue->modify_wq(rxq->ctrl->obj->wq, &mod); in mlx5_rxq_obj_modify_wq_vlan_strip()
73 return mlx5_glue->modify_wq(rxq->ctrl->obj->wq, &mod); in mlx5_ibv_modify_wq()
150 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl; in mlx5_rxq_ibv_cq_create()
224 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl; in mlx5_rxq_ibv_wq_create()
319 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl; in mlx5_rxq_ibv_obj_new()
426 struct mlx5_rxq_obj *rxq_obj = rxq->ctrl->obj; in mlx5_rxq_ibv_obj_release()
437 rxq->ctrl->started = false; in mlx5_rxq_ibv_obj_release()
495 wq[i] = rxq->ctrl->obj->wq; in mlx5_ibv_ind_table_new()
657 if (rxq->ctrl == NULL) in mlx5_rxq_ibv_obj_drop_release()
659 rxq_obj = rxq->ctrl->obj; in mlx5_rxq_ibv_obj_drop_release()
[all …]
/dpdk/lib/net/
H A Drte_ppp.h22 uint8_t ctrl; /**< PPP control(8) */
26 uint8_t ctrl; /**< PPP control(8) */ global() member
/dpdk/drivers/crypto/virtio/
H A Dvirtio_crypto_algs.h25 struct virtio_crypto_op_ctrl_req ctrl; member
/dpdk/doc/guides/regexdevs/
H A Dfeatures_overview.rst21 PCRE back tracking ctrl
22 Support PCRE back tracking ctrl.
/dpdk/lib/node/
H A Dethdev_ctrl.c21 } ctrl; variable
130 ctrl.nb_graphs = nb_graphs; in rte_node_eth_config()
/dpdk/drivers/net/mlx5/
H A Dmlx5_rss.c70 if (rxq == NULL || rxq->ctrl == NULL) in mlx5_rss_hash_update()
72 rxq->ctrl->rxq.rss_hash = !!rss_conf->rss_hf && in mlx5_rss_hash_update()
/dpdk/drivers/common/nfp/
H A Dnfp_common.h38 uint32_t ctrl; member
221 int nfp_reconfig(struct nfp_hw *hw, uint32_t ctrl, uint32_t update);
/dpdk/drivers/net/qede/base/
H A Decore_init_fw_funcs.c1118 u32 ctrl, inc_val, reg_offset; in ecore_init_nig_lb_rl() local
1122 ctrl = in ecore_init_nig_lb_rl()
1125 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl); in ecore_init_nig_lb_rl()
1139 ctrl |= in ecore_init_nig_lb_rl()
1142 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl); in ecore_init_nig_lb_rl()
1146 ctrl = in ecore_init_nig_lb_rl()
1149 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl); in ecore_init_nig_lb_rl()
1163 ctrl |= in ecore_init_nig_lb_rl()
1165 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl); in ecore_init_nig_lb_rl()
1172 ctrl = in ecore_init_nig_lb_rl()
[all …]
/dpdk/doc/guides/vdpadevs/
H A Dfeatures_overview.rst42 ctrl vq
45 ctrl rx

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