1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
3 */
4
5 #include <stddef.h>
6 #include <errno.h>
7 #include <string.h>
8 #include <stdint.h>
9 #include <unistd.h>
10 #include <inttypes.h>
11 #include <sys/queue.h>
12
13 #include "mlx5_autoconf.h"
14
15 #include <rte_mbuf.h>
16 #include <rte_malloc.h>
17 #include <ethdev_driver.h>
18 #include <rte_common.h>
19 #include <rte_eal_paging.h>
20
21 #include <mlx5_glue.h>
22 #include <mlx5_common.h>
23 #include <mlx5_common_mr.h>
24 #include <mlx5_verbs.h>
25 #include <mlx5_rx.h>
26 #include <mlx5_tx.h>
27 #include <mlx5_utils.h>
28 #include <mlx5_malloc.h>
29
30 /**
31 * Modify Rx WQ vlan stripping offload
32 *
33 * @param rxq
34 * Rx queue.
35 *
36 * @return 0 on success, non-0 otherwise
37 */
38 static int
mlx5_rxq_obj_modify_wq_vlan_strip(struct mlx5_rxq_priv * rxq,int on)39 mlx5_rxq_obj_modify_wq_vlan_strip(struct mlx5_rxq_priv *rxq, int on)
40 {
41 uint16_t vlan_offloads =
42 (on ? IBV_WQ_FLAGS_CVLAN_STRIPPING : 0) |
43 0;
44 struct ibv_wq_attr mod;
45 mod = (struct ibv_wq_attr){
46 .attr_mask = IBV_WQ_ATTR_FLAGS,
47 .flags_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING,
48 .flags = vlan_offloads,
49 };
50
51 return mlx5_glue->modify_wq(rxq->ctrl->obj->wq, &mod);
52 }
53
54 /**
55 * Modifies the attributes for the specified WQ.
56 *
57 * @param rxq
58 * Verbs Rx queue.
59 * @param type
60 * Type of change queue state.
61 *
62 * @return
63 * 0 on success, a negative errno value otherwise and rte_errno is set.
64 */
65 static int
mlx5_ibv_modify_wq(struct mlx5_rxq_priv * rxq,uint8_t type)66 mlx5_ibv_modify_wq(struct mlx5_rxq_priv *rxq, uint8_t type)
67 {
68 struct ibv_wq_attr mod = {
69 .attr_mask = IBV_WQ_ATTR_STATE,
70 .wq_state = (enum ibv_wq_state)type,
71 };
72
73 return mlx5_glue->modify_wq(rxq->ctrl->obj->wq, &mod);
74 }
75
76 /**
77 * Modify QP using Verbs API.
78 *
79 * @param txq_obj
80 * Verbs Tx queue object.
81 * @param type
82 * Type of change queue state.
83 * @param dev_port
84 * IB device port number.
85 *
86 * @return
87 * 0 on success, a negative errno value otherwise and rte_errno is set.
88 */
89 static int
mlx5_ibv_modify_qp(struct mlx5_txq_obj * obj,enum mlx5_txq_modify_type type,uint8_t dev_port)90 mlx5_ibv_modify_qp(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
91 uint8_t dev_port)
92 {
93 struct ibv_qp_attr mod = {
94 .qp_state = IBV_QPS_RESET,
95 .port_num = dev_port,
96 };
97 int ret;
98
99 if (type != MLX5_TXQ_MOD_RST2RDY) {
100 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
101 if (ret) {
102 DRV_LOG(ERR, "Cannot change Tx QP state to RESET %s",
103 strerror(errno));
104 rte_errno = errno;
105 return ret;
106 }
107 if (type == MLX5_TXQ_MOD_RDY2RST)
108 return 0;
109 }
110 mod.qp_state = IBV_QPS_INIT;
111 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE | IBV_QP_PORT);
112 if (ret) {
113 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
114 strerror(errno));
115 rte_errno = errno;
116 return ret;
117 }
118 mod.qp_state = IBV_QPS_RTR;
119 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
120 if (ret) {
121 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
122 strerror(errno));
123 rte_errno = errno;
124 return ret;
125 }
126 mod.qp_state = IBV_QPS_RTS;
127 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
128 if (ret) {
129 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
130 strerror(errno));
131 rte_errno = errno;
132 return ret;
133 }
134 return 0;
135 }
136
137 /**
138 * Create a CQ Verbs object.
139 *
140 * @param rxq
141 * Pointer to Rx queue.
142 *
143 * @return
144 * The Verbs CQ object initialized, NULL otherwise and rte_errno is set.
145 */
146 static struct ibv_cq *
mlx5_rxq_ibv_cq_create(struct mlx5_rxq_priv * rxq)147 mlx5_rxq_ibv_cq_create(struct mlx5_rxq_priv *rxq)
148 {
149 struct mlx5_priv *priv = rxq->priv;
150 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
151 struct mlx5_rxq_data *rxq_data = &rxq_ctrl->rxq;
152 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;
153 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
154 struct {
155 struct ibv_cq_init_attr_ex ibv;
156 struct mlx5dv_cq_init_attr mlx5;
157 } cq_attr;
158
159 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
160 .cqe = cqe_n,
161 .channel = rxq_obj->ibv_channel,
162 .comp_mask = 0,
163 };
164 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
165 .comp_mask = 0,
166 };
167 if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
168 cq_attr.mlx5.comp_mask |=
169 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
170 rxq_data->byte_mask = UINT32_MAX;
171 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
172 if (mlx5_rxq_mprq_enabled(rxq_data)) {
173 cq_attr.mlx5.cqe_comp_res_format =
174 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX;
175 rxq_data->mcqe_format =
176 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
177 } else {
178 cq_attr.mlx5.cqe_comp_res_format =
179 MLX5DV_CQE_RES_FORMAT_HASH;
180 rxq_data->mcqe_format =
181 MLX5_CQE_RESP_FORMAT_HASH;
182 }
183 #else
184 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
185 rxq_data->mcqe_format = MLX5_CQE_RESP_FORMAT_HASH;
186 #endif
187 /*
188 * For vectorized Rx, it must not be doubled in order to
189 * make cq_ci and rq_ci aligned.
190 */
191 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
192 cq_attr.ibv.cqe *= 2;
193 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
194 DRV_LOG(DEBUG,
195 "Port %u Rx CQE compression is disabled for HW"
196 " timestamp.",
197 priv->dev_data->port_id);
198 }
199 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
200 if (RTE_CACHE_LINE_SIZE == 128) {
201 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
202 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
203 }
204 #endif
205 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq
206 (priv->sh->cdev->ctx,
207 &cq_attr.ibv,
208 &cq_attr.mlx5));
209 }
210
211 /**
212 * Create a WQ Verbs object.
213 *
214 * @param rxq
215 * Pointer to Rx queue.
216 *
217 * @return
218 * The Verbs WQ object initialized, NULL otherwise and rte_errno is set.
219 */
220 static struct ibv_wq *
mlx5_rxq_ibv_wq_create(struct mlx5_rxq_priv * rxq)221 mlx5_rxq_ibv_wq_create(struct mlx5_rxq_priv *rxq)
222 {
223 struct mlx5_priv *priv = rxq->priv;
224 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
225 struct mlx5_rxq_data *rxq_data = &rxq_ctrl->rxq;
226 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;
227 unsigned int wqe_n = 1 << rxq_data->elts_n;
228 struct {
229 struct ibv_wq_init_attr ibv;
230 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
231 struct mlx5dv_wq_init_attr mlx5;
232 #endif
233 } wq_attr;
234
235 wq_attr.ibv = (struct ibv_wq_init_attr){
236 .wq_context = NULL, /* Could be useful in the future. */
237 .wq_type = IBV_WQT_RQ,
238 /* Max number of outstanding WRs. */
239 .max_wr = wqe_n >> rxq_data->sges_n,
240 /* Max number of scatter/gather elements in a WR. */
241 .max_sge = 1 << rxq_data->sges_n,
242 .pd = priv->sh->cdev->pd,
243 .cq = rxq_obj->ibv_cq,
244 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
245 .create_flags = (rxq_data->vlan_strip ?
246 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
247 };
248 /* By default, FCS (CRC) is stripped by hardware. */
249 if (rxq_data->crc_present) {
250 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
251 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
252 }
253 if (priv->config.hw_padding) {
254 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
255 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
256 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
257 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
258 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
259 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
260 #endif
261 }
262 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
263 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
264 .comp_mask = 0,
265 };
266 if (mlx5_rxq_mprq_enabled(rxq_data)) {
267 struct mlx5dv_striding_rq_init_attr *mprq_attr =
268 &wq_attr.mlx5.striding_rq_attrs;
269
270 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
271 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
272 .single_stride_log_num_of_bytes = rxq_data->log_strd_sz,
273 .single_wqe_log_num_of_strides = rxq_data->log_strd_num,
274 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
275 };
276 }
277 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->cdev->ctx, &wq_attr.ibv,
278 &wq_attr.mlx5);
279 #else
280 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->cdev->ctx, &wq_attr.ibv);
281 #endif
282 if (rxq_obj->wq) {
283 /*
284 * Make sure number of WRs*SGEs match expectations since a queue
285 * cannot allocate more than "desc" buffers.
286 */
287 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
288 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
289 DRV_LOG(ERR,
290 "Port %u Rx queue %u requested %u*%u but got"
291 " %u*%u WRs*SGEs.",
292 priv->dev_data->port_id, rxq->idx,
293 wqe_n >> rxq_data->sges_n,
294 (1 << rxq_data->sges_n),
295 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
296 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
297 rxq_obj->wq = NULL;
298 rte_errno = EINVAL;
299 }
300 }
301 return rxq_obj->wq;
302 }
303
304 /**
305 * Create the Rx queue Verbs object.
306 *
307 * @param rxq
308 * Pointer to Rx queue.
309 *
310 * @return
311 * 0 on success, a negative errno value otherwise and rte_errno is set.
312 */
313 static int
mlx5_rxq_ibv_obj_new(struct mlx5_rxq_priv * rxq)314 mlx5_rxq_ibv_obj_new(struct mlx5_rxq_priv *rxq)
315 {
316 uint16_t idx = rxq->idx;
317 struct mlx5_priv *priv = rxq->priv;
318 uint16_t port_id = priv->dev_data->port_id;
319 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
320 struct mlx5_rxq_data *rxq_data = &rxq_ctrl->rxq;
321 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
322 struct mlx5dv_cq cq_info;
323 struct mlx5dv_rwq rwq;
324 int ret = 0;
325 struct mlx5dv_obj obj;
326
327 MLX5_ASSERT(rxq_data);
328 MLX5_ASSERT(tmpl);
329 tmpl->rxq_ctrl = rxq_ctrl;
330 if (rxq_ctrl->irq) {
331 tmpl->ibv_channel =
332 mlx5_glue->create_comp_channel(priv->sh->cdev->ctx);
333 if (!tmpl->ibv_channel) {
334 DRV_LOG(ERR, "Port %u: comp channel creation failure.",
335 port_id);
336 rte_errno = ENOMEM;
337 goto error;
338 }
339 tmpl->fd = ((struct ibv_comp_channel *)(tmpl->ibv_channel))->fd;
340 }
341 /* Create CQ using Verbs API. */
342 tmpl->ibv_cq = mlx5_rxq_ibv_cq_create(rxq);
343 if (!tmpl->ibv_cq) {
344 DRV_LOG(ERR, "Port %u Rx queue %u CQ creation failure.",
345 port_id, idx);
346 rte_errno = ENOMEM;
347 goto error;
348 }
349 obj.cq.in = tmpl->ibv_cq;
350 obj.cq.out = &cq_info;
351 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
352 if (ret) {
353 rte_errno = ret;
354 goto error;
355 }
356 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
357 DRV_LOG(ERR,
358 "Port %u wrong MLX5_CQE_SIZE environment "
359 "variable value: it should be set to %u.",
360 port_id, RTE_CACHE_LINE_SIZE);
361 rte_errno = EINVAL;
362 goto error;
363 }
364 /* Fill the rings. */
365 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
366 rxq_data->cq_db = cq_info.dbrec;
367 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
368 rxq_data->uar_data.db = RTE_PTR_ADD(cq_info.cq_uar, MLX5_CQ_DOORBELL);
369 #ifndef RTE_ARCH_64
370 rxq_data->uar_data.sl_p = &priv->sh->uar_lock_cq;
371 #endif
372 rxq_data->cqn = cq_info.cqn;
373 /* Create WQ (RQ) using Verbs API. */
374 tmpl->wq = mlx5_rxq_ibv_wq_create(rxq);
375 if (!tmpl->wq) {
376 DRV_LOG(ERR, "Port %u Rx queue %u WQ creation failure.",
377 port_id, idx);
378 rte_errno = ENOMEM;
379 goto error;
380 }
381 /* Change queue state to ready. */
382 ret = mlx5_ibv_modify_wq(rxq, IBV_WQS_RDY);
383 if (ret) {
384 DRV_LOG(ERR,
385 "Port %u Rx queue %u WQ state to IBV_WQS_RDY failed.",
386 port_id, idx);
387 rte_errno = ret;
388 goto error;
389 }
390 obj.rwq.in = tmpl->wq;
391 obj.rwq.out = &rwq;
392 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
393 if (ret) {
394 rte_errno = ret;
395 goto error;
396 }
397 rxq_data->wqes = rwq.buf;
398 rxq_data->rq_db = rwq.dbrec;
399 rxq_data->cq_arm_sn = 0;
400 mlx5_rxq_initialize(rxq_data);
401 rxq_data->cq_ci = 0;
402 priv->dev_data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
403 rxq_ctrl->wqn = ((struct ibv_wq *)(tmpl->wq))->wq_num;
404 return 0;
405 error:
406 ret = rte_errno; /* Save rte_errno before cleanup. */
407 if (tmpl->wq)
408 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
409 if (tmpl->ibv_cq)
410 claim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));
411 if (tmpl->ibv_channel)
412 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->ibv_channel));
413 rte_errno = ret; /* Restore rte_errno. */
414 return -rte_errno;
415 }
416
417 /**
418 * Release an Rx verbs queue object.
419 *
420 * @param rxq
421 * Pointer to Rx queue.
422 */
423 static void
mlx5_rxq_ibv_obj_release(struct mlx5_rxq_priv * rxq)424 mlx5_rxq_ibv_obj_release(struct mlx5_rxq_priv *rxq)
425 {
426 struct mlx5_rxq_obj *rxq_obj = rxq->ctrl->obj;
427
428 if (rxq_obj == NULL || rxq_obj->wq == NULL)
429 return;
430 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
431 rxq_obj->wq = NULL;
432 MLX5_ASSERT(rxq_obj->ibv_cq);
433 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));
434 if (rxq_obj->ibv_channel)
435 claim_zero(mlx5_glue->destroy_comp_channel
436 (rxq_obj->ibv_channel));
437 rxq->ctrl->started = false;
438 }
439
440 /**
441 * Get event for an Rx verbs queue object.
442 *
443 * @param rxq_obj
444 * Verbs Rx queue object.
445 *
446 * @return
447 * 0 on success, a negative errno value otherwise and rte_errno is set.
448 */
449 static int
mlx5_rx_ibv_get_event(struct mlx5_rxq_obj * rxq_obj)450 mlx5_rx_ibv_get_event(struct mlx5_rxq_obj *rxq_obj)
451 {
452 struct ibv_cq *ev_cq;
453 void *ev_ctx;
454 int ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel,
455 &ev_cq, &ev_ctx);
456
457 if (ret < 0 || ev_cq != rxq_obj->ibv_cq)
458 goto exit;
459 mlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);
460 return 0;
461 exit:
462 if (ret < 0)
463 rte_errno = errno;
464 else
465 rte_errno = EINVAL;
466 return -rte_errno;
467 }
468
469 /**
470 * Creates a receive work queue as a filed of indirection table.
471 *
472 * @param dev
473 * Pointer to Ethernet device.
474 * @param log_n
475 * Log of number of queues in the array.
476 * @param ind_tbl
477 * Verbs indirection table object.
478 *
479 * @return
480 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 */
482 static int
mlx5_ibv_ind_table_new(struct rte_eth_dev * dev,const unsigned int log_n,struct mlx5_ind_table_obj * ind_tbl)483 mlx5_ibv_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
484 struct mlx5_ind_table_obj *ind_tbl)
485 {
486 struct mlx5_priv *priv = dev->data->dev_private;
487 struct ibv_wq *wq[1 << log_n];
488 unsigned int i, j;
489
490 MLX5_ASSERT(ind_tbl);
491 for (i = 0; i != ind_tbl->queues_n; ++i) {
492 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev,
493 ind_tbl->queues[i]);
494
495 wq[i] = rxq->ctrl->obj->wq;
496 }
497 MLX5_ASSERT(i > 0);
498 /* Finalise indirection table. */
499 for (j = 0; i != (unsigned int)(1 << log_n); ++j, ++i)
500 wq[i] = wq[j];
501 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
502 (priv->sh->cdev->ctx,
503 &(struct ibv_rwq_ind_table_init_attr){
504 .log_ind_tbl_size = log_n,
505 .ind_tbl = wq,
506 .comp_mask = 0,
507 });
508 if (!ind_tbl->ind_table) {
509 rte_errno = errno;
510 return -rte_errno;
511 }
512 return 0;
513 }
514
515 /**
516 * Destroys the specified Indirection Table.
517 *
518 * @param ind_table
519 * Indirection table to release.
520 */
521 static void
mlx5_ibv_ind_table_destroy(struct mlx5_ind_table_obj * ind_tbl)522 mlx5_ibv_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
523 {
524 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
525 }
526
527 /**
528 * Create an Rx Hash queue.
529 *
530 * @param dev
531 * Pointer to Ethernet device.
532 * @param hrxq
533 * Pointer to Rx Hash queue.
534 * @param tunnel
535 * Tunnel type.
536 *
537 * @return
538 * 0 on success, a negative errno value otherwise and rte_errno is set.
539 */
540 static int
mlx5_ibv_hrxq_new(struct rte_eth_dev * dev,struct mlx5_hrxq * hrxq,int tunnel __rte_unused)541 mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
542 int tunnel __rte_unused)
543 {
544 struct mlx5_priv *priv = dev->data->dev_private;
545 struct ibv_qp *qp = NULL;
546 struct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table;
547 const uint8_t *rss_key = hrxq->rss_key;
548 uint64_t hash_fields = hrxq->hash_fields;
549 int err;
550 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
551 struct mlx5dv_qp_init_attr qp_init_attr;
552
553 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
554 if (tunnel) {
555 qp_init_attr.comp_mask =
556 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
557 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
558 }
559 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
560 if (dev->data->dev_conf.lpbk_mode) {
561 /* Allow packet sent from NIC loop back w/o source MAC check. */
562 qp_init_attr.comp_mask |=
563 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
564 qp_init_attr.create_flags |=
565 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
566 }
567 #endif
568 qp = mlx5_glue->dv_create_qp
569 (priv->sh->cdev->ctx,
570 &(struct ibv_qp_init_attr_ex){
571 .qp_type = IBV_QPT_RAW_PACKET,
572 .comp_mask =
573 IBV_QP_INIT_ATTR_PD |
574 IBV_QP_INIT_ATTR_IND_TABLE |
575 IBV_QP_INIT_ATTR_RX_HASH,
576 .rx_hash_conf = (struct ibv_rx_hash_conf){
577 .rx_hash_function =
578 IBV_RX_HASH_FUNC_TOEPLITZ,
579 .rx_hash_key_len = hrxq->rss_key_len,
580 .rx_hash_key =
581 (void *)(uintptr_t)rss_key,
582 .rx_hash_fields_mask = hash_fields,
583 },
584 .rwq_ind_tbl = ind_tbl->ind_table,
585 .pd = priv->sh->cdev->pd,
586 },
587 &qp_init_attr);
588 #else
589 qp = mlx5_glue->create_qp_ex
590 (priv->sh->cdev->ctx,
591 &(struct ibv_qp_init_attr_ex){
592 .qp_type = IBV_QPT_RAW_PACKET,
593 .comp_mask =
594 IBV_QP_INIT_ATTR_PD |
595 IBV_QP_INIT_ATTR_IND_TABLE |
596 IBV_QP_INIT_ATTR_RX_HASH,
597 .rx_hash_conf = (struct ibv_rx_hash_conf){
598 .rx_hash_function =
599 IBV_RX_HASH_FUNC_TOEPLITZ,
600 .rx_hash_key_len = hrxq->rss_key_len,
601 .rx_hash_key =
602 (void *)(uintptr_t)rss_key,
603 .rx_hash_fields_mask = hash_fields,
604 },
605 .rwq_ind_tbl = ind_tbl->ind_table,
606 .pd = priv->sh->cdev->pd,
607 });
608 #endif
609 if (!qp) {
610 rte_errno = errno;
611 goto error;
612 }
613 hrxq->qp = qp;
614 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
615 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
616 if (!hrxq->action) {
617 rte_errno = errno;
618 goto error;
619 }
620 #endif
621 return 0;
622 error:
623 err = rte_errno; /* Save rte_errno before cleanup. */
624 if (qp)
625 claim_zero(mlx5_glue->destroy_qp(qp));
626 rte_errno = err; /* Restore rte_errno. */
627 return -rte_errno;
628 }
629
630 /**
631 * Destroy a Verbs queue pair.
632 *
633 * @param hrxq
634 * Hash Rx queue to release its qp.
635 */
636 static void
mlx5_ibv_qp_destroy(struct mlx5_hrxq * hrxq)637 mlx5_ibv_qp_destroy(struct mlx5_hrxq *hrxq)
638 {
639 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
640 }
641
642 /**
643 * Release a drop Rx queue Verbs object.
644 *
645 * @param dev
646 * Pointer to Ethernet device.
647 */
648 static void
mlx5_rxq_ibv_obj_drop_release(struct rte_eth_dev * dev)649 mlx5_rxq_ibv_obj_drop_release(struct rte_eth_dev *dev)
650 {
651 struct mlx5_priv *priv = dev->data->dev_private;
652 struct mlx5_rxq_priv *rxq = priv->drop_queue.rxq;
653 struct mlx5_rxq_obj *rxq_obj;
654
655 if (rxq == NULL)
656 return;
657 if (rxq->ctrl == NULL)
658 goto free_priv;
659 rxq_obj = rxq->ctrl->obj;
660 if (rxq_obj == NULL)
661 goto free_ctrl;
662 if (rxq_obj->wq)
663 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
664 if (rxq_obj->ibv_cq)
665 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));
666 mlx5_free(rxq_obj);
667 free_ctrl:
668 mlx5_free(rxq->ctrl);
669 free_priv:
670 mlx5_free(rxq);
671 priv->drop_queue.rxq = NULL;
672 }
673
674 /**
675 * Create a drop Rx queue Verbs object.
676 *
677 * @param dev
678 * Pointer to Ethernet device.
679 *
680 * @return
681 * 0 on success, a negative errno value otherwise and rte_errno is set.
682 */
683 static int
mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev * dev)684 mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev *dev)
685 {
686 struct mlx5_priv *priv = dev->data->dev_private;
687 struct ibv_context *ctx = priv->sh->cdev->ctx;
688 struct mlx5_rxq_priv *rxq = priv->drop_queue.rxq;
689 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
690 struct mlx5_rxq_obj *rxq_obj = NULL;
691
692 if (rxq != NULL)
693 return 0;
694 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
695 if (rxq == NULL) {
696 DRV_LOG(DEBUG, "Port %u cannot allocate drop Rx queue memory.",
697 dev->data->port_id);
698 rte_errno = ENOMEM;
699 return -rte_errno;
700 }
701 priv->drop_queue.rxq = rxq;
702 rxq_ctrl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq_ctrl), 0,
703 SOCKET_ID_ANY);
704 if (rxq_ctrl == NULL) {
705 DRV_LOG(DEBUG, "Port %u cannot allocate drop Rx queue control memory.",
706 dev->data->port_id);
707 rte_errno = ENOMEM;
708 goto error;
709 }
710 rxq->ctrl = rxq_ctrl;
711 rxq_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq_obj), 0,
712 SOCKET_ID_ANY);
713 if (rxq_obj == NULL) {
714 DRV_LOG(DEBUG, "Port %u cannot allocate drop Rx queue memory.",
715 dev->data->port_id);
716 rte_errno = ENOMEM;
717 goto error;
718 }
719 rxq_ctrl->obj = rxq_obj;
720 rxq_obj->ibv_cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
721 if (!rxq_obj->ibv_cq) {
722 DRV_LOG(DEBUG, "Port %u cannot allocate CQ for drop queue.",
723 dev->data->port_id);
724 rte_errno = errno;
725 goto error;
726 }
727 rxq_obj->wq = mlx5_glue->create_wq(ctx, &(struct ibv_wq_init_attr){
728 .wq_type = IBV_WQT_RQ,
729 .max_wr = 1,
730 .max_sge = 1,
731 .pd = priv->sh->cdev->pd,
732 .cq = rxq_obj->ibv_cq,
733 });
734 if (!rxq_obj->wq) {
735 DRV_LOG(DEBUG, "Port %u cannot allocate WQ for drop queue.",
736 dev->data->port_id);
737 rte_errno = errno;
738 goto error;
739 }
740 return 0;
741 error:
742 mlx5_rxq_ibv_obj_drop_release(dev);
743 return -rte_errno;
744 }
745
746 /**
747 * Create a Verbs drop action for Rx Hash queue.
748 *
749 * @param dev
750 * Pointer to Ethernet device.
751 *
752 * @return
753 * 0 on success, a negative errno value otherwise and rte_errno is set.
754 */
755 static int
mlx5_ibv_drop_action_create(struct rte_eth_dev * dev)756 mlx5_ibv_drop_action_create(struct rte_eth_dev *dev)
757 {
758 struct mlx5_priv *priv = dev->data->dev_private;
759 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
760 struct ibv_rwq_ind_table *ind_tbl = NULL;
761 struct mlx5_rxq_obj *rxq;
762 int ret;
763
764 MLX5_ASSERT(hrxq && hrxq->ind_table);
765 ret = mlx5_rxq_ibv_obj_drop_create(dev);
766 if (ret < 0)
767 goto error;
768 rxq = priv->drop_queue.rxq->ctrl->obj;
769 ind_tbl = mlx5_glue->create_rwq_ind_table
770 (priv->sh->cdev->ctx,
771 &(struct ibv_rwq_ind_table_init_attr){
772 .log_ind_tbl_size = 0,
773 .ind_tbl = (struct ibv_wq **)&rxq->wq,
774 .comp_mask = 0,
775 });
776 if (!ind_tbl) {
777 DRV_LOG(DEBUG, "Port %u"
778 " cannot allocate indirection table for drop queue.",
779 dev->data->port_id);
780 rte_errno = errno;
781 goto error;
782 }
783 hrxq->qp = mlx5_glue->create_qp_ex(priv->sh->cdev->ctx,
784 &(struct ibv_qp_init_attr_ex){
785 .qp_type = IBV_QPT_RAW_PACKET,
786 .comp_mask = IBV_QP_INIT_ATTR_PD |
787 IBV_QP_INIT_ATTR_IND_TABLE |
788 IBV_QP_INIT_ATTR_RX_HASH,
789 .rx_hash_conf = (struct ibv_rx_hash_conf){
790 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
791 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
792 .rx_hash_key = rss_hash_default_key,
793 .rx_hash_fields_mask = 0,
794 },
795 .rwq_ind_tbl = ind_tbl,
796 .pd = priv->sh->cdev->pd
797 });
798 if (!hrxq->qp) {
799 DRV_LOG(DEBUG, "Port %u cannot allocate QP for drop queue.",
800 dev->data->port_id);
801 rte_errno = errno;
802 goto error;
803 }
804 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
805 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
806 if (!hrxq->action) {
807 rte_errno = errno;
808 goto error;
809 }
810 #endif
811 hrxq->ind_table->ind_table = ind_tbl;
812 return 0;
813 error:
814 if (hrxq->qp)
815 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
816 if (ind_tbl)
817 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));
818 if (priv->drop_queue.rxq)
819 mlx5_rxq_ibv_obj_drop_release(dev);
820 return -rte_errno;
821 }
822
823 /**
824 * Release a drop hash Rx queue.
825 *
826 * @param dev
827 * Pointer to Ethernet device.
828 */
829 static void
mlx5_ibv_drop_action_destroy(struct rte_eth_dev * dev)830 mlx5_ibv_drop_action_destroy(struct rte_eth_dev *dev)
831 {
832 struct mlx5_priv *priv = dev->data->dev_private;
833 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
834 struct ibv_rwq_ind_table *ind_tbl = hrxq->ind_table->ind_table;
835
836 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
837 claim_zero(mlx5_glue->destroy_flow_action(hrxq->action));
838 #endif
839 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
840 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));
841 mlx5_rxq_ibv_obj_drop_release(dev);
842 }
843
844 /**
845 * Create a QP Verbs object.
846 *
847 * @param dev
848 * Pointer to Ethernet device.
849 * @param idx
850 * Queue index in DPDK Tx queue array.
851 *
852 * @return
853 * The QP Verbs object, NULL otherwise and rte_errno is set.
854 */
855 static struct ibv_qp *
mlx5_txq_ibv_qp_create(struct rte_eth_dev * dev,uint16_t idx)856 mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx)
857 {
858 struct mlx5_priv *priv = dev->data->dev_private;
859 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
860 struct mlx5_txq_ctrl *txq_ctrl =
861 container_of(txq_data, struct mlx5_txq_ctrl, txq);
862 struct ibv_qp *qp_obj = NULL;
863 struct ibv_qp_init_attr_ex qp_attr = { 0 };
864 const int desc = 1 << txq_data->elts_n;
865
866 MLX5_ASSERT(txq_ctrl->obj->cq);
867 /* CQ to be associated with the send queue. */
868 qp_attr.send_cq = txq_ctrl->obj->cq;
869 /* CQ to be associated with the receive queue. */
870 qp_attr.recv_cq = txq_ctrl->obj->cq;
871 /* Max number of outstanding WRs. */
872 qp_attr.cap.max_send_wr = RTE_MIN(priv->sh->dev_cap.max_qp_wr, desc);
873 /*
874 * Max number of scatter/gather elements in a WR, must be 1 to prevent
875 * libmlx5 from trying to affect must be 1 to prevent libmlx5 from
876 * trying to affect too much memory. TX gather is not impacted by the
877 * dev_cap.max_sge limit and will still work properly.
878 */
879 qp_attr.cap.max_send_sge = 1;
880 qp_attr.qp_type = IBV_QPT_RAW_PACKET,
881 /* Do *NOT* enable this, completions events are managed per Tx burst. */
882 qp_attr.sq_sig_all = 0;
883 qp_attr.pd = priv->sh->cdev->pd;
884 qp_attr.comp_mask = IBV_QP_INIT_ATTR_PD;
885 if (txq_data->inlen_send)
886 qp_attr.cap.max_inline_data = txq_ctrl->max_inline_data;
887 if (txq_data->tso_en) {
888 qp_attr.max_tso_header = txq_ctrl->max_tso_header;
889 qp_attr.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
890 }
891 qp_obj = mlx5_glue->create_qp_ex(priv->sh->cdev->ctx, &qp_attr);
892 if (qp_obj == NULL) {
893 DRV_LOG(ERR, "Port %u Tx queue %u QP creation failure.",
894 dev->data->port_id, idx);
895 rte_errno = errno;
896 }
897 return qp_obj;
898 }
899
900 /**
901 * Initialize Tx UAR registers for primary process.
902 *
903 * @param txq_ctrl
904 * Pointer to Tx queue control structure.
905 * @param bf_reg
906 * BlueFlame register from Verbs UAR.
907 */
908 static void
mlx5_txq_ibv_uar_init(struct mlx5_txq_ctrl * txq_ctrl,void * bf_reg)909 mlx5_txq_ibv_uar_init(struct mlx5_txq_ctrl *txq_ctrl, void *bf_reg)
910 {
911 struct mlx5_priv *priv = txq_ctrl->priv;
912 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
913 const size_t page_size = rte_mem_page_size();
914 struct mlx5_txq_data *txq = &txq_ctrl->txq;
915 off_t uar_mmap_offset = txq_ctrl->uar_mmap_offset;
916 #ifndef RTE_ARCH_64
917 unsigned int lock_idx;
918 #endif
919
920 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
921 MLX5_ASSERT(ppriv);
922 if (page_size == (size_t)-1) {
923 DRV_LOG(ERR, "Failed to get mem page size");
924 rte_errno = ENOMEM;
925 }
926 txq->db_heu = priv->sh->cdev->config.dbnc == MLX5_SQ_DB_HEURISTIC;
927 txq->db_nc = mlx5_db_map_type_get(uar_mmap_offset, page_size);
928 ppriv->uar_table[txq->idx].db = bf_reg;
929 #ifndef RTE_ARCH_64
930 /* Assign an UAR lock according to UAR page number. */
931 lock_idx = (uar_mmap_offset / page_size) & MLX5_UAR_PAGE_NUM_MASK;
932 ppriv->uar_table[txq->idx].sl_p = &priv->sh->uar_lock[lock_idx];
933 #endif
934 }
935
936 /**
937 * Create the Tx queue Verbs object.
938 *
939 * @param dev
940 * Pointer to Ethernet device.
941 * @param idx
942 * Queue index in DPDK Tx queue array.
943 *
944 * @return
945 * 0 on success, a negative errno value otherwise and rte_errno is set.
946 */
947 int
mlx5_txq_ibv_obj_new(struct rte_eth_dev * dev,uint16_t idx)948 mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)
949 {
950 struct mlx5_priv *priv = dev->data->dev_private;
951 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
952 struct mlx5_txq_ctrl *txq_ctrl =
953 container_of(txq_data, struct mlx5_txq_ctrl, txq);
954 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
955 unsigned int cqe_n;
956 struct mlx5dv_qp qp;
957 struct mlx5dv_cq cq_info;
958 struct mlx5dv_obj obj;
959 const int desc = 1 << txq_data->elts_n;
960 int ret = 0;
961
962 MLX5_ASSERT(txq_data);
963 MLX5_ASSERT(txq_obj);
964 txq_obj->txq_ctrl = txq_ctrl;
965 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
966 DRV_LOG(ERR, "Port %u MLX5_ENABLE_CQE_COMPRESSION "
967 "must never be set.", dev->data->port_id);
968 rte_errno = EINVAL;
969 return -rte_errno;
970 }
971 if (__rte_trace_point_fp_is_enabled() &&
972 txq_data->offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP)
973 cqe_n = UINT16_MAX / 2 - 1;
974 else
975 cqe_n = desc / MLX5_TX_COMP_THRESH +
976 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
977 txq_obj->cq = mlx5_glue->create_cq(priv->sh->cdev->ctx, cqe_n,
978 NULL, NULL, 0);
979 if (txq_obj->cq == NULL) {
980 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
981 dev->data->port_id, idx);
982 rte_errno = errno;
983 goto error;
984 }
985 txq_obj->qp = mlx5_txq_ibv_qp_create(dev, idx);
986 if (txq_obj->qp == NULL) {
987 rte_errno = errno;
988 goto error;
989 }
990 ret = mlx5_ibv_modify_qp(txq_obj, MLX5_TXQ_MOD_RST2RDY,
991 (uint8_t)priv->dev_port);
992 if (ret) {
993 DRV_LOG(ERR, "Port %u Tx queue %u QP state modifying failed.",
994 dev->data->port_id, idx);
995 rte_errno = errno;
996 goto error;
997 }
998 qp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET;
999 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1000 /* If using DevX, need additional mask to read tisn value. */
1001 if (priv->sh->cdev->config.devx && !priv->sh->tdn)
1002 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
1003 #endif
1004 obj.cq.in = txq_obj->cq;
1005 obj.cq.out = &cq_info;
1006 obj.qp.in = txq_obj->qp;
1007 obj.qp.out = &qp;
1008 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
1009 if (ret != 0) {
1010 rte_errno = errno;
1011 goto error;
1012 }
1013 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1014 DRV_LOG(ERR,
1015 "Port %u wrong MLX5_CQE_SIZE environment variable"
1016 " value: it should be set to %u.",
1017 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1018 rte_errno = EINVAL;
1019 goto error;
1020 }
1021 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
1022 txq_data->cqe_s = 1 << txq_data->cqe_n;
1023 txq_data->cqe_m = txq_data->cqe_s - 1;
1024 txq_data->qp_num_8s = ((struct ibv_qp *)txq_obj->qp)->qp_num << 8;
1025 txq_data->wqes = qp.sq.buf;
1026 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
1027 txq_data->wqe_s = 1 << txq_data->wqe_n;
1028 txq_data->wqe_m = txq_data->wqe_s - 1;
1029 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1030 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
1031 txq_data->cq_db = cq_info.dbrec;
1032 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
1033 txq_data->cq_ci = 0;
1034 txq_data->cq_pi = 0;
1035 txq_data->wqe_ci = 0;
1036 txq_data->wqe_pi = 0;
1037 txq_data->wqe_comp = 0;
1038 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1039 txq_data->wait_on_time = !!(!priv->sh->config.tx_pp &&
1040 priv->sh->cdev->config.hca_attr.wait_on_time &&
1041 txq_data->offloads &
1042 RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP);
1043 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1044 /*
1045 * If using DevX need to query and store TIS transport domain value.
1046 * This is done once per port.
1047 * Will use this value on Rx, when creating matching TIR.
1048 */
1049 if (priv->sh->cdev->config.devx && !priv->sh->tdn) {
1050 ret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn,
1051 &priv->sh->tdn);
1052 if (ret) {
1053 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
1054 "transport domain.", dev->data->port_id, idx);
1055 rte_errno = EINVAL;
1056 goto error;
1057 } else {
1058 DRV_LOG(DEBUG, "Port %u Tx queue %u TIS number %d "
1059 "transport domain %d.", dev->data->port_id,
1060 idx, qp.tisn, priv->sh->tdn);
1061 }
1062 }
1063 #endif
1064 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
1065 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
1066 DRV_LOG(DEBUG, "Port %u: uar_mmap_offset 0x%" PRIx64 ".",
1067 dev->data->port_id, txq_ctrl->uar_mmap_offset);
1068 } else {
1069 DRV_LOG(ERR,
1070 "Port %u failed to retrieve UAR info, invalid libmlx5.so",
1071 dev->data->port_id);
1072 rte_errno = EINVAL;
1073 goto error;
1074 }
1075 mlx5_txq_ibv_uar_init(txq_ctrl, qp.bf.reg);
1076 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1077 return 0;
1078 error:
1079 ret = rte_errno; /* Save rte_errno before cleanup. */
1080 if (txq_obj->cq)
1081 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1082 if (txq_obj->qp)
1083 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1084 rte_errno = ret; /* Restore rte_errno. */
1085 return -rte_errno;
1086 }
1087
1088 /*
1089 * Create the dummy QP with minimal resources for loopback.
1090 *
1091 * @param dev
1092 * Pointer to Ethernet device.
1093 *
1094 * @return
1095 * 0 on success, a negative errno value otherwise and rte_errno is set.
1096 */
1097 int
mlx5_rxq_ibv_obj_dummy_lb_create(struct rte_eth_dev * dev)1098 mlx5_rxq_ibv_obj_dummy_lb_create(struct rte_eth_dev *dev)
1099 {
1100 #if defined(HAVE_IBV_DEVICE_TUNNEL_SUPPORT) && defined(HAVE_IBV_FLOW_DV_SUPPORT)
1101 struct mlx5_priv *priv = dev->data->dev_private;
1102 struct mlx5_dev_ctx_shared *sh = priv->sh;
1103 struct ibv_context *ctx = sh->cdev->ctx;
1104 struct mlx5dv_qp_init_attr qp_init_attr = {0};
1105 struct {
1106 struct ibv_cq_init_attr_ex ibv;
1107 struct mlx5dv_cq_init_attr mlx5;
1108 } cq_attr = {{0}};
1109
1110 if (dev->data->dev_conf.lpbk_mode) {
1111 /* Allow packet sent from NIC loop back w/o source MAC check. */
1112 qp_init_attr.comp_mask |=
1113 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1114 qp_init_attr.create_flags |=
1115 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
1116 } else {
1117 return 0;
1118 }
1119 /* Only need to check refcnt, 0 after "sh" is allocated. */
1120 if (!!(rte_atomic_fetch_add_explicit(&sh->self_lb.refcnt, 1, rte_memory_order_relaxed))) {
1121 MLX5_ASSERT(sh->self_lb.ibv_cq && sh->self_lb.qp);
1122 priv->lb_used = 1;
1123 return 0;
1124 }
1125 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
1126 .cqe = 1,
1127 .channel = NULL,
1128 .comp_mask = 0,
1129 };
1130 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
1131 .comp_mask = 0,
1132 };
1133 /* Only CQ is needed, no WQ(RQ) is required in this case. */
1134 sh->self_lb.ibv_cq = mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(ctx,
1135 &cq_attr.ibv,
1136 &cq_attr.mlx5));
1137 if (!sh->self_lb.ibv_cq) {
1138 DRV_LOG(ERR, "Port %u cannot allocate CQ for loopback.",
1139 dev->data->port_id);
1140 rte_errno = errno;
1141 goto error;
1142 }
1143 sh->self_lb.qp = mlx5_glue->dv_create_qp(ctx,
1144 &(struct ibv_qp_init_attr_ex){
1145 .qp_type = IBV_QPT_RAW_PACKET,
1146 .comp_mask = IBV_QP_INIT_ATTR_PD,
1147 .pd = sh->cdev->pd,
1148 .send_cq = sh->self_lb.ibv_cq,
1149 .recv_cq = sh->self_lb.ibv_cq,
1150 .cap.max_recv_wr = 1,
1151 },
1152 &qp_init_attr);
1153 if (!sh->self_lb.qp) {
1154 DRV_LOG(DEBUG, "Port %u cannot allocate QP for loopback.",
1155 dev->data->port_id);
1156 rte_errno = errno;
1157 goto error;
1158 }
1159 priv->lb_used = 1;
1160 return 0;
1161 error:
1162 if (sh->self_lb.ibv_cq) {
1163 claim_zero(mlx5_glue->destroy_cq(sh->self_lb.ibv_cq));
1164 sh->self_lb.ibv_cq = NULL;
1165 }
1166 rte_atomic_fetch_sub_explicit(&sh->self_lb.refcnt, 1, rte_memory_order_relaxed);
1167 return -rte_errno;
1168 #else
1169 RTE_SET_USED(dev);
1170 return 0;
1171 #endif
1172 }
1173
1174 /*
1175 * Release the dummy queue resources for loopback.
1176 *
1177 * @param dev
1178 * Pointer to Ethernet device.
1179 */
1180 void
mlx5_rxq_ibv_obj_dummy_lb_release(struct rte_eth_dev * dev)1181 mlx5_rxq_ibv_obj_dummy_lb_release(struct rte_eth_dev *dev)
1182 {
1183 #if defined(HAVE_IBV_DEVICE_TUNNEL_SUPPORT) && defined(HAVE_IBV_FLOW_DV_SUPPORT)
1184 struct mlx5_priv *priv = dev->data->dev_private;
1185 struct mlx5_dev_ctx_shared *sh = priv->sh;
1186
1187 if (!priv->lb_used)
1188 return;
1189 MLX5_ASSERT(rte_atomic_load_explicit(&sh->self_lb.refcnt, rte_memory_order_relaxed));
1190 if (!(rte_atomic_fetch_sub_explicit(&sh->self_lb.refcnt, 1,
1191 rte_memory_order_relaxed) - 1)) {
1192 if (sh->self_lb.qp) {
1193 claim_zero(mlx5_glue->destroy_qp(sh->self_lb.qp));
1194 sh->self_lb.qp = NULL;
1195 }
1196 if (sh->self_lb.ibv_cq) {
1197 claim_zero(mlx5_glue->destroy_cq(sh->self_lb.ibv_cq));
1198 sh->self_lb.ibv_cq = NULL;
1199 }
1200 }
1201 priv->lb_used = 0;
1202 #else
1203 RTE_SET_USED(dev);
1204 return;
1205 #endif
1206 }
1207
1208 /**
1209 * Release an Tx verbs queue object.
1210 *
1211 * @param txq_obj
1212 * Verbs Tx queue object..
1213 */
1214 void
mlx5_txq_ibv_obj_release(struct mlx5_txq_obj * txq_obj)1215 mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj)
1216 {
1217 MLX5_ASSERT(txq_obj);
1218 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1219 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1220 }
1221
1222 struct mlx5_obj_ops ibv_obj_ops = {
1223 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_wq_vlan_strip,
1224 .rxq_obj_new = mlx5_rxq_ibv_obj_new,
1225 .rxq_event_get = mlx5_rx_ibv_get_event,
1226 .rxq_obj_modify = mlx5_ibv_modify_wq,
1227 .rxq_obj_release = mlx5_rxq_ibv_obj_release,
1228 .ind_table_new = mlx5_ibv_ind_table_new,
1229 .ind_table_destroy = mlx5_ibv_ind_table_destroy,
1230 .hrxq_new = mlx5_ibv_hrxq_new,
1231 .hrxq_destroy = mlx5_ibv_qp_destroy,
1232 .drop_action_create = mlx5_ibv_drop_action_create,
1233 .drop_action_destroy = mlx5_ibv_drop_action_destroy,
1234 .txq_obj_new = mlx5_txq_ibv_obj_new,
1235 .txq_obj_modify = mlx5_ibv_modify_qp,
1236 .txq_obj_release = mlx5_txq_ibv_obj_release,
1237 .lb_dummy_queue_create = NULL,
1238 .lb_dummy_queue_release = NULL,
1239 };
1240