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/dpdk/doc/guides/prog_guide/img/
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/dpdk/lib/eal/common/
H A Deal_common_class.c18 rte_class_register(struct rte_class *class) in rte_class_register() argument
20 RTE_VERIFY(class); in rte_class_register()
21 RTE_VERIFY(class->name && strlen(class->name)); in rte_class_register()
23 TAILQ_INSERT_TAIL(&rte_class_list, class, next); in rte_class_register()
24 EAL_LOG(DEBUG, "Registered [%s] device class.", class->name); in rte_class_register()
28 rte_class_unregister(struct rte_class *class) in rte_class_unregister() argument
30 TAILQ_REMOVE(&rte_class_list, class, next); in rte_class_unregister()
31 EAL_LOG(DEBUG, "Unregistered [%s] device class.", class->name); in rte_class_unregister()
53 cmp_class_name(const struct rte_class *class, const void *_name) in cmp_class_name() argument
57 return strcmp(class->name, name); in cmp_class_name()
/dpdk/drivers/net/sfc/
H A Dsfc_ef100_rx.c219 sfc_ef100_rx_nt_or_inner_l4_csum(const efx_word_t class) in sfc_ef100_rx_nt_or_inner_l4_csum() argument
221 return EFX_WORD_FIELD(class, in sfc_ef100_rx_nt_or_inner_l4_csum()
228 sfc_ef100_rx_tun_outer_l4_csum(const efx_word_t class) in sfc_ef100_rx_tun_outer_l4_csum() argument
230 return EFX_WORD_FIELD(class, in sfc_ef100_rx_tun_outer_l4_csum()
237 sfc_ef100_rx_class_decode(const efx_word_t class, uint64_t *ol_flags) in sfc_ef100_rx_class_decode() argument
242 if (unlikely(EFX_WORD_FIELD(class, ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS) != in sfc_ef100_rx_class_decode()
246 switch (EFX_WORD_FIELD(class, ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN)) { in sfc_ef100_rx_class_decode()
258 switch (EFX_WORD_FIELD(class, ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS)) { in sfc_ef100_rx_class_decode()
264 *ol_flags |= sfc_ef100_rx_tun_outer_l4_csum(class); in sfc_ef100_rx_class_decode()
271 *ol_flags |= sfc_ef100_rx_tun_outer_l4_csum(class); in sfc_ef100_rx_class_decode()
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/dpdk/app/test/
H A Dtest_devargs.c61 const char *class; member
82 if (eth_class == NULL && list[i].class != NULL && in test_valid_devargs_cases()
83 strcmp(list[i].class, "eth") == 0) in test_valid_devargs_cases()
107 if ((list[i].class_kv > 0 || list[i].class != NULL) && in test_valid_devargs_cases()
116 if (list[i].class != NULL && in test_valid_devargs_cases()
117 strcmp(da.cls->name, list[i].class) != 0) { in test_valid_devargs_cases()
119 list[i].devargs, da.cls->name, list[i].class); in test_valid_devargs_cases()
/dpdk/drivers/net/mlx5/
H A Dmlx5_flow_geneve.c38 uint16_t class; member
77 option_match_type_and_class(uint8_t type, uint16_t class, in option_match_type_and_class() argument
82 if (option->class_mode == 1 && option->class != class) in option_match_type_and_class()
102 uint16_t class) in mlx5_geneve_tlv_option_get() argument
119 if (option_match_type_and_class(type, class, option)) in mlx5_geneve_tlv_option_get()
122 DRV_LOG(ERR, "TLV option type %u class %u doesn't exist.", type, class); in mlx5_geneve_tlv_option_get()
128 mlx5_get_geneve_hl_data(const void *dr_ctx, uint8_t type, uint16_t class, in mlx5_get_geneve_hl_data() argument
144 option = mlx5_geneve_tlv_option_get(priv, type, class); in mlx5_get_geneve_hl_data()
288 uint16_t class, uint8_t dw_offset) in mlx5_get_geneve_option_modify_field_id() argument
301 option = mlx5_geneve_tlv_option_get(priv, type, class); in mlx5_get_geneve_option_modify_field_id()
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/dpdk/lib/eal/windows/include/sys/
H A Dqueue.h155 class type *slh_first; /* first element */ \
168 class type *sle_next; /* next element */ \
288 class type *stqh_first; /* first element */ \
289 class type **stqh_last; /* addr of last next element */ \
302 class type *stqe_next; /* next element */ \
420 class type *lh_first; /* first element */ \
434 class type *le_next; /* next element */ \
435 class type **le_prev; /* address of previous next element */ \
596 class type *tqh_first; /* first element */ \
597 class type **tqh_last; /* addr of last next element */ \
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/dpdk/doc/guides/nics/
H A Dsoftnic.rst76 #. ``tm_qsize0``: size of scheduler queue 0 (traffic class 0) of the pipes/subscribers.
79 #. ``tm_qsize1``: size of scheduler queue 1 (traffic class 1) of the pipes/subscribers.
82 #. ``tm_qsize2``: size of scheduler queue 2 (traffic class 2) of the pipes/subscribers.
85 #. ``tm_qsize3``: size of scheduler queue 3 (traffic class 3) of the pipes/subscribers.
88 #. ``tm_qsize4``: size of scheduler queue 4 (traffic class 4) of the pipes/subscribers.
91 #. ``tm_qsize5``: size of scheduler queue 5 (traffic class 5) of the pipes/subscribers.
94 #. ``tm_qsize6``: size of scheduler queue 6 (traffic class 6) of the pipes/subscribers.
97 #. ``tm_qsize7``: size of scheduler queue 7 (traffic class 7) of the pipes/subscribers.
100 #. ``tm_qsize8``: size of scheduler queue 8 (traffic class 8) of the pipes/subscribers.
103 #. ``tm_qsize9``: size of scheduler queue 9 (traffic class 9) of the pipes/subscribers.
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/dpdk/examples/qos_sched/
H A Dprofile_red.cfg12 ; - Within lowest priority traffic class (best-effort), the byte-level
13 ; WRR weights for the 4 queues of best effort traffic class are set
78 ; RED params per traffic class and color (Green / Yellow / Red)
H A Dprofile.cfg12 ; - Within lowest priority traffic class (best-effort), the byte-level
13 ; WRR weights for the 4 queues of best effort traffic class are set
H A Dprofile_pie.cfg12 ; - Within lowest priority traffic class (best-effort), the byte-level
13 ; WRR weights for the 4 queues of best effort traffic class are set
H A Dprofile_ov.cfg61 ; RED params per traffic class and color (Green / Yellow / Red)
/dpdk/doc/guides/platform/
H A Dmlx5.rst63 (e.g. ``0000:08:00.1,class=eth``).
67 For example: ``class=crypto:regex`` will probe both Crypto and RegEx PMDs.
73 - ``class=compress`` for :doc:`../../compressdevs/mlx5`.
74 - ``class=crypto`` for :doc:`../../cryptodevs/mlx5`.
75 - ``class=eth`` for :doc:`../../nics/mlx5`.
76 - ``class=regex`` for :doc:`../../regexdevs/mlx5`.
77 - ``class=vdpa`` for :doc:`../../vdpadevs/mlx5`.
359 echo [num_vfs] > /sys/class/infiniband/mlx5_0/device/sriov_numvfs
400 auxiliary:mlx5_core.sf.<num>,class=eth:regex
418 echo switchdev > /sys/class/net/<net device>/compat/devlink/mode
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/dpdk/lib/vhost/
H A Dvirtio_net_ctrl.c14 uint8_t class; member
121 if (data_len < sizeof(ctrl_elem->ctrl_req->class) + sizeof(ctrl_elem->ctrl_req->command)) { in virtio_net_ctrl_pop()
198 if (ctrl_req->class == VIRTIO_NET_CTRL_MQ && in virtio_net_ctrl_handle_req()
/dpdk/
H A Dmeson.build150 foreach class:dpdk_driver_classes
151 class_drivers = get_variable(class + '_drivers')
152 output_message += '\n' + class + ':\n\t'
/dpdk/doc/guides/compressdevs/
H A Dmlx5.rst32 class operations can be supported in parallel to the net, vDPA and
33 RegEx class operations.
/dpdk/doc/guides/sample_app_ug/
H A Dqos_scheduler.rst121 The profile configuration file defines all the port/subport/pipe/traffic class/queue parameters
168 * qavg port X subport Y tc Z: Show average queue size per subport for a specific traffic class.
172 … qavg port X subport Y pipe Z tc A: Show average queue size per pipe for a specific traffic class.
208 * A traffic class is the representation of a different traffic type with a specific loss rate,
237 …| | Lowest Priority TC: 4 | class (Best effort) serviced in WRR | …
/dpdk/doc/guides/vdpadevs/
H A Dsfc.rst18 Adding "class=vdpa" parameter helps to specify that this
67 - ``class`` [net|vdpa] (default **net**)
/dpdk/doc/guides/prog_guide/
H A Dsource_org.rst22 library with the format ``librte_X_Y.a`` where ``X`` is the device class
/dpdk/drivers/net/virtio/
H A Dvirtio_ethdev.c163 ctrl.hdr.class = VIRTIO_NET_CTRL_MQ; in virtio_set_multiple_queues_rss()
186 ctrl.hdr.class = VIRTIO_NET_CTRL_MQ; in virtio_set_multiple_queues_auto()
398 ctrl.hdr.class = VIRTIO_NET_CTRL_RX; in virtio_dev_promiscuous_enable()
425 ctrl.hdr.class = VIRTIO_NET_CTRL_RX; in virtio_dev_promiscuous_disable()
452 ctrl.hdr.class = VIRTIO_NET_CTRL_RX; in virtio_dev_allmulticast_enable()
479 ctrl.hdr.class = VIRTIO_NET_CTRL_RX; in virtio_dev_allmulticast_disable()
874 ctrl.hdr.class = VIRTIO_NET_CTRL_MAC; in virtio_mac_table_set()
970 ctrl.hdr.class = VIRTIO_NET_CTRL_MAC; in virtio_mac_addr_set()
1047 ctrl.hdr.class = VIRTIO_NET_CTRL_VLAN; in virtio_vlan_filter_set()
1200 ctrl.hdr.class = VIRTIO_NET_CTRL_ANNOUNCE; in virtio_ack_link_announce()
/dpdk/doc/guides/rawdevs/
H A Dcnxk_gpio.rst46 available under `/sys/class/gpio`. For further details on how Linux represents
55 $ ls /sys/class/gpio
/dpdk/doc/guides/eventdevs/
H A Ddlb2.rst352 If a port's COS is not defined, then it will be allocated from class 0,
353 class 1, class 2, or class 3, in that order, depending on availability.
356 16 LDB ports may be assigned to a given class of service. If port cos is
357 not defined on the command line, then each class is assigned 25% of the
359 Per-port class of service and bandwidth can be specified in the devargs,
/dpdk/doc/guides/cryptodevs/
H A Duadk.rst137 cat /sys/class/uacce/hisi_sec2-2/available_instances
H A Dmlx5.rst139 dpdk-test -c 1 -n 1 -w <dev>,class=crypto,wcs_file=<file_path>
143 dpdk-test -c 1 -n 1 -w <dev>,class=crypto

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