xref: /dpdk/examples/qos_sched/profile_pie.cfg (revision 86dfed2a8ed704e013f054985a92d46f07ff48d1)
1a61b3196SMarcin Danilewicz;   SPDX-License-Identifier: BSD-3-Clause
2a61b3196SMarcin Danilewicz;   Copyright(c) 2010-2019 Intel Corporation.
3a61b3196SMarcin Danilewicz
4a61b3196SMarcin Danilewicz; This file enables the following hierarchical scheduler configuration for each
5a61b3196SMarcin Danilewicz; 10GbE output port:
6a61b3196SMarcin Danilewicz;	* Single subport (subport 0):
7a61b3196SMarcin Danilewicz;		- Subport rate set to 100% of port rate
8a61b3196SMarcin Danilewicz;		- Each of the 13 traffic classes has rate set to 100% of port rate
9a61b3196SMarcin Danilewicz;	* 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
10a61b3196SMarcin Danilewicz;		- Pipe rate set to 1/4K of port rate
11a61b3196SMarcin Danilewicz;		- Each of the 13 traffic classes has rate set to 100% of pipe rate
12a61b3196SMarcin Danilewicz;		- Within lowest priority traffic class (best-effort), the byte-level
13a61b3196SMarcin Danilewicz;		  WRR weights for the 4 queues of best effort traffic class are set
14a61b3196SMarcin Danilewicz;		  to 1:1:1:1
15a61b3196SMarcin Danilewicz;
16a61b3196SMarcin Danilewicz; For more details, please refer to chapter "Quality of Service (QoS) Framework"
17a61b3196SMarcin Danilewicz; of Data Plane Development Kit (DPDK) Programmer's Guide.
18a61b3196SMarcin Danilewicz
19a61b3196SMarcin Danilewicz; Port configuration
20a61b3196SMarcin Danilewicz[port]
21a61b3196SMarcin Danilewiczframe overhead = 24
22a61b3196SMarcin Danilewicznumber of subports per port = 1
23a61b3196SMarcin Danilewicz
24*86dfed2aSBruce Richardsonsubport 0-8 = 0                ; These subports are configured with subport profile 0
25*86dfed2aSBruce Richardson
26a61b3196SMarcin Danilewicz; Subport configuration
27a61b3196SMarcin Danilewicz[subport 0]
28a61b3196SMarcin Danilewicznumber of pipes per subport = 4096
29a61b3196SMarcin Danilewiczqueue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
30a61b3196SMarcin Danilewicz
31*86dfed2aSBruce Richardsonpipe 0-4095 = 0                ; These pipes are configured with pipe profile 0
32a61b3196SMarcin Danilewicz
33a61b3196SMarcin Danilewicz[subport profile 0]
34a61b3196SMarcin Danilewicztb rate = 1250000000           ; Bytes per second
35a61b3196SMarcin Danilewicztb size = 1000000              ; Bytes
36a61b3196SMarcin Danilewicz
37a61b3196SMarcin Danilewicztc 0 rate = 1250000000         ; Bytes per second
38a61b3196SMarcin Danilewicztc 1 rate = 1250000000         ; Bytes per second
39a61b3196SMarcin Danilewicztc 2 rate = 1250000000         ; Bytes per second
40a61b3196SMarcin Danilewicztc 3 rate = 1250000000         ; Bytes per second
41a61b3196SMarcin Danilewicztc 4 rate = 1250000000         ; Bytes per second
42a61b3196SMarcin Danilewicztc 5 rate = 1250000000         ; Bytes per second
43a61b3196SMarcin Danilewicztc 6 rate = 1250000000         ; Bytes per second
44a61b3196SMarcin Danilewicztc 7 rate = 1250000000         ; Bytes per second
45a61b3196SMarcin Danilewicztc 8 rate = 1250000000         ; Bytes per second
46a61b3196SMarcin Danilewicztc 9 rate = 1250000000         ; Bytes per second
47a61b3196SMarcin Danilewicztc 10 rate = 1250000000        ; Bytes per second
48a61b3196SMarcin Danilewicztc 11 rate = 1250000000        ; Bytes per second
49a61b3196SMarcin Danilewicztc 12 rate = 1250000000        ; Bytes per second
50a61b3196SMarcin Danilewicz
51a61b3196SMarcin Danilewicztc period = 10                 ; Milliseconds
52a61b3196SMarcin Danilewicz
53a61b3196SMarcin Danilewicz; Pipe configuration
54a61b3196SMarcin Danilewicz[pipe profile 0]
55a61b3196SMarcin Danilewicztb rate = 305175               ; Bytes per second
56a61b3196SMarcin Danilewicztb size = 1000000              ; Bytes
57a61b3196SMarcin Danilewicz
58a61b3196SMarcin Danilewicztc 0 rate = 305175             ; Bytes per second
59a61b3196SMarcin Danilewicztc 1 rate = 305175             ; Bytes per second
60a61b3196SMarcin Danilewicztc 2 rate = 305175             ; Bytes per second
61a61b3196SMarcin Danilewicztc 3 rate = 305175             ; Bytes per second
62a61b3196SMarcin Danilewicztc 4 rate = 305175             ; Bytes per second
63a61b3196SMarcin Danilewicztc 5 rate = 305175             ; Bytes per second
64a61b3196SMarcin Danilewicztc 6 rate = 305175             ; Bytes per second
65a61b3196SMarcin Danilewicztc 7 rate = 305175             ; Bytes per second
66a61b3196SMarcin Danilewicztc 8 rate = 305175             ; Bytes per second
67a61b3196SMarcin Danilewicztc 9 rate = 305175             ; Bytes per second
68a61b3196SMarcin Danilewicztc 10 rate = 305175            ; Bytes per second
69a61b3196SMarcin Danilewicztc 11 rate = 305175            ; Bytes per second
70a61b3196SMarcin Danilewicztc 12 rate = 305175            ; Bytes per second
71a61b3196SMarcin Danilewicz
72a61b3196SMarcin Danilewicztc period = 40                ; Milliseconds
73a61b3196SMarcin Danilewicz
74a61b3196SMarcin Danilewicztc 12 oversubscription weight = 1
75a61b3196SMarcin Danilewicz
76a61b3196SMarcin Danilewicztc 12 wrr weights = 1 1 1 1
77a61b3196SMarcin Danilewicz
78a61b3196SMarcin Danilewicz[pie]
79a61b3196SMarcin Danilewicztc 0 qdelay ref = 15
80a61b3196SMarcin Danilewicztc 0 max burst = 150
81a61b3196SMarcin Danilewicztc 0 update interval = 15
82a61b3196SMarcin Danilewicztc 0 tailq th = 64
83a61b3196SMarcin Danilewicz
84a61b3196SMarcin Danilewicztc 1 qdelay ref = 15
85a61b3196SMarcin Danilewicztc 1 max burst = 150
86a61b3196SMarcin Danilewicztc 1 update interval = 15
87a61b3196SMarcin Danilewicztc 1 tailq th = 64
88a61b3196SMarcin Danilewicz
89a61b3196SMarcin Danilewicztc 2 qdelay ref = 15
90a61b3196SMarcin Danilewicztc 2 max burst = 150
91a61b3196SMarcin Danilewicztc 2 update interval = 15
92a61b3196SMarcin Danilewicztc 2 tailq th = 64
93a61b3196SMarcin Danilewicz
94a61b3196SMarcin Danilewicztc 3 qdelay ref = 15
95a61b3196SMarcin Danilewicztc 3 max burst = 150
96a61b3196SMarcin Danilewicztc 3 update interval = 15
97a61b3196SMarcin Danilewicztc 3 tailq th = 64
98a61b3196SMarcin Danilewicz
99a61b3196SMarcin Danilewicztc 4 qdelay ref = 15
100a61b3196SMarcin Danilewicztc 4 max burst = 150
101a61b3196SMarcin Danilewicztc 4 update interval = 15
102a61b3196SMarcin Danilewicztc 4 tailq th = 64
103a61b3196SMarcin Danilewicz
104a61b3196SMarcin Danilewicztc 5 qdelay ref = 15
105a61b3196SMarcin Danilewicztc 5 max burst = 150
106a61b3196SMarcin Danilewicztc 5 update interval = 15
107a61b3196SMarcin Danilewicztc 5 tailq th = 64
108a61b3196SMarcin Danilewicz
109a61b3196SMarcin Danilewicztc 6 qdelay ref = 15
110a61b3196SMarcin Danilewicztc 6 max burst = 150
111a61b3196SMarcin Danilewicztc 6 update interval = 15
112a61b3196SMarcin Danilewicztc 6 tailq th = 64
113a61b3196SMarcin Danilewicz
114a61b3196SMarcin Danilewicztc 7 qdelay ref = 15
115a61b3196SMarcin Danilewicztc 7 max burst = 150
116a61b3196SMarcin Danilewicztc 7 update interval = 15
117a61b3196SMarcin Danilewicztc 7 tailq th = 64
118a61b3196SMarcin Danilewicz
119a61b3196SMarcin Danilewicztc 8 qdelay ref = 15
120a61b3196SMarcin Danilewicztc 8 max burst = 150
121a61b3196SMarcin Danilewicztc 8 update interval = 15
122a61b3196SMarcin Danilewicztc 8 tailq th = 64
123a61b3196SMarcin Danilewicz
124a61b3196SMarcin Danilewicztc 9 qdelay ref = 15
125a61b3196SMarcin Danilewicztc 9 max burst = 150
126a61b3196SMarcin Danilewicztc 9 update interval = 15
127a61b3196SMarcin Danilewicztc 9 tailq th = 64
128a61b3196SMarcin Danilewicz
129a61b3196SMarcin Danilewicztc 10 qdelay ref = 15
130a61b3196SMarcin Danilewicztc 10 max burst = 150
131a61b3196SMarcin Danilewicztc 10 update interval = 15
132a61b3196SMarcin Danilewicztc 10 tailq th = 64
133a61b3196SMarcin Danilewicz
134a61b3196SMarcin Danilewicztc 11 qdelay ref = 15
135a61b3196SMarcin Danilewicztc 11 max burst = 150
136a61b3196SMarcin Danilewicztc 11 update interval = 15
137a61b3196SMarcin Danilewicztc 11 tailq th = 64
138a61b3196SMarcin Danilewicz
139a61b3196SMarcin Danilewicztc 12 qdelay ref = 15
140a61b3196SMarcin Danilewicztc 12 max burst = 150
141a61b3196SMarcin Danilewicztc 12 update interval = 15
142a61b3196SMarcin Danilewicztc 12 tailq th = 64
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