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/dflybsd-src/sys/dev/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c105 uint32_t tmp; in gfxhub_v1_0_init_tlb_regs() local
108 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
110 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
111 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
112 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
114 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
116 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v1_0_init_tlb_regs()
117 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
119 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
121 WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
[all …]
H A Dmmhub_v1_0.c83 uint32_t tmp; in mmhub_v1_0_init_system_aperture_regs() local
110 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
111 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
113 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v1_0_init_system_aperture_regs()
118 uint32_t tmp; in mmhub_v1_0_init_tlb_regs() local
121 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
123 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
124 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
125 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
[all …]
H A Dgmc_v8_0.c195 u32 tmp; in gmc_v8_0_mc_resume() local
198 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
199 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume()
200 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
202 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume()
203 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v8_0_mc_resume()
204 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
449 u32 tmp; in gmc_v8_0_mc_program() local
467 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
468 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program()
[all …]
H A Dgmc_v7_0.c107 u32 tmp; in gmc_v7_0_mc_resume() local
110 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
111 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_resume()
112 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v7_0_mc_resume()
114 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v7_0_mc_resume()
115 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v7_0_mc_resume()
116 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
258 u32 tmp; in gmc_v7_0_mc_program() local
276 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
277 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v7_0_mc_program()
[all …]
H A Ddce_v10_0.c235 u32 tmp; in dce_v10_0_page_flip() local
238 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
239 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v10_0_page_flip()
241 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_page_flip()
299 u32 tmp; in dce_v10_0_hpd_set_polarity() local
305 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
307 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v10_0_hpd_set_polarity()
309 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v10_0_hpd_set_polarity()
310 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
325 u32 tmp; in dce_v10_0_hpd_init() local
[all …]
H A Ddce_v11_0.c253 u32 tmp; in dce_v11_0_page_flip() local
256 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
257 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v11_0_page_flip()
259 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_page_flip()
317 u32 tmp; in dce_v11_0_hpd_set_polarity() local
323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_set_polarity()
325 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v11_0_hpd_set_polarity()
327 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v11_0_hpd_set_polarity()
328 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_set_polarity()
343 u32 tmp; in dce_v11_0_hpd_init() local
[all …]
H A Ddf_v1_7.c39 u32 tmp; in df_v1_7_enable_broadcast_mode() local
42 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
43 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK; in df_v1_7_enable_broadcast_mode()
44 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v1_7_enable_broadcast_mode()
52 u32 tmp; in df_v1_7_get_fb_channel_number() local
54 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
55 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; in df_v1_7_get_fb_channel_number()
56 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; in df_v1_7_get_fb_channel_number()
58 return tmp; in df_v1_7_get_fb_channel_number()
73 u32 tmp; in df_v1_7_update_medium_grain_clock_gating() local
[all …]
H A Ddf_v3_6.c40 u32 tmp; in df_v3_6_enable_broadcast_mode() local
43 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v3_6_enable_broadcast_mode()
44 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK; in df_v3_6_enable_broadcast_mode()
45 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v3_6_enable_broadcast_mode()
53 u32 tmp; in df_v3_6_get_fb_channel_number() local
55 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); in df_v3_6_get_fb_channel_number()
56 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK; in df_v3_6_get_fb_channel_number()
57 tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; in df_v3_6_get_fb_channel_number()
59 return tmp; in df_v3_6_get_fb_channel_number()
76 u32 tmp; in df_v3_6_update_medium_grain_clock_gating() local
[all …]
/dflybsd-src/sys/dev/drm/radeon/
H A Dradeon_clocks.c196 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
199 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
201 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
389 uint32_t tmp; in radeon_legacy_set_engine_clock() local
396 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
397 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
398 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
400 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
401 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
402 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
[all …]
H A Dvce_v2_0.c40 u32 tmp; in vce_v2_0_set_sw_cg() local
43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
44 tmp |= 0xe70000; in vce_v2_0_set_sw_cg()
45 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
48 tmp |= 0xff000000; in vce_v2_0_set_sw_cg()
49 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
52 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
[all …]
H A Drs400.c60 uint32_t tmp; in rs400_gart_tlb_flush() local
65 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); in rs400_gart_tlb_flush()
66 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) in rs400_gart_tlb_flush()
108 uint32_t tmp; in rs400_gart_enable() local
110 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); in rs400_gart_enable()
111 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; in rs400_gart_enable()
112 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); in rs400_gart_enable()
147 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
148 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
150 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); in rs400_gart_enable()
[all …]
H A Dr600.c294 u32 tmp = 0; in dce3_program_fmt() local
319 tmp |= FMT_SPATIAL_DITHER_EN; in dce3_program_fmt()
321 tmp |= FMT_TRUNCATE_EN; in dce3_program_fmt()
326 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); in dce3_program_fmt()
328 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); in dce3_program_fmt()
336 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
852 u32 tmp; in r600_hpd_set_polarity() local
858 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_hpd_set_polarity()
860 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
862 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
[all …]
/dflybsd-src/contrib/wpa_supplicant/src/common/
H A Dsae.c24 struct sae_temporary_data *tmp; in sae_set_group() local
36 tmp = sae->tmp = os_zalloc(sizeof(*tmp)); in sae_set_group()
37 if (tmp == NULL) in sae_set_group()
41 tmp->ec = crypto_ec_init(group); in sae_set_group()
42 if (tmp->ec) { in sae_set_group()
46 tmp->prime_len = crypto_ec_prime_len(tmp->ec); in sae_set_group()
47 tmp->prime = crypto_ec_get_prime(tmp->ec); in sae_set_group()
48 tmp->order_len = crypto_ec_order_len(tmp->ec); in sae_set_group()
49 tmp->order = crypto_ec_get_order(tmp->ec); in sae_set_group()
54 tmp->dh = dh_groups_get(group); in sae_set_group()
[all …]
/dflybsd-src/test/sysperf/
H A DMakefile1 TARGETS=/tmp/sc1 /tmp/sc2 /tmp/sc3 /tmp/sc4 /tmp/sc5 /tmp/sc6 /tmp/sc7 \
2 /tmp/loop1 /tmp/loop2 /tmp/loop3 /tmp/loop4 \
3 /tmp/call1 /tmp/call2 /tmp/call3 /tmp/cmp \
4 /tmp/mt2 /tmp/mt3 /tmp/mt4 \
5 /tmp/fork1 /tmp/pipe1 /tmp/pipe2 /tmp/pipe3 \
6 /tmp/umtx1 \
7 /tmp/sp1 \
8 /tmp/sw1 /tmp/sw2 /tmp/sw3 \
9 /tmp/mbw1 \
10 /tmp/exec1 /tmp/exec2 \
[all …]
/dflybsd-src/sys/sys/
H A Dtree.h89 #define SPLAY_ROTATE_RIGHT(head, tmp, field) do { \ argument
90 SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(tmp, field); \
91 SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
92 (head)->sph_root = tmp; \
95 #define SPLAY_ROTATE_LEFT(head, tmp, field) do { \ argument
96 SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(tmp, field); \
97 SPLAY_LEFT(tmp, field) = (head)->sph_root; \
98 (head)->sph_root = tmp; \
101 #define SPLAY_LINKLEFT(head, tmp, field) do { \ argument
102 SPLAY_LEFT(tmp, field) = (head)->sph_root; \
[all …]
/dflybsd-src/sys/dev/drm/i915/
H A Dintel_audio.c203 uint32_t tmp; in intel_eld_uptodate() local
206 tmp = I915_READ(reg_eldv); in intel_eld_uptodate()
207 tmp &= bits_eldv; in intel_eld_uptodate()
209 if (!tmp) in intel_eld_uptodate()
212 tmp = I915_READ(reg_elda); in intel_eld_uptodate()
213 tmp &= ~bits_elda; in intel_eld_uptodate()
214 I915_WRITE(reg_elda, tmp); in intel_eld_uptodate()
226 uint32_t eldv, tmp; in g4x_audio_codec_disable() local
230 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_disable()
231 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) in g4x_audio_codec_disable()
[all …]
/dflybsd-src/sys/vfs/tmpfs/
H A Dtmpfs_vfsops.c99 struct tmpfs_mount *tmp; in tmpfs_mount() local
189 tmp = kmalloc(sizeof(*tmp), M_TMPFSMNT, M_WAITOK | M_ZERO); in tmpfs_mount()
191 tmp->tm_mount = mp; in tmpfs_mount()
192 tmp->tm_nodes_max = nodes; in tmpfs_mount()
193 tmp->tm_nodes_inuse = 0; in tmpfs_mount()
194 tmp->tm_maxfilesize = maxfsize; in tmpfs_mount()
195 LIST_INIT(&tmp->tm_nodes_used); in tmpfs_mount()
197 tmp->tm_pages_max = pages; in tmpfs_mount()
198 tmp->tm_pages_used = 0; in tmpfs_mount()
200 kmalloc_create_obj(&tmp->tm_node_zone, "tmpfs node", in tmpfs_mount()
[all …]
/dflybsd-src/games/hack/
H A Dhack.worm.c79 int tmp; in getwn() local
80 for (tmp = 1; tmp < 32; tmp++) in getwn()
81 if (!wsegs[tmp]) { in getwn()
82 mtmp->wormno = tmp; in getwn()
93 int tmp = mtmp->wormno; in initworm() local
94 if (!tmp) in initworm()
96 wheads[tmp] = wsegs[tmp] = wtmp = newseg(); in initworm()
97 wgrowtime[tmp] = 0; in initworm()
108 int tmp = mtmp->wormno; in worm_move() local
114 (whd = wheads[tmp])->nseg = wtmp; in worm_move()
[all …]
H A Dhack.fight.c78 schar tmp; in hitmm() local
85 tmp = pd->ac + pa->mlevel; in hitmm()
87 tmp += 4; in hitmm()
91 didhit = (tmp > rnd(20)); in hitmm()
215 int tmp; in hmon() local
219 tmp = rnd(2); /* attack with bare hands */ in hmon()
227 tmp = rnd(2); in hmon()
230 tmp = rnd(objects[obj->otyp].wldam); in hmon()
232 tmp += d(2, 6); in hmon()
234 tmp += rnd(4); in hmon()
[all …]
/dflybsd-src/sys/dev/drm/
H A Ddrm_rect.c76 int64_t tmp = src->x1 + (int64_t) diff * hscale; in drm_rect_clip_scaled() local
77 src->x1 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); in drm_rect_clip_scaled()
81 int64_t tmp = src->y1 + (int64_t) diff * vscale; in drm_rect_clip_scaled() local
82 src->y1 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); in drm_rect_clip_scaled()
86 int64_t tmp = src->x2 - (int64_t) diff * hscale; in drm_rect_clip_scaled() local
87 src->x2 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); in drm_rect_clip_scaled()
91 int64_t tmp = src->y2 - (int64_t) diff * vscale; in drm_rect_clip_scaled() local
92 src->y2 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); in drm_rect_clip_scaled()
311 struct drm_rect tmp; in drm_rect_rotate() local
314 tmp = *r; in drm_rect_rotate()
[all …]
/dflybsd-src/lib/libssh/openbsd-compat/
H A Dsys-tree.h88 #define SPLAY_ROTATE_RIGHT(head, tmp, field) do { \ argument
89 SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(tmp, field); \
90 SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
91 (head)->sph_root = tmp; \
94 #define SPLAY_ROTATE_LEFT(head, tmp, field) do { \ argument
95 SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(tmp, field); \
96 SPLAY_LEFT(tmp, field) = (head)->sph_root; \
97 (head)->sph_root = tmp; \
100 #define SPLAY_LINKLEFT(head, tmp, field) do { \ argument
101 SPLAY_LEFT(tmp, field) = (head)->sph_root; \
[all …]
/dflybsd-src/usr.bin/gzip/
H A Dgzexe38 tmp=`/usr/bin/mktemp -d /tmp/gzexeXXXXXXXXXX` || {
43 /usr/bin/gzip -dc > "$tmp/$prog" 2> /dev/null; then
44 /bin/chmod u+x "$tmp/$prog"
45 "$tmp/$prog" ${1+"$@"}
62 tmp=`mktemp /tmp/gzexeXXXXXXXXXX` || {
66 if ! cp "$1" "$tmp"; then
67 echo "$prog: cannot copy $1 to $tmp"
68 rm -f "$tmp"
71 if ! tail +$lines "$tmp" | gzip -vdc > "$1"; then
73 cp "$tmp" "$1"
[all …]
/dflybsd-src/contrib/gdb-7/readline/
H A Dmbutil.c80 size_t tmp, len; local
85 tmp = 0;
105 tmp = mbrtowc (&wc, string+point, len, &ps);
106 if (MB_INVALIDCH ((size_t)tmp))
114 else if (MB_NULLWCH (tmp))
119 point += tmp;
134 tmp = mbrtowc (&wc, string + point, strlen (string + point), &ps);
135 while (MB_NULLWCH (tmp) == 0 && MB_INVALIDCH (tmp) == 0 && wcwidth (wc) == 0)
137 point += tmp;
138 tmp = mbrtowc (&wc, string + point, strlen (string + point), &ps);
[all …]
/dflybsd-src/test/stress/stress2/misc/
H A Dnullfs6.sh39 mount | grep nullfs | grep -q /tmp/1 && umount /tmp/1
41 rm -rf /tmp/1 /tmp/2
42 mkdir /tmp/1 /tmp/2
43 touch /tmp/1/test.file
45 mount -t nullfs /tmp/1 /tmp/2
47 cp /tmp/1/test.file /tmp/2/test.file # scenario by kib
48 mv /tmp/1/test.file /tmp/2/ # panics with lock violation
50 umount /tmp/1
51 rm -rf /tmp/1 /tmp/2
/dflybsd-src/contrib/mpfr/src/
H A Dmul.c41 mp_limb_t *tmp; in mpfr_mul3() local
111 tmp = MPFR_TMP_LIMBS_ALLOC (k); in mpfr_mul3()
115 mpn_mul (tmp, MPFR_MANT(b), bn, MPFR_MANT(c), cn) in mpfr_mul3()
116 : mpn_mul (tmp, MPFR_MANT(c), cn, MPFR_MANT(b), bn); in mpfr_mul3()
125 tmp += k - tn; in mpfr_mul3()
127 mpn_lshift (tmp, tmp, tn, 1); /* tn <= k, so no stack corruption */ in mpfr_mul3()
128 cc = mpfr_round_raw (MPFR_MANT (a), tmp, bq + cq, in mpfr_mul3()
217 mp_limb_t *tmp; in mpfr_mul() local
306 tmp = MPFR_TMP_LIMBS_ALLOC (k); in mpfr_mul()
324 umul_ppmm (tmp[1], tmp[0], MPFR_MANT (b)[0], MPFR_MANT (c)[0]); in mpfr_mul()
[all …]

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