105 	uint32_t tmp;  in gfxhub_v1_0_init_tlb_regs()  local
108 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_init_tlb_regs()
110 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v1_0_init_tlb_regs()
111 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v1_0_init_tlb_regs()
112 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
114 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
116 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);  in gfxhub_v1_0_init_tlb_regs()
117 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
119 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);  in gfxhub_v1_0_init_tlb_regs()
121 	WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_init_tlb_regs()
126 	uint32_t tmp;  in gfxhub_v1_0_init_cache_regs()  local
129 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);  in gfxhub_v1_0_init_cache_regs()
130 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
131 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gfxhub_v1_0_init_cache_regs()
133 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,  in gfxhub_v1_0_init_cache_regs()
135 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);  in gfxhub_v1_0_init_cache_regs()
136 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v1_0_init_cache_regs()
137 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v1_0_init_cache_regs()
138 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);  in gfxhub_v1_0_init_cache_regs()
140 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);  in gfxhub_v1_0_init_cache_regs()
141 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v1_0_init_cache_regs()
142 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
143 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);  in gfxhub_v1_0_init_cache_regs()
145 	tmp = mmVM_L2_CNTL3_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
147 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v1_0_init_cache_regs()
148 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
151 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v1_0_init_cache_regs()
152 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
155 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);  in gfxhub_v1_0_init_cache_regs()
157 	tmp = mmVM_L2_CNTL4_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
158 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
159 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
160 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);  in gfxhub_v1_0_init_cache_regs()
165 	uint32_t tmp;  in gfxhub_v1_0_enable_system_domain()  local
167 	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);  in gfxhub_v1_0_enable_system_domain()
168 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_enable_system_domain()
169 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gfxhub_v1_0_enable_system_domain()
170 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);  in gfxhub_v1_0_enable_system_domain()
193 	uint32_t tmp;  in gfxhub_v1_0_setup_vmid_config()  local
204 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);  in gfxhub_v1_0_setup_vmid_config()
205 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_setup_vmid_config()
206 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v1_0_setup_vmid_config()
208 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
210 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
213 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
215 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
217 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
219 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
221 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
223 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
227 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
229 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);  in gfxhub_v1_0_setup_vmid_config()
281 	u32 tmp;  in gfxhub_v1_0_gart_disable()  local
289 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_gart_disable()
290 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v1_0_gart_disable()
291 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_gart_disable()
295 	WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_gart_disable()
311 	u32 tmp;  in gfxhub_v1_0_set_fault_enable_default()  local
312 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v1_0_set_fault_enable_default()
313 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
315 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
317 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
319 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
321 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_set_fault_enable_default()
325 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
327 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
329 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
331 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
333 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
335 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
338 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
340 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
343 	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v1_0_set_fault_enable_default()