Lines Matching refs:tmp
235 u32 tmp; in dce_v10_0_page_flip() local
238 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
239 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v10_0_page_flip()
241 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_page_flip()
299 u32 tmp; in dce_v10_0_hpd_set_polarity() local
305 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
307 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v10_0_hpd_set_polarity()
309 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v10_0_hpd_set_polarity()
310 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
325 u32 tmp; in dce_v10_0_hpd_init() local
340 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
341 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); in dce_v10_0_hpd_init()
342 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
346 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
347 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v10_0_hpd_init()
348 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
350 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
351 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v10_0_hpd_init()
354 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v10_0_hpd_init()
357 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
377 u32 tmp; in dce_v10_0_hpd_fini() local
385 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_fini()
386 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v10_0_hpd_fini()
387 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_fini()
403 u32 i, j, tmp; in dce_v10_0_is_display_hung() local
406 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
407 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { in dce_v10_0_is_display_hung()
416 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v10_0_is_display_hung()
417 if (tmp != crtc_status[i]) in dce_v10_0_is_display_hung()
432 u32 tmp; in dce_v10_0_set_vga_render_state() local
435 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v10_0_set_vga_render_state()
437 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v10_0_set_vga_render_state()
439 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v10_0_set_vga_render_state()
440 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
443 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_set_vga_render_state()
445 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); in dce_v10_0_set_vga_render_state()
447 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in dce_v10_0_set_vga_render_state()
448 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
470 u32 tmp; in dce_v10_0_disable_dce() local
481 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce()
482 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); in dce_v10_0_disable_dce()
483 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_disable_dce()
498 u32 tmp = 0; in dce_v10_0_program_fmt() local
523 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
524 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
525 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
526 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v10_0_program_fmt()
528 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
529 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v10_0_program_fmt()
535 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
536 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); in dce_v10_0_program_fmt()
541 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v10_0_program_fmt()
548 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); in dce_v10_0_program_fmt()
554 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); in dce_v10_0_program_fmt()
563 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_fmt()
584 u32 tmp, buffer_alloc, i, mem_cfg; in dce_v10_0_line_buffer_adjust() local
614 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v10_0_line_buffer_adjust()
615 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); in dce_v10_0_line_buffer_adjust()
616 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_line_buffer_adjust()
618 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
619 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); in dce_v10_0_line_buffer_adjust()
620 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v10_0_line_buffer_adjust()
623 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
624 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v10_0_line_buffer_adjust()
656 u32 tmp = RREG32(mmMC_SHARED_CHMAP); in cik_get_number_of_dram_channels() local
658 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in cik_get_number_of_dram_channels()
888 u32 tmp, dmif_size = 12288; in dce_v10_0_latency_watermark() local
907 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v10_0_latency_watermark()
908 tmp = min(dfixed_trunc(a), tmp); in dce_v10_0_latency_watermark()
910 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v10_0_latency_watermark()
1021 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; in dce_v10_0_program_watermarks() local
1112 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); in dce_v10_0_program_watermarks()
1113 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1114 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1115 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); in dce_v10_0_program_watermarks()
1116 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); in dce_v10_0_program_watermarks()
1117 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1119 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); in dce_v10_0_program_watermarks()
1120 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1121 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1122 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); in dce_v10_0_program_watermarks()
1123 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); in dce_v10_0_program_watermarks()
1124 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1167 u32 offset, tmp; in dce_v10_0_audio_get_connected_pins() local
1171 tmp = RREG32_AUDIO_ENDPT(offset, in dce_v10_0_audio_get_connected_pins()
1173 if (((tmp & in dce_v10_0_audio_get_connected_pins()
1201 u32 tmp; in dce_v10_0_afmt_audio_select_pin() local
1206 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_audio_select_pin()
1207 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
1208 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_audio_select_pin()
1219 u32 tmp; in dce_v10_0_audio_write_latency_fields() local
1240 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v10_0_audio_write_latency_fields()
1242 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v10_0_audio_write_latency_fields()
1245 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v10_0_audio_write_latency_fields()
1247 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v10_0_audio_write_latency_fields()
1251 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); in dce_v10_0_audio_write_latency_fields()
1261 u32 tmp; in dce_v10_0_audio_write_speaker_allocation() local
1287 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1289 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v10_0_audio_write_speaker_allocation()
1292 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v10_0_audio_write_speaker_allocation()
1295 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v10_0_audio_write_speaker_allocation()
1298 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v10_0_audio_write_speaker_allocation()
1301 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); in dce_v10_0_audio_write_speaker_allocation()
1354 u32 tmp = 0; in dce_v10_0_audio_write_sad_regs() local
1364 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v10_0_audio_write_sad_regs()
1366 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v10_0_audio_write_sad_regs()
1368 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v10_0_audio_write_sad_regs()
1380 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v10_0_audio_write_sad_regs()
1382 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v10_0_audio_write_sad_regs()
1464 u32 tmp; in dce_v10_0_afmt_update_ACR() local
1466 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1467 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v10_0_afmt_update_ACR()
1468 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1469 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1470 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v10_0_afmt_update_ACR()
1471 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1473 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1474 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v10_0_afmt_update_ACR()
1475 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1476 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1477 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v10_0_afmt_update_ACR()
1478 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1480 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1481 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v10_0_afmt_update_ACR()
1482 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1483 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1484 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v10_0_afmt_update_ACR()
1485 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1521 u32 tmp; in dce_v10_0_audio_set_dto() local
1531 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); in dce_v10_0_audio_set_dto()
1532 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, in dce_v10_0_audio_set_dto()
1534 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); in dce_v10_0_audio_set_dto()
1553 u32 tmp; in dce_v10_0_afmt_setmode() local
1575 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1576 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); in dce_v10_0_afmt_setmode()
1577 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v10_0_afmt_setmode()
1581 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1588 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); in dce_v10_0_afmt_setmode()
1589 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in dce_v10_0_afmt_setmode()
1594 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v10_0_afmt_setmode()
1595 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); in dce_v10_0_afmt_setmode()
1600 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v10_0_afmt_setmode()
1601 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); in dce_v10_0_afmt_setmode()
1606 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1608 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1609 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when re… in dce_v10_0_afmt_setmode()
1610 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packet… in dce_v10_0_afmt_setmode()
1611 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packet… in dce_v10_0_afmt_setmode()
1612 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1614 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1616 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in dce_v10_0_afmt_setmode()
1618 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); in dce_v10_0_afmt_setmode()
1619 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1621 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1623 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in dce_v10_0_afmt_setmode()
1624 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1626 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1628 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); in dce_v10_0_afmt_setmode()
1629 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1633 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1635 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); in dce_v10_0_afmt_setmode()
1637 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); in dce_v10_0_afmt_setmode()
1638 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1640 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1642 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in dce_v10_0_afmt_setmode()
1643 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1645 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1648 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v10_0_afmt_setmode()
1651 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v10_0_afmt_setmode()
1653 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v10_0_afmt_setmode()
1654 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1658 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1659 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); in dce_v10_0_afmt_setmode()
1660 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1662 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1663 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in dce_v10_0_afmt_setmode()
1664 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1666 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1667 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); in dce_v10_0_afmt_setmode()
1668 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); in dce_v10_0_afmt_setmode()
1669 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); in dce_v10_0_afmt_setmode()
1670 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); in dce_v10_0_afmt_setmode()
1671 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); in dce_v10_0_afmt_setmode()
1672 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); in dce_v10_0_afmt_setmode()
1673 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1698 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1700 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); in dce_v10_0_afmt_setmode()
1702 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); in dce_v10_0_afmt_setmode()
1703 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1705 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1706 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); in dce_v10_0_afmt_setmode()
1707 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1709 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1711 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); in dce_v10_0_afmt_setmode()
1712 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1835 u32 tmp, viewport_w, viewport_h; in dce_v10_0_crtc_do_set_base() local
1984 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
1985 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v10_0_crtc_do_set_base()
1987 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2005 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2007 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); in dce_v10_0_crtc_do_set_base()
2009 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); in dce_v10_0_crtc_do_set_base()
2010 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2063 u32 tmp; in dce_v10_0_set_interleave() local
2065 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v10_0_set_interleave()
2067 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); in dce_v10_0_set_interleave()
2069 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); in dce_v10_0_set_interleave()
2070 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_set_interleave()
2080 u32 tmp; in dce_v10_0_crtc_load_lut() local
2084 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2085 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); in dce_v10_0_crtc_load_lut()
2086 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); in dce_v10_0_crtc_load_lut()
2087 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2089 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2090 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_v10_0_crtc_load_lut()
2091 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2093 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2094 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); in dce_v10_0_crtc_load_lut()
2095 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2097 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2098 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2099 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2100 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2126 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2127 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2128 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2129 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2130 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2132 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2133 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); in dce_v10_0_crtc_load_lut()
2134 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); in dce_v10_0_crtc_load_lut()
2135 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2137 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2138 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2139 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2140 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2142 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2143 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); in dce_v10_0_crtc_load_lut()
2144 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); in dce_v10_0_crtc_load_lut()
2145 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2152 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2153 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); in dce_v10_0_crtc_load_lut()
2154 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2267 u32 tmp; in dce_v10_0_hide_cursor() local
2269 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_hide_cursor()
2270 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); in dce_v10_0_hide_cursor()
2271 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_hide_cursor()
2278 u32 tmp; in dce_v10_0_show_cursor() local
2285 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_show_cursor()
2286 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); in dce_v10_0_show_cursor()
2287 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); in dce_v10_0_show_cursor()
2288 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_show_cursor()
2908 u32 srbm_soft_reset = 0, tmp; in dce_v10_0_soft_reset() local
2915 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
2916 tmp |= srbm_soft_reset; in dce_v10_0_soft_reset()
2917 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v10_0_soft_reset()
2918 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v10_0_soft_reset()
2919 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
2923 tmp &= ~srbm_soft_reset; in dce_v10_0_soft_reset()
2924 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v10_0_soft_reset()
2925 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
2996 u32 tmp; in dce_v10_0_set_hpd_irq_state() local
3005 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3006 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); in dce_v10_0_set_hpd_irq_state()
3007 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3010 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3011 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); in dce_v10_0_set_hpd_irq_state()
3012 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3148 u32 tmp; in dce_v10_0_hpd_int_ack() local
3155 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3156 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); in dce_v10_0_hpd_int_ack()
3157 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
3163 u32 tmp; in dce_v10_0_crtc_vblank_int_ack() local
3170 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vblank_int_ack()
3171 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); in dce_v10_0_crtc_vblank_int_ack()
3172 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vblank_int_ack()
3178 u32 tmp; in dce_v10_0_crtc_vline_int_ack() local
3185 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vline_int_ack()
3186 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); in dce_v10_0_crtc_vline_int_ack()
3187 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vline_int_ack()